Semiconductor structure and manufacturing method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a substrate; the stacking structure is located on the substrate, and the stacking structure comprises a plurality of storage unit structures and a plurality of insulation structures which are alternately stacked; a single memory cell structure at least comprises a semiconductor layer and a capacitor structure at a first end close to the stacked structure, the capacitor structure comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer, and the first electrode layer is electrically connected with the semiconductor layer; wherein each first electrode layer comprises two sunken parts which are sunken in the direction away from the first end, and the semiconductor layer is located between the two sunken parts of the first electrode layer. By adopting the semiconductor structure, a semiconductor device with relatively high storage performance and relatively high reliability can be obtained.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures based on existing structures is a favorable means to break through existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cell (MHC), which generally includes a plurality of transistors stacked on a substrate, meets the above requirements.

[0004] However, the space of multi-layer horizontal storage units is still relatively limited, and how to further increase the storage capacity of storage units has become a common problem. Summary of the invention

[0005] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a stacking structure located on the substrate, the stacking structure comprising a plurality of memory cell structures and a plurality of insulating structures stacked alternately; a single memory cell structure comprises at least a semiconductor layer and a capacitor structure near a first end of the stacking structure, the capacitor structure comprising a first electrode layer, a capacitor dielectric layer and a second electrode layer, the first electrode layer being electrically connected to the semiconductor layer; wherein the single first electrode layer comprises two recessed portions recessed in a direction away from the first end, and the semiconductor layer is located between the two recessed portions of the first electrode layer.

[0006] In some embodiments, in the same memory cell structure, the two recessed portions of the first electrode layer are electrically connected through the semiconductor layer.

[0007] In some embodiments, in the same memory cell structure, the two recessed portions of the first electrode layer are connected at an end of the semiconductor layer close to the first end.

[0008] In some embodiments, in the same memory cell structure, the structures and shapes of the two recessed portions of the first electrode layer are symmetrically arranged with respect to the semiconductor layer.

[0009] In some embodiments, the two recessed portions of the first electrode layer and the semiconductor layer are stacked alternately in a direction perpendicular to the substrate surface.

[0010] In some embodiments, the second electrode layer includes a plurality of protrusions and connecting portions; each of the protrusions is respectively embedded in each of the recessed portions, and the recessed portions and the protrusions are separated by the capacitor dielectric layer; the connecting portion extends in a direction perpendicular to the surface of the substrate and is electrically connected to each of the protrusions at the first end.

[0011] In some embodiments, at the second end of the stacked structure, the memory cell structure further includes a transistor structure, a first source and drain of the transistor structure close to the first end is connected to the semiconductor layer, wherein the second end is arranged opposite to the first end.

[0012] In some embodiments, the semiconductor structure further includes: a word line structure and a bit line structure, the word line structure is connected to the gate of the transistor structure, and the bit line structure is connected to the second source and drain of the transistor structure close to the second end.

[0013] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a stacked structure consisting of a plurality of semiconductor material layers and a plurality of sacrificial material layers alternately stacked on the substrate; performing side etching from a first end of the stacked structure to remove a portion of the plurality of sacrificial material layers to form a recessed gap recessed in a direction away from the first end, and the retained semiconductor material layer is located between two adjacent recessed gaps to serve as a semiconductor layer; forming a capacitor structure in the recessed gap, comprising a first electrode layer, a capacitor dielectric layer and a second electrode layer formed in sequence; removing the remaining plurality of sacrificial material layers to form a plurality of insulating structures to isolate adjacent semiconductor layers; wherein a single first electrode layer comprises two recessed portions recessed in a direction away from the first end, and the semiconductor layer is located between the two recessed portions of the first electrode layer.

[0014] In some embodiments, a stacked structure consisting of multiple semiconductor material layers and multiple sacrificial material layers alternately stacked is formed on the substrate, including: through an epitaxial growth process, a staggered stack of multiple first semiconductor material layers, multiple sacrificial material layers, and multiple second semiconductor material layers are formed on the substrate, wherein a single sacrificial material layer is located between adjacent single first semiconductor material layers and single second semiconductor material layers.

[0015] In some embodiments, after forming the first electrode layer and before forming the second electrode layer, the manufacturing method also includes: selectively removing a portion of the second semiconductor material layer to form an isolation gap between adjacent first electrode layers, the second electrode layer including a first protrusion embedded in the recess and a second protrusion embedded in the isolation gap.

[0016] In some embodiments, the remaining multiple sacrificial material layers are removed to form an insulating structure to isolate the adjacent semiconductor layers, including: removing the remaining multiple sacrificial material layers and replacing them with multiple first insulating layers; removing the remaining multiple second semiconductor material layers and replacing them with multiple second insulating layers; the multiple first insulating layers and the multiple second insulating layers together constitute the multiple insulating structures.

[0017] In some embodiments, after forming the recessed gap and before forming the first electrode layer, the manufacturing method further includes: selectively removing all of the plurality of second semiconductor material layers and replacing them with a plurality of third insulating layers.

[0018] In some embodiments, the remaining multiple sacrificial material layers are removed to form an insulating structure to isolate the adjacent semiconductor layers, including: removing the remaining multiple sacrificial material layers and replacing them with multiple fourth insulating layers; the multiple third insulating layers and the multiple fourth insulating layers together constitute the multiple insulating structures.

[0019] In some embodiments, the method for manufacturing the semiconductor structure also includes: forming a transistor structure at the second end of the stacked structure, the first source and drain of the transistor structure close to the first end being connected to the semiconductor layer, wherein the second end is arranged opposite to the first end; forming a word line structure and a bit line structure, the word line structure connecting the gate of the transistor structure, and the bit line structure connecting the second source and drain of the transistor structure close to the second end. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram showing providing a substrate according to an exemplary embodiment;

[0021] Figure 2 is a schematic diagram showing a stacked structure according to an exemplary embodiment;

[0022] Figure 3 According to an exemplary embodiment, Figure 2 Schematic diagram of the cross section along the A-A' direction;

[0023] Figures 4 to 5 is a schematic diagram showing a recessed gap formed by side etching at a first end of a stacked structure according to an exemplary embodiment;

[0024] Figure 6 is a schematic diagram showing a method of forming a first electrode layer on an inner wall of a recessed gap according to an exemplary embodiment;

[0025] Figure 7 is a schematic diagram showing selectively removing a portion of the second semiconductor material layer according to an exemplary embodiment;

[0026] Figure 8 is a schematic diagram showing the formation of a capacitor dielectric layer and a second electrode layer according to an exemplary embodiment;

[0027] Fig. 9 is a schematic diagram showing the removal of the remaining sacrificial material layer and the replacement of the first insulating layer according to an exemplary embodiment;

[0028] Fig.10 is a schematic diagram showing the removal of the remaining second semiconductor material layer and replacing it with a second insulating layer according to an exemplary embodiment;

[0029] Fig.11 According to an exemplary embodiment, Fig.10 Schematic diagram of the cross section along the A-A' direction;

[0030] Fig.12 is a schematic diagram showing a method of forming a 3D DRAM according to an exemplary embodiment;

[0031] Fig.13 is a schematic diagram showing a method of forming a 3D DRAM according to another exemplary embodiment;

[0032] Fig.14 is a schematic diagram showing the formation of a recessed gap according to another exemplary embodiment;

[0033] Figures 15 to 17 is a schematic diagram showing selectively removing the entire second semiconductor material layer and replacing it with a third insulating layer according to another exemplary embodiment;

[0034] Fig.18 is a schematic diagram showing a method of forming a first electrode layer on an inner wall of a recessed gap according to another exemplary embodiment;

[0035] Fig.19 is a schematic diagram showing the formation of a capacitor dielectric layer and a second electrode layer according to another exemplary embodiment;

[0036] Fig. 20 is a schematic diagram showing the removal of the remaining second semiconductor material layer and the replacement of the layer with a fourth insulating layer according to another exemplary embodiment;

[0037] Fig.21 According to another exemplary embodiment, Fig. 20 Schematic diagram of the cross section along the A-A' direction;

[0038] Fig. 22 is a schematic diagram showing a method of forming a 3D DRAM according to another exemplary embodiment;

[0039] Fig.23 FIG. 4 is a schematic diagram showing a method of forming a 3D DRAM according to yet another exemplary embodiment. DETAILED DESCRIPTION

[0040] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0042] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0043] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0044] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0045] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0046] In the related art, the process flow of the 3D memory structure usually needs to form a stack of semiconductor materials and insulating materials, and then form a memory cell structure based on the semiconductor material, such as a storage transistor, a storage capacitor, a bit line, a word line and other structures. In the process of forming the memory cell structure, especially in the process of forming the capacitor structure, it is usually necessary to remove part of the semiconductor material to form a gap in the stack, and then form a storage capacitor structure in the gap. However, the inventors of the present application found that: in the stack in the 3D memory structure, by removing part of the semiconductor material to form a gap, the space size of the gap is relatively limited, and the morphology of the inner wall of the gap is not relatively flat. The subsequent filling of the storage capacitor material in the gap, on the one hand, has a high process difficulty, and is prone to poor filling problems. In severe cases, the capacitor material cannot contact the remaining semiconductor material, thereby causing a short circuit, which directly affects the yield of the device; on the other hand, the storage capacitor formed in the narrow gap is also greatly limited in capacitance, which affects the storage performance of the memory cell device.

[0047] In view of the above technical problems, the present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. Figures 1 to 23 A semiconductor structure and a method for preparing the semiconductor structure exemplarily provided by the present disclosure are specifically introduced. Figures 1 to 11 The following is a schematic diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure. Figures 14 to 21 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor structure according to another exemplary embodiment of the present disclosure, and shows steps and a structure thereof. Fig.12 , Fig.13 , Fig. 22 and Fig.23 FIG. 4 is a schematic diagram of a 3D DRAM structure according to multiple exemplary embodiments of the present disclosure.

[0048] In an exemplary embodiment of the present disclosure, referring to Figure 1 As shown, a substrate 101 is provided.

[0049] The material of the substrate 101 may be at least one of the following materials: semiconductor materials or III-V materials such as silicon, germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In an exemplary embodiment of the present disclosure, the material of the substrate 101 is single crystal silicon.

[0050] In an exemplary embodiment of the present disclosure, referring to Figure 2 and Figure 3 As shown, Figure 3 For along Figure 2In the cross-sectional view along the A-A' direction, a stacked structure 102 is formed on a substrate 101, wherein a plurality of semiconductor material layers and a plurality of sacrificial material layers 1021 are alternately stacked, wherein the plurality of semiconductor material layers include a plurality of first semiconductor material layers 1023 and a plurality of second semiconductor material layers 1022. In some embodiments, the plurality of first semiconductor material layers 1023 and the plurality of second semiconductor material layers 1022 are alternately interspersed, that is, Figure 2 As shown, a single layer of second semiconductor material layer 1022 is interspersed between any two adjacent single layers of first semiconductor material layer 1023, a single layer of first semiconductor material layer 1023 is interspersed between any two adjacent single layers of second semiconductor material layer 1022, and a single layer of sacrificial material layer 1021 is interspersed between any adjacent single layers of first semiconductor material layer 1023 and single layers of second semiconductor material layer 1022. In the semiconductor material layer, the first semiconductor material layer 1023 or the second semiconductor material layer 1022 is closer to the substrate, and the present disclosure does not make specific limitations.

[0051] The materials of the semiconductor material layer and the sacrificial material layer 1021 may be at least one or any combination of the following materials: silicon, germanium, silicon germanium (SiGe), III-V materials, indium gallium zinc oxide (IGZO), and two-dimensional materials. In an exemplary embodiment of the present disclosure, the material of the sacrificial material layer 1021 is silicon germanium, and the material of the semiconductor material layer is silicon. Specifically, in some embodiments, the material of the first semiconductor material layer 1023 is phosphorus-doped silicon or undoped silicon, and the material of the second semiconductor material layer 1022 is boron-doped silicon.

[0052] In an exemplary embodiment of the present disclosure, a method for forming a stacked structure 102 includes: using a single crystal silicon (Si) surface of a substrate 101 as an initial base layer, and using an epitaxial growth method to grow a stacked structure 102 of alternately stacked silicon-silicon germanium (Si-SiGe) on the substrate 101. In which, a germanium source gas can be added during the epitaxial growth of a silicon layer to form a silicon germanium layer as a sacrificial material layer 1021, a phosphorus source gas can be added to form phosphorus-doped silicon as a first semiconductor material layer 1023 or no other source gas is added to form undoped silicon as the first semiconductor material layer 1023, and a boron source gas can be added to form boron-doped silicon as a second semiconductor material layer 1022.

[0053] In some embodiments, the number of layers of the sacrificial material layer 1021 and the semiconductor material layer (the sum of the number of layers of the first semiconductor material layer and the second semiconductor material layer) in the stacked structure 102 is the same, and both are greater than or equal to 4. In other embodiments, the number of layers of the sacrificial material layer 1021 in the stacked structure 102 is 1 more than the number of layers of the semiconductor material layer. In some embodiments, the number of layers of the first semiconductor material layer 1023 in the stacked structure 102 is the same as the number of layers of the second semiconductor material layer 1022. In other embodiments, the difference between the number of layers of the first semiconductor material layer 1023 and the number of layers of the second semiconductor material layer 1022 in the stacked structure 102 is less than or equal to 1.

[0054] In some embodiments, before or after forming the stacked structure 102 on the substrate 101 , an isolation layer (not shown) is formed on other regions of the substrate 101 , wherein the isolation layer has the same height as the stacked structure 102 .

[0055] In an exemplary embodiment of the present disclosure, Figure 3 As shown, in the cross section along the AA' direction, it can be seen that the stacked structure 102 also includes an insulating spacer layer 1024, so that the sacrificial material layer 1021, the first semiconductor material layer 1023, and the second semiconductor material layer 1022 located in the same horizontal layer are spaced apart in a direction parallel to the substrate surface.

[0056] Specifically, in some embodiments, the depth direction of the insulating spacer layer 1024 is perpendicular to the surface of the substrate 10, and the extension direction of the insulating spacer layer 1024 is perpendicular to the cross section along the A-A' direction, so that in the structure located in the same horizontal layer, the insulating spacer layer 1024 and the sacrificial material layer 1021, the first semiconductor material layer 1023 or the second semiconductor material layer 1022 are arranged alternately. It can be understood that the insulating material layer 1021, the first semiconductor material layer 1023 or the second semiconductor material layer 1022 in a single horizontal layer are arranged in parallel and spaced apart in strips.

[0057] In some embodiments, the insulating spacer layer 1024 may be made of at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride. In an exemplary embodiment of the present disclosure, the insulating spacer layer 1024 is made of silicon oxide.

[0058] In an exemplary embodiment of the present disclosure, after forming the stacked structure 102, as shown in FIG. Figure 4As shown, side etching is performed from the first end of the stacked structure 102 to remove part of the plurality of sacrificial material layers 1021 and to retain recessed gaps between the plurality of semiconductor material layers. Specifically, by first forming a groove (not shown) to expose one end of all the sacrificial material layers 1021 in the stacked structure 102, side etching is performed using wet chemical etching to remove part of the sacrificial material layers 1021 and to retain a plurality of first semiconductor material layers 1023 and second semiconductor material layers 1022 spaced apart in a direction perpendicular to the substrate 101, and initial recessed gaps 1020a are formed between adjacent first semiconductor material layers 1023 and second semiconductor material layers 1022, and the initial recessed gaps 1020a are recessed in a direction away from the first end of the stacked structure 102.

[0059] In some embodiments, a silicon germanium etchant is used to side-etch the sacrificial material layer 1021 . Specifically, the silicon germanium etchant may include a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) and a silicon corrosion inhibitor.

[0060] In some embodiments, before side etching is performed, a protective layer (not shown) is pre-formed at the bottom of the first end of the stacked structure 102, and the thickness of the protective layer is higher than the sacrificial material layer 1021 of the bottom layer (i.e., the single layer closest to the substrate 101) in the stacked structure 102, so that the sacrificial material layer 1021 of the bottom layer does not contact the etching solution and is thus not etched, so that it is subsequently replaced by an insulating layer to ensure that the subsequently formed storage unit structure is insulated and isolated from the substrate.

[0061] In an exemplary embodiment of the present disclosure, reference Figure 5 As shown, after the initial recessed gap 1020a is formed, the initial recessed gap 1020a is rapidly processed by wet chemical etching to expand the initial recessed gap 1020a into a recessed gap 1020a'.

[0062] In some embodiments, a silicon etchant is used for rapid wet chemical etching. Specifically, an ammonia-deionized water mixture (ADM), a potassium hydroxide solution (KOH) or tetramethylammonium hydroxide (TMAH) is used as a silicon etchant to selectively etch the semiconductor material layer. The processing time can be 5-20 seconds, so that the first semiconductor material layer 1023 and the second semiconductor material layer 1022 exposed by the initial recessed gap 1020a are slightly corroded, thereby expanding the initial recessed gap 1020a to a recessed gap 1020a', that is, the thickness of the recessed gap 1020a' is greater than that of the initial recessed gap 1020a. It should be noted that the direction of "thickness" here refers to the direction perpendicular to the surface of the substrate 101. In addition, the inner wall of the recessed gap 1020a' is smoother than the initial recessed gap 1020a, which is more conducive to the subsequent formation of a capacitor structure in the recessed gap. It should be noted that the “inner wall” here refers not only to the inner wall parallel to the surface of the substrate 101 , but also to the inner wall perpendicular to the surface of the substrate 101 .

[0063] In an exemplary embodiment of the present disclosure, after forming the recessed gap 1020a', referring to Figure 6 As shown, a first electrode layer 1031 of the capacitor structure 103 is formed in the recessed gap 1020a'. The first electrode layer 1031 includes a recessed portion formed by adhering to the inner wall of the recessed gap 1020a', and the recessed portion is recessed toward the first end away from the stacked structure 102. In some embodiments, the recessed portions of the first electrode layer 1031 located in each recessed gap 1020a' are disconnected at the first end of the stacked structure 102, that is, the recessed portions of the first electrode layer 1031 located in each recessed gap 1020a' are not directly connected to each other.

[0064] In some embodiments, the material of the first electrode layer 1031 includes: any one or more of titanium nitride (TiN), titanium (Ti), and silicon-doped titanium nitride (TiSiN). In some embodiments, the deposition method of the first electrode layer 1031 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating sputtering.

[0065] In some embodiments, before forming the first electrode layer 1031, a sacrificial metal layer is formed in the recessed gap 1020a' to cover the first semiconductor material layer 1023 and the surface of the second semiconductor material layer 1022 exposed by the recessed gap 1020a', and then annealing is performed to form a metal silicide at the contact interface between the sacrificial metal layer and the semiconductor material layer, and then the unreacted sacrificial metal layer is removed to form a metal semiconductor contact layer (not shown) whose material is metal silicide, which is used to at least reduce the subsequent contact resistance between the first semiconductor material layer 1023 and the first electrode layer 1031.

[0066] In an exemplary embodiment of the present disclosure, after forming the first electrode layer 1031, as shown in FIG. Figure 7 As shown, part of the second semiconductor material layer 1022 is selectively removed to form an isolation gap 1020b between adjacent first electrode layers 1031. Specifically, a wet chemical etching process is used to selectively etch the second semiconductor material layer 1022 from the first end of the stacked structure 102, to remove part of the second semiconductor material layer 1022 between the recessed parts of the adjacent first electrode layers 1031 and retain the first semiconductor material layer 1023, and the space left after removing part of the second semiconductor material layer 1022 forms the isolation gap 1020b.

[0067] In some embodiments, the depth of the isolation gap 1020b is less than or equal to the recessed gap 1020a', which facilitates the subsequent filling of the capacitor dielectric layer and the second electrode layer. It should be noted that the direction of "depth" here refers to the direction parallel to the surface of the substrate 102 and away from the first end.

[0068] In some embodiments, in some embodiments, a silicon etchant is used for wet chemical etching, specifically, an ammonia deionized water mixture (ADM), a potassium hydroxide solution (KOH) or a tetramethylammonium hydroxide (TMAH) is used as a silicon etchant to selectively etch the second semiconductor material layer 1022. Since the etching selectivity of boron-doped silicon to phosphorus-doped or undoped silicon can be in the range of 20:1-100:1, the second semiconductor material layer 1022 can be selectively etched while the first semiconductor material layer 1023 is retained.

[0069] In an exemplary embodiment of the present disclosure, after forming the isolation gap 1020b, as shown in FIG. Figure 8As shown, a capacitor dielectric layer 1032 and a second electrode layer 1033 are formed in sequence. The capacitor dielectric layer 1032 covers the surface of the first electrode layer 1031, and the second electrode layer 1033 covers the surface of the capacitor dielectric layer 1032. The capacitor dielectric layer 1032 and the second electrode layer 1033 also fill the recessed gap 1020a' and the isolation gap 1020b, and the second electrode layer 1033 includes a first protrusion 1033a correspondingly embedded in the recessed gap 1020a' and a second protrusion 1033c correspondingly embedded in the isolation gap 1020b, the protrusions (the first protrusion 1033a and the second protrusion 1033c) are isolated from the recessed part by the capacitor dielectric layer 1032, and a connecting part 1033b located at the first end of the stacked structure 102 and connecting each first protrusion 1033a and each second protrusion 1033c. The connecting portion 1033b extends in a direction perpendicular to the surface of the substrate 101 and connects the first protruding portion 1033a and the second protruding portion 1033c in the same column. The first electrode layer 1031 , the capacitor dielectric layer 1032 and the second electrode layer 1033 together form the capacitor structure 103 .

[0070] In some embodiments, the material of the capacitor dielectric layer 1032 includes: a combination of at least one or more of zirconium oxide (ZrO2) and aluminum oxide (Al2O3). In other embodiments, the material of the capacitor dielectric layer 1032 may also be a combination of at least one or more of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In some embodiments, the material of the second electrode layer 1033 includes: a combination of any one or more of titanium nitride (TiN), titanium (Ti), and silicon-doped titanium nitride (TiSiN).

[0071] In some embodiments, the deposition method of the capacitor dielectric layer 1032 and the second electrode layer 1033 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and electroplating sputtering.

[0072] In an exemplary embodiment of the present disclosure, after forming the capacitor dielectric layer 1032 and the second electrode layer 1033, as shown in FIG. Fig. 9As shown, the remaining multiple sacrificial material layers 1021 are removed and replaced with multiple first insulating layers 1025. Specifically, wet chemical etching is used to side-etch the remaining multiple sacrificial material layers 1021 from the second end of the stacked structure 102 to form a first insulating gap, and then the first insulating layer 1025 is filled in the first insulating gap. In an exemplary embodiment of the present disclosure, after the first insulating layer 1025 is formed, as shown in FIG. Fig.10 As shown, the remaining multiple second semiconductor material layers 1022 are removed and replaced with multiple second insulating layers 1026. Specifically, wet chemical etching is used to selectively etch the remaining multiple second semiconductor material layers 1022 from the second end of the stacked structure 102 to form a second insulating gap, and then the second insulating gap is filled with the second insulating layer 1026. The second end of the stacked structure 102 and the first end of the stacked structure 102 in the above embodiment are two opposite ends.

[0073] In some embodiments, a silicon germanium etchant is used to perform side etching on the remaining sacrificial material layer 1021. Specifically, the silicon germanium etchant may include a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and a silicon corrosion inhibitor. In some embodiments, a silicon etchant is used to perform selective etching on the remaining second semiconductor material layer 1022. Specifically, an ammonia-deionized water mixed solution (ADM), a potassium hydroxide solution (KOH), or tetramethylammonium hydroxide (TMAH) is used as the silicon etchant.

[0074] In some embodiments, the material of the first insulating layer 1025 and the second insulating layer 1026 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In some embodiments, the deposition method of the first insulating layer 1025 and the second insulating layer 1026 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), thermal oxidation growth.

[0075] In an exemplary embodiment of the present disclosure, reference Fig.10 and Fig.11 As shown, Fig.11 for Fig.10, after forming the first insulating layer 1025 and the second insulating layer 1026, the stacked structure 102 becomes a stacked structure 102', wherein the stacked structure 102' includes a plurality of memory cell structures and a plurality of insulating structures stacked alternately, and a single memory cell structure is located near a first end of the stacked structure, such as Fig.10 As shown in the partially enlarged schematic diagram of the dotted frame portion, at least one semiconductor layer (first semiconductor material layer 1023) and a capacitor structure 103 are included. The capacitor structure 103 includes a first electrode layer 1031, a capacitor dielectric layer 1032, and a second electrode layer 1033 (including at least a first protruding portion 1033a and a connecting portion 1033b). The single first electrode layer 1031 includes two recessed portions that are recessed in a direction away from the first end. As shown in the partially enlarged schematic diagram, the semiconductor layer (first semiconductor material layer 1023) is located between the two recessed portions and is electrically connected to the recessed portions. In some embodiments, the structure and shape of the two recessed portions belonging to the same first electrode layer 1031 are symmetrically arranged with respect to the semiconductor layer electrically connected thereto. In some embodiments, the two recessed portions belonging to the same first electrode layer 1031 and the semiconductor layer electrically connected thereto are staggered and stacked in a direction perpendicular to the surface of the substrate 101.

[0076] In an exemplary embodiment of the present disclosure, after forming the first insulating layer 1025 and the second insulating layer 1026, as shown in FIG. Fig.12 or Fig.13 As shown, a transistor structure is formed at the second end of the stacked structure 102 (or stacked structure 102'), and the first source and drain of the transistor structure near the first end are connected to the semiconductor layer to form a word line structure and a bit line structure, the word line structure is connected to the gate of the transistor structure, and the bit line structure is connected to the second source and drain of the transistor structure near the second end. Wherein, the "first end" and "second end" here correspond to the first end and the second end relative to each other in the stacked structure 102 (or stacked structure 102') in the aforementioned embodiment, respectively. Specifically, the portion of the remaining first semiconductor material layer 1023 that is not in contact with the recessed portion of the first electrode layer 1031 forms a transistor structure, and the two ends of the transistor structure may have a first source and drain electrode and a second source and drain electrode that are doped with N-type or P-type and a channel region located between the two source and drain electrodes, and the first source and drain electrode of the transistor structure is connected to the semiconductor layer as a whole and is electrically connected to the first electrode layer 1031 of the capacitor structure 103 through the semiconductor layer.

[0077] In some embodiments, reference Fig.12 As shown, the word line structure 105a runs through the stacked structure 102' and is connected to the channel region of the transistor structure in the same column through a gate dielectric layer (not shown) to control the on or off of the transistor structure in the column. It should be noted that the direction of the "column" here is perpendicular to the surface of the substrate 101, which can be understood as referring to Fig.11 The respective columns separated by the insulating spacer layer 1024 shown in FIG. 1 ; the bit line structure 104a is located at the second end of the stacked structure 102' and is connected to the second source and drain of the transistor structure in the same row, and is used to provide or sense the stored charge in the capacitor structure 103. Here, the direction of the "row" is parallel to the surface of the substrate 101 and perpendicular to the direction extending from the semiconductor layer, which can be understood as referring to Fig.11 The rows of first semiconductor material layers 1023 shown in FIG. 1 are parallel to the substrate surface 101 .

[0078] In some embodiments, reference Fig.13 As shown, the word line structure 105b is connected to the channel region of the transistor structure in the same row through a gate dielectric layer (not shown) to control the on or off of the transistor structure in the column. It should be noted that the direction of the "row" here is parallel to the surface of the substrate 101 and perpendicular to the direction extending in the semiconductor layer, which can be understood as referring to Fig.11 The first semiconductor material layer 1023 in each row parallel to the substrate surface 101 shown in FIG. 1 ; the bit line structure 104b runs through the stacked structure 102' and is connected to the second source and drain of the transistor structure in the same column, for providing or sensing the stored charge in the capacitor structure 103, where the direction of the "column" is perpendicular to the surface of the substrate 101, which can be understood as referring to Fig.11 The individual columns shown in FIG. 1 are separated by insulating spacer layers 1024 .

[0079] In another exemplary embodiment of the present disclosure, Fig.14 As shown, a substrate 201 is provided, and a stacked structure 202 is formed on the substrate 201, wherein a plurality of semiconductor material layers and a plurality of sacrificial material layers 2021 are alternately stacked, wherein the semiconductor material layer includes a first semiconductor material layer 2023 and a second semiconductor material layer 2022. Side etching is performed on the first end of the stacked structure 202 to remove a portion of the plurality of sacrificial material layers 2021 to form a recessed gap 2020a recessed in a direction away from the first end. The specific process method and steps can be the same as those in the aforementioned embodiment. Figures 1 to 5 The steps are the same and will not be repeated here.

[0080] In another exemplary embodiment of the present disclosure, referring to Figures 15 to 17 After forming the recessed gap 2020a, a sacrificial insulating layer 206 is filled in the recessed gap 2020a. Fig.15 In some embodiments, the sacrificial insulating layer 206 fills the recessed gap 2020a. After the sacrificial insulating layer 206 is formed, Fig.16As shown, all the second semiconductor material layers 2022 are selectively removed and replaced with a plurality of third insulating layers 2027. Specifically, all the second semiconductor material layers 2022 are selectively etched from the first end of the stacked structure 202 to form a third insulating gap, and then the third insulating gap is filled with the third insulating layer 2027. After the third insulating layer 2027 is formed to fill the third insulating gap, as shown in FIG. Fig.17 As shown, the sacrificial insulating layer 206 is selectively removed to form a new recessed gap 2020a'.

[0081] In some embodiments, the materials of the sacrificial insulating layer 206 and the third insulating layer 2027 may be any one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon nitride oxide. The material of the third insulating layer 2027 is different from that of the sacrificial insulating layer 206, so that an etching solution with a higher etching selectivity ratio can be selected to remove the sacrificial insulating layer 206. In an exemplary embodiment of the present disclosure, the material of the sacrificial insulating layer 206 is silicon oxide, and the material of the third insulating layer 2027 is silicon nitride. In some embodiments, the formation method of the sacrificial insulating layer 206 and the third insulating layer 2027 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), thermal oxidation growth, and spin-on dielectric (SOD).

[0082] In some embodiments, the entire second semiconductor material layer 2022 is selectively etched using a silicon etchant. Specifically, an ammonia-deionized water mixture (ADM), a potassium hydroxide solution (KOH), or tetramethylammonium hydroxide (TMAH) is used as the silicon etchant. It should be noted that since the etching selectivity of boron-doped silicon relative to phosphorus-doped or undoped silicon can range from 20:1 to 100:1, the second semiconductor material layer 2022 can be selectively etched while retaining the first semiconductor material layer 2023. Unlike the aforementioned embodiment, the etching time for removing the entire second semiconductor material layer 2022 is relatively long, resulting in a small amount of consumption of the first semiconductor material layer 2023 at the first end, such as Fig.16 As shown, the remaining first semiconductor material layer 2023 forms a gap at the first end of the stacked structure. In some embodiments, a diluted hydrofluoric acid solution (DHF) or a mixed solution of hydrofluoric acid and ammonium fluoride is used to selectively remove the sacrificial insulating layer 206.

[0083] In another exemplary embodiment of the present disclosure, referring to Figure 18 to Figure 19 As shown, a first electrode layer 2031, a capacitor dielectric layer 2032 and a second electrode layer 2033 are sequentially formed in the new recessed gap 2020a'. The first electrode layer 2031 covers the inner wall of the new recessed gap 2020a', and the two recessed portions of the first electrode layer 2031 in the same memory cell structure are located at the gap formed at the first end of the stacked structure by removing all the second semiconductor material layer 2022 in the aforementioned embodiment. The two recessed portions are connected as a whole at the end of the remaining first semiconductor material layer 2023 close to the first end; the first electrode layer 2031 in the adjacent memory cell structure is disconnected at the end of the third insulating layer 2027 close to the first end. The capacitor dielectric layer 2032 covers the surface of the first electrode layer 2031, and the second electrode layer 2033 covers the surface of the capacitor dielectric layer 2032, wherein the second electrode layer 2033 at least includes protrusions 2032a respectively embedded in the recesses of the first electrode layer 2031, the protrusions 2032a are separated from the recesses by the capacitor dielectric layer 2032, and a connecting portion 2032b located at the first end of the stacked structure 202 and connecting the protrusions 2032a, and the connecting portion 2032b extends in a direction perpendicular to the surface of the substrate 202. The first electrode layer 2031, the capacitor dielectric layer 2032 and the second electrode layer 2033 together constitute the capacitor structure 203.

[0084] In some embodiments, before forming the first electrode layer 2031, a sacrificial metal layer is formed in the new recessed gap 2020a' to cover the surface of the first semiconductor material layer 2023 exposed by the new recessed gap 2020a', and then annealing is performed to form a metal silicide at the contact interface between the sacrificial metal layer and the first semiconductor material layer 2023, and then the unreacted sacrificial metal layer is removed to form a metal semiconductor contact layer (not shown) whose material is metal silicide, which is used to at least reduce the subsequent contact resistance between the first semiconductor material layer 2023 and the first electrode layer 2031.

[0085] In some embodiments, the materials and deposition processes of the first electrode layer 2031, the capacitor dielectric layer 2032 and the second electrode layer 2033 are the same as the optional ranges for preparing the first electrode layer 1031, the capacitor dielectric layer 1032 and the second electrode layer 1033 in the aforementioned embodiments, and are not repeated here.

[0086] In another exemplary embodiment of the present disclosure, after forming the capacitor structure 203, as shown in FIG. Fig. 20As shown, the remaining multiple sacrificial material layers 2021 are removed and replaced with multiple fourth insulating layers 2025. The third insulating layer 2027 and the fourth insulating layer 2025 together constitute an insulating structure. Specifically, wet chemical etching is used to selectively etch the remaining multiple sacrificial material layers 2021 from the second end of the stacked structure 202 to form a fourth insulating gap, and then the fourth insulating gap is filled with the fourth insulating layer 2025. The second end of the stacked structure 202 and the first end of the stacked structure 202 in the aforementioned embodiment are two opposite ends.

[0087] In some embodiments, a silicon germanium etchant is used to selectively etch the remaining sacrificial material layer 2021 . Specifically, the silicon germanium etchant may include a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) and a silicon corrosion inhibitor.

[0088] In some embodiments, the material of the fourth insulating layer 2025 can be any one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon nitride. In some embodiments, the fourth insulating layer 2025 can be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), thermal oxidation growth, spin-on dielectric (SOD).

[0089] In another exemplary embodiment of the present disclosure, referring to Fig. 20 and Fig.21 As shown, Fig.21 for Fig. 20 , after forming the fourth insulating layer 2025, the stacked structure 202 becomes a stacked structure 202', wherein the stacked structure 202' includes a plurality of memory cell structures and a plurality of insulating structures stacked alternately, and a single memory cell structure is located near a first end of the stacked structure, such as Fig. 20As shown in the partially enlarged schematic diagram of the dotted frame portion, at least one semiconductor layer (first semiconductor material layer 2023) and a capacitor structure 203 are included. The capacitor structure 203 includes a first electrode layer 2031, a capacitor dielectric layer 2032, and a second electrode layer 2033 (including at least a first protruding portion 2033a and a connecting portion 2033b). The single first electrode layer 2031 includes two recessed portions that are recessed in a direction away from the first end. As shown in the partially enlarged schematic diagram, the semiconductor layer (first semiconductor material layer 2023) is located between the two recessed portions and is electrically connected to the recessed portions. In some embodiments, the structure and shape of the two recessed portions belonging to the same first electrode layer 2031 are symmetrically arranged with respect to the semiconductor layer electrically connected thereto. In some embodiments, the two recessed portions belonging to the same first electrode layer 2031 and the semiconductor layer electrically connected thereto are staggered and stacked in a direction perpendicular to the surface of the substrate 201.

[0090] In another exemplary embodiment of the present disclosure, after forming the fourth insulating layer 2025, as shown in FIG. Fig. 22 or Fig.23 As shown, a transistor structure is formed at the second end of the stacked structure 202 (or stacked structure 202'), and the first source and drain of the transistor structure near the first end are connected to the semiconductor layer to form a word line structure and a bit line structure, the word line structure is connected to the gate of the transistor structure, and the bit line structure is connected to the second source and drain of the transistor structure near the second end. Wherein, the "first end" and "second end" here correspond to the first end and the second end relative to each other in the stacked structure 202 (or stacked structure 202') in the aforementioned embodiment, respectively. Specifically, the portion of the remaining first semiconductor material layer 2023 that is not in contact with the recessed portion of the first electrode layer 2031 forms a transistor structure, and the two ends of the transistor structure may have a first source and drain electrode and a second source and drain electrode doped with N-type or P-type and a channel region located between the two source and drain electrodes, and the first source and drain electrode of the transistor structure is connected to the semiconductor layer as a whole and is electrically connected to the first electrode layer 2031 of the capacitor structure 203 through the semiconductor layer.

[0091] In some embodiments, reference Fig. 22 As shown, the word line structure 205a runs through the stacked structure 202' and is connected to the channel region of the transistor structure in the same column through a gate dielectric layer (not shown) to control the on or off of the transistor structure in the column. It should be noted that the direction of the "column" here is perpendicular to the surface of the substrate 201, which can be understood as referring to Fig.21 The columns shown in the figure are separated by the insulating spacer layer 2024; the bit line structure 204a is located at the second end of the stacked structure 202' and is connected to the second source and drain of the transistor structure in the same row, and is used to provide or sense the stored charge in the capacitor structure 203. Here, the direction of the "row" is parallel to the surface of the substrate 201 and perpendicular to the direction extending from the semiconductor layer, which can be understood as referring to Fig.21 The rows of first semiconductor material layers 2023 shown in FIG. 2 are parallel to the substrate surface 201 .

[0092] In some embodiments, reference Fig.23 As shown, the word line structure 205b is connected to the channel region of the transistor structure in the same row through a gate dielectric layer (not shown) to control the on or off of the transistor structure in the column. It should be noted that the direction of the "row" here is parallel to the surface of the substrate 201 and perpendicular to the direction extending in the semiconductor layer, which can be understood as referring to Fig.21 The first semiconductor material layer 2023 in each row is parallel to the substrate surface 201 shown in the figure; the bit line structure 204b runs through the stacked structure 202' and is connected to the second source and drain of the transistor structure in the same column, for providing or sensing the storage charge in the capacitor structure 203. Here, the direction of the "column" is the direction perpendicular to the surface of the substrate 201, which can be understood as referring to Fig.21 The individual columns shown in FIG. 2 are separated by insulating spacer layers 2024 .

[0093] The semiconductor structure and the method for manufacturing the semiconductor structure provided by the present disclosure, in terms of structure, compared with the capacitor structure with only a single depression formed in the gap of the stacked structure with a smaller size and a deeper extension in the related art, in the stacked structure in the semiconductor structure provided by the present disclosure, the capacitor structure in the single storage unit structure has double depressions, and the thickness of each depression is relatively large, which greatly improves the capacitor storage capacity and the storage performance of the semiconductor structure. The double depressions are electrically connected to a semiconductor layer as an interlayer, and the double depressions are symmetrically arranged about the semiconductor layer, which further improves the stability of the stacked structure; in terms of manufacturing method, compared with the related art, the method for manufacturing the semiconductor structure provided by the present disclosure forms a depression gap with a larger thickness, which can provide a better coverage effect for the first electrode layer deposited in the depression gap and a better filling effect for the subsequent capacitor dielectric layer and the second electrode layer. In addition, the inner wall of the depression gap is relatively flat and smooth, which further improves the better coverage effect of the first electrode layer deposited in the depression gap, and the performance of the capacitor structure formed subsequently is greatly improved, and the stability and reliability of the stacked structure in the manufacturing process are also improved.

[0094] It should be noted that the semiconductor structure in the embodiment of the present disclosure can be used to manufacture 3D DRAM devices, and can also be used to manufacture other 3D devices that require metal-semiconductor contact in a stacked structure, and no excessive restrictions are made here.

[0095] The various semiconductor structures shown in this specific embodiment can be used for electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM).

[0096] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A stacking structure, located on the substrate, comprising a plurality of memory cell structures and a plurality of insulating structures stacked alternately; A single storage unit structure comprises at least a semiconductor layer and a capacitor structure at a first end close to the stack structure, wherein the capacitor structure comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer, and the first electrode layer is electrically connected to the semiconductor layer; Wherein, a single first electrode layer includes two recessed portions recessed in a direction away from the first end, and the semiconductor layer is located between the two recessed portions of the first electrode layer.

2. The semiconductor structure according to claim 1, characterized in that: In the same memory cell structure, the two recessed portions of the first electrode layer are electrically connected through the semiconductor layer.

3. The semiconductor structure according to claim 1, characterized in that: In the same memory cell structure, the two recessed portions of the first electrode layer are connected at an end of the semiconductor layer close to the first end.

4. The semiconductor structure according to claim 1, characterized in that In the same memory cell structure, the structures and shapes of the two recessed portions of the first electrode layer are symmetrically arranged with respect to the semiconductor layer.

5. The semiconductor structure according to claim 4, characterized in that: The two recessed portions of the first electrode layer and the semiconductor layer are stacked alternately in a direction perpendicular to the substrate surface.

6. The semiconductor structure according to claim 1, characterized in that The second electrode layer includes a plurality of protrusions and connecting portions; Each of the protruding parts is respectively embedded in each of the recessed parts, and the recessed parts and the protruding parts are separated by the capacitor dielectric layer; The connecting portion extends in a direction perpendicular to the surface of the substrate and is electrically connected to each of the protruding portions at the first end.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: At the second end of the stacked structure, the memory cell structure further includes a transistor structure, a first source and drain of the transistor structure close to the first end is connected to the semiconductor layer, wherein the second end is arranged opposite to the first end.

8. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further includes: a word line structure and a bit line structure, wherein the word line structure is connected to the gate of the transistor structure, and the bit line structure is connected to the second source and drain of the transistor structure close to the second end.

9. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure consisting of a plurality of semiconductor material layers and a plurality of sacrificial material layers alternately stacked on the substrate; Performing side etching from the first end of the stacked structure to remove part of the plurality of sacrificial material layers to form a recessed gap recessed in a direction away from the first end, and the remaining semiconductor material layer is located between two adjacent recessed gaps to serve as a semiconductor layer; forming a capacitor structure in the recessed gap, including a first electrode layer, a capacitor dielectric layer, and a second electrode layer formed in sequence; removing the remaining plurality of sacrificial material layers to form a plurality of insulating structures to isolate adjacent semiconductor layers; Wherein, a single first electrode layer includes two recessed portions recessed in a direction away from the first end, and the semiconductor layer is located between the two recessed portions of the first electrode layer.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: A stacked structure consisting of a plurality of semiconductor material layers and a plurality of sacrificial material layers alternately stacked is formed on the substrate, comprising: Through an epitaxial growth process, a staggered stack of multiple first semiconductor material layers, multiple sacrificial material layers, and multiple second semiconductor material layers are formed on the substrate, wherein a single sacrificial material layer is located between adjacent single first semiconductor material layers and single second semiconductor material layers.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: After forming the first electrode layer and before forming the second electrode layer, the manufacturing method also includes: selectively removing a portion of the second semiconductor material layer to form an isolation gap between adjacent first electrode layers, the second electrode layer including a first protrusion embedded in the recess and a second protrusion embedded in the isolation gap.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: Removing the remaining plurality of sacrificial material layers to form an insulating structure to isolate adjacent semiconductor layers comprises: removing the remaining multiple sacrificial material layers and replacing them with multiple first insulating layers; removing the remaining plurality of second semiconductor material layers and replacing them with a plurality of second insulating layers; The plurality of first insulating layers and the plurality of second insulating layers together constitute the plurality of insulating structures.

13. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: After forming the recessed gap and before forming the first electrode layer, the manufacturing method further includes: selectively removing all of the plurality of second semiconductor material layers and replacing them with a plurality of third insulating layers.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: Removing the remaining plurality of sacrificial material layers to form an insulating structure to isolate adjacent semiconductor layers comprises: removing the remaining multiple sacrificial material layers and replacing them with multiple fourth insulating layers; The plurality of third insulating layers and the plurality of fourth insulating layers together constitute the plurality of insulating structures.

15. The method for manufacturing a semiconductor structure according to any one of claims 9 to 14, characterized in that: The method for manufacturing the semiconductor structure further includes: A transistor structure is formed at a second end of the stacked structure, wherein a first source and drain of the transistor structure close to the first end is connected to the semiconductor layer, wherein the second end is arranged opposite to the first end; A word line structure and a bit line structure are formed, wherein the word line structure is connected to the gate of the transistor structure, and the bit line structure is connected to the second source and drain of the transistor structure close to the second end.

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