Level shift circuit

Abstract

The present invention improves the speed of a level shifter using a positive DC power supply and a negative DC power supply. This level shifter circuit is equipped with: a level shifter unit for level shifting a signal from a first potential to a second potential and outputting the signal via an output terminal; a current path setting unit for setting, as the output terminal, a second current path separated from the first current path from the level shifter unit to the output terminal; and a switching unit for switching between the first current path and the second current path. The second potential may be provided with a positive DC potential and a negative DC potential. The second current path may be a discharge path for discharging the charge via the output terminal, or a charge path for charging the charge via the output terminal.

Description

Technical Field

[0001] The present technology relates to a level shift circuit. In particular, the present technology relates to a level shift circuit using a positive DC voltage and a negative DC voltage. Background Art

[0002] In an electronic circuit, a level shift circuit can be used to perform level shifting of a signal. As a level shift circuit, for example, a technology has been proposed in which, in a case where a signal undergoes level shifting from a first potential to a second potential, a power supply of an intermediate potential between the first potential and the second potential is supplied, and the signal is once converted to a signal of the intermediate potential and the conversion is repeated in a state where the potential difference is not too large (see, for example, Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 9-148913 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] However, in the above-mentioned conventional technology, the load is charged and discharged only by the power supply current, and the impedance of the power supply and the level shift circuit is greatly limited in increasing the charging and discharging speed of the load.

[0008] The present technology has been made in view of such circumstances, and an object thereof is to increase the level shift speed using positive DC voltage and negative DC voltage.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and the first aspect of the present technology is a level shift circuit including: a level shift unit that level-shifts a signal from a first potential to a second potential and outputs the signal via an output terminal; a current path setting unit that sets a second current path in the output terminal that is separate from the first current path from the level shift unit to the output terminal; and an opening / closing unit that opens and closes the first current path and the second current path. This brings about an effect of reducing the limitation of the impedance of charging and discharging to the load at the time of level shifting.

[0011] In addition, in the first aspect, the current path setting unit can set the second current path to the output terminal so that the potential of the output terminal approaches the second potential when the output terminal is disconnected from the second potential. This brings about an effect of reducing the charge amount of charging and discharging of the load when the output terminal is switched to the second potential.

[0012] In addition, in the first aspect, the second current path may include at least one of a discharge path for releasing charge via the output terminal and a charge path for charging charge via the output terminal. This brings about the effect of ensuring a second current path for charging and discharging the load separately from the first current path when the output terminal is switched to the second potential.

[0013] In addition, in the first aspect, the second potential may include a positive DC potential and a negative DC potential, and the level shift unit may selectively convert the first potential into a positive DC potential or a negative DC potential, and output the result via the output terminal. This brings about the effect that the signal of the first potential is level-shifted to a positive DC potential or a negative DC potential.

[0014] In addition, in the first aspect, the level shift unit may include: a first switch element connecting the positive DC potential to the output terminal; and a second switch element connecting the negative DC potential to the output terminal. This brings about the effect that the signal of the first potential is selectively converted into a positive DC potential or a negative DC potential.

[0015] Furthermore, in the first aspect, the current path setting unit may include: a third switch element connecting the output terminal to the third potential. This brings about an effect of ensuring a current path for charging and discharging the load.

[0016] Furthermore, in the first aspect, the third potential may be a ground potential, a power supply potential, or an intermediate potential between a positive DC potential and a negative DC potential. This brings about the effect of charging and discharging the load without inserting a level shift unit.

[0017] In addition, in the first aspect, the opening / closing unit may connect the output terminal to the positive DC potential, disconnect the output terminal from the positive DC potential, and then connect the output terminal to the ground potential, and disconnect the output terminal from the ground potential, and then connect the output terminal to the negative DC potential. This brings about an effect that the load is discharged before the potential of the output terminal is switched from the positive DC potential to the negative DC potential.

[0018] In addition, in the first aspect, the opening / closing unit may connect the output terminal to the positive DC potential, disconnect the output terminal from the positive DC potential, and then connect the output terminal to the intermediate potential, and disconnect the output terminal from the intermediate potential, and then connect the output terminal to the negative DC potential. This brings about an effect that the load is discharged to approach the negative DC potential before the potential of the output terminal is switched from the positive DC potential to the negative DC potential.

[0019] In addition, in the first aspect, the opening / closing unit may connect the output terminal to the negative DC potential, disconnect the output terminal from the negative DC potential, and then connect the output terminal to the power supply potential, and disconnect the output terminal from the power supply potential and connect the output terminal to the positive DC potential. This has the effect of charging the load before the potential of the output terminal is switched from the negative DC potential to the positive DC potential.

[0020] In addition, in the first aspect, the opening / closing unit may connect the output terminal to the negative DC potential, disconnect the output terminal from the negative DC potential, then connect the output terminal to the intermediate potential, disconnect the output terminal from the intermediate potential, and then connect the output terminal to the positive DC potential. This brings about an effect that the load is charged to approach the positive DC potential before the potential of the output terminal is switched from the negative DC potential to the positive DC potential.

[0021] Furthermore, in the first aspect, the current path setting unit may include a fourth switch element connecting the output terminal to the fourth potential. This brings about an effect that the current path for the discharge load and the current path for the charge load are separately ensured.

[0022] In addition, in the first aspect, the third potential may be a ground potential, and the fourth potential may be a power supply potential. This brings about an effect of charging and discharging the load via a current path in which the level shift unit is not inserted.

[0023] In addition, in the first aspect, the third potential is a positive intermediate potential between the positive DC potential and the negative DC potential, and the fourth potential is a negative intermediate potential between the positive DC potential and the negative DC potential. This brings about an effect that the load is charged and discharged via a current path without a level shift unit inserted to approach a positive DC potential or a negative DC potential.

[0024] In addition, in the first aspect, the level shift circuit may further include a delay circuit that delays connection of the second potential to the output terminal when the signal is level-shifted from the first potential to the second potential. This brings about the effect of ensuring time for charging and discharging the load before the signal is level-shifted from the first potential to the second potential.

[0025] In the first aspect, the opening / closing unit may open the first current path and close the second current path while delaying the connection of the second potential to the output terminal. This has the effect of charging and discharging the load before the signal level shifts from the first potential to the second potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram showing a functional configuration example of the level shift circuit according to the first embodiment.

[0027] Figure 2 : is a diagram showing an example of a load of the level shift circuit according to the first embodiment.

[0028] Figure 3 : is a diagram showing a circuit configuration example of the level shift circuit according to the first embodiment.

[0029] Figure 4 : is a timing chart showing a first operation example of the level shift circuit according to the first embodiment.

[0030] Figure 5 is a diagram showing a current path according to a first example of the level shift operation according to the first embodiment.

[0031] Figure 6 is a diagram showing a current path according to a first example of the level shift operation according to the first embodiment.

[0032] Figure 7 is a diagram showing a current path based on a first example of the level shift operation according to the first embodiment.

[0033] Figure 8 : is a diagram showing a waveform when the gate voltage drops based on the level shift operation according to the first embodiment.

[0034] Fig. 9 2 is a timing chart showing a second operation example of the level shift circuit according to the first embodiment.

[0035] Fig.10 is a diagram showing a current path based on a second example of the level shift operation according to the first embodiment.

[0036] Fig.11 is a diagram showing a current path based on a second example of the level shift operation according to the first embodiment.

[0037] Fig.12 is a diagram showing a current path based on a second example of the level shift operation according to the first embodiment.

[0038] Fig.13 : is a diagram showing a waveform at the time of rising of the gate voltage based on the level shift operation according to the first embodiment.

[0039] Fig.14 : is a diagram showing a circuit configuration example of the level shift circuit according to the first embodiment.

[0040] Fig.15 : is a diagram showing the relationship between the discharge time and the switching time to the output of the level shift circuit according to the first embodiment.

[0041] Fig.16 : is a diagram showing a circuit configuration example of a level shift circuit according to the second embodiment.

[0042] Fig.17 : is a diagram showing a circuit configuration example of a level shift circuit according to the third embodiment.

[0043] Fig.18 : is a diagram showing a circuit configuration example of a level shift circuit according to a fourth embodiment. DETAILED DESCRIPTION

[0044] A mode for carrying out the present technology (hereinafter, referred to as an embodiment) will be described below. The description will be given in the following order.

[0045] 1. First Embodiment (Example of Providing a Charging / Discharging Path at Ground Potential)

[0046] 2. Second Embodiment (Example of Providing a Charging / Discharging Path at Power Supply Potential)

[0047] 3. Third Embodiment (Example of Providing Charging / Discharging Paths at Ground Potential and Power Supply Potential)

[0048] 4. Fourth Embodiment (Example of Providing a Charging / Discharging Path at an Intermediate Potential Between a Positive DC Potential and a Negative DC Potential)

[0049] <1. First Embodiment>

[0050] Figure 1 is a block diagram showing a functional configuration example of the level shift circuit according to the first embodiment.

[0051] In the drawings, the level shift circuit 100 sets a second current path separate from the first current path for level shifting of a signal, performs charging and discharging via the second current path, and then performs level shifting of the signal via the first current path. Note that in this specification, both charging and discharging are not necessarily performed, and only charging or only discharging may be performed. The level shift circuit 100 includes a level shift unit 101, an input / output opening / closing unit 102, and a charging / discharging unit 103.

[0052] The level shift unit 101 shifts the digital signal VC from a first potential level to a second potential and outputs the digital signal VC. The second potential may include a positive DC potential VIP and a negative DC potential VIN. At this time, the level shift unit 101 may selectively convert the digital signal VC of the first potential into a positive DC potential VIP or a negative DC potential VIN and output the signal.

[0053] The input / output opening / closing unit 102 opens / closes the path between the output of the level shift unit 101 and the input of the charging / discharging unit 103 based on the control signals Φ1 and Φ2. The control signal Φ1 controls the level shift to the positive DC potential VIP, and the control signal Φ2 controls the level shift to the negative DC potential VIN. At this time, when the path between the output of the level shift unit 101 and the input of the charging / discharging unit 103 is in an open state, the output OUT of the level shift unit 101 is disconnected from the positive DC potential VIP and the negative DC potential VIN, and the charging / discharging current flows to the output OUT via the charging / discharging unit 103. When the path between the output of the level shift unit 101 and the input of the charging / discharging unit 103 is in a closed state, the charging / discharging current flowing to the output OUT via the charging / discharging unit 103 is cut off, and the output OUT is selectively connected to the positive DC potential VIP or the negative DC potential VIN.

[0054] Based on the control signal Φ3, the charge / discharge unit 103 sets a second current path separate from the first current path for level shifting of the signal. When the output terminal of the level shift circuit 100 is disconnected from the two potentials, the charge / discharge unit 103 can set the second current path to the output terminal so that the potential of the output terminal is close to the second potential. The second current path can be a discharge path for discharging the charge via the output terminal of the level shift circuit 100, or it can be a charging path for charging the charge via the output terminal of the level shift circuit 100. At this time, the charge / discharge unit 103 can connect the output terminal of the level shift circuit 100 to a third potential. The third potential can be a ground potential, a power supply potential, or an intermediate potential between a positive DC potential and a negative DC potential. When the output OUT of the level shift unit 101 is switched from the positive DC potential VIP to the negative DC potential VIN, the charge / discharge unit 103 releases the charge accumulated in the load providing the output OUT. When the output OUT of the level shift unit 101 is switched from the negative DC potential VIN to the positive DC potential VIP, the charge / discharge unit 103 charges the load provided with the output OUT.

[0055] It should be noted that the input / output opening / closing unit 102 is an example of an opening / closing unit that opens and closes the first current path described in the claims. The charging / discharging unit 103 is an example of a current path setting unit described in the claims and an opening / closing unit that opens / closes the second current path.

[0056] Figure 2 : is a diagram showing an example of a load of the level shift circuit according to the first embodiment.

[0057] In the drawing, for example, an NMOS transistor 110 is provided as a load of the level shift circuit 100. The output terminal TO of the level shift circuit 100 is connected to the gate of the NMOS transistor 110. At this time, the level shift circuit 100 controls the gate voltage of the NMOS transistor 110 based on the output OUT from the output terminal TO.

[0058] Figure 3 : is a diagram showing a circuit configuration example of the level shift circuit according to the first embodiment.

[0059] In the drawing, the level shift circuit 100 includes switch elements 201 to 203 and a control circuit 205. Note that each of the switch elements 201 to 203 may be a MOS transistor.

[0060] The switch element 201 connects the positive DC potential VIP to the output terminal TO based on the control signal Φ1. The switch element 202 connects the negative DC potential VIN to the output terminal TO based on the control signal Φ2. The switch element 203 connects the output terminal TO to the ground potential GND based on the control signal Φ3. The control circuit 205 generates control signals Φ1 to Φ3 based on the digital signal VC, and outputs the control signals Φ1 to Φ3 to the switch elements 201 to 203, respectively.

[0061] Here, it is assumed that when the output OUT is at the negative DC potential VIN, the control circuit 205 converts the digital signal VC level to the positive DC potential VIP. At this time, the control circuit 205 turns on the switch element 201 with a delay according to the input timing of the digital signal VC, and connects the positive DC potential VIP to the output terminal TO. Here, the control circuit 205 turns on the switch element 203 before turning on the switch element 201, connects the output terminal TO to the ground potential GND, and charges via the output terminal TO.

[0062] On the other hand, it is assumed that when the output OUT is at the positive DC potential VIP, the control circuit 205 converts the digital signal VC level to the negative DC potential VIN. At this time, the control circuit 205 turns on the switch element 202 with a delay according to the input timing of the digital signal VC, and connects the negative DC potential VIN to the output terminal TO. Here, the control circuit 205 turns on the switch element 203 before turning on the switch element 202, connects the output terminal TO to the ground potential GND, and discharges through the output terminal TO.

[0063] Note that the switch elements 201 and 202 are examples of a level shift unit and an opening / closing unit that opens / closes a first current path described in the claims. The switch element 203 is an example of a current path setting unit and an opening / closing unit that opens / closes a second current path described in the claims.

[0064] Figure 4 is a timing chart showing a first operation example of the level shift circuit according to the first embodiment, and Figures 5 to 7 is a diagram showing a current path based on a first example of the level shift operation according to the first embodiment. Figures 5 to 7 , a capacitive load 206 connected to the output terminal TO is equivalently shown. For example, the capacitive load 206 is Figure 2 The gate capacitance of the NMOS transistor 110 in FIG.

[0065] exist Figure 4 In the case where the control signal Φ1 is at a high level, the switch element 201 is turned on. Figure 5 As shown, the output terminal TO is connected to the positive DC potential VIP, and the current IN1 flows from the positive DC potential VIP to the capacitive load 206. Then, electric charges are accumulated in the capacitive load 206, and the output OUT is set to the positive DC potential VIP.

[0066] Assume that when the output OUT is set to the positive DC potential VIP, the digital signal VC has changed from a low level to a high level. At this time, the control circuit 205 changes the control signal Φ1 from a high level to a low level to turn off the switch element 201, and changes the control signal Φ3 from a low level to a high level to turn on the switch element 203. When the switch element 203 is turned on, Figure 6 As shown, the output terminal TO is connected to the ground potential GND, and the current IN2 flows from the capacitive load 206 to the ground potential GND. Then, the charge accumulated in the capacitive load 206 is discharged to the ground potential GND, so that the potential of the output terminal TO decreases.

[0067] Next, after the delay time TD has elapsed, the control circuit 205 changes the control signal Φ3 from a high level to a low level to turn off the switch element 203, and changes the control signal Φ2 from a low level to a high level to turn on the switch element 202. Figure 7 As shown, when the switch element 202 is turned on, the output terminal TO is connected to the negative DC potential VIN, and the current IN3 flows from the capacitive load 206 to the negative DC potential VIN. Then, the charge accumulated in the capacitive load 206 is discharged to the negative DC potential VIN, so that the potential of the output terminal TO is reduced. Then, after the setting time TC, the potential of the output terminal TO is set to the negative DC potential VIN. At this time, the switching time T for switching the potential of the output OUT from the positive DC potential VIP to the negative DC potential VIN can be given as TC+TD.

[0068] Figure 8is a diagram showing a waveform when the gate voltage drops based on the level shift operation according to the first embodiment. Note that in the accompanying drawings, a waveform WN1 of the output OUT is indicated by a solid line, where when the potential of the output OUT is switched from the positive DC potential VIP to the negative DC potential VIN, the charge accumulated in the capacitive load 206 is discharged to the ground potential GND. A waveform WN2 of the output OUT is indicated by a dotted line, where when the potential of the output OUT is switched from the positive DC potential VIP to the negative DC potential VIN, the charge accumulated in the capacitive load 206 is not discharged to the ground potential GND.

[0069] In the figure, it is assumed that when the potential of the output OUT is switched from the positive DC potential VIP to the negative DC potential VIN, the charge accumulated in the capacitive load 206 is not discharged to the ground potential GND. Figure 1 The level shift unit 101 in the circuit is discharged, and a switching time T′ for switching the potential of the output OUT from the positive DC potential VIP to the negative DC potential VIN is limited by the impedance of the level shift unit 101 .

[0070] On the other hand, it is assumed that when the potential of the output OUT is switched from the positive DC potential VIP to the negative DC potential VIN, the charge accumulated in the capacitive load 206 is discharged to the ground potential GND. At this time, until the delay time TD elapses, the charge accumulated in the capacitive load 206 is discharged without passing through Figure 1 . Therefore, until the delay time TD elapses, there is no limit to the impedance of the level shift unit 101 at the time of discharge of the charge accumulated in the capacitive load 206. Therefore, when the potential of the output OUT is switched from the positive DC potential VIP to the negative DC potential VIN, the switching time T in which the discharge to the ground potential GND exists is shorter than the switching time T' in which the discharge to the ground potential GND does not exist, and the level shift can be accelerated.

[0071] Fig. 9 is a timing chart showing a second operation example of the level shift circuit according to the first embodiment, and Figures 10 to 12 is a diagram showing a current path based on a first example of the level shift operation according to the first embodiment.

[0072] exist Fig. 9 In the case where the control signal Φ2 is at a high level, the switch element 202 is turned on. Fig.10 As shown, the output terminal TO is connected to the negative DC potential VIN, and the current LP1 flows to the negative DC potential VIN from the capacitive load 206. Then, the charge is discharged from the capacitive load 206, and the output OUT is set to the negative DC potential VIN.

[0073] Assume that when the output OUT is set to the negative DC potential VIN, the digital signal VC has changed from a low level to a high level. At this time, the control circuit 205 changes the control signal Φ2 from a high level to a low level to turn off the switch element 202, and changes the control signal Φ3 from a low level to a high level to turn on the switch element 203. When the switch element 203 is turned on, Fig.11 As shown, the output terminal TO is connected to the ground potential GND, and the current LP2 flows from the ground potential GND to the capacitive load 206. Then, electric charges are charged from the ground potential GND to the capacitive load 206, so that the potential of the output terminal TO increases.

[0074] Next, after the delay time TD has passed, the control circuit 205 changes the control signal Φ3 from a high level to a low level to turn off the switch element 203, and changes the control signal Φ1 from a low level to a high level to turn on the switch element 201. When the switch element 201 is turned on, Fig.12 As shown, the output terminal TO is connected to the positive DC potential VIP, and the current LP3 flows from the positive DC potential VIP to the capacitive load 206. Then, the capacitive load 206 is charged from the positive DC potential VIP, so that the potential of the output terminal TO increases. Then, after the setting time TC, the potential of the output terminal TO is set to the positive DC potential VIP. At this time, the switching time T for switching the potential of the output OUT from the negative DC potential VIN to the positive DC potential VIP can be given as TC+TD.

[0075] Fig.13 1 is a diagram showing a waveform at the time of the rise of the gate voltage in the level shift operation based on the first embodiment. Note that in the accompanying drawings, the waveform WP1 of the output OUT is indicated by a solid line, in which the capacitive load 206 is charged from the ground potential GND when the potential of the output OUT is switched from the negative DC potential VIN to the positive DC potential VIP. The waveform WP2 of the output OUT in which the capacitive load 206 is not charged from the ground potential GND when the potential of the output OUT is switched from the negative DC potential VIN to the positive DC potential VIP is indicated by a dotted line.

[0076] In the figure, it is assumed that when the potential of the output OUT is switched from the negative DC potential VIN to the positive DC potential VIP, the capacitive load 206 is not charged from the ground potential GND. Figure 1 The level shift unit 101 in the circuit is charged, and a switching time T′ for switching the potential of the output OUT from the negative DC potential VIN to the positive DC potential VIP is limited by the impedance of the level shift unit 101 .

[0077] On the other hand, it is assumed that when the potential of the output OUT is switched from the negative DC potential VIN to the positive DC potential VIP, the capacitive load 206 is charged from the ground potential GND. At this time, until the delay time TD has passed, the capacitive load 206 is charged without Figure 1 . Therefore, until the delay time TD elapses, there is no limitation due to the impedance of the level shift unit 101 in the charging of the capacitive load 206. Therefore, when the potential of the output OUT is switched from the negative DC potential VIN to the positive DC potential VIP, the switching time T in which there is charging from the ground potential GND is shorter than the switching time T' in which there is no charging from the ground potential GND, and the level shift can be accelerated.

[0078] Fig.14 : is a diagram showing a circuit configuration example of a level shift circuit according to the first embodiment.

[0079] In the drawings, the switch element 201 includes a PMOS transistor 281. The switch element 202 includes an NMOS transistor 282. The switch element 203 includes an NMOS transistor 283. The control circuit 205 includes a delay circuit 211, an XOR circuit 212, an OR circuit 213, an AND circuit 217, and inverters 214 to 216, 218, and 219. In addition, the control circuit 205 also includes PMOS transistors 221, 222, 241, 242, 261, and 262 and NMOS transistors 231, 232, 251, 252, 271, and 272.

[0080] The PMOS transistor 221 and the NMOS transistor 231 are connected in series with each other. The PMOS transistor 222 and the NMOS transistor 232 are connected in series with each other. The PMOS transistor 241 and the NMOS transistor 251 are connected in series with each other. The PMOS transistor 242 and the NMOS transistor 252 are connected in series with each other. The PMOS transistor 261 and the NMOS transistor 271 are connected in series with each other. The PMOS transistor 262 and the NMOS transistor 272 are connected in series with each other. The PMOS transistor 281 and the NMOS transistor 282 are connected in series with each other.

[0081] The power supply terminal TVD is connected to the power supply of the XOR circuit 212, the power supply of the OR circuit 213, the power supply of the AND circuit 217, the power supplies of the inverters 214 to 216, 218 and 219, and the sources of the PMOS transistors 221 and 222. The power supply voltage VDD is supplied to the power supply terminal TVD.

[0082] The signal input terminal TVC is connected to an input terminal of the delay circuit 211, one input terminal of the XOR circuit 212, one input terminal of the OR circuit 213, and one input terminal of the AND circuit 217. A digital signal VC is input to the signal input terminal TVC.

[0083] The positive DC terminal TIP is connected to the source of each of the PMOS transistors 241, 242, 261, and 281. A positive DC potential VIP is supplied to the positive DC terminal TIP.

[0084] The negative DC terminal TIN is connected to the source of each of the NMOS transistors 231, 232, 272, and 282. A negative DC potential VIN is supplied to the negative DC terminal TIN.

[0085] The output of the delay circuit 211 is connected to the other input of the XOR circuit 212. The output terminal of the XOR circuit 212 is connected to the other input terminal of the OR circuit 213, to the input terminal of the inverter 214, and to the gate of the NMOS transistor 283. The output terminal of the inverter 214 is connected to the other input terminal of the AND circuit 217. The output of the OR circuit 213 is connected to the input of the inverter 215, and the output of the inverter 215 is connected to the input of the inverter 216 and to the gate of the PMOS transistor 222. The output of the AND circuit 217 is connected to the input of the inverter 218, and the output of the inverter 218 is connected to the input of the inverter 219 and the gate of the NMOS transistor 252.

[0086] The gate of the PMOS transistor 241 is connected to the drain of the PMOS transistor 242, and the gate of the PMOS transistor 242 is connected to the drain of the PMOS transistor 241. In addition, the drain of the PMOS transistor 242 is connected to the gate of the PMOS transistor 261 and the gate of the NMOS transistor 271. In addition, the drain of the NMOS transistor 271 is connected to the gate of the PMOS transistor 281, and the source of the NMOS transistor 271 is connected to the source of the PMOS transistor 262. The sources of the NMOS transistors 251 and 252 are connected to the source of the NMOS transistor 283. The source of the NMOS transistor 283 is connected to the ground potential GND, and the drain of the NMOS transistor 283 is connected to the output terminal TO.

[0087] The gate of the NMOS transistor 231 is connected to the drain of the NMOS transistor 232, and the gate of the NMOS transistor 232 is connected to the drain of the NMOS transistor 231. In addition, the drain of the NMOS transistor 232 is connected to the gate of the PMOS transistor 262 and the gate of the NMOS transistor 272. The drain of the NMOS transistor 272 is connected to the gate of the NMOS transistor 282.

[0088] Here, the control circuit 205 generates control signals Φ1 to Φ3 based on the digital signal VC. Then, the control circuit 205 outputs the control signal Φ1 to the gate of the PMOS transistor 281, outputs the control signal Φ2 to the gate of the NMOS transistor 282, and outputs the control signal Φ3 to the gate of the NMOS transistor 283. At this time, the control circuit 205 can Figure 4 Here, the delay circuit 211 can set the delay time TD.

[0089] Fig.15 is a diagram showing the relationship between the discharge time of the level shift circuit according to the first embodiment and the switching time of the output. Fig.14 The level shift circuit is simulated to obtain this relationship.

[0090] In the figure, the discharge time is equal to Fig. 9 The delay time TD in the output OUT is 27 μs when the discharge time is 0 μs. When the discharge time is extended, the switching time T of the output OUT tends to be shortened. For example, the switching time T of the output OUT when the discharge time is 10 μs is 19 μs, which is 30% shorter than the switching time T' of the output OUT when the discharge time is 0 μs.

[0091] As described above, in the above-mentioned first embodiment, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, the level shift circuit 100 connects the output terminal TO to the ground potential GND, and provides a current path to the ground potential GND via the output terminal TO. Therefore, it is possible to reduce the restriction on the impedance of charging and discharging the capacitive load 206 at the time of level shifting, and accelerate the level shifting.

[0092] <2. Second Embodiment>

[0093] In the first embodiment described above, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, the output terminal TO is connected to the ground potential GND, and the current path through the output terminal TO is set at the ground potential GND. In the second embodiment, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, the output terminal TO is connected to the power supply potential VDD, and the power supply potential VDD is provided through the current path through the output terminal TO.

[0094] Fig.16 : is a diagram showing a circuit configuration example of a level shift circuit according to the second embodiment.

[0095] In the drawing, the level shift circuit 300 includes a switch element 204 instead of the switch element 203 of the above-described first embodiment. The other configuration of the level shift circuit 300 of the second embodiment is similar to that of the level shift circuit 100 of the above-described first embodiment.

[0096] The switch element 204 connects the output terminal TO to the power supply potential VDD based on the control signal Φ4. The power supply potential VDD may be set between the ground potential GND and the positive DC potential VIP, or may be higher than the positive DC potential VIP.

[0097] Here, the power supply potential VDD is set between the ground potential GND and the positive DC potential VIP. Then, it is assumed that when the output OUT is at the negative DC potential VIN, the control circuit 205 converts the digital signal VC level to the positive DC potential VIP. At this time, the control circuit 205 turns on the switch element 201 with a delay according to the input timing of the digital signal VC, and connects the positive DC potential VIP to the output terminal TO. Here, before turning on the switch element 201, the control circuit 205 turns on the switch element 204 and connects the output terminal TO to the power supply potential VDD to perform charging via the output terminal TO.

[0098] On the other hand, it is assumed that when the output OUT is at the positive DC potential VIP, the control circuit 205 converts the digital signal VC level to the negative DC potential VIN. At this time, the control circuit 205 turns on the switch element 202 with a delay according to the input timing of the digital signal VC, and connects the negative DC potential VIN to the output terminal TO. Here, the control circuit 205 turns on the switch element 204 before turning on the switch element 202, connects the output terminal TO to the power supply potential VDD, and discharges through the output terminal TO.

[0099] Note that, when the power supply potential VDD is greater than the positive DC potential VIP, even if the output terminal TO is connected to the power supply potential VDD, discharge cannot be performed via the output terminal TO. Therefore, when the power supply potential VDD is greater than the positive DC potential VIP, the output terminal TO can be connected to the power supply potential VDD, and charging can be performed only via the output terminal TO.

[0100] As described above, in the above-mentioned second embodiment, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, the level shift circuit 300 connects the output terminal TO to the power supply potential VDD, and provides a current path to the power supply potential VDD via the output terminal TO. Therefore, it is possible to reduce the restriction on the impedance of charging and discharging the capacitive load 206 at the time of level shifting, and accelerate the level shifting.

[0101] <3. Third Implementation>

[0102] In the first embodiment described above, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, the output terminal TO is connected to the ground potential GND, and the current path through the output terminal TO is set at the ground potential GND. In the third embodiment, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, the current path through the output terminal TO is set at the ground potential GND and the power supply potential VDD.

[0103] Fig.17 : is a diagram showing a circuit configuration example of a level shift circuit according to the third embodiment.

[0104] In the drawing, in a level shift circuit 400, the switch element 204 of the second embodiment described above is added to the level shift circuit 100 of the first embodiment described above. The other configuration of the level shift circuit 400 of the third embodiment is similar to that of the level shift circuit 100 of the first embodiment described above.

[0105] Assume that when the output OUT is at the negative DC potential VIN, the control circuit 205 converts the digital signal VC level into the positive DC potential VIP. At this time, the control circuit 205 turns on the switch element 201 with a delay according to the input timing of the digital signal VC, and connects the positive DC potential VIP to the output terminal TO. Here, before turning on the switch element 201, the control circuit 205 turns on the switch element 204 and connects the output terminal TO to the power supply potential VDD to perform charging via the output terminal TO.

[0106] On the other hand, it is assumed that when the output OUT is at the positive DC potential VIP, the control circuit 205 converts the digital signal VC level to the negative DC potential VIN. At this time, the control circuit 205 turns on the switch element 202 with a delay according to the input timing of the digital signal VC, and connects the negative DC potential VIN to the output terminal TO. Here, the control circuit 205 turns on the switch element 203 before turning on the switch element 202, connects the output terminal TO to the ground potential GND, and discharges through the output terminal TO.

[0107] As described above, in the third embodiment, the power supply potential VDD connected to the charging path can be made higher than the ground potential GND connected to the discharging path. Therefore, when the level shift from the negative DC potential VIN to the positive DC potential VIP is performed, the charging via the output terminal TO can be accelerated, and the level shift can be accelerated.

[0108] <4. Fourth Embodiment>

[0109] In the first embodiment described above, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, a current path via the output terminal TO is set at the ground potential GND and the power supply potential VDD. In the fourth embodiment, when level shifting is performed between the negative DC potential VIN and the positive DC potential VIP, a current path via the output terminal TO is provided at an intermediate potential between the negative DC potential VIN and the positive DC potential VIP.

[0110] Fig.18 : is a diagram showing a circuit configuration example of a level shift circuit according to a fourth embodiment.

[0111] In the accompanying drawings, the level shift circuit 500 can be configured similarly to the level shift circuit 400 of the third embodiment described above. However, the switch element 203 connects the output terminal TO to the intermediate potential VM2 based on the control signal Φ3. The switch element 204 connects the output terminal TO to the intermediate potential VM1 based on the control signal Φ4. The intermediate potentials VM1 and VM2 can satisfy the relationship of VIN<VM2<VM1<VIP. The intermediate potential VM1 can be a positive intermediate potential between the positive DC potential VIP and the negative DC potential VIN, and the intermediate potential VM2 can be a negative intermediate potential between the positive DC potential VIP and the negative DC potential VIN. At this time, the intermediate potential VM1 is preferably set to a value close to the positive DC potential VIP, and the intermediate potential VM2 is preferably set to a value close to the negative DC potential VIN.

[0112] Assume that when the output OUT is at the negative DC potential VIN, the control circuit 205 converts the digital signal VC level to the positive DC potential VIP. At this time, the control circuit 205 turns on the switch element 201 with a delay according to the input timing of the digital signal VC, and connects the positive DC potential VIP to the output terminal TO. Here, the control circuit 205 turns on the switch element 204 before turning on the switch element 201, connects the output terminal TO to the intermediate potential VM1, and charges via the output terminal TO.

[0113] On the other hand, it is assumed that when the output OUT is at the positive DC potential VIP, the control circuit 205 converts the digital signal VC level to the negative DC potential VIN. At this time, the control circuit 205 turns on the switch element 202 with a delay according to the input timing of the digital signal VC, and connects the negative DC potential VIN to the output terminal TO. Here, before turning on the switch element 202, the control circuit 205 turns on the switch element 203 and connects the output terminal TO to the intermediate potential VM2, so as to perform discharge via the output terminal TO.

[0114] As described above, in the fourth embodiment described above, the intermediate potential VM1 connected to the charging path can be made close to the positive DC potential VIP, and the intermediate potential VM2 connected to the discharging path can be made close to the negative DC potential VIN. Therefore, at the time of level shift between the negative DC potential VIN and the positive DC potential VIP, charging and discharging via the output terminal TO can be accelerated, and the level shift can be accelerated.

[0115] Note that the above-described level shift circuit can be applied to, for example, a communication integrated circuit (IC), an inverter for driving a motor or the like, or a semiconductor integrated circuit in which a plurality of power supplies are mixed.

[0116] In addition, the above-mentioned embodiments illustrate examples for embodying the present technology, and the various contents in the embodiments and the various contents of the present invention specified in the claims have a corresponding relationship. Similarly, the corresponding matters specifying the present invention in the claims have a corresponding relationship with the corresponding matters with the same name in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the gist of the present technology. In addition, the effects described in this specification are only examples and are not limited, and other effects may be provided.

[0117] It should be noted that the present technology may also have the following configurations.

[0118] (1) A level shift circuit comprising:

[0119] a level shift unit that level-shifts a signal from a first potential to a second potential and outputs the signal via an output terminal;

[0120] a current path setting unit that sets a second current path in the output terminal that is separate from a first current path from the level shift unit to the output terminal; and

[0121] The opening / closing unit opens and closes the first current path and the second current path.

[0122] (2) A level shift circuit according to (1), wherein:

[0123] The current path setting unit sets the second current path to the output terminal so that the potential of the output terminal approaches the second potential when the output terminal is disconnected from the second potential.

[0124] (3) A level shift circuit according to (1) or (2), wherein:

[0125] The second current path includes at least one of a discharge path that releases electric charge via the output terminal and a charge path that charges electric charge via the output terminal.

[0126] (4) The level shift circuit according to any one of (1) to (3), wherein:

[0127] The second potential includes a positive DC potential and a negative DC potential, and

[0128] The level shift unit selectively converts the first potential into a positive DC potential or a negative DC potential and outputs the result via an output terminal.

[0129] (5) A level shift circuit according to (4), wherein:

[0130] The level shift unit includes:

[0131] a first switching element connecting a positive DC potential to the output terminal, and

[0132] The second switching element connects the negative DC potential to the output terminal.

[0133] (6) A level shift circuit according to (5), wherein:

[0134] The current path setting unit includes:

[0135] The third switch element connects the output terminal to a third potential.

[0136] (7) A level shift circuit according to (6), wherein:

[0137] The third potential is a ground potential, a power supply potential, or an intermediate potential between a positive DC potential and a negative DC potential.

[0138] (8) A level shift circuit according to (7), wherein:

[0139] The opening / closing unit connects the output terminal to a positive DC potential, disconnects the output terminal from the positive DC potential, and then connects the output terminal to a ground potential, and disconnects the output terminal from the ground potential, and then connects the output terminal to a negative DC potential.

[0140] (9) A level shift circuit according to (7), wherein:

[0141] The opening / closing unit connects the output terminal to a positive DC potential, disconnects the output terminal from the positive DC potential, and then connects the output terminal to an intermediate potential, and disconnects the output terminal from the intermediate potential, and then connects the output terminal to a negative DC potential.

[0142] (10) A level shift circuit according to (7), wherein:

[0143] The opening / closing unit connects the output terminal to a negative DC potential, disconnects the output terminal from the negative DC potential, and then connects the output terminal to a power supply potential, and disconnects the output terminal from the power supply potential, and then connects the output terminal to a positive DC potential.

[0144] (11) A level shift circuit according to (7), wherein:

[0145] The opening / closing unit connects the output terminal to a negative DC potential, disconnects the output terminal from the negative DC potential, and then connects the output terminal to an intermediate potential, and disconnects the output terminal from the intermediate potential, and then connects the output terminal to a positive DC potential.

[0146] (12) The level shift circuit according to any one of (6) to (11), wherein:

[0147] The current path setting unit includes:

[0148] The fourth switch element connects the output terminal to a fourth potential.

[0149] (13) A level shift circuit according to (12), wherein:

[0150] The third potential is a ground potential, and the fourth potential is a power supply potential.

[0151] (14) A level shift circuit according to (12), wherein:

[0152] The third potential is a positive intermediate potential between the positive DC potential and the negative DC potential, and the fourth potential is a negative intermediate potential between the positive DC potential and the negative DC potential.

[0153] (15) The level shift circuit according to any one of (1) to (14), further comprising:

[0154] The delay circuit delays connection of the second potential to the output terminal when the signal is level-shifted from the first potential to the second potential.

[0155] (16) Level shift according to (15), where

[0156] the opening / closing unit opens the first current path and closes the second current path while delaying connection of the second potential to the output terminal;

[0157] Reference Symbols List

[0158] 100, 300, 400, 500 Level Shifter Circuit

[0159] 101 Level Shift Unit

[0160] 102 Input / output open / close unit

[0161] 103 Charge / discharge unit

[0162] 201 to 204 Switching elements

[0163] 205 Control Circuit

[0164] 206 Capacitive load.

Claims

1. A level shift circuit, comprising: a level shift unit that level-shifts a signal from a first potential to a second potential and outputs the signal via an output terminal; a current path setting unit that sets a second current path in the output terminal that is separate from a first current path from the level shift unit to the output terminal; as well as An opening / closing unit opens and closes the first current path and the second current path.

2. The level shift circuit according to claim 1, wherein: The current path setting unit sets the second current path to the output terminal so that the potential of the output terminal approaches the second potential when the output terminal is disconnected from the second potential.

3. The level shift circuit according to claim 1, wherein: The second current path includes at least one of a discharge path that releases electric charge through the output terminal and a charge path that charges electric charge through the output terminal.

4. The level shift circuit according to claim 1, wherein: The second potential includes a positive DC potential and a negative DC potential, and The level shift unit selectively converts the first potential into the positive DC potential or the negative DC potential and outputs the result via the output terminal.

5. The level shift circuit according to claim 4, wherein: The level shift unit comprises: a first switching element connecting the positive DC potential to the output terminal, and The second switching element connects the negative DC potential to the output terminal.

6. The level shift circuit according to claim 5, wherein: The current path setting unit includes: The third switch element connects the output terminal to a third potential.

7. The level shift circuit according to claim 6, wherein: The third potential is a ground potential, a power supply potential, or an intermediate potential between the positive DC potential and the negative DC potential.

8. The level shift circuit according to claim 7, wherein: The opening / closing unit connects the output terminal to the positive DC potential, disconnects the output terminal from the positive DC potential, and then connects the output terminal to the ground potential, and disconnects the output terminal from the ground potential and then connects the output terminal to the negative DC potential.

9. The level shift circuit according to claim 7, wherein: The opening / closing unit connects the output terminal to the positive DC potential, disconnects the output terminal from the positive DC potential, and then connects the output terminal to the intermediate potential, and disconnects the output terminal from the intermediate potential and then connects the output terminal to the negative DC potential.

10. The level shift circuit according to claim 7, wherein: The opening / closing unit connects the output terminal to the negative DC potential, disconnects the output terminal from the negative DC potential, and then connects the output terminal to the power supply potential, and disconnects the output terminal from the power supply potential and then connects the output terminal to the positive DC potential.

11. The level shift circuit according to claim 7, wherein: The opening / closing unit connects the output terminal to the negative DC potential, disconnects the output terminal from the negative DC potential, and then connects the output terminal to the intermediate potential, and disconnects the output terminal from the intermediate potential and then connects the output terminal to the positive DC potential.

12. The level shift circuit according to claim 6, wherein: The current path setting unit includes: The fourth switch element connects the output terminal to a fourth potential.

13. The level shift circuit according to claim 12, wherein: The third potential is a ground potential, and the fourth potential is a power supply potential.

14. The level shift circuit according to claim 12, wherein: The third potential is a positive intermediate potential between the positive DC potential and the negative DC potential, and the fourth potential is a negative intermediate potential between the positive DC potential and the negative DC potential.

15. The level shift circuit according to claim 1, further comprising: A delay circuit delays connection of the second potential to the output terminal when the signal is level-shifted from the first potential to the second potential.

16. The level shift circuit according to claim 15, wherein: The opening / closing unit opens the first current path and closes the second current path while delaying connection of the second potential to the output terminal.

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