Memory device and method of assembling same

Abstract

Techniques are disclosed for a memory device having a memory die flip-chip bonded to one or more interposers mounted to a system board. The memory device may be an SSD, and the system board may be an M.2 board. A memory controller die may be bonded to one of the interposer boards. In one aspect, the memory controller die is flip-chip bonded to the interposer board. In one aspect, a heat sink is attached to a top surface of the flip-chip bonded controller die and a top surface of the group of memory dies. The memory dies and the interposers are neither covered by the molding compound. Performance of the memory device is improved by, for example, reducing inductance and improving heat dissipation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 356,838, entitled “MEMORY DEVICE AND METHOD OF ASSEMBLING SAME,” filed in the U.S. Patent and Trademark Office on July 21, 2023, and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 386,973, filed on December 12, 2022. Background Art

[0003] Strong growth in demand for portable consumer electronic devices has driven the need for high-capacity storage devices. Non-volatile semiconductor memory devices (such as flash memory storage cards) are now widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, and rugged design, as well as their high reliability and large capacity, make such memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, cellular phones, and solid-state drives (SSDs).

[0004] Although many different packaging configurations are known, flash memory storage cards can be assembled as a system-in-package (SiP) or a multi-chip module (MCM), in which multiple dies are mounted and interconnected on a substrate with a small footprint. The substrate may include a rigid dielectric base having a conductive layer etched on one or both sides. An electrical connection is formed between the die and the conductive layer, and the conductive layer provides an electrical lead structure for connecting the die to a host device. Once the electrical connection between the die and the substrate is formed, the assembly is encapsulated in a molding compound that provides a protective package.

[0005] Figure 1A conventional memory device 100 is shown. The substrate 102 can be a variety of different chip-carrying media, including a printed circuit board (PCB). A semiconductor die stack 104 is formed on the substrate 102. The semiconductor die stack 104 has a plurality of semiconductor dies 124. A die bonding pad 126 is depicted on each semiconductor die 124, but each die 124 may include many more die bonding pads 126. Bonding wires 130 are used to electrically connect the bonding pads 126 to contact pads 131 on the substrate 102, thereby allowing signal transmission between the substrate and the semiconductor die 124. A memory controller die 114 is located on the substrate 102. A die bonding pad 128 is depicted on the memory controller die 114, but many more die bonding pads 128 may be present on the memory controller die 114. Bond wires 132 are used to electrically connect bond pads 128 to contact pads 133 on substrate 102, thus allowing signal transmission between substrate 102 and memory controller die 114. Bond wires 130, 132 may be formed of gold, gold alloys, or other materials.

[0006] There are a plurality of contact pads 108 on the bottom surface of substrate 102. Solder balls 154 may be attached to contact pads 108 on the bottom surface of substrate 102. Solder balls 154 may be used to attach memory device 100 to a host device (not shown). Memory device 100 may be encapsulated in a mold compound 142. Mold compound 142 may include, for example, solid epoxy, phenolic, fused silica, crystalline silica, carbon black, and / or metal hydroxides.

[0007] In order to increase memory capacity, but maintain the package footprint, it is known to stack semiconductor dies on top of each other on the surface of a substrate. The dies may be offset and / or overlapped with each other and separated by spacers or wire-wrap films. Figure 1 An example is depicted where the stack 104 has four dies 124 with an offset. However, the memory device may stack even more dies. However, stacking more and more dies 124 on top of each other requires making the individual dies 124 thinner to avoid the stack height becoming too large given the packaging constraints. However, thinning the dies 124 can lead to cracking and warping.

[0008] Furthermore, the stack 104 of semiconductor dies will typically have a large number of leads (eg, leads 130 , 132 ) bonded to the substrate 102 . This large number of leads contributes a significant amount of inductance to the memory device 100 .

[0009] In addition, the SiP process has a large number of steps including testing and packaging. These tests increase the cost and time of assembling memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A conventional memory device is shown.

[0011] Figure 2 is an illustration of one embodiment of a memory device having a memory die flip-chip bonded on an interposer board mounted to a system board.

[0012] Figure 3 is an illustration of one embodiment of a memory device having a memory die flip-chip bonded to an interposer board mounted to a system board, and an additional memory die directly bonded to the system board.

[0013] Figure 4 A memory device is depicted in which both major surfaces of a system board are used to mount an interposer board with flip-chip bonded memory dies.

[0014] Figure 5 is an illustration of a memory device with a heat sink attached to a memory die flip-chip bonded on an interposer board.

[0015] Figure 6 Shown is a top view before flip chip bonding of the memory die to the interposer board.

[0016] Figure 7 Shown is a side view of a memory die after it has been flip-chip bonded to an interposer board.

[0017] Figure 8 Shown is a top view after flip chip bonding of the memory die to the interposer board.

[0018] Fig. 9 is a flow chart of one embodiment of a process of assembling a memory device having a memory die flip-chip bonded to an interposer board mounted to a system board.

[0019] Fig.10 is a flow chart of another embodiment of a process of assembling a memory device having a memory die and a memory controller die flip-chip bonded to an interposer board mounted to a system board.

[0020] Fig.11 is a flow chart of another embodiment of a process of assembling a memory device having a heat sink attached to dies that are flip-chip bonded to an interposer board that is mounted to a system board. DETAILED DESCRIPTION

[0021] The present technology will now be described with reference to the figures, which in embodiments relate to a memory device having a memory die bonded to one or more interposer boards mounted to a system board in a flip-chip manner, and a method of assembling the memory device. The system board may be an M.2 board, but the embodiment is not limited to M.2. In an embodiment, the memory device is a solid-state drive (SSD). The memory controller die may be bonded to one of the interposer boards. In one embodiment, the memory controller die is bonded to the interposer board in a flip-chip manner. In an embodiment, each memory die may be a die referred to herein as a "bare die", "bare chip", "unencapsulated die" or "unencapsulated chip". The bare die does not have a molded cover (e.g., solid epoxy, phenolic resin, fused silica, crystalline silica, carbon black and / or metal hydroxide) present in a packaged die. In an embodiment, the memory controller die is a bare die. In one embodiment, a heat sink is attached to the top surface of the bare controller die bonded in a flip-chip manner and the top surface of the group of bare memory dies.

[0022] Because a large number of memory dies do not need to be stacked, wafer thinning operations are eliminated. As a result, problems such as wafer breakage and warping are reduced or eliminated. Some assembly steps and tests typically used for system-in-package (SiP) are also eliminated, saving time and cost.

[0023] Moreover, because the memory die is bonded in a flip chip manner, the bonding wires that are usually used when stacking memory die are eliminated. Therefore, the cost of wires is eliminated. Moreover, the inductance is reduced, thereby improving the performance of the memory device. Moreover, because the memory die can be bare, the die packaging cost is saved. For example, the cost of the molding compound used for packaging is eliminated. In addition, for embodiments in which a heat sink is attached to the bare die, the performance of the memory device is improved due to better heat dissipation. Even without using a heat sink, the heat dissipation of the bare die is more effective than that of the packaged die.

[0024] It should be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and the present invention will be fully communicated to those skilled in the art. In fact, the present invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are all included in the scope and essence of the present invention as defined by the appended claims. In addition, in the following specific embodiments of the present invention, many specific details are given in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention can be implemented without such specific details.

[0025] The terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal", and forms thereof, as used herein, are used herein by way of example only and for illustrative purposes, and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "approximately" mean that a specified dimension or parameter may vary within acceptable manufacturing tolerances for a given application.

[0026] For purposes of this disclosure, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when a first element is referred to as being connected, attached, mounted, or coupled to a second element, the first element and the second element may be directly connected, attached, mounted, or coupled to each other or indirectly connected, attached, mounted, or coupled to each other. When a first element is referred to as being directly connected, attached, mounted, or coupled to a second element, there are no intermediate elements between the first element and the second element (except for an adhesive or molten metal that may be used to connect, attach, mount, or couple the first element and the second element).

[0027] Figures 2 to 5 Embodiments of memory devices such as solid-state drives (SSDs) are depicted. In embodiments, the memory die is flip-chip bonded to a substrate (e.g., Figures 2 to 5 ). In an embodiment, each memory die may be a die referred to herein as a "bare die," "bare chip," "unpackaged die," or "unpackaged chip." A bare die does not have the plastic molded cover present in a packaged die.

[0028] Figure 2200 is a diagram of an embodiment of a memory device 200. In one embodiment, the memory device 200 is an SSD. The memory device 200 has a plurality of memory tube cores 202. Each memory tube core 202 includes a memory cell. The memory cell can be volatile or non-volatile. In an embodiment, each memory tube core 202 includes one or more memory structures and peripheral circuits that control chip-level operations such as reading, writing and erasing. The types of memory cells may include, but are not limited to: flash memory NAND, ReRAM (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM and phase change memory (e.g., PCM). Examples of suitable technologies for memory cell architectures of memory structures in memory tube cores 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like. The memory device 200 has a memory controller tube core 208. The memory controller tube core 208 communicates with all memory tube cores 202. Memory controller die 208 may be, for example, an ASIC for controlling the transfer of signals and data to and from memory die 202 .

[0029] The memory device 200 has a system board 203. The system board 203 is a signal bearing medium provided for transmitting electrical signals between a semiconductor die mounted on and in the system board and a host device. The system board 203 may be a printed circuit board (PCB), including those having edge connectors for connecting to a host device such as a motherboard. The system board 203 may be a PCB or other PCB having solder balls for soldering the system board 203 to a host device such as a motherboard. The system board 203 may have a specific form factor. The system board 203 may be an M.2 board, but is not limited to M.2 (formerly known as the next generation size (NGFF)). In one embodiment, the memory device 200 is an M.2 SSD. The system board 203 may have a connector 228 that provides a physical and electrical connection to, for example, a host. Thus, data may be transmitted between the host and the memory die 202. The connector 228 may have a variety of form factors, including but not limited to SATA (Serial Advanced Technology Attachment), SAS (Serial Attached Small Computer System Interface), PCIe (Peripheral Component Interconnect Express). The memory controller 208 controls the writing (storage) of data received on the interface 228 into the memory die 202. The memory controller die 208 controls the reading of data stored in the memory die 202 and provides the data to the host through the connector 228. The memory controller die 208 may encode the data before storage and decode (and correct errors) the data before transmission to the host. In an embodiment, the memory controller die 208 may be used to store data in the memory die 202. Figures 2 to 5No cover is required on the components in any of the figures. For example, the M.2 SSD form factor does not require a cover. In addition, in an embodiment, neither the interposer board 206 nor the system board 203 is covered by a molding compound. Optionally, Figure 2 A cover or the like may be added to the components in the embodiment, but a cover is not required. For example, in some operating environments, a cover for EMI (electromagnetic interference) protection may be added.

[0030] Figure 2 The memory device 200 has a first interposer board 206-1 (or more simply "interposer") and a second interposer board 206-2. The interposer board 206 is a substrate with components attached. The interposer 206 is directly mounted to the system board 203, such as with solder balls 220, as will be discussed below. Multiple memory dies 202 are flip-chip bonded to the primary side (or first major surface) 204 of the first interposer board 206-1. The memory controller die 208 is also directly mounted to the primary side 204 of the first interposer 206-1. The power management integrated circuit (PMIC) 210 is also directly mounted to the primary side 204 of the first interposer 206-1. Multiple memory dies 202 are also flip-chip bonded to the secondary side (or second major surface) 212 of the first interposer 206-1. The first interposer 206-1 is directly mounted to the system board 203. In an embodiment, a ball grid array (BGA) is used to mount the first interposer 206-1 directly to the system board 203. There are a plurality of contact pads 214 on the secondary side 212 of the first interposer 206-1. There are a similar number of contact pads 216 on the top surface of the substrate 102. Solder balls 218 may be used to electrically connect the pairs of contact pads 214, 216.

[0031] The second interposer 206-2 is also mounted directly to the system board 203 in a manner similar to the first interposer 206-1. A plurality of memory dies 202 are flip-chip bonded to the primary side 204 of the second interposer 206-2. Also, a plurality of memory dies 202 are flip-chip bonded to the secondary side 212 of the second interposer 206-2. In this example, only the memory dies 202 are attached to the second interposer 206-1. That is, the second interposer 206-2 does not include a controller die or a PMIC.

[0032] Additional components 222, 224, 226 are mounted directly to system board 203. Additional components 222, 224, 226 may be passive components, such as resistors, capacitors, inductors, etc. However, additional components 222, 224, 226 are not limited to being passive components. System board 203 may be connected to a host (not shown) via connector 228. According to an embodiment of the present invention, one skilled in the art will note that neither memory die 202 nor interposer 206 of memory device 200 includes any molding compound covering either of memory die 202.

[0033] Figure 3 2 is a diagram of one embodiment of a memory device 300. In an embodiment, the memory device is an SSD. The first interposer 206-1 as shown and described with respect to the memory device 200 is mounted directly to the system board 203. The plurality of additional memory dies 202 are mounted directly to the system board 203. The memory device 300 will not be discussed further. Figure 2 In an embodiment, the additional memory die 202 is flip-chip bonded to the system board 203.

[0034] In some embodiments, both major surfaces of the system board 203 can be used to directly mount the interposer 206 . Figure 4 A memory device 400 is depicted in which two major surfaces of a system board 203 are used to directly mount interposers 206. Interposers 206-1 and 206-2 are mounted directly to a first major surface 402 of the system board 203. Interposers 206-3 and 206-4 are mounted directly to a second major surface 404 of the system board 203. Interposers 206-3 and 206-4 are similar to interposer 206-2, each having a plurality of memory dies 202 mounted in a flip-chip manner to a primary side 204 and a secondary side 212. In an embodiment, the memory device 400 is an SSD. The memory device 400 and its components will not be discussed further. Figure 2 The same elements as the memory device 200 in FIG.

[0035] In some embodiments, one or more heat sinks are attached to the top surfaces of the memory controller die 208 and the memory die 202 . Figure 5is an illustration of a memory device 500 having two heat sinks. In an embodiment, the memory device 500 is an SSD. A first heat sink 502 is attached to a top surface of a memory die 202 on a primary side 204 of a first interposer 206-1, a top surface of a memory die 202 on a primary side 204 of a second interposer 206-2, a memory controller die 208 on a primary side 204 of the first interposer 206-1, and a power management IC 210 on a primary side 204 of the first interposer 206-1. A second heat sink 504 is attached to a top surface of a memory die 202 on a primary side 204 of a third interposer 206-3 and a top surface of a memory die 202 on a primary side 204 of a fourth interposer 206-4. Each heat sink 502, 504 is thermally coupled to (or in thermal contact with) a respective die top surface to cool the memory controller die 208, the memory die 202, and / or the power management IC 210. Note that the die 202, 208 may be unencapsulated die for better heat transfer. The heat sink 502, 504 may be directly attached to the die 202, 208 as there are no intervening components other than adhesives (e.g., epoxy), thermal interface materials, etc. used to attach the heat sink and / or aid in heat transfer. The memory controller die 208 may generate more heat than the memory die 202 alone. Flip-chip mounting the memory controller die 208 and attaching the heat sink 502 to the memory controller die provides an effective way to cool the memory controller die 208. The memory device 500 will not be discussed further with respect to FIG. Figure 2 Although heat sinks 502 and 504 are shown as finned heat sinks, fins are not required and the size of the heat sink can be determined based on the overall physical dimensions specified for memory device 500.

[0036] Figures 6 to 8 Further details of an embodiment of flip chip bonding to the interposer board 206 are provided. In an embodiment, the memory die 202 is flip chip bonded to the interposer board 206. In an embodiment, the memory controller die 208 is flip chip bonded to the interposer board 206. Figures 6 to 8 The discussion will be with respect to four memory dies 202 being flip-chip bonded to one side of an interposer 206 . Figure 6 A top view is shown before four memory dies 202 are flip-chip bonded to an interposer 206 . Figure 7 A side view of one memory die 202 is shown after it has been flip-chip bonded to an interposer 206 . Figure 8A top view is shown after four memory dies 202 are flip-chip bonded to the interposer 206. This example is consistent with four memory dies 202 being flip-chip bonded to the primary side 204 of the interposer 206-2, 206-3, or 206-4. Similar techniques may be used to flip-chip bond the memory controller die 208 to the interposer 206. The interposer 206 has four conductive patterns 604. Each conductive pattern 604 has a cluster of contact pads 608. Each memory die 202 may include a cluster of bump pads 618 that are configured to mate with a corresponding cluster of contact pads 608 on the interposer 206. The cluster of "bump pads" 618 is located on a face of the memory die 202. The memory die 202 may be referred to as a "flip-chip semiconductor die". There may be more than one bump pad in a corresponding cluster. Figure 6 Many more bump pads 618 and contact pads 608 are shown in FIG. Figure 7 , each bump pad 618 may include a solder bump 618b that may be adhered to an electrical contact 618a on the face of the die 202 during the semiconductor wafer fabrication steps. Thus, the solder bump 618b may be added to the face of the die 202 before the solder bump 618b is bonded to the interposer 206. The key aspects of flip chip die creation are the bump layout and RDL (redistribution layer) design. The parameters considered are bump size, bump pitch, bump pattern / layout, RDL line width, and RDL spacing. In some embodiments, the bump pattern / layout is optimized for the bottom fill process.

[0037] To attach the memory die 202 to the interposer 206, each memory die 202 is removed from Figure 6 The positions shown are inverted so that the cluster of bump pads 618 matches the corresponding cluster of contact pads 608 on the interposer 206. The solder bumps 618b are then melted and cured in an oven using a reflow process. Optionally, an electrically insulating adhesive can be bottom-filled into any space around the solder bumps 618b between the memory die 202 and the interposer 206 to provide a stronger mechanical connection, provide a thermal bridge, and reduce stress on the solder joints caused by the different heating of the chip and the substrate. The electrical traces 602 on the interposer 206 are connected to various contact pads 608. The traces 602 and contact pads 608 shown are only examples, and the interposer 206 may include more traces 602 and / or contact pads 608 than shown in the figure, and these traces and contact pads may be in different positions than shown in the figure. Note that flip chip bonding of the dies 202 , 208 to the interposer board 206 results in the dies 202 , 208 being directly connected to the interposer board 206 as there are no intervening components between the dies 202 , 208 and the interposer board 206 other than, for example, solder bumps 618 b or other elements providing an electrical bond.

[0038] The use of a flip chip configuration to mount the memory die 202 on the interposer 206 allows many memory dies to be included in a memory device without using stacking of memory dies 116. Thus, issues with wafer thinning leading to wafer cracking and wafer warping are reduced or eliminated. Other advantages are: elimination of bond wires, reduced interconnect lengths, improved electrical performance and reduced noise, high packaging density, high I / O count, and reduced package / device footprint.

[0039] In an embodiment, each memory die 202 may be a die referred to herein as a “bare die,” “bare chip,” “unpackaged die,” or “unpackaged chip.” A bare die does not have the plastic molded cap that is present in a packaged die. Figure 7 A top surface 704 of one of the memory dies 202 facing away from the interposer 206 is shown. The top surface 704 may be referred to herein as a "bare top surface" or "unencapsulated top surface" because the die is a bare die or unencapsulated die without a molded cover. In some embodiments, a heat sink is thermally coupled to the bare top surface 704 to cool the memory die 202. In a similar manner, the memory controller die 208 may be flip-chip bonded to the interposer 206. A heat sink may also be thermally coupled to the bare top surface of the memory controller die 208 to cool the memory controller die 208.

[0040] Fig. 9900 is a simplified flow chart of an embodiment of a process 900 for assembling a memory device. The memory device may be an SSD. In an embodiment, the memory device is an M.2 SSD. Process 900 illustrates a process in which a memory device has one or more interposers (such as, interposers 206-1, 206-2, 206-3, or 206-4). Process 900 will be discussed with one of the interposers (e.g., any one of 206-1, 206-2, 206-3, 2060-4) (which will be referred to as interposer 206) as an example. Step 902 includes: bonding the memory die 202 to the primary side 204 of the interposer 206 in a flip chip manner. In one embodiment, for each memory die 202 in the first set of memory die 202, step 902 includes: placing a cluster of bump pads 618 on the memory die 202 in contact with a corresponding cluster of contact pads 608 on the primary side 204 of the interposer 206, and performing solder reflow. However, techniques other than solder reflow may be used in step 902, including, but not limited to, compression bonding techniques and laser welding. In an embodiment, the memory controller die 208 and the PMIC 210 are attached to the primary side 204 of the interposer (e.g., the interposer 206-1). The process 900 is not limited to any particular technique for adding the memory controller die. Further details of adding the memory controller die 208 and the PMIC 210 are provided in conjunction with Fig.10 Let's discuss.

[0041] Step 904 includes flip-chip bonding more memory dies 202 to the secondary side 212 of the interposer 206. In one embodiment, for each memory die 202 in the second set of memory dies 202, step 904 includes placing a cluster of bump pads 618 on the memory die 202 in contact with a corresponding cluster of contact pads 608 on the secondary side of the interposer 206, and performing solder reflow. However, other techniques including, but not limited to, compression bonding techniques and laser welding may be used in step 904. In steps 902 and 904, the memory die 202 may be a bare die that is not in a package (e.g., no package). Moreover, the order of steps 902 and 904 may be reversed.

[0042] Step 906 includes attaching solder balls 218 to contact pads 214 on the secondary side 212 of the interposer 206. Step 908 includes attaching the interposer 206 directly to the system board 203. Step 908 includes mating the solder balls 218 with the contact pads 216 on the system board 203 and performing a solder reflow process. The interposer 206 may be attached to a single major surface (e.g., 402 or 404) of the system board 203 or both major surfaces 402, 404 of the system board 203. Other elements such as passive components (e.g., 222, 224, 226) may also be added to the system board 203. It should be understood that some steps are not described in detail. Fig. 9 For example, an electrically insulating adhesive may be underfilled into any space between the memory die 202 and the interposer 206 surrounding the solder bumps 618b.

[0043] Fig.10 1 is a flow chart of another embodiment of a process 1000 for assembling a memory device. The memory device may be an SSD. In an embodiment, the memory device is an M.2 SSD. Process 1000 describes a process in which the memory device has an interposer such as interposer 206-1. Process 900 may be used to attach additional interposers such as interposers 206-2, 206-3, 206-3 to a system board (see step 1014). Step 1002 includes: flip-chip bonding the memory die 202 to the primary side 204 of the interposer 206-1. Step 1002 may be similar to Fig. 9 Thus, step 1002 may include a solder reflow process, although other techniques may be used to bond the clusters of bump pads 618 on the respective memory die 202 to the corresponding clusters of contact pads 608 on the primary side of the interposer 206-1. In step 1002, the memory die 202 is a bare die that is not in a package (e.g., no package).

[0044] Step 1004 includes attaching the memory controller die 208 to the primary side of the interposer 206-1. The process 1000 has two options for adding the memory controller die 208. In option A (step 1004a), the memory controller die 208 is in a package (e.g., a BGA package). In one embodiment of step 1004a, the memory controller die 208 is in a flip chip chip scale package (FCCSP); however, other packages may be used. In option B (step 1004b), the memory controller die 208 is not in a package (no package), that is, the memory controller die 208 is a bare die with bumps. Therefore, the controller die 208 has a cluster of bump pads similar to the cluster of bump pads 618 of the memory die (but the pattern will likely be different). The bump pad clusters of the memory controller die 208 are placed in contact with the corresponding clusters of contact pads 608 on the primary side of the interposer 206-1, and then, in an embodiment, a solder reflow is performed. In an embodiment, this is the same solder reflow process used to flip-chip bond the memory die 206 to the primary side of the interposer 206-1 in step 1002. However, other techniques including, but not limited to, compression bonding techniques and laser welding may be used to flip-chip bond the memory controller die 208 to the interposer 206-1.

[0045] Step 1006 includes attaching a power management IC to the primary side 204 of the interposer 206. Step 1008 includes flip-chip bonding the memory die 202 to the secondary side 204 of the interposer 206-1. Step 1008 may be similar to Fig. 9 904 in step 1006. Thus, step 1006 may include a reflow process, but other techniques may be used to bond the clusters of bump pads 618 on the respective memory die 202 with the corresponding clusters of contact pads 608 on the secondary side of the interposer 206. Step 1008 may be performed before steps 1002 to 1006. In step 1008, the memory die 202 may be a bare die that is not in a package (e.g., no package).

[0046] Step 1010 includes attaching solder balls 218 directly to contact pads 214 on the secondary side of interposer 206-1, which will allow interposer 206-1 to be directly connected to system board 203. Step 1012 includes attaching passive components directly to system board 203. In one embodiment, additional memory die 202 are flip-chip bonded to system board 203. Step 1014 includes attaching interposer 206-1 directly to system board 203. Step 1014 includes matching solder balls 218 of interposer 206-1 with contact pads 216 on system board 203 and, in an embodiment, performing a solder reflow process. Step 1014 may also include attaching additional interposers 206-2, 206-3, 206-4 directly to system board 203, as Fig. 9 It should be understood that some steps are not described in step 906 to step 908. Fig.10 For example, an electrically insulating adhesive may be underfilled into any space surrounding solder bumps between the flip-chip mounted memory die 202 and the flip-chip mounted control die 208 and the interposer 206 - 1 .

[0047] Fig.11 1 is a flow chart of another embodiment of a process 1100 for assembling a memory device. The process 1100 describes a process for assembling a memory device having one or more heat sinks. Step 1102 includes: assembling an interposer 206 having a memory die 202 bonded in a flip chip manner. Step 1102 may include: assembling interposers 206, such as interposers 206-1, 206-2, 206-3, and / or 206-4. Step 1102 may include several solder reflow steps. In one embodiment, for each side of each interposer 206, a separate solder reflow is performed to flip chip bond the die to the corresponding side. For example, a solder reflow is performed to flip chip bond the memory die 202 and the memory controller die 208 to the primary side 204 of the interposer 206-1. Another solder reflow is performed to flip chip bond the memory die 202 to the secondary side 212 of the interposer 206-1. Note that the order of these reflow steps can be reversed, i.e., reflow of the secondary side is performed before reflow of the primary side 204. In step 1102, preferably, the memory die 202 is a bare die that is not in a package (e.g., no package). In an embodiment, the memory controller die 208 is a bare die. Step 1103 includes mounting the components directly to the system board 203.

[0048] Step 1104 includes mounting one or more of the interposers 206 directly to the first major surface 402 of the system board 203. In one embodiment, step 1104 includes attaching solder balls 218 to contact pads 214 on the secondary side 212 of the respective interposers 206-1, 206-2, mating the solder balls 218 with the contact pads 216 on the first major surface 402 of the system board 203, and performing a solder reflow process. Step 1106 includes mounting one or more of the interposers 206 directly to the second major surface 404 of the system board 203. In one embodiment, step 1106 includes attaching solder balls 218 to contact pads 214 on the secondary side 212 of the respective interposers 206-3, 206-4, mating the solder balls 218 with the contact pads 216 on the second major surface 404 of the system board 203, and performing a solder reflow process. The order of step 1104 and step 1106 may be reversed.

[0049] Step 1108 includes attaching heat sink 502 to the die associated with first major surface 402. For example, heat sink 502 is attached to memory die 202 and memory control die 208 on interposer 206-1. Heat sink 502 may also be attached to memory die 202 on interposer 206-2. Heat sink 502 may be thermally coupled to the top surface of memory controller die 208 and to the top surface of the collection of memory die 202. Heat sink 502 is attached using adhesive (e.g., epoxy), thermal interface material, etc. after reflow (see steps 1102, 1104, 1106). Step 1110 includes attaching heat sink 504 to the die associated with second major surface 404. For example, heat sink 504 is attached to memory die 202 and memory control die 208 on interposer 206-3 and interposer 206-4. Heat sink 504 may be thermally coupled to the top surface of the set of memory die 202. Heat sink 504 is attached after reflow (see steps 1102, 1104, 1106) using an adhesive (eg, epoxy), thermal interface material, or the like.

[0050] In summary, in one example, the present technology relates to a memory device comprising a system board having an interface configured to connect to a host, and an interposer board mounted directly to the system board. The interposer board comprises a plurality of conductive patterns. Each conductive pattern comprises a cluster of contact pads. The memory device comprises a plurality of memory dies bonded to the interposer board in a flip-chip manner. Each memory die comprises a memory cell. Each memory die comprises a cluster of bump pads on a face of the memory die. For each particular memory die, the cluster of bump pads of the particular memory die is electrically bonded to a cluster of contact pads of one of the conductive patterns of the interposer board.

[0051] In another example, the plurality of memory dies are bare dies.

[0052] In another example, the memory device further includes a memory controller die bonded to the interposer board. The memory controller die communicates with the plurality of memory dies and is configured to control storage of data received on the interface of the system board in the plurality of memory dies.

[0053] In another example, a memory controller die is flip-chip bonded to an interposer board. The memory controller die includes a cluster of bump pads on a face of the memory controller die. The cluster of bump pads of the memory controller die is electrically bonded to a cluster of contact pads of one of the conductive patterns of the interposer board.

[0054] In another example, the interposer board includes a primary side and a secondary side. The primary side faces away from the system board. The secondary side faces the system board. The memory controller die is directly flip-chip bonded to the primary side of the interposer board. The memory controller die is a bare die.

[0055] In another example, the heat sink is thermally coupled to the unencapsulated top surface of the memory controller die and to the unencapsulated top surface of the set of the plurality of memory dies that are flip-chip bonded to the primary side of the interposer board. The unencapsulated top surface of the memory controller die and the unencapsulated top surface of the set of memory dies face away from the system board.

[0056] In another example, the interposer board includes a primary side and a secondary side. The plurality of memory dies includes a first plurality of memory dies flip-chip bonded to the primary side of the interposer board and a second plurality of memory dies flip-chip bonded directly to the secondary side of the interposer board.

[0057] In another example, the memory device further includes additional memory dies flip-chip bonded to the system board, wherein the additional memory dies are unencapsulated dies.

[0058] In another example, the memory device further includes one or more additional interposer boards mounted directly to the system board. The memory device further includes additional memory dies flip-chip bonded to the one or more additional interposer boards. The additional memory dies are bare dies.

[0059] In another example, the system board has a first major surface and a second major surface. At least one of the interposer boards is mounted directly to the first major surface. At least one of the interposer boards is mounted directly to the second major surface. Neither the interposer board nor the system board is covered by a molding compound.

[0060] In another example, the system board includes an M.2 board.

[0061] One embodiment includes a method for assembling a solid state drive (SSD). The method includes flip-chip bonding a first group of bare memory dies directly to a primary side of an interposer board and flip-chip bonding a second group of bare memory dies directly to a secondary side of the interposer board. Each memory die in the first group and the second group includes a non-volatile memory cell. The method includes mounting the interposer board directly to a system board.

[0062] One embodiment includes a solid state drive (SSD). The SSD includes a substrate member, the substrate member including a substrate contact member for providing electrical contact to the substrate member. The substrate member includes a member for transmitting data between the SSD and a host. The SSD includes a plurality of interposer members mounted directly to the substrate member, wherein each of the interposer members includes a first set of interposer-die contact members located on the primary side of the interposer member and a second set of interposer-die contact members located on the secondary side of the interposer member. Each of the interposer members includes an interposer-substrate contact member located on the secondary side of the interposer member. The interposer-substrate contact member is bonded to the substrate contact member. The SSD includes a plurality of memory dies, each memory die including a non-volatile memory cell. Each memory die includes a die bonding member located on a face of the memory die. The plurality of memory dies includes a first set of memory dies, each memory die having a face mounted directly to a primary side of one of the plurality of interposer components, wherein a die bonding member is electrically bonded to one of the first set of interposer-die contact members. The plurality of memory dies includes a second set of memory dies, each memory die having a face mounted directly to a secondary side of one of the plurality of interposer components, wherein a die bonding member is electrically bonded to one of the second set of interposer-die contact members.

[0063] In an embodiment, the substrate member includes one or more of a system board 203, a printed circuit board (PCB), or an M.2 board. In an embodiment, a member for providing electrical contact to the substrate member includes a contact pad 216. In an embodiment, a member for transmitting data between a solid-state storage system and a host includes one or more of a connector 228, a SATA (serial advanced technology attachment) interface, a SAS (serial attached small computer system interface) interface, or a PCIe (peripheral component express interconnect) interface. In an embodiment, an interposer member includes an interposer board 206. In an embodiment, an interposer-die contact member includes a contact pad 608 cluster. In an embodiment, an interposer-substrate contact member includes a contact pad 214. In an embodiment, a die bonding member includes a bump pad 618 cluster and / or a solder bump 618b cluster.

[0064] In another embodiment, the SSD includes a memory controller die having a face mounted directly to a primary side of one of the plurality of interposer members. The memory controller die includes a memory controller bonding member located on the face of the memory controller die. The memory controller bonding member is bonded to one of the first sets of interposer-die contact members. In an embodiment, the memory controller bonding member includes a cluster of bump pads 618 and / or a cluster of solder bumps 618b.

[0065] In another embodiment, the SSD includes a means for exchanging heat, wherein the means for exchanging heat is thermally coupled to a top surface of a memory controller die and a top surface of a collection of memory dies. The top surface of the memory controller die is opposite to a face of the memory controller die, wherein a top surface of each respective memory die is opposite to a face of a respective memory die. In an embodiment, the means for exchanging heat includes a heat sink 502.

[0066] The above specific embodiments of the present invention have been proposed for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In light of the above teachings, many modifications and variations are possible. The embodiments are selected to best illustrate the principles of the present invention and its practical application, so that other technical personnel in the field can best use the present invention with various modifications suitable for the specific purpose contemplated in various embodiments. The scope of the present invention is intended to be limited by the appended claims.

Claims

1. A memory device, comprising: a system board having an interface configured to connect to a host; an interposer board mounted directly to the system board, wherein the interposer board includes a plurality of conductive patterns, each conductive pattern including a cluster of contact pads; and A plurality of memory dies are flip-chip bonded to the interposer board, wherein each memory die comprises a memory cell, wherein each memory die comprises a cluster of bump pads on a face of the memory die, wherein for each specific memory die, the cluster of bump pads of the specific memory die is electrically bonded to the cluster of contact pads of one of the conductive patterns of the interposer board.

2. The memory device of claim 1, wherein the plurality of memory dies are bare dies.

3. The memory device according to claim 1, further comprising: A memory controller die is bonded to the interposer board, wherein the memory controller die is in communication with the plurality of memory dies and is configured to control storage in the plurality of memory dies of data received on the interface of the system board.

4. The memory device of claim 3, wherein: The memory controller die is flip-chip bonded to the interposer board; The memory controller die includes a cluster of bump pads on a face of the memory controller die; and The cluster of bump pads of the memory controller die is electrically bonded to the cluster of contact pads of one of the conductive patterns of the interposer board.

5. The memory device of claim 4, wherein: The interposer board comprises a primary side and a secondary side, the primary side faces away from the system board, and the secondary side faces the system board; the memory controller die being flip-chip bonded to the primary side of the interposer board; and The memory controller die is a bare die.

6. The memory device according to claim 5, further comprising: a heat sink thermally coupled to an unencapsulated top surface of the memory controller die and to an unencapsulated top surface of a set of the plurality of memory dies flip-chip bonded to the primary side of the interposer board, wherein the unencapsulated top surface of the memory controller die and the unencapsulated top surfaces of the set of memory dies face away from the system board.

7. The memory device of claim 1, wherein: The interposer board includes a primary side and a secondary side; and The plurality of memory dies includes a first plurality of memory dies flip-chip bonded to the primary side of the interposer board and a second plurality of memory dies flip-chip bonded to the secondary side of the interposer board.

8. The memory device of claim 1, further comprising: An additional memory die is flip-chip bonded to the system board, wherein the additional memory die is an unencapsulated die.

9. The memory device of claim 1 , further comprising: one or more additional interposer boards mounted directly to the system board; and An additional memory die is flip-chip bonded to the one or more additional interposer boards, wherein the additional memory die is a bare die.

10. The memory device of claim 9, wherein: The system board has a first major surface and a second major surface; at least one of the interposer boards is mounted directly to the first major surface; At least one of the interposer boards is mounted directly to the second major surface; and Neither the interposer board nor the system board is covered by molding compound.

11. The memory device of claim 1, wherein the system board comprises an M.2 board.

12. A method for assembling a solid state drive (SSD), the method comprising: flip-chip bonding a first set of bare memory dies directly to a primary side of an interposer board; flip-chip bonding a second group of bare memory dies directly to the secondary side of the interposer board, wherein each memory die in the first group and the second group includes a non-volatile memory cell; as well as The interposer board is mounted directly to a system board.

13. The method according to claim 12, further comprising: A memory controller die is flip-chip bonded directly to the primary side of the interposer board, wherein the memory controller die communicates with the first group of memory dies and the second group of memory dies, wherein the memory controller die is a bare die.

14. The method according to claim 13, further comprising: After mounting the secondary side of the interposer board directly to the system board, a heat sink is attached in thermal contact with the top surface of the first group of bare memory dies and with the top surface of the memory controller die.

15. The method of claim 13, wherein flip-chip bonding the memory controller die directly to the primary side of the interposer board comprises: forming a conductive pattern on the primary side of the interposer board, the conductive pattern comprising a cluster of contact pads; as well as The memory controller die is directly attached to the primary side of the interposer board in a flip chip arrangement in which a cluster of bump pads on the memory controller die is electrically bonded to a cluster of contact pads of the conductive pattern on the primary side of the interposer board.

16. The method of claim 12, wherein flip chip bonding the first set of memory dies directly to the primary side of the interposer board comprises: forming a plurality of conductive patterns on the primary side of the interposer board, each conductive pattern comprising a cluster of contact pads; as well as Each memory die in the first group of memory die is directly attached to the primary side of the interposer board in a flip chip arrangement, wherein in the flip chip arrangement, a cluster of bump pads on a corresponding memory die in the first group of memory die is electrically bonded to a cluster of contact pads of one of the conductive patterns on the primary side of the interposer board.

17. A solid state drive (SSD), the SSD comprising: a substrate member including a substrate contact member for providing electrical contact to the substrate member, the substrate member including a member for transmitting data between the SSD and a host; a plurality of interposer components directly mounted to the substrate component, wherein each of the plurality of interposer components includes a first set of interposer-die contact components on a primary side of the interposer component and a second set of interposer-die contact components on a secondary side of the interposer component, wherein each of the interposer components includes an interposer-substrate contact component on the secondary side of the interposer component, wherein the interposer-substrate contact components are directly connected to the substrate contact components; and A plurality of memory dies, each memory die comprising a non-volatile memory cell, wherein each memory die comprises a die bonding member located on a face of the memory die, the plurality of memory dies comprising a first set of memory dies, each memory die having the face mounted directly to the primary side of one of the plurality of interposer members, wherein the die bonding member is electrically bonded to one of the first set of interposer-die contact members, the plurality of memory dies comprising a second set of memory dies, each memory die having the face mounted directly to the secondary side of one of the plurality of interposer members, wherein the die bonding member is electrically bonded to one of the second set of interposer-die contact members.

18. The solid state drive of claim 17, wherein the plurality of memory dies are bare dies, and neither the memory dies nor the interposer member are covered by a molding compound.

19. The solid state drive of claim 18, further comprising: a memory controller die having a face mounted directly to the primary side of one of the plurality of interposer members, the memory controller die including a memory controller bonding member on the face of the memory controller die, wherein the memory controller bonding member is bonded to one of the first sets of interposer-die contact members, wherein the memory controller die is a bare die.

20. The solid state drive of claim 19, further comprising: a means for exchanging heat, wherein the means for exchanging heat is thermally coupled to a top surface of the memory controller die and to a top surface of the first set of memory dies, wherein the top surface of the memory controller die is opposite to the face of the memory controller die, wherein the top surface of each respective memory die is opposite to the face of the respective memory die.

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