Imaging element and electronic device

Abstract

The purpose of the present invention is to provide finer patterning of an imaging element. The imaging element includes a pixel, a well region electrode, and a signal generation unit. The pixel includes: a photoelectric conversion unit formed on a semiconductor substrate for photoelectrically converting incident light; a charge holding unit that holds charges generated by the photoelectric conversion; and a charge transfer unit that transfers the charge to the charge holding unit. The well region electrode is arranged to be embedded in the semiconductor substrate and connected to the well region of the semiconductor substrate. The signal generation unit generates a pixel signal, which is a signal generated in accordance with the charge held by the charge holding unit.

Description

Technical Field

[0001] The present disclosure relates to an imaging element and an electronic device. Background Art

[0002] An imaging element of the complementary metal oxide semiconductor (CMOS) type in which a plurality of pixels are arranged is used. Arranged in the pixel are: a photoelectric conversion unit including a photodiode that performs photoelectric conversion of incident light; a charge holding unit that holds the charge generated by the photoelectric conversion; and a transfer transistor that transfers the charge from the photoelectric conversion unit to the charge holding unit. A signal corresponding to the charge held in the charge holding unit is generated and output as an image signal. Among these imaging elements, an imaging element configured by stacking a semiconductor substrate (sensor substrate) in which pixels are arranged and a semiconductor substrate (transistor substrate) in which a circuit for generating an image signal is arranged is proposed (for example, see Patent Document 1).

[0003] In the above imaging element, in order to provide a reference potential from the transistor substrate to the sensor substrate, a via plug for transmitting the reference potential to the transistor substrate and the sensor substrate is provided. The via plug is connected to the well region of the sensor substrate and transmits the reference potential.

[0004] Prior art

[0005] Patent Literature

[0006] Patent Document 1: WO 2020 / 262643 A Summary of the invention

[0007] Technical issues

[0008] However, in the above-mentioned related art technique, a semiconductor region for connecting a via plug for transmitting a reference potential to a well region is provided for each pixel, and thus there is a problem that miniaturization is difficult.

[0009] Therefore, the present disclosure proposes an imaging element and an electronic device that are easily miniaturized.

[0010] Solution to the problem

[0011] An imaging element according to the present disclosure includes a pixel, a well region electrode, and a signal generating unit. A pixel includes: a photoelectric conversion unit that performs photoelectric conversion of incident light, the photoelectric conversion unit being formed in a semiconductor substrate; a charge holding unit that holds charges generated by the photoelectric conversion; and a charge transfer unit that transfers the charges to the charge holding unit. The well region electrode is provided by being embedded in the semiconductor substrate, and the well region electrode is connected to the well region of the semiconductor substrate. The signal generating unit generates a pixel signal, which is a pixel signal corresponding to the charges held in the charge holding unit.

[0012] In addition, an electronic device according to the present disclosure includes a pixel, a well region electrode, a signal generating unit, and a processing circuit. The pixel includes: a photoelectric conversion unit that performs photoelectric conversion of incident light, and the photoelectric conversion unit is formed in a semiconductor substrate; a charge holding unit that holds the charge generated by the photoelectric conversion; and a charge transfer unit that transfers the charge to the charge holding unit. The well region electrode is provided by being embedded in the semiconductor substrate, and the well region electrode is connected to the well region of the semiconductor substrate. The signal generating unit generates a pixel signal, which is a signal corresponding to the charge held in the charge holding unit. The processing circuit processes the pixel signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a configuration example of an imaging element according to an embodiment of the present disclosure.

[0014] Figure 2 is a circuit diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure.

[0015] Figure 3 : is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure.

[0016] Figure 4 : is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure.

[0017] Figure 5 : is a diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure.

[0018] Fig. 6A 1 is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0019] Figure 6B : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0020] Figure 6C : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0021] Fig.6D : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0022] Fig. 6E : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0023] Fig. 6F : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0024] Figure 6G : is a diagram illustrating one example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0025] Figure 6H : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0026] Fig.6I : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0027] Figure 6J 1 is a diagram illustrating one example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0028] Figure 6K : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0029] Figure 6L : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0030] Figure 7 : is a diagram showing a structural example of a pixel block according to a first modification example of the first embodiment of the present disclosure.

[0031] Figure 8 : is a diagram showing a structural example of a pixel block according to a first modification example of the first embodiment of the present disclosure.

[0032] Fig. 9 : is a diagram showing a structural example of a pixel block according to a second modification example of the first embodiment of the present disclosure.

[0033] Fig.10 : is a diagram showing a structural example of a pixel block according to a third modification example of the first embodiment of the present disclosure.

[0034] Fig.11 : is a diagram showing a structural example of a pixel block according to a fourth modification example of the first embodiment of the present disclosure.

[0035] Fig.12 : is a diagram showing a structural example of a pixel block according to a fourth modification example of the first embodiment of the present disclosure.

[0036] Fig.13 : is a diagram showing a structural example of a pixel block according to a fourth modification example of the first embodiment of the present disclosure.

[0037] Fig.14A : is a diagram showing a structural example of a pixel block according to a fifth modification example of the first embodiment of the present disclosure.

[0038] Fig. 14B : is a diagram showing a structural example of a pixel block according to a fifth modification example of the first embodiment of the present disclosure.

[0039] Fig.15 : is a diagram showing a structural example of a pixel block according to a sixth modification example of the first embodiment of the present disclosure.

[0040] Fig.16A : is a diagram showing a structural example of a pixel block according to a seventh modification example of the first embodiment of the present disclosure.

[0041] Fig. 16B : is a diagram showing a structural example of a pixel block according to a seventh modification example of the first embodiment of the present disclosure.

[0042] Fig.17 : is a diagram showing a structural example of a pixel block according to an eighth modification example of the first embodiment of the present disclosure.

[0043] Fig.18 : is a diagram showing a structural example of a pixel block according to the second embodiment of the present disclosure.

[0044] Fig.19A : is a diagram showing a structural example of a pixel block according to the second embodiment of the present disclosure.

[0045] Fig.19B : is a diagram showing a structural example of a pixel block according to the second embodiment of the present disclosure.

[0046] Fig. 20 : is a diagram showing a structural example of a pixel block according to the second embodiment of the present disclosure.

[0047] Fig.21A : is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0048] Fig. 21B 2 is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0049] Fig. 21C : is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0050] Fig.21D : is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0051] Fig.21E : is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0052] Fig.21F: is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0053] Figure 21G : is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0054] Fig.21H 2 is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0055] Fig.21I : is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0056] Fig.21J 2 is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0057] Figure 21K 2 is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0058] Figure 21L 2 is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0059] Figure 21M 2 is a diagram illustrating an example of a method of manufacturing an imaging element according to the second embodiment of the present disclosure.

[0060] Fig. 22 : is a diagram showing a structural example of a pixel block according to a first modification example of the second embodiment of the present disclosure.

[0061] Fig.23 : is a diagram showing a structural example of a pixel block according to a second modification example of the second embodiment of the present disclosure.

[0062] Fig.24 : is a diagram showing a structural example of a pixel block according to a third modification example of the second embodiment of the present disclosure.

[0063] Fig.25 : is a diagram showing a structural example of a pixel block according to a fourth modification example of the second embodiment of the present disclosure.

[0064] Fig.26 : is a diagram showing a structural example of a pixel block according to a fifth modification example of the second embodiment of the present disclosure.

[0065] Fig.27A : is a diagram showing a structural example of a pixel block according to a sixth modification example of the second embodiment of the present disclosure.

[0066] Fig.27B: is a diagram showing a structural example of a pixel block according to a sixth modification example of the second embodiment of the present disclosure.

[0067] Fig.28 : is a diagram showing a structural example of a pixel block according to a sixth modification example of the second embodiment of the present disclosure.

[0068] Fig.29 is a diagram illustrating another configuration example of an imaging element.

[0069] Fig.30 is a cross-sectional view showing another configuration example of the imaging element.

[0070] Fig.31 A diagram showing one example of a schematic configuration of an imaging system including an imaging device according to one embodiment and a modified example thereof.

[0071] Fig.32 It is shown in Fig.31 Schematic diagram of an example of an imaging process of the imaging system shown in .

[0072] Fig.33 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0073] Fig.34 1 is a diagram to help explain an example of the installation positions of the vehicle exterior information detection section and the imaging section.

[0074] Fig.35 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0075] Fig.36 is a block diagram describing an example of the functional configuration of a camera head and a camera control unit (CCU). DETAILED DESCRIPTION

[0076] Hereinafter, embodiments of the present disclosure will be described in detail based on the accompanying drawings. Description will be given in the following order. Note that in each of the following embodiments, the same components are represented by the same symbols, and redundant descriptions will be omitted.

[0077] 1. First Implementation

[0078] 2. Modification of the First Embodiment

[0079] 3. Second Implementation

[0080] 4. Modification of the Second Embodiment

[0081] 5. Other structural examples

[0082] 6. Application Examples

[0083] 7. Application examples for mobile objects

[0084] 8. Application examples of endoscopic surgery systems

[0085] (1. First Embodiment)

[0086] [Configuration of imaging element]

[0087] Figure 1 1 is a diagram showing a configuration example of an imaging element according to an embodiment of the present disclosure. The figure is a block diagram showing a configuration example of an imaging element 1. An electronic device according to an embodiment of the present disclosure is described by taking the imaging element 1 as an example. The imaging element 1 is a semiconductor element that generates image data of a subject. The imaging element 1 includes a pixel array section 90, a vertical drive section 93, a column signal processing section 94, and a control unit 95.

[0088] The pixel array section 90 includes a plurality of pixel blocks 100 arranged therein. In the pixel array section 90, the plurality of pixel blocks 100 are arranged in the shape of a two-dimensional matrix. In this example, the pixel block 100 includes: a plurality of pixels, a photoelectric conversion section having a photoelectric conversion section for performing photoelectric conversion of incident light; and a charge holding section (charge holding section 103a to 103d to be described later) for holding the charge generated by the photoelectric conversion. For example, a photodiode can be used for the photoelectric conversion section. In addition, a pixel circuit (a pixel circuit 120 to be described later) is arranged in each pixel block 100. The pixel circuit 120 generates a pixel signal based on the charge held in the charge holding section 103a to 103d of the pixel block 100.

[0089] The signal line 91 is wired to each pixel block 100. The pixel block 100 is controlled by a control signal transmitted by the signal line 91. In addition, a signal line 92 is wired in the pixel block 100. A pixel signal is output from the pixel block 100 to the signal line 92. It should be noted that the signal line 91 is provided for each row in a row forming a two-dimensional matrix and is wired to a plurality of pixel blocks 100 arranged in a row in a shared manner. The signal line 92 is arranged in the column direction of the two-dimensional matrix and is wired to a plurality of pixel blocks 100 arranged in one column in a shared manner.

[0090] The vertical drive section 93 generates a control signal for the above-described pixel block 100. The vertical drive section 93 in the figure generates a control signal for each row of the two-dimensional matrix of the pixel array section 90, and sequentially outputs the control signal via the signal line 91.

[0091] The column signal processing section 94 processes the pixel signals generated by the pixel blocks 100. The column signal processing section 94 in the drawing simultaneously processes the pixel signals transmitted via the signal line 92 from the plurality of pixel blocks 100 arranged in one row of the pixel array section 90. As the processing, for example, analog-to-digital conversion for converting the analog pixel signals generated by the pixel blocks 100 into digital pixel signals or correlated double sampling (CDS) for removing offset errors of the pixel signals may be performed. The processed pixel signals are output to a circuit or the like outside the imaging element 1.

[0092] The control unit 95 controls the vertical drive section 93 and the column signal processing section 94. The control unit 95 in the figure outputs a control signal via each of the signal lines 96 and 97 to control the vertical drive section 93 and the column signal processing section 94. It should be noted that the pixel array section 90 in the figure is an example of an imaging element. The column signal processing section 94 is an example of a processing circuit. In addition, the imaging element 1 in the figure is an example of an electronic device.

[0093] [Pixel configuration]

[0094] Figure 2 1 is a circuit diagram showing a configuration example of a pixel block according to a first embodiment of the present disclosure. This figure is a circuit diagram showing a configuration example of a pixel block 100. The pixel block 100 in the figure includes pixels 110a to 110d and a pixel circuit 120.

[0095] The pixel 110a includes a photoelectric conversion unit 101a, a charge transfer unit 102a, and a charge retention unit 103a. The pixel 110b includes a photoelectric conversion unit 101b, a charge transfer unit 102b, and a charge retention unit 103b. The pixel 110c includes a photoelectric conversion unit 101c, a charge transfer unit 102c, and a charge retention unit 103c. The pixel 110d includes a photoelectric conversion unit 101d, a charge conversion unit 102d, and a charge retention unit 103d. Photodiodes can be used for the photoelectric conversion units 101a to 101d. N-channel MOS transistors can be used for the charge transfer units 102a to 102d.

[0096] The pixel circuit 120 includes a reset transistor 123, a coupling transistor 124, an amplifying transistor 121, and a selecting transistor 122. N-channel MOS transistors may be used for the reset transistor 123, the coupling transistor 124, the amplifying transistor 121, and the selecting transistor 122.

[0097] As described above, the signal line 91 and the signal line 92 are wired in the pixel block 100. The signal line 91 in the figure includes signal lines TG1 to TG4, a signal line FDG, a signal line RST, and a signal line SEL. In addition, the power line Vdd is wired in the pixel block 100. The power line Vdd supplies power to the pixel block 100.

[0098] The anode of the photoelectric conversion unit 101a is grounded, and the cathode is connected to the source of the charge transfer unit 102a. The anode of the photoelectric conversion unit 101b is grounded, and the cathode is connected to the source of the charge transfer unit 102b. The anode of the photoelectric conversion unit 101c is grounded, and the cathode is connected to the source of the charge transfer unit 102c. The anode of the photoelectric conversion unit 101d is grounded, and the cathode is connected to the source of the charge transfer unit 102d.

[0099] The drains of the charge transfer units 102a to 102d are connected to the source of the coupling transistor 124, the gate of the amplifier transistor 121, and the first ends of the charge holding units 103a to 103d. The second ends of the charge holding units 103a to 103d are grounded. The drain of the coupling transistor 124 is connected to the source of the reset transistor 123. The drain of the reset transistor 123 and the drain of the amplifier transistor 121 are connected to the power supply line Vdd. The source of the amplifier transistor 121 is connected to the drain of the selection transistor 122, and the source of the selection transistor 122 is connected to the signal line 92.

[0100] The gates of the charge transfer sections 102a to 102d are connected to the signal lines TG1 to TG4, respectively. The gate of the coupling transistor 124 is connected to the signal line FDG, the gate of the reset transistor 123 is connected to the signal line RST, and the gate of the selection transistor 122 is connected to the signal line SEL.

[0101] The photoelectric conversion units 101a to 101d perform photoelectric conversion on incident light. The photoelectric conversion units 101a to 101d may include photodiodes formed on a semiconductor substrate 130 described later. The photoelectric conversion units 101a to 101d perform photoelectric conversion of incident light in an exposure period and hold charges generated by the photoelectric conversion.

[0102] The charge holding portions 103a to 103d hold charges generated by the photoelectric conversion portions 101a to 101d, respectively. The charge holding portions 103a to 103d may include a floating diffusion (FD) region as a semiconductor region formed in the semiconductor substrate 130.

[0103] The charge transfer units 102a to 102d transfer charges. The charge conversion units 102a to 102d transfer charges generated by the photoelectric conversion units 101a to 101d to the charge holding units 103a to 103d, respectively. The charge conversion unit 102a etc. transfers charges by electrically connecting the photoelectric conversion unit 101a etc. to the charge holding unit 103 etc., respectively. Control signals for the charge transfer units 102a to 102d are respectively sent through the signal lines TG1 to TG4.

[0104] The pixel circuit 120 generates a pixel signal based on the charge held by the charge holding portions 103a to 103d. As described above, the pixel circuit 120 includes the coupling transistor 124, the reset transistor 123, the amplification transistor 121, and the selection transistor 122.

[0105] The coupling transistor 124 couples the capacitance connected to its drain to the charge holding portions 103a to 103d. Through the coupling of this capacitance, the holding capacitance of the charge holding portion 103a etc. can be increased, and the sensitivity of the pixel 110a etc. can be switched. The control signal of the coupling transistor 124 is transmitted by the signal line FDG.

[0106] The reset transistor 123 resets the charge holding portions 103a to 103d. This reset can be performed by electrically connecting the charge holding portions 103a to 103d and the power supply line Vdd to release the charges of the charge holding portions 103a to 103d. At the time of this reset, the coupling transistor 124 is turned on. The control signal of the reset transistor 123 is transmitted through the signal line RST.

[0107] The amplifier transistor 121 amplifies the voltage of the charge holding portions 103a to 103d. The gate of the amplifier transistor 121 is connected to the charge holding portions 103a to 103d. Therefore, a pixel signal having a voltage corresponding to the charge held in the charge holding portions 103a to 103d is generated at the source of the amplifier transistor 121. In addition, the pixel signal can be output to the signal line 92 by turning on the selection transistor 122. The control signal for selecting the transistor 122 is transmitted by the signal line SEL.

[0108] The photoelectric conversion units 101a to 101d perform photoelectric conversion on incident light during the exposure period to generate electric charge and accumulate the electric charge in themselves. After the exposure period, the charge conversion units 102a to 102d transfer the electric charge of the photoelectric conversion units 101a to 101d to the charge holding units 103a to 103d to hold them in the charge holding units 103a to 103d. Based on the held electric charge, a pixel signal is generated by the pixel circuit 120. Note that the circuit including the amplification transistor 121 and the selection transistor 122 constitutes the signal generation unit 129.

[0109] [Pixel configuration]

[0110] Figure 3 1 is a diagram showing a structural example of a pixel block according to a first embodiment of the present disclosure. The figure is a plan view showing a structural example of pixels 110a to 110d in a pixel block 100. The pixels 110a to 110d are formed in a semiconductor substrate (a semiconductor substrate 130 described later). The pixels 110a to 110d are configured to have a square shape in a plan view. An isolation portion 144 is arranged at a boundary between the pixels 110a to 110d.

[0111] In addition, the hollow circle in the figure represents a through wiring 269. The through wiring 269 is configured to penetrate the semiconductor substrate (semiconductor substrate 230 described later) stacked on the semiconductor substrate 130. The through wiring 269 arranged in the center of the figure is connected to the charge holding portion common electrode 153. The charge holding portion common electrode 153 is an electrode commonly connected to the charge holding portions 103a to 103d (not shown). In addition, the through wiring 269 on the through wiring 269 shown in the figure is connected to the well region of the semiconductor substrate 130. As described later, the photoelectric conversion unit 101 is formed near the back side of the semiconductor substrate 130.

[0112] The charge transfer sections 102a to 102d are arranged at the respective pixels 110a to 110d. In the drawing, a gate electrode 150 of a MOS transistor included in the charge transfer section 102a and the like is shown.

[0113] It is to be noted that a well region electrode 143 to be described later is arranged by being embedded in the isolation portion 144 in which the charge holding portion common electrode 153 is arranged.

[0114] [Structure of a cross section of a pixel]

[0115] Figure 4 1 is a diagram showing a structural example of a pixel block according to a first embodiment of the present disclosure. The figure is a cross-sectional view showing a structural example of a pixel block 100 in a pixel array section 90. The pixel block 100 in the figure includes a semiconductor substrate 130, a wiring region 160, a semiconductor substrate 230, a wiring region 260, a color filter 191, and an on-chip lens 192. Note that pixels 110a and 110b are shown in the figure. The structure of the pixel block 100 will be described by taking a portion of the pixel 110a as an example. It is to be noted that Figure 4 Schematically shows the Figure 3 The shape of the cross section taken by line AB in FIG.

[0116] The semiconductor substrate 130 is a semiconductor substrate provided with the photoelectric conversion unit 101b and the like. The semiconductor substrate 130 may be made of silicon (Si), for example. The photoelectric conversion unit 101b is arranged in a well region formed in the semiconductor substrate 130. For convenience, it is assumed that the semiconductor substrate 130 in the drawings includes a p-type well region. An element (its diffusion layer) may be formed by arranging n-type and p-type semiconductor regions in the p-type well region. The rectangle shown in the semiconductor substrate 130 in the drawings represents a semiconductor region.

[0117] The isolation part 142 and the isolation part 144 are arranged in the semiconductor substrate 130 at the boundaries between the pixels 110a to 110d. These separate the pixels 110 from each other electrically and optically. The isolation part 144 is an isolation part arranged on the front side of the semiconductor substrate 130. The isolation part 144 is arranged in the opening part 159 formed in the semiconductor substrate 130. The isolation part 144 can be made of, for example, silicon oxide (SiO2).

[0118] The isolation portion 142 is an isolation portion provided on the back surface of the semiconductor substrate 130. The isolation portion 142 is provided in the opening 159 formed in the semiconductor substrate 130. The isolation portion 142 may be made of, for example, SiO2.

[0119] The semiconductor region 139 is arranged around the isolation portion 142. The semiconductor region 139 is a p-type semiconductor region having a relatively high impurity concentration. By providing the semiconductor region 139, the surface level of the semiconductor substrate 130 can be fixed. Note that a fixed charge film can be provided between the semiconductor region 139 and the isolation portion 142. The fixed charge film is a film made of a dielectric having a negative fixed charge. A hole accumulation region can be formed near the interface of the semiconductor substrate 130 by the negative fixed charge, and the influence of the interface state of the semiconductor substrate 130 can be reduced. The fixed charge film can be made of, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3) or tantalum oxide (Ta2O5).

[0120] A well region electrode 143 embedded in the semiconductor substrate 130 is provided in the isolation portion 144. The well region electrode 143 is connected to the well region of the semiconductor substrate 130 and provides a reference potential. The reference potential is provided through the through wiring 269 ( Figure 5 ) is transferred to the well region electrode 143. Note that the well region electrode 143 is provided below the charge holding portion 103. The well region electrode 143 can be made of, for example, polysilicon containing impurities.

[0121] The insulating film 145 is provided on the well region electrode 143. The insulating film 145 corresponds to a barrier film when processing an opening portion where the through wiring 269 is arranged. The insulating film 145 can be made of SiN, for example.

[0122] The photoelectric conversion unit 101 includes an n-type semiconductor region 131. Specifically, a photodiode including a pn junction formed at an interface between the n-type semiconductor region 131 and a surrounding p-type semiconductor region or a well region corresponds to the photoelectric conversion unit 101.

[0123] The charge holding portion 103 includes an n-type semiconductor region 132 having a relatively high impurity concentration. The n-type semiconductor region 132 is called a floating diffusion region. The charge holding portion 103 in the figure is disposed near the front surface of the semiconductor substrate 130. The semiconductor regions 132 of the charge holding portions 103a to 103d are connected in common through a charge holding portion common electrode 153. The charge holding portion common electrode 153 may be made of, for example, impurity-containing polysilicon.

[0124] In addition, the charge transfer unit 102 is provided near the isolation unit 142 at the corner of the pixel 110. As described above, the charge transfer unit 102 includes the gate electrode 150. When the on voltage is applied to the gate electrode 150, a channel is formed in the well region adjacent to the gate electrode 150, and the photoelectric conversion unit 101 and the charge holding unit 103 are electrically connected to each other. Therefore, the charge accumulated in the photoelectric conversion unit 101 is transferred to the charge holding unit 103. Note that the gate electrode 150 can be made of polycrystalline silicon containing impurities. In the figure, a side wall 152 is provided at the gate electrode 150. The side wall 152 is composed of an insulator installed on the side of the gate electrode 150.

[0125] The semiconductor region 133 is provided in a region adjacent to the well region electrode 143 in the semiconductor substrate 130. The semiconductor region 133 has a relatively high impurity concentration. By providing the semiconductor region 133, the resistance with the well region electrode 143 can be reduced.

[0126] Insulating films 141 and 190 are disposed on the front and back surfaces of the semiconductor substrate 130. The insulating films 141 and 190 may be made of, for example, silicon oxide (SiO2) or silicon nitride (SiN). Note that an insulating film is also provided between the gate electrode 150 and the semiconductor substrate 130. The insulating film corresponds to a gate insulating film.

[0127] The wiring region 160 is provided on the front surface of the semiconductor substrate 130, and is a region in which wiring of signals of transmission elements and the like is provided. The wiring region 160 in the figure includes an insulating layer 161. The insulating layer 161 insulates the gate electrode 150, wiring and the like arranged on the surface of the semiconductor substrate 130. The insulating layer 161 can be made of, for example, SiO2.

[0128] The semiconductor substrate 230 is a substrate composed of a semiconductor configured with the pixel circuit 120. The semiconductor substrate 230 is stacked on the semiconductor substrate 130. The back surface of the semiconductor substrate 230 is bonded to the surface of the wiring region 160 of the semiconductor substrate 130, thereby stacking the semiconductor substrates 130 and 230. Similar to the semiconductor substrate 130, the semiconductor substrate 230 can be made of Si.

[0129] As described above, the pixel circuit 120 is provided in the semiconductor substrate 230. The selection transistor 122 of the pixel circuit 120 is shown in the drawing on the semiconductor substrate 230. The semiconductor element of the pixel circuit 120 is formed by the semiconductor region 231 or the gate electrode formed in the semiconductor substrate 230. In addition, the insulating film 241 is provided on the front surface of the semiconductor substrate 230.

[0130] The wiring region 260 is provided on the front surface of the semiconductor substrate 230. The wiring region 260 includes wirings 262, contact plugs 263, and an insulating layer 261.

[0131] Similar to the insulating layer 161, the insulating layer 261 insulates the wiring and the like. The insulating layer 261 may be made of, for example, SiO2. The wiring 262 transmits a signal and the like to an element in the pixel block 100. The wiring 262 may be made of a metal such as copper (Cu) or W. The contact plug 263 electrically connects the wiring and a member in the semiconductor substrate. The contact plug 253 may be made of, for example, W and the like in a columnar shape.

[0132] The color filter 191 is an optical filter that transmits light having a predetermined wavelength among incident light. As the color filter 191, a color filter that transmits red light, green light, or blue light can be used.

[0133] The on-chip lens 192 collects incident light. The on-chip lens 192 is formed in, for example, a hemispherical shape and collects incident light on the photoelectric conversion unit 101 and the like.

[0134] Figure 5 : is a diagram showing a structural example of a pixel block according to the first embodiment of the present disclosure. Figure 4 Similarly, this figure is a cross-sectional view showing a structural example of a pixel block 100 in the pixel array section 90 . Figure 5 is a schematic diagram showing the Figure 3 Schematic diagram of the shape of the cross section taken along line CD in FIG.

[0135] As described above, the through wiring 269 connects the charge holding portion common electrode 153 and the like of the semiconductor substrate 130 to the wiring 262 of the semiconductor substrate 230. The through wiring 269 is formed in a shape that penetrates the semiconductor substrate 230. Specifically, the through wiring 269 is provided in an opening that penetrates the semiconductor substrate 230, and is insulated from the semiconductor substrate 230 by the insulating layer 251. In addition, the through wiring 269 is also connected to the well region electrode 143.

[0136] As shown in the figure, the well region electrode 143 is arranged along the boundary between the pixels 110. The reference potential is supplied to the well region of the semiconductor substrate 130 in contact with the well region electrode 143 via the semiconductor region 133. As a result, the substrate potential of the semiconductor substrate 130 can be fixed.

[0137] As described above, the pixel 110 is separated from the adjacent pixel 110 by the isolation portions 142 and 144. Therefore, it is necessary to supply a reference potential to each pixel 110. However, by configuring the through wiring 269 as a supply path for the reference potential for each pixel 110, the size (area) of each pixel 110 becomes large, making it difficult to achieve miniaturization. However, by setting the well region electrode 143 for transmitting the reference potential in the isolation portion 144 at the boundary of the pixel 110 and allowing the well region electrode 143 to be shared between adjacent pixels 110, the size of the pixel 110 can be reduced.

[0138] In addition, by providing the well region electrode 143 embedded in the isolation portion 144, the area where other components such as the charge transfer portion 102 or the charge retention portion 103 are provided on the surface of the semiconductor substrate 130 can be expanded. Therefore, the charge transfer portion 102 and the charge retention portion 103 can be provided to be separated from each other, so that the electric field concentration near the gate electrode 150 of the charge transfer portion 102 can be reduced. Therefore, defects caused by the electric field concentration such as the generation of white spots can be reduced. In addition, the channel of the charge transfer portion 102 can be expanded, so that the charge transfer characteristics of the photoelectric conversion portion 101 can be improved. For example, the short channel effect of the charge transfer portion 102 can be reduced.

[0139] Furthermore, since the number of through wirings 269 for transmitting a reference potential can be reduced, the arrangement region of the pixel circuits 120 can also be expanded in the semiconductor substrate 230 .

[0140] [Method for manufacturing imaging element]

[0141] FIG. 6A to FIG. 6L 1 is a diagram showing an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure. The drawings show an example of a method for manufacturing a pixel block 100 in the imaging element 1. The manufacturing process of the pixel block 100 will be described with reference to the drawings.

[0142] First, the hard mask 500 is provided on the semiconductor substrate 130 where the semiconductor region 131 of the photoelectric conversion unit 101 is formed. In the hard mask 500, the opening 501 is arranged at the region where the opening 159 is to be formed. Next, the semiconductor substrate 130 is etched to form the opening 159 ( Fig. 6A ).

[0143] Next, a SiN film 502 is provided on the surface of the semiconductor substrate 130 including the opening 159. Then, an opening 158 is formed at the bottom of the opening 159. Next, impurities are implanted into the semiconductor substrate 130 on the side surface of the opening 158 to form a semiconductor region 139 ( Figure 6B ).

[0144] Next, the SiN film 502 is removed. Next, the isolation portions 142 and 144 are formed. This can be performed by, for example, placing a film of components of the isolation portions 142 and 144 on the surface of the semiconductor substrate 130 including the openings 158 and 159 and grinding the surface of the semiconductor substrate 130 ( Figure 6C ). For the grinding, chemical mechanical polishing (CMP) can be used.

[0145] Next, a resist 505 is disposed on the semiconductor substrate 130. In the resist 505, an opening 506 is provided in a region of the opening 159 in which the well region electrode 143 is arranged. Next, using the resist 505 as a mask, the isolation portion 144 ( Fig.6D ).

[0146] Next, the well region electrode 143 is formed. For example, the well region electrode 143 can be formed by providing a film of a component of the well region electrode 143 on the surface of the semiconductor substrate 130 including the opening 159 and performing etching back. Then, the SiN film 507 is provided. Next, impurities are implanted into the well region electrode 143 using the SiN film 507 as a mask ( Fig. 6E ).

[0147] Subsequently, the SiN film 507 is removed, and the insulating film 145 and the isolation portion 144 are sequentially stacked in the opening 159 ( Fig. 6F ).

[0148] Next, the hard mask 503 is removed, and the surface of the semiconductor substrate 130 is ground to be flat. Next, a semiconductor region 133 is formed in the semiconductor substrate 130. This can be performed by ion implantation ( Figure 6G ).

[0149] Next, the gate electrode 150 is formed. This can be performed by providing a film of the components of the gate electrode 150 on the surface of the semiconductor substrate 130 and removing the region outside the gate electrode 150. Next, the sidewall 152 is formed. For example, the sidewall 152 can be provided by providing a film of the components of the sidewall 152 on the surface of the semiconductor substrate 130 and performing etching back ( Figure 6H ).

[0150] Next, the semiconductor region 132 of the charge holding portion 103 is formed. This can be performed by ion implantation ( Fig.6I ).

[0151] Next, a SiO2 film (not shown) is arranged as a processing stopper film. In the SiO2 film, an opening is formed in the region where the charge retention portion common electrode 153 is to be formed. Next, the charge retention portion common electrode 153 is formed. This can be performed by setting the films of the constituent components of the charge retention portion common electrode 153 and removing the region outside the charge retention portion common electrode 153. Next, impurities are injected into the charge retention portion common electrode 153 to form a conductor ( Figure 6J ).

[0152] Next, a SiN film 171 is provided on the surface of the semiconductor substrate 130. Next, an opening is formed in the SiN film 171 in a region where the through wiring 269 is to be arranged, and the wiring region 160 is arranged. Next, the through wiring 269 ( Figure 6L ).

[0153] Then, the semiconductor substrate 230 is stacked, and the back side of the semiconductor substrate 130 is ground to be thinned. Next, the back side of the semiconductor substrate 130 is processed. With the above process, the pixel block 100 can be manufactured.

[0154] As described above, in the imaging element 1 according to the first embodiment of the present disclosure, the well region electrode 143 is provided in the isolation portion 144 at the boundary of the pixel 110, and the well region electrode 143 is connected to the through wiring 269 that supplies the reference potential to the well region of the semiconductor substrate 130 of the pixel 110. As a result, the size (area) of the pixel 110 can be easily reduced.

[0155] (2. Modification of the first embodiment)

[0156] Next, a modification of the above-mentioned first embodiment will be described.

[0157] [First Modification]

[0158] Figure 7 and Figure 8 : is a diagram showing a structural example of a pixel block according to a first modification example of the first embodiment of the present disclosure. Figure 7 shows a planar structure of a pixel block 100, and Figure 8 The cross-sectional structure of the pixel block 100 is shown. Figure 7 and Figure 8 1 is a diagram showing an example in which, in the pixel block 100 , the well region electrode 143 is arranged in the isolation section 144 on the side where the charge transfer sections 102 of adjacent pixels 110 are disposed facing each other.

[0159] [Second Modification]

[0160] Fig. 92 is a diagram showing a structural example of a pixel block according to a second modification example of the first embodiment of the present disclosure. Figure 4 , is a cross-sectional view showing a structural example of the pixel block 100 in the figure. The pixel 110 in the figure shows an example of providing an isolation portion 142 made of polysilicon containing impurities. In the figure, a negative bias voltage can be applied to the isolation portion 142.

[0161] [Third Modification]

[0162] Fig.10 is a diagram showing a structural example of a pixel block according to a third modified example of the first embodiment of the present disclosure. Figure 5 , is a schematic cross-sectional view showing a structural example of the pixel block 100 in the figure. The pixel 110 in the figure shows an example in which the well region electrode 143 in the region connected to the through wiring 269 has a shape extending near the surface of the semiconductor substrate 130 .

[0163] [Fourth Modification]

[0164] Fig.11 is a diagram showing a structural example of a pixel block according to a fourth modification example of the first embodiment of the present disclosure. Figure 4 , is a cross-sectional view showing a structural example of the pixel block 100 in the figure. The pixel 110 in the figure shows an example of using a charge transfer portion 102 including a MOS transistor having a vertical transfer gate that transfers charges in the thickness direction of the semiconductor substrate 130. By providing the charge transfer portion 102 in the figure, the area of ​​the charge holding portion 103 on the surface of the pixel 110 can be expanded.

[0165] Fig.12 is a diagram showing a structural example of a pixel block according to a fourth modification example of the first embodiment of the present disclosure. Figure 3 , shows an example of the structure of the pixel block 100 in the figure. The charge transfer unit 102 in the figure includes a MOS transistor having a vertical transfer gate as described above. In addition, the gate electrode 150 in the figure shows an example of a rectangular shape in plan view.

[0166] Fig.13 1 is a diagram showing a structural example of a pixel block according to a fourth modified example of the first embodiment of the present disclosure. Fig.12 A cross-sectional view of the pixel block 100 taken along line EF.

[0167] [Fifth Modification]

[0168] Fig.14A and Fig. 14B1 is a diagram showing a structural example of a pixel block according to a fifth modification example of the first embodiment of the present disclosure. Figure 3 , showing a structural example of the pixel block 100 in the figure. Fig.14A The pixel block 100 in FIG. 1 shows an example in which the charge holding portion common electrode 153 having a rectangular shape is provided. Fig. 14B is a diagram showing an example in which the charge transfer section 102 is provided apart from the boundary of the pixel 110 .

[0169] [Sixth Modification]

[0170] Fig.15 1 is a diagram showing a structural example of a pixel block according to a sixth modification example of the first embodiment of the present disclosure. Figure 3 , is a plan view showing a structural example of the pixel block 100 in the figure. The pixel block 100 in the figure shows an example including eight pixels 110 of the pixels 110a to 110h. The pixels 110a to 110h are connected to one pixel circuit 120. The charge holding portion common electrode 153 in the figure can be formed in a shape commonly connected to the charge holding portion 103 of the pixels 110a to 110h.

[0171] [Seventh Modification]

[0172] Fig.16A and Fig. 16B 1 is a diagram showing a structural example of a pixel block according to a seventh modification example of the first embodiment of the present disclosure. Fig.15 Similarly, is a plan view showing an example of a pixel block 100 including eight pixels 110 among the pixels 110a to 110h. Note that in this figure, the dashed rectangle represents the charge holding portion common electrode 153. Fig.16A , the pixel 110a and the pixel 110b are formed to have a rectangular shape obtained by dividing a square into two. The pixel 110a and the pixel 110b can be used as phase difference pixels for detecting the phase difference of the image plane. In addition, in the case of generating a normal image signal, the charge generated by the photoelectric conversion of the pixel 110a and the pixel 110b is simultaneously transferred to the charge holding portion 103 to generate a pixel signal. It should be noted that Fig. 16B An example is shown in which the pixel 110 a , the pixel 110 b , and so on are separated by the isolation portion 144 having a notch in the center portion.

[0173] [Eighth Modification]

[0174] Fig.17 1 is a diagram showing a structural example of a pixel block according to an eighth modification example of the first embodiment of the present disclosure. Figure 3, is a plan view showing a structural example of the pixel block 100 in the figure. The figure shows an example of a pixel block 100 formed in a semiconductor substrate 130. An amplifying transistor 121 is provided in the pixel 110a in the figure. At the same time, a selecting transistor 122 is provided in a pixel 110b. In addition, a reset transistor 123 is provided in a pixel 110c. At the same time, a coupling transistor 124 is provided in a pixel 110d. An isolation region 149 is provided between the elements of the pixel circuit 120 and the charge holding portion 103. The isolation region 149 can be formed by an insulating member provided with a shallow groove-shaped opening. Also in the pixel block 100 in the figure, a well region electrode 143 is arranged by being embedded in the isolation portion 144.

[0175] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and therefore, a description thereof is omitted.

[0176] (3. Second Embodiment)

[0177] In the imaging element 1 of the first embodiment described above, the charge transfer section 102 is provided on the surface of the semiconductor substrate 130. Meanwhile, the imaging element 1 according to the second embodiment of the present disclosure is different from the first embodiment in that the charge transfer section 102 is configured by being embedded in the semiconductor substrate 130.

[0178] [Configuration of Imaging Device]

[0179] Fig.18 2 is a diagram showing a structural example of a pixel block according to a second embodiment of the present disclosure. Figure 3 1 is a plan view showing a structural example of the pixel block 100. The charge transfer unit 102 in the figure is Figure 3 The charge transfer section of the pixel block 100 in the figure is different in that the charge transfer section 102 is provided by being embedded in the semiconductor substrate 130. The charge transfer section 102 includes a gate electrode 155. The dashed rectangle in the figure represents the gate electrode 155. The gate electrode 155 has a shape embedded in the semiconductor substrate 130. The gate electrode 155 is provided adjacent to the isolation section 144. Also in the pixel block 100 in the figure, the well region electrode 143 is arranged by being embedded in the isolation section 144 at the boundary of the pixel 110.

[0180] [Configuration of Imaging Device]

[0181] Fig.19A and Fig.19B 2 is a diagram showing a structural example of a pixel block according to a second embodiment of the present disclosure. Fig.18 2 is a cross-sectional view of a structural example of a pixel block 100 shown in FIG. Fig.19A is a schematic diagram showing the Fig.18Schematic diagram of the shape of the cross section taken along line GH in FIG. Fig.19B is a schematic diagram showing the Fig.17 Illustration of the shape of the cross section taken along line IJ in FIG.

[0182] The semiconductor region 131 of the photoelectric conversion unit 101 in the figure is arranged from the rear surface to the vicinity of the front surface of the semiconductor substrate 130. In addition, the semiconductor region 132 of the charge holding unit 103 is provided on the front surface of the semiconductor substrate 130 and has a shape that occupies a wide portion of the surface of the pixel 110. The semiconductor region 137 is provided between the semiconductor regions 131 and 132. The semiconductor region 137 is formed as a p-type and separates the semiconductor regions 131 and 132. The semiconductor region 137 corresponds to a well region.

[0183] As described above, the charge transfer section 102 in the figure has a shape embedded in the semiconductor substrate 130. Specifically, the charge transfer section 102 in the figure is arranged below the surface of the semiconductor substrate 130 in contact with the wiring region 160. The gate electrode 155 is arranged adjacent to the semiconductor region 137. A channel is formed in the semiconductor region 137 adjacent to the gate electrode 155. In this way, the charge transfer section 102 in the figure constitutes a MOS transistor with a vertical transfer gate. In addition, the gate electrode 155 has a shape extending to the boundary region of the pixel 110. The through wiring 269 is connected at the portion of the gate electrode 155 extending to the boundary region of the pixel 110. As described above, the charge transfer section 102 in the figure is arranged adjacent to the isolation section 144. In addition, the through wiring 269 in the figure is an example of a columnar wiring.

[0184] The gate electrode 155 may be made of, for example, impurity-containing polysilicon. Donors such as phosphorus (P) may be used as impurities of the gate electrode 155. Incidentally, for example, a SiO2 (or SiON) film may be used as a gate insulating film. Alternatively, the gate electrode 155 may be made of a metal such as tungsten (W). In this case, a high dielectric constant (high-k) insulating film may be used as the gate insulating film.

[0185] The insulating layer 148 is provided between the gate electrode 155 and the front surface of the semiconductor substrate 130. The insulating layer 148 insulates the gate electrode 155. The insulating layer 148 may be made of, for example, SiO2. In addition, an insulating film 146 may be provided on the upper surface of the gate electrode 155. The insulating film 146 is equivalent to a stopper film during etching processing. The insulating film 146 may be made of, for example, SiN.

[0186] The semiconductor region 133 in the figure may be formed in a shape adjacent to the semiconductor region 131 of the photoelectric conversion unit 101 and adjacent to the bottom surface of the gate electrode 155 .

[0187] Fig. 202 is a diagram showing a structural example of a pixel block according to a second embodiment of the present disclosure. Fig.18 The through wiring 269 connects the well region electrode 143 .

[0188] The pixel block 100 of the second embodiment of the present disclosure can allow the size (area) of the pixel 110 to be further reduced by embedding the well region electrode 143 and the charge transfer unit 102 in the semiconductor substrate 130. In addition, the charge transfer unit 102 and the charge retention unit 103 can also be arranged separately from each other. In this case, the electric field concentration near the gate electrode 155 of the charge transfer unit 102 can be alleviated. Therefore, defects caused by electric field concentration such as the generation of white spots can be reduced. In addition, since the gate electrode 155 of the charge transfer unit 102 is configured as a vertical transfer gate, the increase in the occupied area on the surface of the pixel 110 can be prevented even when the channel length is extended. Therefore, the channel length of the charge transfer unit 102 can be easily adjusted, so that the charge transfer range can be expanded.

[0189] [Method for manufacturing imaging element]

[0190] FIG. 21A to FIG. 21M These are diagrams showing one example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure. These diagrams show an example of a manufacturing process of a pixel block 100 in the imaging element 1.

[0191] First, the semiconductor region 131 of the photoelectric conversion unit 101 is formed in the semiconductor substrate 130. This can be performed, for example, by ion implantation. Next, a hard mask 510 composed of SiN or the like is arranged on the semiconductor substrate 130. In the hard mask 500, an opening 511 is arranged at a region where the opening 159 is to be formed. Next, the semiconductor substrate 130 is etched to form the opening 159 ( Fig.21A ).

[0192] Next, set the reference Figure 6B The SiN film 502 is removed to form the opening 158. Next, the semiconductor region 139 is formed by solid phase diffusion or plasma doping. Then, the SiN film 502 is removed ( Fig. 21B ).

[0193] Next, the sidewalls of the openings 158 and 159 are oxidized. Then, polysilicon is embedded in the openings 158 and 159. Subsequently, the embedded polysilicon is etched back to place the polysilicon in the portion of the opening 158. In the process on the back side of the semiconductor substrate 130, the polysilicon is removed. For convenience, in the following process, the process with Fig.19A and the same hatched isolation portion 142 ( Fig. 21C ).

[0194] Next, the isolation portion 144 is provided in the opening 159. This can be performed by providing a component of the isolation portion 144 (e.g., SiO2) in the opening 159 and on the surface of the semiconductor substrate 130 and grinding the surface of the semiconductor substrate 130. Then, the hard mask 510 ( Fig.21D ).

[0195] Next, semiconductor region 133 and semiconductor region 137 ( Fig.21E The semiconductor region 133 may be formed by arranging a resist having an opening along the periphery of the opening 159 on the surface of the semiconductor substrate 130 and performing partial ion implantation. In addition, the semiconductor region 137 may be formed by performing ion implantation on the front surface of the semiconductor substrate 130.

[0196] Next, a hard mask 512 is provided on the surface of the semiconductor substrate 130. In the hard mask 512, an opening 520 ( Fig.21F ). Next, the semiconductor substrate 130 is etched to form an opening in the region where the gate electrode 155 is to be provided. Then, a gate insulating film is formed. Next, a component 521 of the gate electrode 155 is embedded in the opening 520. Subsequently, the gate electrode 155 ( Figure 21G ) is subjected to ion implantation such as P. In the case where polycrystalline silicon containing impurities (such as P) is provided as a constituent member of the gate electrode 155, ion implantation of the gate electrode 155 can be omitted. Note that after the opening 520 is formed, n-type or p-type ion implantation can also be performed in order to adjust the channel region when the semiconductor region is generated by self-alignment in a subsequent stage.

[0197] Next, a hard mask 513 is provided on the hard mask 512. Then, an opening 514 is formed in the hard masks 512 and 513. Next, etch-back is performed to remove the isolation portion 142 except near the bottom of the opening 159. Next, a well region electrode 143 ( Fig.21H ). By heat treatment such as treatment of the semiconductor substrate 230, impurities (for example, boron (B)) are diffused from the well region electrode 143 to the semiconductor substrate 130, and a semiconductor region 133 having a high impurity concentration is formed.

[0198] Next, a resist 515 is provided on the surface of the semiconductor substrate 130 including the opening 514 of the hard mask 512. In the resist 515, an opening 516 is provided in the region of the gate electrode 155. Next, the feature 521 is etched back to form the gate electrode 155 ( Fig.21I ).

[0199] Then, the insulating film 146 is provided on the gate electrode 155. Next, the member 517 ( Fig.21J ).

[0200] Subsequently, the hard masks 512 and 513 are removed. Then, the semiconductor region 132 is formed. This can be performed by ion implantation. Next, the oxide film on the surface of the semiconductor substrate 130 is removed, and the film 518 ( Figure 21K ).

[0201] Next, the film 518 is etched to form the charge holding portion common electrode 153. Next, the insulating layer 147 ( Figure 21L ).

[0202] Then, the wiring region 160 is arranged, the semiconductor substrate 230 is stacked, and the through wiring 269 ( Figure 21M ). Then, backside processing is performed. For example, polysilicon of the isolation portion 142 is removed, and backfilling with SiO2 or the like is performed. Using the above process, the pixel block 100 can be manufactured.

[0203] The configuration of the imaging element 1 other than this is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and therefore, description thereof is omitted.

[0204] As described above, the imaging element 1 according to the second embodiment of the present disclosure can easily reduce the size (area) of the pixel 110 by embedding the charge transfer section 102 in the semiconductor substrate 130 in addition to the well region electrode 143. In addition, since the charge transfer section 102 has a shape embedded in the semiconductor substrate 130, self-aligned ion implantation or entire surface ion implantation can be applied when forming the semiconductor region of the pixel 110, etc. The yield of the manufacturing process can be improved.

[0205] (4. Modification of the Second Embodiment)

[0206] Next, a modification of the above-mentioned second embodiment will be described.

[0207] [First Modification]

[0208] Fig. 22 2 is a diagram showing a structural example of a pixel block according to a first modification example of the second embodiment of the present disclosure. Fig.181 is a plan view showing a structural example of the pixel block 100. As shown in the figure, the through wiring 269 connected to the well region electrode 143 can also be arranged in an area other than the intersection area of ​​the isolation portion 144. In addition, the gate electrode 155 can also be formed in a square shape. Note that the gate electrode 155 can be arranged at a desired position. In addition, the charge holding portion common electrode 153 can be formed in any shape other than a rectangle. The figure shows an example in which the charge holding portion common electrode 153 is formed in a rhombus shape.

[0209] [Second Modification]

[0210] Fig.23 1 is a diagram showing a structural example of a pixel block according to a second modification of the second embodiment of the present disclosure. This figure is a plan view showing a configuration example of a pixel block 100. In addition, this figure shows an example of a pixel block 100 including pixels 110a to 110h, and Fig.15 The charge holding portion common electrode 153 in the figure may be formed in a shape commonly connected to the charge holding portions 103 of the pixels 110 a to 110 h.

[0211] [Third Modification]

[0212] Fig.24 1 is a diagram showing a structural example of a pixel block according to a third modified example of the second embodiment of the present disclosure. The figure is a plan view showing a configuration example of a pixel block 100. The figure shows an example in which the charge holding portion common electrode 153 is omitted. In the figure, a through wiring 269 is arranged for each charge holding portion 103.

[0213] [Fourth Modification]

[0214] Fig.25 1 is a diagram showing a structural example of a pixel block according to a fourth modification example of the second embodiment of the present disclosure. The figure is a plan view showing a configuration example of a pixel block 100. In addition, the figure shows an example of a pixel block 100 including pixels 110a to 110h having a rectangular shape, Fig. 16B Also in the example of this figure, the charge transfer unit 102 may be embedded in the semiconductor substrate 130. It should be noted that the same Fig.16A A structure similar to the structure in .

[0215] [Fifth Modification]

[0216] Fig.261 is a diagram showing a structural example of a pixel block according to a fifth variant of the second embodiment of the present disclosure. The figure is a cross-sectional view showing a structural example of a pixel block 100. The figure shows an example in which the insulating layer 148 on the gate electrode 155 is omitted and the semiconductor region 132 is set by extension. Note that the openings 158 and 159 at the boundary of the pixel 110 can be formed to have the same width. In this case, the opening shape does not have a step. The openings 158 and 159 can be formed by any manufacturing method. For example, the opening 158 can also be formed from the back side of the semiconductor substrate 130.

[0217] [Sixth Modification]

[0218] Fig.27A and Fig.27B : is a diagram showing a structural example of a pixel block according to a sixth modification example of the second embodiment of the present disclosure. Fig.27A is a plan view showing a structural example of the pixel block 100. Fig.27B is a cross-sectional view showing a structural example of the pixel block 100. It should be noted that Fig.27B is schematically shown along Fig.27A Illustration of the cross-sectional shape taken along line MN in FIG.

[0219] Fig.27B 142 in the figure shows an example in which the isolation portion 142 is formed of a conductive member such as impurity-containing polysilicon. The isolation portion 142 is arranged at a deeper position than the well region electrode 143. In this figure, a negative bias can be applied to the isolation portion 142. Therefore, the pinning effect can be improved. A through wiring 269 that transmits a negative bias can be set at any position inside or outside the pixel 110. Note that the isolation portion 142 in the figure is an example of an isolation portion electrode.

[0220] Fig.28 1 is a diagram showing a structural example of a pixel block according to a sixth modification of the second embodiment of the present disclosure. This figure is a cross-sectional view showing a structural example of a pixel block 100. This figure schematically shows a cross-sectional view along Fig.27A The through wiring 269 on the left side of the figure represents an example of the through wiring 269 that transmits the above-mentioned negative bias. The figure shows an example of a shape in which the well region electrode 143 in the region connected to the through wiring 269 is configured to extend near the surface of the semiconductor substrate 130.

[0221] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and therefore, a description thereof is omitted.

[0222] (5. Other configuration examples)

[0223] Fig.301 is a diagram showing another configuration example of an imaging element. The imaging element 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging element 1 has a three-dimensional structure formed by bonding the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0224] The first substrate 10 includes a plurality of sensor pixels 12 that perform photoelectric conversion in a semiconductor substrate 11. The semiconductor substrate 11 is equivalent to a specific example of the “first semiconductor substrate” of the present disclosure. The plurality of sensor pixels 12 are arranged in a matrix shape in a pixel region 13 of the first substrate 10. The second substrate 20 includes a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixel 12 in a semiconductor substrate 21, and the readout circuit 22 is provided for every four sensor pixels 12. The semiconductor substrate 21 is equivalent to a specific example of the “second semiconductor substrate” of the present disclosure. The second substrate 20 includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 includes a logic circuit 32 that processes a pixel signal in a semiconductor substrate 31. The semiconductor substrate 31 is equivalent to a specific example of the “third semiconductor substrate” of the present disclosure. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal driving circuit 35) outputs to the outside the output voltage Vout of each sensor pixel 12. In the logic circuit 32, for example, a low resistance region made of silicide formed using a self-aligned silicide process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0225] For example, the vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12 row by row. The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on the pixel signal output from each sensor pixel 12 of the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts the signal level of the pixel signal by performing, for example, CDS processing, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. For example, the horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36 ​​controls, for example, the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0226] Fig.31 is a cross-sectional view showing another configuration example of an imaging element. Fig.30 An example of a cross-sectional structure in the vertical direction of the imaging element 1 in FIG. Fig.31An example of a cross-sectional structure of a portion of the imaging element 1 that faces the sensor pixel 12 is shown. The imaging element 1 is configured by sequentially stacking a first substrate 10, a second substrate 20, and a third substrate 30, and further includes a color filter 40 and a light receiving lens 50 on the back side (light incident side) of the first substrate 10. For example, one color filter 40 and one light receiving lens 50 are provided for each sensor pixel 12. That is, the imaging element 1 is a back-illuminated type.

[0227] The first substrate 10 is formed by stacking an insulating layer 46 on a semiconductor substrate 11. The first substrate 10 includes the insulating layer 46 as a part of the interlayer insulating film 51. The insulating layer 46 is included in a gap between the semiconductor substrate 11 and a semiconductor substrate 21 to be described later. The semiconductor substrate 11 is formed of a silicon substrate. For example, the semiconductor substrate 11 has a p-well layer 42 in a part of the front surface and its vicinity and a PD 41 having a conductivity type different from that of the p-well layer 42 in other regions (regions deeper than the p-well layer 42). The p-well layer 42 is formed of a p-type semiconductor region. The PD 41 is formed of a semiconductor region of a conductivity type different from that of the p-well layer 42 (specifically, n-type). The semiconductor substrate 11 has a floating diffusion FD as a semiconductor region of a conductivity type different from that of the p-well layer 42 (specifically, n-type) in the p-well layer 42.

[0228] The first substrate 10 includes a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 has a structure in which the transfer transistor TR and the floating diffusion FD are included in a portion on the front surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 includes an element isolation portion 43 that isolates each sensor pixel 12. The element isolation portion 43 is formed to extend along the normal direction of the semiconductor substrate 11 (the direction perpendicular to the surface of the semiconductor substrate 11). The element isolation portion 43 is included between two sensor pixels 12 adjacent to each other. The element isolation portion 43 electrically isolates the sensor pixels 12 adjacent to each other from each other. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43, for example, penetrates the semiconductor substrate 11. For example, the first substrate 10 further includes a p-well layer 44, that is, a side surface of the element isolation portion 43 and in contact with the surface on the photodiode PD side. The p-well layer 44 is formed by a semiconductor region of a conductivity type different from that of the photodiode PD (specifically, a p-type). For example, the first substrate 10 further includes a fixed charge film 45 in contact with the back side of the semiconductor substrate 11. In order to suppress the generation of dark current caused by the interface state on the light-receiving surface side of the semiconductor substrate 11, the fixed charge film 45 is negatively charged. The fixed charge film 45 is formed of, for example, an insulating film having a negative fixed charge. Examples of the material of such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light-receiving surface side of the semiconductor substrate 11 by the electric field induced by the fixed charge film 45. The hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back side of the semiconductor substrate 11. The color filter 40 is in contact with the fixed charge film 45, for example, and is included at a position facing the sensor pixel 12 via the fixed charge film 45. The light receiving lens 50 is in contact with the color filter 40, for example, and is included at a position facing the sensor pixel 12 via the color filter 40 and the fixed charge film 45.

[0229] The second substrate 20 is formed by stacking an insulating layer 52 on a semiconductor substrate 21. The second substrate 20 includes the insulating layer 52 as a part of the interlayer insulating film 51. The insulating layer 52 is included in the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is formed of a silicon substrate. The second substrate 20 includes one readout circuit 22 for every four sensor pixels 12. The second substrate 20 has a structure in which the readout circuit 22 is included in a portion on the front surface side (third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 in a manner that the back surface of the semiconductor substrate 11 faces the front surface side of the semiconductor substrate 21. That is, the second substrate 20 is bonded to the first substrate 10 in a face-to-back manner. The second substrate 20 further includes an insulating layer 53 that penetrates the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The second substrate 20 includes the insulating layer 53 as a part of the interlayer insulating film 51. The insulating layer 53 is included in a manner that covers the side of the through wiring 54 described later.

[0230] The stacked body including the first substrate 10 and the second substrate 20 includes an interlayer insulating film 51 and a through wiring 54 included in the interlayer insulating film 51. The stacked body has one through wiring 54 for each sensor pixel 12. The through wiring 54 extends in the normal direction of the semiconductor substrate 21, and penetrates a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through wiring 54. Specifically, the through wiring 54 is electrically connected to the floating diffusion FD and the connection wiring 55 described later.

[0231] The stacked body including the first substrate 10 and the second substrate 20 further includes through wirings 47 and 48 included in the interlayer insulating film 51. The stacked body has one through wiring 47 and one through wiring 48 for each sensor pixel 12. The through wirings 47, 48 extend in the normal direction of the semiconductor substrate 21, penetrating a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through wirings 47 and 48. Specifically, the through wiring 47 is electrically connected to the P well layer 42 of the semiconductor substrate 11 and the wiring of the second substrate 20. The through wiring 48 is electrically connected to the transfer gate TG and the pixel drive line 23.

[0232] For example, the second substrate 20 includes a plurality of connection portions 59 electrically connected to the readout circuit 22 and the semiconductor substrate 21 in the insulating layer 52. For example, the second substrate 20 further includes a wiring layer 56 on the insulating layer 52. The wiring layer 56 includes, for example, an insulating layer 57 and a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 included in the insulating layer 57. The wiring layer 56 also includes, for example, a plurality of connection lines 55 in the insulating layer 57, wherein one connection line is provided for every four sensor pixels 12. The connection lines 55 are electrically connected to each other through the conductive wires 54, and the conductive wires 54 are electrically connected to the floating diffusion FD included in the four sensor pixels 12 of the shared readout circuit 22. Here, the total number of through-wirings 54 and 48 is greater than the total number of sensor pixels 12 included in the first substrate 10, which is twice the total number of sensor pixels 12 included in the first substrate 10. In addition, the total number of through-wirings 54, 48, and 47 is greater than the total number of sensor pixels 12 included in the first substrate 10, which is three times the total number of sensor pixels 12 included in the first substrate 10.

[0233] The wiring layer 56 also includes, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed of a metal such as copper (Cu) or aluminum (Al). Each pad electrode 58 is exposed on the front surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding between the second substrate 20 and the third substrate 30. For example, one pad electrode 58 is provided for each pair of pixel drive lines 23 and vertical signal lines 24. Here, the total number of pad electrodes 58 (or the total number of bonding between the pad electrodes 58 and the pad electrodes 64 (described later)) is less than the total number of sensor pixels 12 included in the first substrate 10.

[0234] For example, the third substrate 30 is formed by stacking an interlayer insulating film 61 on a semiconductor substrate 31. As will be described later, since the third substrate 30 is bonded on the second substrate 20 with its front surfaces facing each other, when describing the structure in the third substrate 30, the description in the vertical direction is opposite to the vertical direction in the drawings. The semiconductor substrate 31 is formed of a silicon substrate. The third substrate 30 has a structure in which the logic circuit 32 is included in a portion on the front surface side of the semiconductor substrate 31. For example, the third substrate 30 further includes a wiring layer 62 located on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and a plurality of pad electrodes 64 included in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the front surface of the wiring layer 62. Each pad electrode 64 is used for electrical connection between the second substrate 20 and the third substrate 30 and bonding between the second substrate 20 and the third substrate 30. In addition, the number of pad electrodes 64 is not necessarily plural, and even one pad electrode can achieve electrical connection with the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other through the bonding between the pad electrodes 58 and 64. That is, the gate (transmission gate TG) of the transfer transistor TR is electrically connected to the logic circuit 32 via the through wire 54 and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 in a manner that the front surface of the semiconductor substrate 31 faces the front surface side of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 in a face-to-face manner.

[0235] Fig.30 and Fig.23 The first substrate 10 and the second substrate 20 in the embodiment correspond to the semiconductor substrate 130 and the semiconductor substrate 230 of the first embodiment, respectively. A semiconductor substrate corresponding to the third substrate 30 described above may also be stacked on the semiconductor substrate 230. In addition, four or more semiconductor substrates may be stacked. Such a configuration in which three or more semiconductor substrates are stacked may be applied to each embodiment of the present disclosure.

[0236] It should be noted that the arrangement of the circuit elements constituting the pixel block 100 is not limited to Figure 5 For example, all elements of the pixel circuit 120 may be included in the semiconductor substrate 130. A pixel circuit formed of an analog circuit or a digital circuit, a signal processing circuit, a storage circuit, a logic circuit, etc. can be ideally provided in the semiconductor substrate 230 or in a semiconductor substrate that is ideally further increased.

[0237] (6. Application examples)

[0238] Fig.32 It is a diagram showing an example of a schematic configuration of an imaging system 7 including an imaging device 1 according to one embodiment and a modified example thereof.

[0239] The imaging system 7 is an electronic device such as an imaging apparatus such as a digital still camera or a video camera, or a portable terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, the imaging device 1 according to the above-described embodiment and one of its modifications, a DSP circuit 743, a frame memory 744, a display section 745, a storage section 746, an operation section 747, and a power supply section 748. In the imaging system 7, according to the imaging device 1 of one of the embodiments and its modifications, the DSP circuit 743, the frame memory 744, the display section 745, the storage section 746, the operation section 747, and the power supply section 748 are connected to each other via a bus 749.

[0240] The imaging device 1 according to one of the embodiments and its modified examples outputs image data corresponding to incident light. The DSP circuit 743 is a signal processing circuit that processes a signal (image data) output from the imaging device 1 according to one of the embodiments and its modified examples. The frame memory 744 temporarily holds the image data processed by the DSP circuit 743 for each frame. The display section 745 includes a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays a moving image or a still image captured by the imaging device 1 according to one of the embodiments and its modified examples. The storage section 746 records the image data of the moving image or the still image captured by the imaging device 1 according to the embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation section 747 issues operation commands regarding various functions of the imaging system 7 based on the operation of the user. The power supply section 748 appropriately supplies various power sources as operation power sources of the imaging device 1 according to one embodiment and its modified examples, the DSP circuit 743, the frame memory 744, the display section 745, the storage section 746, and the operation section 747 to these supply objects.

[0241] Next, the imaging process in the imaging system 7 will be described.

[0242] Fig.33 7 is a diagram showing an example of a flowchart of an imaging operation in the imaging system 7. The user instructs to start imaging by operating the operation section 747 (step S101). Then, the operation section 747 sends an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit 36) performs imaging according to a predetermined imaging scheme (step S103).

[0243] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 743. Incidentally, the image data refers to the data of all pixels of the pixel signal generated based on the charge temporarily held in the floating diffusion FD. The DSP circuit 743 performs predetermined signal processing (for example, noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 743 causes the frame memory 744 to hold the image data that has been subjected to the predetermined signal processing, and the frame memory 744 causes the storage section 746 to record the image data (step S105). In this way, imaging in the imaging system 7 is performed.

[0244] In this application example, the imaging device 1 according to one of the above-described embodiments and their modifications is applied to an imaging system 7. Therefore, the imaging device 1 can be downsized or have high definition, and thus, a downsized or high definition imaging system 7 can be provided.

[0245] (7. Application example of mobile object)

[0246] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device to be installed on any type of mobile body such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot.

[0247] Fig.34 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied. .

[0248] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.34 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0249] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device to control: a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine, a drive motor, etc., a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle, etc.

[0250] The body system control unit 12020 controls the operation of various types of equipment configured for the body according to various programs. For example, the body system control unit 12020 is used as a control device to control the following items: a keyless entry system, a smart key system, a power window device, or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, the body system control unit 12020 can receive as input radio waves transmitted from a mobile device that replaces the key or signals from various switches. The body system control unit 12020 receives these input radio waves or signals to control the door lock device, power window device, lights, etc. of the vehicle.

[0251] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the vehicle exterior, and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 may perform a process of detecting an object (such as a person, vehicle, obstacle, sign, symbol, etc. on the road), or perform a process of detecting the distance to the object.

[0252] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0253] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 may be connected to a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 may calculate the driver's fatigue level or the driver's concentration level, or may distinguish whether the driver is dozing off.

[0254] The microcomputer 12051 can calculate a control target value for a driving force generation device, a steering mechanism, or a braking device based on information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control of functions intended to implement ADAS (Advanced Driver Assistance System), which includes collision avoidance or impact buffering for the vehicle, follow-up driving based on vehicle-to-vehicle distance, vehicle speed maintenance driving, an alarm for vehicle collision, an alarm for vehicle lane deviation, and the like.

[0255] In addition, the microcomputer 12051 can control the driving force generating device, the steering mechanism, and the braking device based on the information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby performing collaborative control intended for automatic driving, etc. that is independent of the driver's operation.

[0256] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to change from high beam to low beam based on the position of the preceding vehicle or oncoming vehicle detected by the exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare by controlling the headlights.

[0257] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can notify information to the passengers of the vehicle or the outside of the vehicle in a visual or auditory manner. Fig.15 In the example of FIG. 1206 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0258] Fig.35 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0259] exist Fig.35 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0260] For example, the imaging units 12101, 12102, 12103, 12104, and 12105 may be arranged at the positions of the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper portion of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield inside the vehicle is mainly used to detect front vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0261] By the way, Fig.35 An example of the shooting range of the imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of the imaging unit 12101 arranged at the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 arranged at the side mirrors. Imaging range 12114 represents the imaging range of the imaging unit 12104 arranged at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above can be obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0262] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0263] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the leading vehicle, which specifically exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained from the leading vehicle, and perform automatic braking control (including following parking control), automatic acceleration control (including following starting control), etc. Therefore, cooperative control intended for automatic driving, etc. that does not depend on the operation of the driver, can be performed.

[0264] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, and extract the classified three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes whether the obstacles around the vehicle 12100 are obstacles that can be visually identified by the driver of the vehicle 12100, or obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0265] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 is capable of identifying pedestrians by determining whether there are pedestrians in the imaging images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following programs: a program for extracting characteristic points in the imaging images of the imaging units 12101 to 12104 as infrared cameras, and a program for determining whether it is a pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there are pedestrians in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasizing the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon representing a pedestrian at a desired position.

[0266] An exemplary vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the above components. Specifically, Figure 1 The imaging element 1 in can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, degradation of the image quality of the imaging section 12031 can be prevented.

[0267] (8. Application examples of endoscopic surgery systems)

[0268] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0269] Fig.36 It is a diagram of one example of a schematic configuration of an endoscopic surgery system to which the technology (the present technology) according to one embodiment of the present disclosure can be applied.

[0270] exist Fig.36 , a state is shown in which a surgeon (medical doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As depicted, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112, a support arm device 11120 supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0271] The endoscope 11100 includes a lens barrel 11101 of which a predetermined length region at the distal end is inserted into a body cavity of a patient 11132 and a camera 11102 connected to the proximal end of the lens barrel 11101. In the depicted example, the endoscope 11100 is depicted as including a hard scope having a hard lens barrel 11101. However, the endoscope 11100 may also include a soft scope having a soft lens barrel 11101.

[0272] The lens barrel 11101 has an opening at its distal end for mounting an objective lens. The light source device 11203 is connected to the endoscope 11100 so that light generated by the light source device 11203 is introduced into the distal end of the lens barrel 11101 through a light guide extending in the lens barrel 11101 and irradiated through the objective lens toward an observation target of the body cavity of the patient 11132. It should be noted that the endoscope 11100 may be a straight-view mirror or may be an oblique mirror or a side-view mirror.

[0273] The camera 11102 is provided with an optical system and an imaging element so that the reflected light (observation light) from the observation target is collected on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as RAW data.

[0274] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc. to integrally control the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera 11102 and performs various image processing on the image signal for displaying an image based on the image signal, such as development processing (demosaic processing).

[0275] The display device 11202 displays thereon an image based on an image signal on which image processing has been performed by the CCU 11201 under the control of the CCU 11201 .

[0276] The light source device 11203 includes a light source such as a light emitting diode (LED) or the like, and supplies irradiation light when imaging the surgical area onto the endoscope 11100 .

[0277] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information or instructions into the endoscopic surgery system 11000 through the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0278] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for burning or cutting of tissues, sealing of blood vessels, etc. The pneumoperitoneum device 11206 feeds gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity to ensure the field of view of the endoscope 11100 and the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing information related to the operation in various forms such as text, images or charts.

[0279] In addition, the light source device 11203 that supplies irradiation light when imaging the surgical area to the endoscope 11100 may include a white light source, including, for example, an LED, a laser source, or a combination thereof. When the white light source includes a combination of red, green, and blue (RGB) laser sources, since the output intensity and output time of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. Further, in this case, if the laser beams of the respective RGB laser sources are irradiated on the observation target in time, the driving of the imaging element of the camera 11102 is controlled synchronously with the irradiation time, and images corresponding to the R, G, and B colors individually can be captured in time. According to this method, a color image can be obtained even if a color filter is not provided to the imaging element.

[0280] Furthermore, the light source device 11203 can be controlled so that the output light intensity changes for each predetermined time. By controlling the driving of the imaging element of the camera 11102 in synchronization with the time of the change in light intensity to acquire images differentiated according to time, and synthesizing the images, a high dynamic range image without underexposed thick shadows and overexposed highlight areas can be generated.

[0281] Further, the light source device 11203 can be configured to supply light of a predetermined wavelength band, ready for specific light observation. In specific light observation, for example, by utilizing the wavelength dependence of the absorption of light by body tissues, using a narrow-band irradiation light compared to the irradiation light (i.e., white light) during ordinary observation, a predetermined tissue such as blood vessels on the surface of a mucosa is imaged with high contrast, which is narrow-band observation (narrow-band imaging). Alternatively, in specific light observation, fluorescence observation can be performed to obtain an image from the fluorescence generated by irradiating excitation light. In fluorescence observation, fluorescence observation (autofluorescence observation) of body tissues can be performed by irradiating excitation light on body tissues, or a fluorescent image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into body tissues and irradiating excitation light corresponding to the fluorescence wavelength of the reagent onto the body tissues. The light source device 11203 can be configured to supply such narrow-band light and / or excitation light suitable for the above-mentioned specific light observation.

[0282] Fig.29 It is a depiction Fig.36 A block diagram of an example of the functional configuration of camera 11102 and CCU 11201 is depicted in FIG.

[0283] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 for communication with each other.

[0284] The lens unit 11401 is an optical system provided at a connection position with the lens barrel 11101. Observation light collected by the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses, including a zoom lens and a focusing lens.

[0285] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). When the imaging unit 11402 is configured as a multi-board type, for example, image signals corresponding to each R, G and B are generated by each imaging element, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a three-dimensional (3D) display, respectively. If a 3D display is performed, the surgeon 11131 can more accurately understand the depth of the living tissue in the surgical area. It should be noted that when the imaging unit 11402 is configured as a multi-board type, the lens unit 11401 also provides multiple systems corresponding to each imaging element.

[0286] Furthermore, the camera unit 11402 may not necessarily be disposed on the camera head 11102. For example, the camera unit 11402 may be disposed immediately after the objective lens in the lens barrel 11101.

[0287] The driving unit 11403 includes an actuator and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Thus, the magnification and focus of the image captured by the camera unit 11402 can be appropriately adjusted.

[0288] The communication unit 11404 includes a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired by the imaging unit 11402 to the CCU 11201 through the transmission cable 11400 as RAW data.

[0289] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201 and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, such as information specifying a frame rate for capturing an image, information specifying an exposure value when capturing an image, and / or information specifying a magnification and a focus for capturing an image.

[0290] It should be noted that imaging conditions such as frame rate, exposure value, magnification or focus may be appropriately specified by the user, or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are mounted in the endoscope 11100.

[0291] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0292] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera 11102 through the transmission cable 11400.

[0293] Further, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted through electrical communication, optical communication, or the like.

[0294] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data transmitted thereto from the camera 11102 .

[0295] The control unit 11413 performs various controls related to imaging of the operation area, etc., through the endoscope 11100 , and displaying the captured image obtained by imaging the operation area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0296] Further, the control unit 11413 controls the display device 11202 to display the captured image based on the image signal that has been image-processed by the image processing unit 11412, in which the surgical area, etc. are imaged. At this time, the control unit 11413 can use various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can identify surgical tools such as forceps, etc., specific living areas, bleeding, fog when using the energy treatment tool 11112, etc. by detecting the shape, color, etc. of the edge of the object contained in the captured image. When it controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical support information in a manner overlapping with the image of the surgical area. When the surgical support information is displayed and presented to the surgeon 11131 in an overlapping manner, the burden of the surgeon 11131 can be reduced and the surgeon 11131 can continue the operation with certainty.

[0297] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable for communication of electric signals, an optical fiber for optical communication, or a composite cable for both electric communication and optical communication.

[0298] Here, although wired communication is performed by utilizing the transmission cable 11400 in the described example, communication between the camera 11102 and the CCU 11201 may also be wireless communication.

[0299] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 11402 of the endoscope 11100 or the camera 11102 in the above-mentioned components. Specifically, Figure 1 The imaging element 1 in can be applied to the image pickup unit 11402. By applying the technology according to the present disclosure to the image pickup unit 11402, it is possible to prevent degradation of the image quality of the image pickup unit 11402.

[0300] It should be noted that in this example, an endoscopic surgical system has been described as an example, however, the technology according to the present disclosure may be applied to other systems, such as a microsurgery system.

[0301] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above embodiments, and various modifications may be made without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0302] It should be noted that the effects described herein are merely examples and are not limiting, and other effects may also be achieved.

[0303] It should be noted that the present technology may also have the following configurations.

[0304] (1) An imaging element comprising:

[0305] A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; a charge holding portion that holds charges generated by the photoelectric conversion; and a charge transfer portion that transfers the charges to the charge holding portion;

[0306] a well region electrode provided by embedding the semiconductor substrate, the well region electrode being connected to a well region of the semiconductor substrate; and

[0307] The signal generating unit generates a pixel signal corresponding to the charge held in the charge holding unit.

[0308] (2) The imaging element according to (1) above, wherein the charge holding portion is provided on the front surface of the semiconductor substrate.

[0309] (3) The imaging element according to (2) above, wherein the well region electrode is provided below the charge holding portion in the semiconductor substrate.

[0310] (4) The imaging element according to any one of (1) to (3) above, wherein the well region electrode is made of polysilicon containing impurities.

[0311] (5) The imaging element according to any one of (1) to (4) above, further including a semiconductor region provided in a region adjacent to the well region electrode of the semiconductor substrate, the semiconductor region having an impurity concentration higher than that of the well region.

[0312] (6) The imaging element according to any one of (1) to (5) above,

[0313] wherein the semiconductor substrate includes a wiring region disposed adjacent to the surface, and

[0314] The charge transfer section is provided below a surface of the semiconductor substrate in contact with the wiring region.

[0315] (7) The imaging element according to (6) above, wherein the charge transfer portion transfers the charge of the photoelectric conversion portion in a thickness direction of the semiconductor substrate.

[0316] (8) The imaging element according to (6) above, wherein the charge transfer portion is provided on a well region electrode in the semiconductor substrate.

[0317] (9) The imaging element according to (8) above, wherein the charge transfer portion includes a gate electrode made of polysilicon containing an impurity.

[0318] (10) The imaging element according to any one of (1) to (9) above, further comprising: a partition provided at a boundary of the pixel.

[0319] (11) The imaging element according to (10) above, wherein the well region electrode is provided in the isolation portion.

[0320] (12) The imaging element according to the above (10), wherein the charge transfer portion is arranged adjacent to the isolation portion.

[0321] (13) The imaging element according to (10) above, wherein the charge transfer portion includes a gate electrode connected to a columnar wiring provided in the isolation portion.

[0322] (14) The imaging element according to (13) above,

[0323] wherein the semiconductor substrate includes a wiring region disposed adjacent to the surface, and

[0324] The columnar wiring is connected to the gate electrode below the surface of the semiconductor substrate in contact with the wiring region.

[0325] (15) The imaging element according to the above (10), wherein the isolation portion has a shape penetrating the semiconductor substrate.

[0326] (16) The imaging element according to the above (15), further comprising: an isolation portion electrode provided below the well region electrode of the semiconductor substrate in the isolation portion.

[0327] (17) The imaging element according to (16) above, wherein a bias voltage is applied to the separator electrode.

[0328] (18) An electronic device comprising:

[0329] A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; a charge holding portion that holds charges generated by the photoelectric conversion; and a charge transfer portion that transfers the charges to the charge holding portion;

[0330] A well region electrode is provided by embedding the semiconductor substrate, the well region electrode being connected to a well region of the semiconductor substrate;

[0331] a signal generating section that generates a pixel signal corresponding to the charge held in the charge holding section; and

[0332] A processing circuit processes pixel signals.

[0333] Explanation of symbols

[0334] 1 imaging element 90 pixel array unit 94 column signal processing unit 100 pixel block

[0335] 101, 101a, 101b, 101c, 101d photoelectric conversion unit

[0336] 102, 102a, 102b, 102c, 102d charge transfer unit

[0337] 103, 103a, 103b, 103c, 103d charge holding portion

[0338] 110, 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h pixels

[0339] 129 signal generating unit 130, 230 semiconductor substrate

[0340] 131 to 133, 137, 139 semiconductor regions 142, 144 isolation portions

[0341] 143 Well region electrode 148 Insulating layer 150, 155 Gate electrode

[0342] 153 The charge holding unit common electrode 160, 260 wiring area 269 is through-wired.

Claims

1. An imaging element, comprising: A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; a charge holding portion that holds charges generated by the photoelectric conversion; and a charge transfer portion that transfers the charges to the charge holding portion; a well region electrode, provided by embedding the semiconductor substrate, the well region electrode being connected to a well region of the semiconductor substrate; and The signal generating unit generates a pixel signal corresponding to the charge held in the charge holding unit.

2. The imaging element according to claim 1, wherein The charge holding portion is provided on the front surface of the semiconductor substrate.

3. The imaging element according to claim 2, wherein: The well region electrode is provided in the semiconductor substrate below the charge holding portion.

4. The imaging element according to claim 1, wherein The well region electrode is made of polysilicon containing impurities.

5. The imaging element according to claim 1, further comprising: A semiconductor region is provided in a region adjacent to the well region electrode of the semiconductor substrate, and has an impurity concentration higher than that of the well region.

6. The imaging element according to claim 1, in, The semiconductor substrate includes a wiring region disposed adjacent to the surface, and The charge transfer section is provided below a surface of the semiconductor substrate in contact with the wiring region.

7. The imaging element according to claim 6, wherein: The charge transfer portion transfers the charges of the photoelectric conversion portion in a thickness direction of the semiconductor substrate.

8. The imaging element according to claim 6, wherein: The charge transfer section is provided on the well region electrode in the semiconductor substrate.

9. The imaging element according to claim 8, wherein: The charge transfer section includes a gate electrode made of polysilicon containing impurities.

10. The imaging element according to claim 1, further comprising: The isolation portion is provided at a boundary of the pixel.

11. The imaging element according to claim 10, wherein The well region electrode is provided in the isolation portion.

12. The imaging element according to claim 10, wherein: The charge transfer section is arranged adjacent to the isolation section.

13. The imaging element according to claim 10, wherein: The charge transfer section includes a gate electrode connected to a columnar wiring provided in the isolation section.

14. The imaging element according to claim 13, in, The semiconductor substrate includes a wiring region disposed adjacent to the surface, and The columnar wiring is connected to the gate electrode below a surface of the semiconductor substrate in contact with the wiring region.

15. The imaging element according to claim 10, wherein The isolation portion has a shape that penetrates the semiconductor substrate.

16. The imaging element according to claim 15, further comprising: The isolation portion electrode is disposed below the well region electrode of the semiconductor substrate in the isolation portion.

17. The imaging element according to claim 16, wherein: A bias voltage is applied to the separator electrode.

18. An electronic device comprising: A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; a charge holding portion that holds charges generated by the photoelectric conversion; and a charge transfer portion that transfers the charges to the charge holding portion; A well region electrode is provided by embedding the semiconductor substrate, the well region electrode being connected to a well region of the semiconductor substrate; a signal generating section that generates a pixel signal corresponding to the charge held in the charge holding section; and The processing circuit processes the pixel signal.

Images