Imaging element and electronic device

Abstract

In the present invention, the size (non-shared area) per pixel among a plurality of pixels arranged in an imaging element is easily reduced. The imaging element has pixels and a signal generation unit. A pixel provided to an imaging element is provided with a photoelectric conversion unit that is formed on a semiconductor substrate and photoelectrically converts incident light, and a charge holding unit that is provided to be embedded in the semiconductor substrate and holds charges generated by the photoelectric conversion. A signal generation unit provided to the imaging element generates a pixel signal corresponding to the charge held by the charge holding unit.

Description

Technical Field

[0001] The present disclosure relates to an imaging element and an electronic device. Background Art

[0002] An imaging element of a complementary metal oxide semiconductor (CMOS) type in which a plurality of pixels are arranged is used. In the pixel, a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that holds the charge generated by the photoelectric conversion are arranged. A signal corresponding to the charge held in the charge holding unit is generated and output as an image signal. In such an imaging element, an imaging element in which a photoelectric conversion unit is formed near the back side of a semiconductor substrate and a charge holding unit is formed on the front side of the semiconductor substrate is proposed (for example, see Patent Document 1).

[0003] In the above-mentioned imaging element, the photoelectric conversion unit performs photoelectric conversion on the incident light irradiating the back side of the semiconductor substrate for each pixel to generate electric charge. The electric charge is transferred to the charge holding unit (floating diffusion region) formed on the front surface of the semiconductor substrate, and a signal is generated through the circuit of the pixel.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: JP 2021-077870 A Summary of the invention

[0007] Technical issues

[0008] However, in the above-mentioned technology of the related art, since the charge holding portion and the pixel circuit are arranged on the front surface of the semiconductor substrate, there is a problem that miniaturization is difficult.

[0009] Therefore, the present disclosure proposes an imaging element and an electronic device that are easily miniaturized.

[0010] Solution to the problem

[0011] An imaging element according to the present disclosure includes a pixel and a signal generating unit. A pixel includes: a photoelectric conversion unit that performs photoelectric conversion of incident light, the photoelectric conversion unit being formed in a semiconductor substrate; and a charge holding unit that holds the charge generated by the photoelectric conversion, the charge holding unit being provided by being embedded in the semiconductor substrate. The signal generating unit generates a pixel signal, the pixel signal corresponding to the charge held in the charge holding unit.

[0012] In addition, an imaging element according to the present disclosure includes a pixel, a pixel circuit, a semiconductor region, and a second embedded electrode. A pixel includes a photoelectric conversion unit that performs photoelectric conversion of incident light, the photoelectric conversion unit being formed in a semiconductor substrate having a wiring region disposed adjacent to the semiconductor substrate. The pixel circuit generates a signal based on the charge generated by the photoelectric conversion. The semiconductor region is disposed adjacent to a side surface of an opening formed in the semiconductor substrate at a boundary of the pixel and away from a surface of the semiconductor substrate in contact with the wiring region. A second embedded electrode is disposed in the opening and spaced apart from the surface of the semiconductor substrate in contact with the wiring region, and the second embedded electrode is connected to the semiconductor region.

[0013] In addition, an electronic device according to the present disclosure includes a pixel, a signal generating unit, and a processing circuit. A pixel includes: a photoelectric conversion unit that performs photoelectric conversion of incident light, the photoelectric conversion unit is formed in a semiconductor substrate; and a charge holding unit that holds the charge generated by the photoelectric conversion, the charge holding unit being set by being embedded in the semiconductor substrate. The signal generating unit generates a pixel signal, the pixel signal corresponds to the charge held in the charge holding unit. The processing circuit processes the generated pixel signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing a configuration example of an imaging element according to an embodiment of the present disclosure.

[0015] Figure 2 is a circuit diagram showing a configuration example of a pixel block according to the first embodiment of the present disclosure.

[0016] Figure 3 : is a diagram showing a structural example of a pixel block according to the first embodiment of the present disclosure.

[0017] Figure 4 is a diagram showing a structural example of a pixel block according to the first embodiment of the present disclosure.

[0018] Figure 5 is a diagram showing a structural example of a pixel block according to the first embodiment of the present disclosure.

[0019] Figure 6 is a diagram showing a structural example of a pixel block according to the first embodiment of the present disclosure.

[0020] Fig. 7A : are diagrams illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0021] Figure 7B : are diagrams illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0022] Figure 7C : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0023] Fig.7D : is a diagram illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0024] Fig. 7E : is a diagram illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0025] Figure 7F : is a diagram illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0026] Figure 7G is a diagram illustrating an embodiment of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0027] Figure 7H is a schematic diagram illustrating an example of a method for manufacturing an imaging element according to a first embodiment of the present disclosure.

[0028] Fig.7I : is a diagram illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0029] Figure 7J : are diagrams illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0030] Figure 7K : is a diagram illustrating an example of a method for manufacturing an imaging element according to the first embodiment of the present disclosure.

[0031] Figure 7L : is a diagram illustrating an example of a method of manufacturing an imaging element according to the first embodiment of the present disclosure.

[0032] Figure 8 : is a diagram showing a structural example of a pixel block according to a first modification example of the first embodiment of the present disclosure.

[0033] Fig. 9 : is a diagram showing a structural example of a pixel block according to a second modification example of the first embodiment of the present disclosure.

[0034] Fig.10 : is a diagram showing a structural example of a pixel block according to a second modification example of the first embodiment of the present disclosure.

[0035] Fig.11A : is a diagram showing a structural example of a pixel block according to a third modification example of the first embodiment of the present disclosure.

[0036] Fig. 11B : is a diagram showing a structural example of a pixel block according to a third modification example of the first embodiment of the present disclosure.

[0037] Fig. 12A : is a diagram showing a structural example of a pixel block according to a fourth modification example of the first embodiment of the present disclosure.

[0038] Fig. 12B : is a diagram showing a structural example of a pixel block according to a fourth modification example of the first embodiment of the present disclosure.

[0039] Fig.13A : is a diagram showing a structural example of a pixel block according to a fifth modification example of the first embodiment of the present disclosure.

[0040] Fig. 13B : is a diagram showing a structural example of a pixel block according to a fifth modification example of the first embodiment of the present disclosure.

[0041] Fig.14 : is a diagram showing a structural example of a pixel block according to a sixth modification example of the first embodiment of the present disclosure.

[0042] Fig.15 : is a diagram showing a structural example of a pixel block according to a second embodiment of the present disclosure.

[0043] Fig.16A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a second embodiment of the present disclosure.

[0044] Fig. 16B : is a diagram illustrating an example of a method of manufacturing an imaging element according to a second embodiment of the present disclosure.

[0045] Fig. 16C 2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure.

[0046] Fig.16D 2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure.

[0047] Fig.16E 2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure.

[0048] Fig.16F 2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure.

[0049] Figure 16G2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure.

[0050] Fig.16H : is a diagram illustrating an example of a method of manufacturing an imaging element according to a second embodiment of the present disclosure.

[0051] Fig.16I 2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure.

[0052] Fig.16J : is a diagram illustrating an example of a method of manufacturing an imaging element according to a second embodiment of the present disclosure.

[0053] Figure 16K : is a diagram illustrating an example of a method of manufacturing an imaging element according to a second embodiment of the present disclosure.

[0054] Figure 16L is a diagram illustrating an embodiment of a method of manufacturing an imaging element according to a second embodiment of the present disclosure.

[0055] Figure 16M 2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure.

[0056] Fig.17 is a diagram showing a structural example of a pixel according to a third embodiment of the present disclosure.

[0057] Fig.18A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a third embodiment of the present disclosure.

[0058] Fig.18B A diagram for explaining an embodiment of a method for manufacturing an imaging element according to a third embodiment of the present invention.

[0059] Fig. 18C : is a diagram illustrating an example of a method of manufacturing an imaging element according to a third embodiment of the present disclosure.

[0060] Fig.18D : is a diagram illustrating an example of a method of manufacturing an imaging element according to a third embodiment of the present disclosure.

[0061] Fig.18E : is a diagram showing an embodiment of a method of manufacturing an imaging element according to a third embodiment of the present invention.

[0062] Fig.19 is a diagram showing a structural example of a pixel according to a fourth embodiment of the present disclosure.

[0063] Fig. 20A: is a schematic diagram illustrating an embodiment of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0064] Fig. 20B : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0065] Fig. 20C : is a schematic diagram illustrating an embodiment of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0066] Fig.20D : is a schematic diagram illustrating an embodiment of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0067] Fig.20E : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0068] Fig.20F : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fourth embodiment of the present invention.

[0069] Figure 20G : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0070] Fig. 20H : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0071] Fig.20I : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0072] Fig. 20J : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0073] Figure 20K is a schematic diagram illustrating an example of a method for manufacturing an imaging element according to a fourth embodiment of the present disclosure.

[0074] Fig.21A : is a diagram showing a structural example of a pixel according to a first modification example of the second embodiment of the present disclosure.

[0075] Fig. 21B : is a diagram showing a structural example of a pixel according to a second modification example of the second embodiment of the present disclosure.

[0076] Fig. 21C : is a diagram showing a structural example of a pixel according to a third modification example of the second embodiment of the present disclosure.

[0077] Fig.21D : is a diagram showing a structural example of a pixel according to a fourth modification example of the second embodiment of the present disclosure.

[0078] Fig.21E : is a diagram showing a structural example of a pixel according to a fifth modification example of the second embodiment of the present disclosure.

[0079] Fig. 22 is a diagram showing a structural example of a pixel block according to a fifth embodiment of the present disclosure.

[0080] Fig.23A is a diagram showing a structural example of a pixel block according to a fifth embodiment of the present disclosure.

[0081] Fig. 23B is a diagram showing a structural example of a pixel block according to a fifth embodiment of the present disclosure.

[0082] Fig.23C is a diagram showing a structural example of a pixel block according to a fifth embodiment of the present disclosure.

[0083] Fig.24A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0084] Fig. 24B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0085] Fig.24C : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0086] Fig.25A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0087] Fig.25B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0088] Fig.25C : is a schematic diagram illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0089] Fig.26A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0090] Fig.26B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0091] Fig.26C: is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0092] Fig.27A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0093] Fig.27B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0094] Fig.27C : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0095] Fig.28A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0096] Fig.28B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0097] Fig.28C It is a diagram showing an example of a method for manufacturing an imaging element according to the fifth embodiment of the present invention.

[0098] Fig.29A It is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0099] Fig.29B 2 is a diagram illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0100] Fig.29C is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0101] Fig. 30A 1 is a diagram illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0102] Fig. 30B A diagram showing one example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure;

[0103] Fig. 30C is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0104] Fig.31A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0105] Fig.31B: are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0106] Fig.31C A diagram for explaining an example of a method for manufacturing an imaging element according to a fifth embodiment of the present invention.

[0107] Fig.32A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0108] Fig.32B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0109] Fig.32C : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0110] Fig.33A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0111] Fig.33B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0112] Fig.33C It is a diagram showing an example of a method for manufacturing an imaging element according to the fifth embodiment of the present invention.

[0113] Fig.34A : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0114] Fig.34B : are diagrams illustrating an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0115] Fig.34C : is a diagram illustrating an example of a method of manufacturing an imaging element according to a fifth embodiment of the present disclosure.

[0116] Fig.35 : is a diagram showing a structural example of a pixel block according to a first modification example of the fifth embodiment of the present disclosure.

[0117] Fig.36 : is a diagram showing a structural example of a pixel block according to a first modification example of the fifth embodiment of the present disclosure.

[0118] Fig.37A : is a diagram showing a structural example of a pixel block according to a second modification example of the fifth embodiment of the present disclosure.

[0119] Fig.37B: is a diagram showing a structural example of a pixel block according to a second modification example of the fifth embodiment of the present disclosure.

[0120] Fig.38 : is a diagram showing a structural example of a pixel block according to a third modification example of the fifth embodiment of the present disclosure.

[0121] Fig.39 : is a diagram showing a structural example of a pixel block according to a fourth modification example of the fifth embodiment of the present disclosure.

[0122] Fig.40A : is a diagram showing a structural example of a pixel block according to a fourth modification example of the fifth embodiment of the present disclosure.

[0123] Fig.40B : is a diagram showing a structural example of a pixel block according to a fourth modification example of the fifth embodiment of the present disclosure.

[0124] Fig.41 : is a diagram showing a structural example of a pixel block according to a fifth modification example of the fifth embodiment of the present disclosure.

[0125] Fig.42 : is a diagram showing a structural example of a pixel block according to a sixth modification example of the fifth embodiment of the present disclosure.

[0126] Fig.43 is a diagram showing another configuration example of an imaging element.

[0127] Fig.44 is a cross-sectional view showing another configuration example of an imaging element.

[0128] Fig.45 : is a diagram showing an example of a schematic configuration of an imaging system including an imaging device according to one of the embodiment and its modified examples.

[0129] Fig.46 It is shown Fig.45 Schematic diagram of an embodiment of an imaging process of an imaging system shown in .

[0130] Fig.47 is a block diagram illustrating an embodiment of a schematic configuration of a vehicle control system.

[0131] Fig.48 It is a diagram to help explain an embodiment of the installation positions of the vehicle exterior information detection unit and the imaging unit.

[0132] Fig.49 This is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0133] Fig.50is a block diagram depicting an example of the functional configuration of a camera head and a camera control unit (CCU). DETAILED DESCRIPTION

[0134] Hereinafter, embodiments of the present disclosure will be described in detail based on the accompanying drawings. Description will be given in the following order. Note that in each of the following embodiments, the same components are represented by the same symbols, and redundant descriptions will be omitted.

[0135] 1. First Implementation

[0136] 2. Modification of the First Embodiment

[0137] 3. Second Implementation

[0138] 4. Third Implementation

[0139] 5. Fourth embodiment

[0140] 6. Modification of the Second Embodiment

[0141] 7. Fifth Implementation

[0142] 8. Modification of the Fifth Embodiment

[0143] 9. Other configuration embodiments

[0144] 10. Application Examples

[0145] 11. Application examples for mobile objects

[0146] 12. Application examples of endoscopic surgery systems

[0147] (1. First Embodiment)

[0148] [Configuration of imaging element]

[0149] Figure 1 1 is a diagram showing a configuration example of an imaging element according to an embodiment of the present disclosure. The accompanying figure is a block diagram showing a configuration example of an imaging element 1. An electronic device according to an embodiment of the present disclosure is described by taking the imaging element 1 as an example. The imaging element 1 is a semiconductor element that generates image data of a subject. The imaging element 1 includes a pixel array section 90, a vertical drive section 93, a column signal processing section 94, and a control unit 95.

[0150] The pixel array section 90 includes a plurality of pixel blocks 100 arranged therein. In the pixel array section 90, the plurality of pixel blocks 100 are arranged in the shape of a two-dimensional matrix. In this embodiment, the pixel block 100 includes: a plurality of pixels, a photoelectric conversion section that performs photoelectric conversion of incident light; and a charge holding section (charge holding section 103a to 103d to be described later) that holds the charge generated by the photoelectric conversion. For example, a photodiode can be used for the photoelectric conversion section. In addition, a pixel circuit (a pixel circuit 120 to be described later) is arranged in each pixel block 100. The pixel circuit 120 generates a pixel signal based on the charge held in the charge holding section 103a to 103d of the pixel block 100.

[0151] The signal line 91 is wired to each pixel block 100. The pixel block 100 is controlled by a control signal transmitted by the signal line 91. In addition, a signal line 92 is wired in the pixel block 100. A pixel signal is output from the pixel block 100 to the signal line 92. It should be noted that the signal line 91 is provided for each row in a row forming a two-dimensional matrix and is wired to a plurality of pixel blocks 100 arranged in a row in a shared manner. The signal line 92 is arranged in the column direction of the two-dimensional matrix and is wired to a plurality of pixel blocks 100 arranged in one column in a shared manner.

[0152] The vertical drive section 93 generates a control signal for the above-described pixel block 100. The vertical drive section 93 in the figure generates a control signal for each row of the two-dimensional matrix of the pixel array section 90, and sequentially outputs the control signal via the signal line 91.

[0153] The column signal processing section 94 processes the pixel signals generated by the pixel blocks 100. The column signal processing section 94 in the drawing simultaneously processes the pixel signals transmitted via the signal line 92 from the plurality of pixel blocks 100 arranged in one row of the pixel array section 90. As the processing, for example, analog-to-digital conversion for converting the analog pixel signals generated by the pixel blocks 100 into digital pixel signals or correlated double sampling (CDS) for removing offset errors of the pixel signals may be performed. The processed pixel signals are output to a circuit or the like outside the imaging element 1.

[0154] The control unit 95 controls the vertical drive section 93 and the column signal processing section 94. The control unit 95 in the figure outputs a control signal via each of the signal lines 96 and 97 to control the vertical drive section 93 and the column signal processing section 94. It should be noted that the pixel array section 90 in the figure is an embodiment of an imaging element. The column signal processing section 94 is an embodiment of a processing circuit. In addition, the imaging element 1 in the figure is an embodiment of an electronic device.

[0155] [Pixel configuration]

[0156] Figure 21 is a circuit diagram showing a configuration example of a pixel block according to a first embodiment of the present disclosure. 100 is a circuit diagram showing a configuration example of a pixel block 100. The pixel block 100 in the figure includes pixels 110a to 110d and a pixel circuit 120.

[0157] The pixel 110a includes a photoelectric conversion unit 101a, a charge transfer unit 102a, and a charge retention unit 103a. The pixel 110b includes a photoelectric conversion unit 101b, a charge transfer unit 102b, and a charge retention unit 103b. The pixel 110c includes a photoelectric conversion unit 101c, a charge transfer unit 102c, and a charge retention unit 103c. The pixel 110d includes a photoelectric conversion unit 101d, a charge conversion unit 102d, and a charge retention unit 103d. Photodiodes can be used for the photoelectric conversion units 101a to 101d. N-channel MOS transistors can be used for the charge transfer units 102a to 102d.

[0158] The pixel circuit 120 includes a reset transistor 123, a coupling transistor 124, an amplifying transistor 121, and a selecting transistor 122. N-channel MOS transistors may be used for the reset transistor 123, the coupling transistor 124, the amplifying transistor 121, and the selecting transistor 122.

[0159] As described above, the signal lines 91 and 92 are wired in the pixel block 100. The signal line 91 in the figure includes signal lines TG1 to TG4, signal line FDG, signal line RST, and signal line SEL. In addition, the power line Vdd is wired in the pixel block 100. The power line Vdd supplies power to the pixel block 100.

[0160] The anode of the photoelectric conversion unit 101a is grounded, and the cathode is connected to the source of the charge transfer unit 102a. The anode of the photoelectric conversion unit 101b is grounded, and the cathode is connected to the source of the charge transfer unit 102b. The anode of the photoelectric conversion unit 101c is grounded, and the cathode is connected to the source of the charge transfer unit 102c. The anode of the photoelectric conversion unit 101d is grounded, and the cathode is connected to the source of the charge transfer unit 102d.

[0161] The drains of the charge transfer units 102a to 102d are connected to the source of the coupling transistor 124, the gate of the amplifier transistor 121, and the first ends of the charge holding units 103a to 103d. The second ends of the charge holding units 103a to 103d are grounded. The drain of the coupling transistor 124 is connected to the source of the reset transistor 123. The drain of the reset transistor 123 and the drain of the amplifier transistor 121 are connected to the power supply line Vdd. The source of the amplifier transistor 121 is connected to the drain of the selection transistor 122, and the source of the selection transistor 122 is connected to the signal line 92.

[0162] The gates of the charge transfer sections 102a to 102d are connected to the signal lines TG1 to TG4, respectively. The gate of the coupling transistor 124 is connected to the signal line FDG, the gate of the reset transistor 123 is connected to the signal line RST, and the gate of the selection transistor 122 is connected to the signal line SEL.

[0163] The photoelectric conversion units 101a to 101d perform photoelectric conversion on incident light. The photoelectric conversion units 101a to 101d may include photodiodes formed on a semiconductor substrate 130 described later. The photoelectric conversion units 101a to 101d perform photoelectric conversion of incident light in an exposure period and hold charges generated by the photoelectric conversion.

[0164] The charge holding portions 103a to 103d hold charges generated by the photoelectric conversion portions 101a to 101d, respectively. The charge holding portions 103a to 103d may include a floating diffusion (FD) region as a semiconductor region formed in the semiconductor substrate 130.

[0165] The charge transfer units 102a to 102d transfer charges. The charge conversion units 102a to 102d transfer charges generated by the photoelectric conversion units 101a to 101d to the charge holding units 103a to 103d, respectively. The charge conversion unit 102a and others transfer charges by electrically connecting the photoelectric conversion unit 101a and others to the charge holding unit 103 and others, respectively. Control signals for the charge transfer units 102a to 102d are respectively sent through the signal lines TG1 to TG4.

[0166] The pixel circuit 120 generates a pixel signal based on the charge held by the charge holding portions 103a to 103d. As described above, the pixel circuit 120 includes the coupling transistor 124, the reset transistor 123, the amplification transistor 121, and the selection transistor 122.

[0167] The coupling transistor 124 couples the capacitance connected to its drain to the charge holding portions 103a to 103d. By coupling of this capacitance, the holding capacitance of the charge holding portion 103a etc. can be increased, and the sensitivity of the pixel 110a etc. can be switched. The control signal of the coupling transistor 124 is transmitted by the signal line FDG.

[0168] The reset transistor 123 resets the charge holding portions 103a to 103d. This resetting can be performed by electrically connecting the charge holding portions 103a to 103d and the power supply line Vdd to release the charges of the charge holding portions 103a to 103d. At the time of this resetting, the coupling transistor 124 is turned on. The control signal of the reset transistor 123 is transmitted through the signal line RST.

[0169] The amplifier transistor 121 amplifies the voltage of the charge holding portions 103a to 103d. The gate of the amplifier transistor 121 is connected to the charge holding portions 103a to 103d. Therefore, a pixel signal having a voltage corresponding to the charge held in the charge holding portions 103a to 103d is generated at the source of the amplifier transistor 121. In addition, the pixel signal can be output to the signal line 92 by turning on the selection transistor 122. The control signal for selecting the transistor 122 is transmitted by the signal line SEL.

[0170] The photoelectric conversion units 101a to 101d perform photoelectric conversion on incident light during the exposure period to generate electric charge and accumulate the electric charge in themselves. After the exposure period, the charge conversion units 102a to 102d transfer the electric charge of the photoelectric conversion units 101a to 101d to the charge holding units 103a to 103d to hold them in the charge holding units 103a to 103d. Based on the held electric charge, a pixel signal is generated by the pixel circuit 120. Note that the circuit including the amplification transistor 121 and the selection transistor 122 constitutes the signal generation unit 129.

[0171] [Pixel configuration]

[0172] Figure 3 and Figure 4 is a diagram showing a structural example of a pixel block according to the first embodiment of the present disclosure. Figure 3 1 is a plan view showing an example of a configuration of pixels 110 a to 110 d in the pixel block 100 . The pixels 110 a to 110 d are formed on a semiconductor substrate 130 . Figure 3 1 is a diagram showing the structure of the pixel 110a and the like on the front surface of the semiconductor substrate 130. The pixels 110a to 110d are configured to have a square shape in a plan view. The isolation section 144 is arranged at the boundary between the pixels 110a to 110d.

[0173] In addition, the hollow circle in the figure represents a through-wire 260. The through-wire 260 is arranged to penetrate the semiconductor substrate (semiconductor substrate 230 described later) stacked on the semiconductor substrate 130. The through-wire 260 arranged in the center of the figure is commonly connected to the charge holding parts 103a to 103d (not shown). In addition, the through-wire 260 provided at the left end in the figure is connected to the well region of the semiconductor substrate 130. As described later, the photoelectric conversion part 101 is formed near the back surface of the semiconductor substrate 130.

[0174] The charge transfer sections 102a to 102d are arranged at the respective pixels 110a to 110d. Figure 3 , a gate electrode 148 of a MOS transistor included in the charge transfer portion 102a and others is shown. A coupling transistor 124 is provided in the pixel 110c. Figure 3The coupling transistor 124 includes a semiconductor region 133 constituting a drain, a semiconductor region 132 constituting a source, and a gate electrode 172. In addition, a reset transistor 123 is provided in the pixel 110d. Similar to the coupling transistor 124, the reset transistor 123 also includes semiconductor regions constituting a drain and a source, and a gate electrode.

[0175] Figure 4 1 is a diagram showing a structural example of a pixel according to the first embodiment of the present disclosure. The accompanying figure is a diagram showing an arrangement example of an amplifying transistor 121 and a selecting transistor 122 arranged on a semiconductor substrate 230. The selecting transistor 122 in the figure includes a semiconductor region 231 constituting a drain, a semiconductor region 232 constituting a source, and a gate electrode 248. Similar to the selecting transistor 122, the amplifying transistor 121 also includes semiconductor regions constituting a drain and a source, and a gate electrode.

[0176] As shown in the drawings, the amplifying transistor 121 and the selecting transistor 122 may be configured to have a ratio Figure 3 The size of the reset transistor 123 is larger than that of the transistor 124.

[0177] [Structure of a cross section of a pixel]

[0178] Figure 5 1 is a diagram showing a structural example of a pixel block according to the first embodiment of the present disclosure. The accompanying drawing is a cross-sectional view showing a structural example of a pixel block 100 in a pixel array section 90. The pixel block 100 in the accompanying drawing includes a semiconductor substrate 130, a wiring area 150, a semiconductor substrate 230, a wiring area 250, a color filter 191, and an on-chip lens 192. Note that pixels 110b and 110c are shown in the accompanying drawing. The structure of the pixel block 100 will be described by taking a part of the pixel 110c as an example. Note that the accompanying drawing schematically shows a structure along Figure 3 The shape of the cross section taken by line AB in .

[0179] The semiconductor substrate 130 is a semiconductor substrate provided with the photoelectric conversion unit 101b and the like. The semiconductor substrate 130 may be made of silicon (Si), for example. The photoelectric conversion unit 101b is arranged in a well region formed in the semiconductor substrate 130. For convenience, the semiconductor substrate 130 in the drawings is based on the premise that it includes a p-type well region. An element (its diffusion layer) may be formed by arranging n-type and p-type semiconductor regions in the p-type well region. The rectangle shown in the semiconductor substrate 130 in the drawings represents a semiconductor region.

[0180] The isolation part 142 and the isolation part 144 are arranged at the boundaries between the pixels 110a to 110d in the semiconductor substrate 130. These electrically and optically separate the pixels 110 from each other. The isolation part 144 is an isolation part provided on the front side of the semiconductor substrate 130. The isolation part 144 may be made of, for example, silicon oxide (SiO 2 ) is made.

[0181] The isolation portion 142 is an isolation portion provided on the rear side of the semiconductor substrate 130. The isolation portion 142 may be made of, for example, polycrystalline silicon. The semiconductor region 139 is provided around the isolation portion 142. The semiconductor region 139 is a p-type semiconductor region having a relatively high impurity concentration. By providing the semiconductor region 139, the surface level of the semiconductor substrate 130 can be fixed. Note that a fixed charge film may be provided between the semiconductor region 139 and the isolation portion 142. The fixed charge film is a film made of a dielectric having a negative fixed charge. A hole accumulation region can be formed near the interface of the semiconductor substrate 130 by the negative fixed charge, and the influence of the interface state of the semiconductor substrate 130 can be reduced. The fixed charge film may be made of, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) or tantalum oxide (Ta 2 O 5 ) is made.

[0182] An embedded electrode 143 embedded in the semiconductor substrate 130 is arranged between the isolation portion 142 and the isolation portion 144. The embedded electrode 143 is connected to a well region near the photoelectric conversion portion 101 of the semiconductor substrate 130 and supplies a reference potential to the well region. The reference potential is transmitted to the embedded electrode 143 through a wire 260 (not shown).

[0183] The photoelectric conversion portion 101 includes an n-type semiconductor region 131. Specifically, a photodiode including a pn junction formed at an interface between the n-type semiconductor region 131 and a surrounding p-type well region corresponds to the photoelectric conversion portion 101.

[0184] The charge holding portion 103 includes an n-type semiconductor region 134 having a relatively high impurity concentration. The n-type semiconductor region 134 is called a floating diffusion region. The charge holding portion 103 in the figure is configured in a shape embedded in a well region formed in a semiconductor substrate 130. The charge holding portions 103a, 103b, and 103d of other pixels (pixels 110a, 110b, and 110d) are similarly configured in a shape embedded in a well region of the semiconductor substrate 130.

[0185] These charge holding portions 103a to 103d are commonly connected by a charge holding portion common electrode 145. The charge holding portion common electrode 145 has a shape embedded in a partition 144 disposed at a boundary between pixels 110. The charge holding portion common electrode 145 may be made of, for example, polysilicon containing impurities.

[0186] The coupling transistor 124 is provided in the pixel 110c. The coupling transistor 124 in the drawing includes the above-mentioned semiconductor regions 132 and 133 and a gate electrode 149. The semiconductor region 133 constituting the source of the coupling transistor 124 and the charge holding portion 103c are connected through a charge holding portion connecting portion 135. Similar to the charge holding portion 103c, the charge holding portion connecting portion 135 can be composed of a semiconductor region having a relatively high impurity concentration.

[0187] The element isolation region 136 is provided between the semiconductor region 131 included in the photoelectric conversion portion 101 and the charge holding portion 103. The element isolation region 136 can be configured of, for example, a p-type semiconductor region having a relatively high impurity concentration.

[0188] In addition, the charge transfer section 102 is arranged near the isolation section 142 at the corner of the pixel 110. The charge transfer section 102 includes a MOS transistor that transfers charge in the thickness direction of the semiconductor substrate 130. As described above, the charge transfer section 102 includes a gate electrode 148. The gate electrode 148 includes a columnar portion partially embedded in the isolation section 142 and having a depth reaching near the charge holding section 103. When the on-voltage is applied to the gate electrode 148, a channel is formed in a well region adjacent to the gate electrode 148, and the photoelectric conversion section 101 and the charge holding section 103 are electrically connected to each other. Therefore, the charge accumulated in the photoelectric conversion section 101 is transferred to the charge holding section 103. The thick arrow in the figure indicates the transfer. As described above, the charge transfer section 102 is configured to be embedded in the semiconductor substrate 130. Note that the gate electrode 148 can be made of polysilicon containing impurities.

[0189] Insulating films 141 and 190 are respectively disposed on the front and back surfaces of the semiconductor substrate 130. The insulating films 141 and 190 may be made of, for example, silicon oxide (SiO 2 ), silicon nitride (SiN). Note that an insulating film is also provided between the gate electrode 149 and the semiconductor substrate 130. The insulating film corresponds to a gate insulating film.

[0190] The wiring area 150 is provided on the front surface of the semiconductor substrate 130, and is an area in which wirings for transmitting signals of the element and the like are provided. The wiring area 150 in the figure includes an insulating layer 151. The insulating layer 151 insulates the gate electrode 149, wirings, and the like arranged on the front side of the semiconductor substrate 130. The insulating layer 151 may be made of, for example, SiO 2Made.

[0191] The semiconductor substrate 230 is a semiconductor substrate on which the signal generating section 129 of the pixel circuit 120 is arranged. The semiconductor substrate 230 is stacked on the semiconductor substrate 130. The back surface of the semiconductor substrate 230 is bonded to the front side of the wiring region 150 of the semiconductor substrate 130, thereby stacking the semiconductor substrates 130 and 230. Similar to the semiconductor substrate 130, the semiconductor substrate 230 can be made of Si.

[0192] As described above, the amplifier transistor 121 and the selection transistor 122 constituting the signal generation unit 129 are arranged on the semiconductor substrate 230. The semiconductor regions 231 and 232 of the selection transistor 122 are arranged in the semiconductor substrate 230 in the drawing. In addition, the selection transistor 122 includes a gate electrode 248. At the same time, as shown in the figure, the amplifier transistor 121 represents an embodiment composed of a fin MOS transistor. It should be noted that the amplifier transistor 121 in the drawing shows an embodiment including one fin. A MOS transistor including a plurality of fins can also be used as the amplifier transistor 121. In addition, an insulating film 241 is provided on the front surface of the semiconductor substrate 230.

[0193] The wiring region 250 is provided on the front surface of the semiconductor substrate 230. The wiring region 250 includes wirings 252, contact plugs 253, and an insulating layer 251.

[0194] Similar to the insulating layer 151, the insulating layer 251 insulates wiring and the like. The insulating layer 251 may be made of, for example, SiO 2 Made.

[0195] The wire 252 transmits a signal or the like to an element in the pixel block 100. The wire 252 may be made of a metal such as copper (Cu) or W. The contact plug 253 electrically connects the wiring to a member in the semiconductor substrate. The contact plug 253 may be made of, for example, W or the like in a columnar shape.

[0196] In addition, the line 252 in the figure indicates an example of connecting the through-wire 260. As described above, the through-wire 260 connects the gate electrode 149 of the semiconductor substrate 130 and other wirings of the semiconductor substrate 230. The through-wire 260 is formed in a shape that penetrates the semiconductor substrate 230. Specifically, the through-wire 260 is provided in an opening that penetrates the semiconductor substrate 230 and is insulated from the semiconductor substrate 230 by the insulating layer 251. Note that the through-wire 260 is also connected to the charge holding portion common electrode 145.

[0197] The color filter 191 is an optical filter that transmits light having a predetermined wavelength among incident light. As the color filter 191, a color filter that transmits red light, green light, or blue light can be used.

[0198] The on-chip lens 192 collects incident light. The on-chip lens 192 is formed in, for example, a hemispherical shape and collects incident light on the photoelectric conversion unit 101 and the like.

[0199] Figure 6 is a diagram showing a structural example of a pixel block according to a first embodiment of the present disclosure. Figure 5 1 is a cross-sectional view showing a structural embodiment of a pixel block 100 in a pixel array section 90. The accompanying drawing is a diagram showing a configuration embodiment of a portion of pixels 110c and 110d, and is a diagram showing a structural embodiment of a reset transistor 123 and a coupling transistor 124. In the accompanying drawing, a semiconductor region 138 constituting a source of the reset transistor 123 and a semiconductor region 137 constituting a drain of the coupling transistor 124 are shown. An electrode 146 is provided between the semiconductor regions 138 and 137. The electrode 146 is provided at a boundary of the pixel 110 and connects the reset transistor 123 and the coupling transistor 124. By using the electrode 146, the reset transistor 123 and the coupling transistor 124 can be connected in the semiconductor substrate 130, whereby wiring or contact plugs for connection can be omitted.

[0200] [Method for manufacturing imaging element]

[0201] Fig. 7A 7M to 7M are diagrams showing an example of a method for manufacturing the imaging element according to the first embodiment of the present disclosure. The diagram shows an example of a manufacturing process of the pixel 110 in the imaging element 1. The method for manufacturing the pixel 110 will be described with reference to the drawings.

[0202] First, a well region is formed in the semiconductor substrate 130. Next, a resist 500 is disposed on the semiconductor substrate 130. In the resist 500, an opening 501 is formed in the region where the isolation portions 142 and 144 are to be formed. Next, the semiconductor substrate 130 is etched using the resist 500 as a mask to form the opening 401. Dry etching can be applied to this etching. Next, impurities are doped into the semiconductor substrate 130 in the lower layer portion of the opening 401 to form the semiconductor region 139. Next, a component constituting the isolation portion 142, such as a polycrystalline silicon film, is provided on the surface of the semiconductor substrate 130 and the opening 401. This can be performed by, for example, chemical vapor deposition (CVD). Next, the polycrystalline silicon film is etched back to form the isolation portion 142 ( Fig. 7A ).

[0203] Next, the embedded electrode 143 is formed in the opening 401 ( Figure 7B ). For example, the embedded electrode 143 may be formed by disposing an element of the embedded electrode 143 (eg, a polysilicon film containing impurities) on the surface of the semiconductor substrate 130 and the opening 401 and performing etching back.

[0204] Next, the isolation portion 144 ( Figure 7C ). For example, this can be achieved by providing a component of the isolation portion 144 (eg, SiO 2 The process is performed by removing a film (film) and grinding the surface of the semiconductor substrate 130. For this grinding, for example, chemical mechanical polishing (CMP) can be adopted.

[0205] Next, a resist 502 is provided on the surface of the semiconductor substrate 130 ( Fig.7D ). In the resist 502, an opening 503 is formed at a portion of the opening 401 where the charge retention portion common electrode 145 is to be arranged.

[0206] Next, etching back is performed using the resist 502 as a mask to form the isolation portion 144′ ( Fig. 7E ). The isolation portion 144 ′ insulates the embedded electrode 143 from the charge holding portion common electrode 145 .

[0207] Next, the charge retention portion common electrode 145 is formed in the opening 401. For example, a component of the charge retention portion common electrode 145 (e.g., a polysilicon film containing impurities) is disposed on the surface of the semiconductor substrate 130 and the opening 401, and etching back is performed, thereby enabling the charge retention portion common electrode 145 to be formed. Next, the resist 502 ( Figure 7F ).

[0208] Next, an isolation portion 144' is formed in the opening 401. This can be done by Figure 7C Next, the resist 500 ( Figure 7G ).

[0209] Next, a resist 504 is provided on the surface of the semiconductor substrate 130 ( Figure 7H ). In the resist 504, an opening 505 is formed at a region where a columnar portion of the gate electrode 148 of the charge transfer section 102 is to be formed.

[0210] Next, etching is performed using the resist 504 as a mask to form an opening 402 ( Fig.7I ).

[0211] Next, a gate electrode 148 ( Figure 7J ). For example, this can be performed by providing a film of a component of the gate electrode 148 on the surface of the semiconductor substrate 130 and the opening 402 and etching a region outside the gate electrode 148 .

[0212] Next, a semiconductor region 131, an element isolation region 136, and a semiconductor region 134 are sequentially formed in the semiconductor substrate 130. This can be performed by ion implantation. Next, a charge holding portion connection portion 135 and a semiconductor region 133 ( Figure 7K ).

[0213] Next, the gate electrode 149 and the semiconductor region 132 are formed on and in the semiconductor substrate 130 ( Figure 7L ). First, the wiring region 150 is formed on the semiconductor substrate 130. Next, the semiconductor substrate 230 is stacked on the semiconductor substrate 130. Next, the through wire 260 is formed. Through the above-mentioned steps, the imaging element 1 can be manufactured.

[0214] Note that the imaging element 1 according to the first embodiment of the present disclosure is not limited to this example. For example, a configuration in which the semiconductor substrate 230 is omitted may also be adopted. In this case, all elements of the pixel block 100 are formed on or in the semiconductor substrate 130.

[0215] As described above, the pixel 110 (pixels 110a to 110d) according to the first embodiment of the present disclosure uses the charge holding portion 103 (charge holding portions 103a to 103d) having a shape embedded in the semiconductor substrate 130. Since the charge holding portion 103 is not arranged on the surface of the semiconductor substrate 130, the size (area) of the pixel 110 can be easily reduced.

[0216] (2. Modification of the first embodiment)

[0217] Next, a modification of the imaging element 1 according to the first embodiment described above will be described.

[0218] [First Modification]

[0219] Figure 8 1 is a diagram showing a structural example of a pixel block according to a first variation of the first embodiment of the present disclosure. Figure 5 100 is a cross-sectional view of a structural embodiment of a pixel block 100. The pixel block 100 in the figure is Figure 5 The pixel block 100 in FIG. 1 is different in that the amplifying transistor 121 includes a MOS transistor having a planar gate.

[0220] [Second Modification]

[0221] Fig. 9 1 is a diagram showing a structural example of a pixel block according to a second modification example of the first embodiment of the present disclosure. Figure 3 The pixel block 100 in the figure is similar to the plan view of the structural embodiment of the pixel block 100. Figure 3The difference between the pixel block 100 in FIG. 1 and FIG. 2 is that the coupling transistor 124 is omitted. In this case, Figure 2 In the circuit diagram of FIG. 1 , the source of the reset transistor 123 is connected to the charge holding portion 103. Note that the reset transistor 123 in the drawing shows an example in which a through wire 260 connected to the power supply line Vdd is shared with the reset transistor 123 of the adjacent pixel block 100.

[0222] Fig.10 is a diagram showing a structural example of a pixel block according to a second modified example of the first embodiment of the present disclosure. Figure 5 The figure also shows a structural embodiment of the reset transistor 123 of the adjacent pixel block 100. The pixel 110a and the pixel 110d in the figure are pixels arranged in the adjacent pixel block 100.

[0223] In the pixel 110a and the pixel 110d, the reset transistor 123a and the reset transistor 123d are arranged respectively. The semiconductor region 138a constituting the drain of the reset transistor 123a and the semiconductor region 138d constituting the drain of the reset transistor 123d are commonly connected to the electrode 146. The through wire 260 is connected to the electrode 146. The power supply (Vdd) is provided to the through wire 260 through the wiring of the semiconductor substrate 230. By using this electrode 146, the power supply path can be shared in the adjacent reset transistors 123 and the through wire 260 can be reduced.

[0224] [Third Modification]

[0225] Fig.11A and Fig. 11B 1 is a diagram showing a structural example of a pixel block according to a third modification example of the first embodiment of the present disclosure. The accompanying figure is a cross-sectional view showing a structural example of a pixel 110 of a pixel block 100. For convenience, the wiring area 150 and the like are omitted in the figure.

[0226] Fig.11A 142 is a diagram showing an embodiment in which the semiconductor region 139 adjacent to the isolation portion 142 is omitted. In this case, a fixed charge film may be provided between the isolation portion 142 and the semiconductor substrate 130. Fig. 11B 1 is a diagram showing an example of providing a semiconductor region 139 formed by a solid phase diffusion method.

[0227] [Fourth Modification]

[0228] Fig. 12A and Fig. 12B 1 is a diagram showing a configuration example of a pixel block according to a fourth modification of the first embodiment of the present disclosure. This diagram illustrates an electrode for supplying a reference potential to a well region near an element of the pixel circuit 120.

[0229] Fig. 12A An example is shown in which a reference potential is supplied to a well region by an electrode 147 provided near the front surface of a semiconductor substrate 130 at a boundary of a pixel 110. The electrode 147 is formed in a shape in contact with a well region of the semiconductor substrate 130 and is connected to the well region. A through wire 260 is connected to the electrode 147. The electrode 147 may be made of, for example, polysilicon containing impurities.

[0230] Fig. 12B 14 is a diagram showing an embodiment in which a part of the isolation section 144 is omitted and the reference potential of the elements of the pixel circuit 120 is supplied from the embedded electrode 143 .

[0231] [Fifth Modification]

[0232] Fig.13A and Fig. 13B : is a diagram showing a structural example of a pixel block according to a fifth modification example of the first embodiment of the present disclosure. Fig.13A 103 is a diagram showing a modified example of the charge holding portion 103. The drawing shows an embodiment of the charge holding portion 103 having a reduced size. A hollow area adjacent to the charge holding portion 103 in the drawing represents a semiconductor region 186 containing no impurities.

[0233] Fig. 13B is a diagram showing an example of the coupling transistor 124 including a vertical transistor that transfers charges in the thickness direction of the semiconductor substrate 130 .

[0234] [Sixth Modification]

[0235] Fig.14 is a diagram showing a structural example of a pixel block according to the sixth variant of the first embodiment of the present disclosure. The accompanying drawing is a plan view showing an example of a pixel block 100 including eight pixels 110 of pixels 110a to 110h. Pixel 110a and pixel 110b are formed to have a rectangular shape obtained by dividing a square into two. In addition, pixel 110a and pixel 110b are separated by an isolation portion 144 having a cutout portion at the center. Pixel 110a and pixel 110b can be used as a phase difference pixel for detecting an image plane phase difference. In addition, in the case of generating a normal image signal, the charge generated by the photoelectric conversion of pixel 110a and pixel 110b is simultaneously transmitted to the charge holding portion 103 to generate a pixel signal.

[0236] Pixel 110c, pixel 110d, pixel 110e, pixel 110f, pixel 110g and pixel 110h may also adopt a configuration similar to pixel 110a and pixel 110b. The pixel circuit 120 of the pixel block 100 in the figure is commonly connected to the eight pixels 110. Note that in the pixel circuit 120 in the figure, the coupling transistor 124 is omitted. Also in the pixel block 100 in the accompanying drawings, the charge holding portion 103 embedded in the semiconductor substrate 130 may be used.

[0237] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and therefore, a description thereof is omitted.

[0238] (3. Second Embodiment)

[0239] In the imaging element 1 of the above-described first embodiment, the semiconductor region 134 of the charge holding portion 103 of the pixel 110 is formed by ion implantation. Meanwhile, the imaging element 1 according to the second embodiment of the present disclosure is different from the above-described first embodiment in that the semiconductor region 134 of the charge holding portion 103 is formed by thermal diffusion.

[0240] [Structure of a cross section of a pixel]

[0241] Fig.15 1 is a diagram showing a structural example of a pixel according to a second embodiment of the present disclosure. The accompanying drawing is a cross-sectional view showing a structural example of a pixel 110. In the accompanying drawing, a pixel 110a and a pixel 110b adjacent to each other are shown. The structure of the pixel 110 will be described using the pixel 110a as an example. In the pixel 110 in the accompanying drawing, a photoelectric conversion unit 101, a charge conversion unit 102, and a charge retention unit 103 are shown.

[0242] The pixel 110 in the drawing is formed in a semiconductor substrate 130. A wiring region 150 is provided on the front side of the semiconductor substrate 130. The wiring region 150 includes an insulating layer 151, wirings 152, and contact plugs 153.

[0243] The isolation section 142 and the isolation section 144 are arranged at the boundary between the pixels 110 in the semiconductor substrate 130. Figure 5 In the pixel 110 in FIG. 1 , the isolation portion 144 is provided on the front side of the semiconductor substrate 130, and the isolation portion 142 is provided on the rear side of the semiconductor substrate 130. Note that the isolation portion 142 and the isolation portion 144 are formed in a groove-shaped opening 189 formed at a boundary between the pixels 110.

[0244] The embedded electrode 171 is provided in the opening 189. The embedded electrode 171 is formed to have a shape in contact with the charge holding portion 103 and is connected to the charge holding portion 103. The embedded electrode 171 is formed to be adjacent to the side surface of the opening 189, and is arranged away from the surface of the wiring area 150 in contact with the semiconductor substrate 130. The embedded electrode 171 in the figure shows an example of being arranged between the isolation portion 142 and the isolation portion 144. It should be noted that the embedded electrode 171 in the figure shows an embodiment of the charge holding portion 103 commonly connected to the adjacent pixels 110. The embedded electrode 171 may be made of polysilicon containing impurities.

[0245] and Figure 5 Similar to the photoelectric conversion unit 101 in FIG. 1 , the photoelectric conversion unit 101 includes a semiconductor region 131 and is provided near the back surface of a semiconductor substrate 130 .

[0246] The charge holding portion 103 includes a semiconductor region 134. The charge holding portion 103 is configured in a shape embedded in the semiconductor substrate 130, similar to Figure 5 The charge holding portion 103 in the charge holding portion 103. Specifically, the charge holding portion 103 in the figure is formed in a shape adjacent to the side surface of the opening 189, and is arranged away from the surface of the wiring region 150 in contact with the semiconductor substrate 130. As described above, the charge holding portion 103 is in contact with the embedded electrode 171. The semiconductor region 134 included in the charge holding portion 103 is a semiconductor region formed in the semiconductor substrate 130 by thermal diffusion of impurities from the embedded electrode 171. That is, the same impurities as those of the embedded electrode 171 are added to the charge holding portion 103.

[0247] The embedded electrode 171 connected to the semiconductor region 134 of the charge holding portion 103 is commonly connected to the charge holding portion 103 of the adjacent pixel 110. In the drawing, the charge holding portions 103 of the pixel 110a and the pixel 110b are commonly connected to the embedded electrode 171. The contact plug 153 connected to the embedded electrode 171 forms a path for transmitting the potential (indicated as "FD" in the drawing) of the charge holding portion 103. Note that the embedded electrode 171 in the drawing is an example of a second embedded electrode.

[0248] The charge transfer portion 102 in the figure includes a vertical transistor that transfers charge in the thickness direction of the semiconductor substrate 130. The gate electrode 148 of the charge transfer portion 102 has a columnar portion having a depth reaching near the photoelectric conversion portion 101, and the columnar portion has a shape close to the charge holding portion 103. When an on-voltage is applied to the gate electrode 148, a channel is formed in a well region adjacent to the gate electrode 148, and the photoelectric conversion portion 101 and the charge holding portion 103 are electrically connected to each other. Therefore, the charge accumulated in the photoelectric conversion portion 101 is transferred to the charge holding portion 103.

[0249] The semiconductor region 181 has a relatively high impurity concentration, and transmits a reference potential to the well region of the pixel 110. The reference potential (indicated as "GND" in the figure) is transmitted to the embedded electrode 171 connected to the semiconductor region 181 via the contact plug 153. The embedded electrode 171 is commonly connected to the semiconductor region 181 of the adjacent pixel 110. In the drawing, the semiconductor region 181 of the pixel 110a and the pixel 110 to the left of the pixel 110a are commonly connected to the embedded electrode 171. Similar to the semiconductor region 134, the semiconductor region 181 is formed by thermal diffusion of impurities from the embedded electrode 171. That is, the same impurities as those of the embedded electrode 171 are added to the semiconductor regions 134 and 181.

[0250] As shown in the drawings, since the semiconductor region 134 included in the charge holding portion 103 is embedded in the semiconductor substrate 130, the charge holding portion 103 is arranged to be spaced apart from the surface of the semiconductor substrate 130. Therefore, the charge holding portion 103 can be arranged away from a member arranged on the surface of the semiconductor substrate 130, for example, the gate electrode 148. The electric field concentration between the charge holding portion 103 and the gate electrode 148 can be alleviated, and image quality degradation due to charge mixing can be prevented. In addition, by alleviating the electric field concentration, reliability can be improved. Similarly, the semiconductor region 181 for providing a reference potential to the well region can be set to be separated from the gate electrode 148. As a result, the size (area) of the pixel 110 can be easily reduced.

[0251] Note that the embedded electrode 171 may be connected to a semiconductor region of an element of the pixel circuit 120 .

[0252] [Method for manufacturing imaging element]

[0253] FIG. 16A to FIG. 16M 1 is a diagram showing an example of a method for manufacturing an imaging element according to a second embodiment of the present disclosure. The diagram shows an example of a manufacturing process of a pixel 110 in the imaging element 1. The method for manufacturing the pixel 110 will be described with reference to the drawings.

[0254] First, a well region is formed in the semiconductor substrate 130 to form the semiconductor region 131. Next, a resist 510 is disposed on the semiconductor substrate 130. In the resist 510, an opening 511 ( Fig.16A ).

[0255] Next, the semiconductor substrate 130 is etched using the resist 510 as a mask to form an opening 189 ( Fig. 16B ).

[0256] Next, the isolation portion 142 is formed in the opening 189 ( Fig. 16CFor example, the isolation portion 142 may be provided on the surface of the semiconductor substrate 130 and the opening 189 (eg, SiO 2 The isolation portion 142 is formed by etching back the isolation portion 142.

[0257] Next, a component (eg, a film 513 of polysilicon containing impurities) in which the electrode 171 is embedded is provided on the surface of the semiconductor substrate 130 and in the opening 189 ( Fig.16D ).

[0258] Next, the film 513 is etched back to form the embedded electrode 171 ( Fig.16E Next, the resist 510 is removed ( Fig.16F ).

[0259] Next, the isolation portion 144 is formed in the opening 189 ( Figure 16G This can be achieved by, for example, configuring a component of the isolation portion 144, such as SiO 2 The surface of the semiconductor substrate 130 is polished.

[0260] Next, a resist 514 is disposed on the surface of the semiconductor substrate 130. In the resist 514, an opening 515 ( Fig.16H Next, the semiconductor substrate 130 is etched using the resist 514 as a mask to form an opening 188 ( Fig.16I ).

[0261] Next, a film 516 of a component of the gate electrode 148 is provided on the surface of the semiconductor substrate 130 and in the opening 188 ( Fig.16J ). Next, a resist 517 is provided on the surface of the semiconductor substrate 130. In the resist 517, an opening 518 is formed in a region other than the region of the gate electrode 148 ( Figure 16K ).

[0262] Next, the film 516 is etched using the resist 517 as a mask to form a gate electrode 148 ( Figure 16L ).

[0263] Next, the semiconductor region 134 is formed by thermal diffusion. Subsequently, the wiring region 150 is formed on the semiconductor substrate 130 (16M). Through the above-described processes, the imaging element 1 can be manufactured.

[0264] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and therefore, a description thereof is omitted.

[0265] As described above, the imaging element 1 according to the second embodiment of the present disclosure uses the charge holding portion 103 having a shape embedded in the semiconductor substrate 130. Since the charge holding portion 103 is not arranged on the surface of the semiconductor substrate 130, the size (area) of the pixel 110 can be easily reduced.

[0266] (4. Third Embodiment)

[0267] The imaging element 1 of the above-described second embodiment uses the charge transfer portion 102 including the gate electrode 148. Meanwhile, the imaging element 1 according to the third embodiment of the present disclosure is different from the above-described third embodiment in that a side wall is provided at the gate electrode 148.

[0268] [Structure of a cross section of a pixel]

[0269] Fig.17 is a diagram showing a structural example of a pixel according to a third embodiment of the present disclosure. Fig.15 A cross-sectional view of a structural embodiment of a similar pixel 110. The gate electrode 148 in this figure has a Fig.15 The pixels 110 have different side walls.

[0270] As described above, the side wall 182 is provided at the gate electrode 148 of the charge transfer portion 102. The side wall 182 is composed of an insulator installed on the side of the gate electrode 148. In addition, an opening 183 is formed in the isolation portion 144 in the figure.

[0271] [Method for manufacturing imaging element]

[0272] FIG. 18A to FIG. 18E 1 is a diagram showing an example of a method for manufacturing an imaging element according to a third embodiment of the present invention. The diagram shows an example of a manufacturing process of a pixel 110 in the imaging element 1. The method for manufacturing the pixel 110 will be described with reference to the drawings.

[0273] First, execute FIG. 16A to FIG. 16L The gate electrode 148 is formed on the semiconductor substrate 130 by a process Fig.18A ). At this time, Fig.16D In the process of, a polysilicon film 513 containing no impurities is used. Similarly, in Fig.16J In the method, a polysilicon film 516 containing no impurities is used. Next, the isolation portion 144 is etched to form an opening 183 ( Fig.18B ).

[0274] Next, the sidewall 182 is disposed at the gate electrode 148 ( Fig.18B ). For example, the sidewall 182 may be provided by providing a film of a component of the sidewall 182 on the surface of the semiconductor substrate 130 and in the opening 183 and performing etching back.

[0275] Next, impurities are implanted into the gate electrode 148 and the embedded electrode 171 ( Fig.18D ). This reduces the resistance of the gate electrode 148 and the embedded electrode 171.

[0276] Next, the semiconductor region 134 is formed by thermal diffusion. First, the wiring region 150 ( Fig.18E ). Through the above-mentioned process, the imaging element 1 can be manufactured.

[0277] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the second embodiment of the present disclosure, and therefore, description thereof is omitted.

[0278] As described above, the imaging element 1 according to the third embodiment of the present disclosure uses the gate electrode 148 having the sidewall 182. The resistance of the gate electrode 148 and the embedded electrode 171 can be reduced by ion implantation.

[0279] (5. Fourth Embodiment)

[0280] In the imaging element 1 of the third embodiment described above, the side wall 182 is provided at the gate electrode 148. On the other hand, the imaging element 1 according to the fourth embodiment of the present disclosure is different from the above embodiments in that the side wall 182 having a shape covering the stepped portion formed near the opening 189 of the semiconductor substrate 130 is used.

[0281] [Structure of a cross section of a pixel]

[0282] Fig.19 1 is a diagram showing a structural example of a pixel according to a fourth embodiment of the present disclosure. Fig.15 A cross-sectional view of a structural embodiment of a similar pixel 110. A step 185 is formed in an opening 189 in the drawing. The step 185 can be formed by overlappingly forming an opening having a width greater than the width of the opening 189. In addition, the side wall 184 in the region adjacent to the step 185 has a shape reaching the bottom portion of the step 185. In addition, the semiconductor region 134 of the charge holding portion 103 is formed in a shape adjacent to the bottom of the step 185.

[0283] Since the gate electrode 148 and the semiconductor region 134 on the surface of the semiconductor substrate 130 are separated by the step 185 , the concentration of the electric field can be further alleviated. In addition, the semiconductor region 134 can be insulated by the sidewall 184 .

[0284] [Method for manufacturing imaging element]

[0285] FIG. 20A to FIG. 20K1 is a diagram showing an example of a method for manufacturing an imaging element according to a fourth embodiment of the present disclosure. The diagram shows an example of a manufacturing process of a pixel 110 in the imaging element 1. The method for manufacturing the pixel 110 will be described with reference to the drawings.

[0286] First, a well region is formed in the semiconductor substrate 130 to form the semiconductor region 131. Next, a resist 520 is disposed on the semiconductor substrate 130. In the resist 520, an opening 521 ( Fig. 20A ).

[0287] Next, the semiconductor substrate 130 is etched using the resist 520 as a mask to form openings 188 and 189 ( Fig. 20B ).

[0288] Next, an insulating film 141 ( Fig. 20C Next, a resist 522 is provided on the surface of the semiconductor substrate 130 and in the opening 188 ( Fig.20D ). An opening 523 is formed in the resist 522 in the region of the opening 189 .

[0289] Next, etching is performed using the resist 502 as a mask to remove the insulating film 141 in the opening 189. Next, the isolation portion 142 ( Fig.20E ).

[0290] Then, the resist 522 is removed. Subsequently, a film 524 of a component of the gate electrode 148 is provided on the surface of the semiconductor substrate 130 and in the openings 188 and 189 ( Fig.20F ).

[0291] Next, a resist 525 is provided on the surface of the semiconductor substrate 130. In the resist 525, an opening 526 ( Figure 20G ).

[0292] Next, the semiconductor substrate 130 is etched using the resist 525 as a mask to form a step 185 ( Fig. 20H ). Then, the resist 525 is removed. Next, the gate electrode 148 is formed. Then, the sidewall 184 ( Fig.20I ).

[0293] Next, impurities are implanted into the gate electrode 148 and the embedded electrode 171 ( Fig. 20J ). Next, the semiconductor region 134 is formed by thermal diffusion. Subsequently, the wiring region 150 ( Figure 20K ). Through the above-mentioned process, the imaging element 1 can be manufactured.

[0294] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the third embodiment of the present disclosure, and therefore, a description thereof is omitted.

[0295] As described above, the imaging element 1 according to the fourth embodiment of the present disclosure can further relax the concentration of the electric field by forming the step 185 that separates the gate electrode 148 from the semiconductor region 134 of the charge holding portion 103 .

[0296] (6. Modification of the Second Embodiment)

[0297] Next, a modification of the second embodiment will be described.

[0298] [First Modification]

[0299] Fig.21A is a diagram showing a structural example of a pixel according to a first modification example of the second embodiment of the present disclosure. Fig.17 A cross-sectional view of a similar structural embodiment of pixel 110. This figure shows an embodiment using a gate electrode 148 with a planar gate.

[0300] [Second Modification]

[0301] Fig. 21B is a diagram showing a structural example of a pixel according to a second modification example of the second embodiment of the present disclosure. Fig.15 A cross-sectional view of a similar structural embodiment of the pixel 110. The figure shows the charge transfer section 102 including the gate electrode 148, which has a shape that does not overlap with the opening 189 when viewed from the normal direction of the surface of the semiconductor substrate 130. By making the gate electrode 148 close to the periphery of the opening 189, the size (area) of the pixel 110 can be further reduced.

[0302] [Third Modification]

[0303] Fig. 21C is a diagram showing a structural example of a pixel according to a third modification example of the second embodiment of the present disclosure. Fig.15 A cross-sectional view of a similar structural embodiment of the pixel 110. This figure shows an embodiment in which the isolation portion 142 having a shape reaching the rear surface of the semiconductor substrate 130 is provided.

[0304] [Fourth Modification]

[0305] Fig.21D is a diagram showing a structural example of a pixel according to a fourth modification example of the second embodiment of the present disclosure. Fig.15A cross-sectional view of an example of a structure of a similar pixel 110. This figure shows an example in which the embedded electrode 171 is adjacent to one side surface of the opening 189. This figure shows an example in which one charge transfer portion 102 is connected to the charge holding portion 103.

[0306] [Fifth Modification]

[0307] Fig.21E 1 is a diagram showing a structural example of a pixel according to a fifth modification of the second embodiment of the present disclosure. The accompanying drawing is a plan view showing a structural example of a pixel 110. The figure shows an example in which four charge transfer units 102 (charge transfer units 102a to 102d) are connected to a charge holding unit 103.

[0308] The pixel 110 of this embodiment can generate a pixel signal corresponding to visible light or infrared light. In addition, the pixel 110 of this embodiment can also be applied to imaging elements other than imaging elements.

[0309] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the second embodiment of the present disclosure, and therefore, description thereof is omitted.

[0310] (7. Fifth embodiment)

[0311] The fifth embodiment of the present invention proposes an imaging element 1 that reduces the number of pixel circuits 120 and connection portions connecting a plurality of pixels 110 and the pixel circuits 120 by increasing the number of pixels 110 connected to the pixel circuits 120 in the pixel block 100 .

[0312] The imaging element 1 of the above-described first embodiment uses a pixel block 100 including four pixels 110 and a pixel circuit 120. Meanwhile, the imaging element 1 according to the fifth embodiment of the present disclosure is different from the above-described first embodiment in that a pixel block 100 including eight pixels 110 is used. The pixel block 100 according to the fifth embodiment of the present disclosure includes a pixel 110a, a pixel 110b, a pixel 110c, a pixel 110d, a pixel 110e, a pixel 110f, a pixel 110g, and a pixel 110h.

[0313] [Pixel configuration]

[0314] Fig. 221 is a diagram showing a structural example of a pixel block according to a fifth embodiment of the present disclosure. The accompanying drawings are plan views showing a structural example of pixels 110a to 110h in a pixel block 100. A charge transfer unit 102 is arranged in each pixel 110. For example, a charge transfer unit 102a is arranged in the pixel 110a. The charge transfer unit 102 includes a gate electrode 148. The charge transfer unit 102 includes a MOS transistor having a vertical gate described later. Note that a MOS transistor having a flat gate can also be applied to the charge transfer unit 102.

[0315] In the pixel block 100, a plurality of embedded electrodes having a shape embedded in the semiconductor substrate 130 are arranged. Specifically, in the semiconductor substrate 130, the above-mentioned charge holding portion common electrode 145 and the embedded electrode 179 that transmits the reference potential to the well region in the semiconductor substrate 130 are arranged. The dashed rectangle in the figure represents these embedded electrodes. In the pixel block 100 in the accompanying drawings, the charge holding portion common electrodes 145a and 145b and the embedded electrodes 179a and 179b are shown. The figure shows an embodiment in which the charge holding portion common electrode 145 and the embedded electrode 179 are formed in a rectangular shape in a plan view. Note that the charge holding portion common electrode 145 and the embedded electrode 179 can also be formed in a cross shape in a plan view. Alternatively, the charge holding portion common electrode 145 and the embedded electrode 179 may have different shapes. As shown in the figure, the charge holding portion common electrode 145 and the embedded electrode 179 may have a shape in which a portion thereof contacts the semiconductor region of the semiconductor substrate 130. The details of the structure of the charge holding portion common electrode 145 and the embedded electrode 179 will be described later.

[0316] The charge retention portion common electrode 145a is arranged near the pixels 110a to 110d and is commonly connected to the charge retention portions 103 of these pixels 110. Furthermore, the charge retention portion common electrode 145b is arranged near the pixels 110e to 110h and is commonly connected to the charge retention portions 103 of these pixels 110.

[0317] The pixel block 100 in the figure also includes a plurality of embedded wirings. The embedded wirings are embedded in the semiconductor substrate 130 at the boundaries between the pixels 110 to connect the embedded electrodes to each other. Specifically, the pixel block 100 in the figure includes: a charge holding portion wiring 160, which is an embedded wiring connecting the charge holding portion common electrode 145; and an embedded wiring 165, which is an embedded wiring connecting the embedded electrode 179. The figure shows an embodiment in which the charge holding portion wiring 160 and the embedded wiring 165 are arranged in the isolation portion 144. The charge holding portion wiring 160 connects the charge holding portion common electrode 145a and the charge holding portion common electrode 145b. Similarly, the embedded wiring 165 connects the embedded electrode 179a and the embedded electrode 179b. In addition, the through wire 260 is connected to each of the charge holding portion wiring 160 and the embedded wiring 165. The charge holding portion wiring 160 is connected to the pixel circuit 120 (not shown) via the through wire 260.

[0318] [Structure of a cross section of a pixel]

[0319] FIG. 23A to FIG. 23C 1 is a diagram showing a structural example of a pixel block according to a fifth embodiment of the present disclosure. The accompanying drawings are cross-sectional diagrams showing a structural example of a pixel block 100 in a pixel array section 90. Fig.23A is schematically shown along Fig. 22 Illustration of the shape of the cross section taken along line EF in FIG. Fig. 23B is schematically shown along Fig. 22 Schematic diagram of the shape of the cross section taken along line GH in FIG. Fig.23C is schematically shown along Fig. 22 Illustration of the shape of the cross section taken along line IJ in FIG.

[0320] exist Fig.23A , the charge retention unit common electrodes 145a and 145b are embedded in the isolation portion 144. The charge retention unit wiring 160 is arranged between the charge retention unit common electrodes 145a and 145b and connects the charge retention unit common electrodes 145a and 145b. Note that the figure shows an embodiment in which the charge retention unit wiring 160 has a shape in which its upper surface is in contact with the surface of the semiconductor substrate 130. By adopting this structure, the through wire 260 can be arranged at any position on the upper surface of the charge retention unit wire 160. The charge retention unit wiring 160 can be composed of, for example, polycrystalline silicon containing impurities or metals. It should be noted that, similar to the first embodiment of the present invention, the imaging element 1 according to the fifth embodiment of the present invention includes a stacked semiconductor substrate 130 and a semiconductor substrate 230. The pixel circuit 120 (not shown) is provided in the semiconductor substrate 230.

[0321] exist Fig. 23B, the charge holding portion wiring 160 has a shape embedded in the isolation portion 144. Therefore, the charge holding portion wiring 160 is insulated from the well region and others of the semiconductor substrate 130. Similarly, the embedded wiring 165 also has a shape embedded in the isolation portion 144. Note that the semiconductor region 134 included in the charge holding portion 103 in the figure can be formed by ion implantation.

[0322] exist Fig.23C In the example shown in the figure, the embedded electrodes 179a and 179b are embedded in the isolation portion 144. In addition, the embedded electrode 179 has a shape in which the side surface perpendicular to or parallel to the paper surface is in contact with the well region of the semiconductor substrate 130 and is electrically connected to the well region. The embedded wiring 165 is arranged between the embedded electrodes 179a and 179b and connects the embedded electrodes 179a and 179b. In addition, in the example shown in the figure, the embedded wiring 165 has a shape in which the upper surface is in contact with the surface of the semiconductor substrate 130. The embedded electrode 179 and the embedded wiring 165 can be made of, for example, polysilicon containing impurities or metal.

[0323] [Method for manufacturing imaging element]

[0324] FIG. 24A to FIG. 24C , FIG. 25A to FIG. 25C , FIG. 26A to FIG. 26C , FIG. 27A to FIG. 27C , FIG. 28A to FIG. 28C , FIG. 29A to FIG. 29C , FIG. 30A to FIG. 30C , FIG. 31A to FIG. 31C , FIG. 32A to FIG. 32C , FIG. 33A to FIG. 33C , FIG. 34A to FIG. 34C and Fig.35 A to Fig.34C 1 is a diagram showing an example of a method for manufacturing an imaging element according to a fifth embodiment of the present disclosure. The diagram shows an example of a manufacturing process of a pixel 110 in the imaging element 1. The method for manufacturing the pixel 110 will be described with reference to the drawings.

[0325] Fig.24A is a plan view showing the structure of the pixel 110 . Fig.24A The semiconductor substrate 130 in an on-chip process and a hard mask and a resist disposed on a surface of the semiconductor substrate 130 are shown. Fig. 24B It is along Fig.24A A schematic cross-sectional view taken along line KL in FIG. Fig.24C It is along Fig.24A 26 to 27. Fig.35 Have similar structure of drawings.

[0326] In Fig. 24, a hard mask 530 is provided on the surface of a semiconductor substrate 130 having an insulating film formed thereon (Fig. 24). In the hard mask 530, an opening 531 is formed in a region where the isolation portion 144 is arranged. For example, a SiN film can be applied to the hard mask 530.

[0327] Next, the semiconductor substrate 130 is etched through the hard mask 530 to form an opening 410 ( FIG. 25 ).

[0328] Next, an insulating film is formed on the side surface of the opening 410 (FIG. 26). This can be performed by thermal oxidation.

[0329] Next, the isolation part 142 is arranged in the opening 410 (FIG. 27). This can be performed by forming a material film (eg, a polysilicon film) of the isolation part 142 on the surface of the semiconductor substrate 130 including the opening 410 and performing etching back to remove unnecessary portions.

[0330] Next, the isolation portion 144 is arranged in the opening 410 ( FIG. 28 ). This can be achieved by providing a material film (eg, SiO 20 ) of the isolation portion 144 on the surface of the semiconductor substrate 130 including the opening 410. 2 film) and is performed by removing unnecessary portions by performing CMP.

[0331] Next, a resist 532 ( FIG. 29 ) is provided on the surface of the semiconductor substrate 130. In the resist 532, an opening 533 is formed in a region where the charge retention section common electrode 145 and the charge retention section wiring 160 are to be arranged.

[0332] Next, the isolation portion 144 is etched using the resist 532 as a mask to form an opening 411 ( FIG. 30 ).

[0333] Next, the resist 532 is removed. Next, a member 412, which is a material of the charge holding section common electrode 145 and the charge holding section wiring 160, is arranged in the opening 411 (FIG. 31). This can be performed by forming a film of the member 412 on the surface of the semiconductor substrate 130 including the opening 411 and etching back to remove unnecessary parts. For example, polysilicon containing impurities can be used for the member 412.

[0334] Next, a resist 534 (FIG. 32) is provided on the surface of the semiconductor substrate 130. In the resist 534, an opening 535 is formed in a region where the charge retention portion common electrode 145 is to be arranged.

[0335] Next, the member 412 is etched using the resist 534 as a mask so as to be thinned in the region of the opening 535. Thus, the charge retention portion common electrode 145 and the charge retention portion wiring 160 are formed (FIG. 33).

[0336] Next, the resist 534 is removed. Next, a material film of the isolation portion 144 is arranged on the upper layer of the charge holding portion common electrode 145 of the opening 411 to form the isolation portion 144 (isolation portion 144') (FIG. 34). This can be performed by providing a material film of the isolation portion 144 on the surface of the semiconductor substrate 130 including the opening 411 and removing unnecessary portions by performing CMP.

[0337] Then, the hard mask 530 is removed. Description of subsequent processes will be omitted.

[0338] Through the above-described process, it is possible to manufacture the pixel 110. It should be noted that the above-described manufacturing process shows an example of a case where the charge holding portion common electrode 145 and the charge holding portion wiring 160 are formed at the same time.

[0339] As mentioned above, Fig. 22 The pixel block 100 shown in includes a charge retention portion common electrode 145a and pixels 110a to 110d commonly connected to the charge retention portion common electrode 145a. The pixel block 100 further includes a charge retention portion common electrode 145b and pixels 110e to 110h commonly connected to the charge retention portion common electrode 145b. Here, a plurality of pixels 110 and a charge retention portion common electrode 145 commonly connected to a plurality of pixels 110 are referred to as a pixel group. The charge retention portion common electrodes 145a and 145b of these pixel groups are connected by a charge retention portion wiring 160 embedded in a semiconductor substrate 130. A through wire 260 is provided on the charge retention portion wiring 160, and the charge retention portion common electrodes 145a and 145b are connected to the pixel circuit 120 via the through wire 260. With use Figure 3 Compared with the case of the pixel block 100 in FIG. 1 , the number of pixel circuits 120 arranged in the pixel array section 90 can be reduced. In addition, the number of through wires 260 connected to the charge holding section common electrode 145 can also be reduced.

[0340] Therefore, by applying Fig. 22 The effective area of ​​the semiconductor substrate 230 is expanded by increasing the pixel block 100 in the semiconductor substrate 230. In addition, the effective area refers to an area where the elements of the pixel circuit 120 can be configured. It is preferable to increase the size of the amplifier transistor 121 as the effective area is expanded. This is because the reset transistor 123 and the like are used as switching elements, and the amplifier transistor 121 that amplifies the signal is expected to improve performance due to the expansion of the size. For example, noise can be reduced by expanding the size of the amplifier transistor 121.

[0341] The amplifier transistor 121 outputs charge fluctuations (due to heat, etc.) in the gate and channel as noise. This noise becomes random noise generated in the pixel 110. The amplifier transistor 121 includes a MOS transistor. In the MOS transistor, an input capacitor is formed between the gate and the source as an input terminal. Here, the capacitance of the input capacitor of the gate is represented by C, and the input voltage V of the amplifier transistor 121 can be represented by the following formula.

[0342] V=Q / C

[0343] Here, Q represents the amount of charge input to the amplifier transistor 121. When fluctuation (ΔQ) occurs in Q, V fluctuates. The fluctuation (ΔV) of V is amplified and output as noise.

[0344] According to the above equation, ΔV can be reduced by increasing C. Increasing C can be performed by increasing the area of ​​the gate (gate electrode 148 ). That is, the noise of the pixel 110 can be reduced by increasing the size of the amplifying transistor 121 .

[0345] It should be noted that the pixel block 100 according to the fifth embodiment of the present disclosure is not limited to this embodiment. For example, a configuration in which three or more pixel groups are arranged in the pixel block 100 may also be adopted. In this case, each charge retention unit wiring 160 connects the charge retention unit common electrode 145 of one pixel group.

[0346] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and therefore, a description thereof is omitted.

[0347] As described above, in the pixel block 100 according to the fifth embodiment of the present disclosure, the charge retention portion wiring 160 is arranged, and the through wire 260 and the pixel circuit 120 are shared by a plurality of pixel groups. Therefore, the effective area of ​​the pixel block 100 can be increased.

[0348] (8. Modification of the Fifth Embodiment)

[0349] Next, a modification of the imaging element 1 according to the fifth embodiment described above will be described.

[0350] [First Modification]

[0351] Fig.35 1 is a diagram showing a structural example of a pixel block according to a first variation of the fifth embodiment of the present disclosure. Fig. 22 FIG. 1 is a plan view of a structural embodiment of a pixel block 100. The pixel block 100 in the figure is Fig. 22 The pixel block 100 in FIG. 1 is different in that it includes a wire 155 that connects the charge holding portion wirings 160 to each other.

[0352] [Structure of a cross section of a pixel]

[0353] Fig.36 1 is a diagram showing a structural example of a pixel block according to a first variation of the fifth embodiment of the present disclosure. Fig.23A is a cross-sectional view showing an example of a structure of a pixel block 100 in the pixel array section 90 . Fig.36 is schematically shown along Fig.35 1 is a diagram showing the shape of a cross section taken along line OP in FIG. As shown in the figure, wiring 155 is provided in wiring region 150 of semiconductor substrate 130. Wiring 155 also connects a plurality of charge holding portion wirings 160. Through-wires 260 are connected to wire 155. Conductor 155 may be made of, for example, polycrystalline silicon containing impurities. By using wiring 155, the number of through-wires 260 may be reduced compared to the case where through-wires 260 are provided for each charge holding portion wiring 160.

[0354] [Second Modification]

[0355] Fig.37A and Fig.37B 1 is a diagram showing a structural example of a pixel block according to a second modified example of the fifth embodiment of the present disclosure. The accompanying drawing is a plan view showing a configuration example of a pixel block 100. The pixel block 100 in the figure shows an example in which each pixel 110a and pixel 110c, pixel 110b and pixel 110d, pixel 110e and pixel 110g, and pixel 110f and pixel 110h is formed into a rectangular shape obtained by dividing a square into two. Since the functions of the pixels 110a and pixel 110c and other functions are similar to each other, the pixel 110a and pixel 110c are different from each other. Fig.14 is similar to that in , so its description will be omitted.

[0356] Fig.37A The pixel block 100 in FIG. 1 represents an embodiment including four embedded electrodes 179 and two embedded wirings 165. Fig.37B An embodiment including six embedded electrodes 179 and four embedded wires 165 is shown.

[0357] [Third Modification]

[0358] Fig.38 1 is a diagram showing a structural example of a pixel block according to a third modified example of the fifth embodiment of the present disclosure. Fig. 221 is a plan view of a structural embodiment of a pixel block 100. The pixel block 100 in the figure shows an embodiment in which the semiconductor substrate 230 is omitted. In the pixel block 100 in the figure, the pixel circuit 120 is arranged in the semiconductor substrate 130. Specifically, an amplification transistor 121, a selection transistor 122, a reset transistor 123, and a coupling transistor 124 are arranged for each pixel 110. In addition, a contact plug 153 is connected to the charge retention unit wiring 160 or the like instead of the through wire 260.

[0359] [Fourth Modification]

[0360] Fig.39 1 is a diagram showing a structural example of a pixel block according to a fourth modified example of the fifth embodiment of the present disclosure. Fig. 22 FIG. 1 is a plan view of a structural embodiment of a pixel block 100. The pixel block 100 in the figure is Fig. 22 The pixel block 100 in FIG. 1 is different in that it includes a charge holding portion wiring 160 and an embedded wiring 165 arranged away from the surface of the wiring region 150 in contact with the semiconductor substrate 130. By arranging the charge holding portion wiring 160 in the isolation portion 144 in this way, parasitic capacitance can be reduced.

[0361] The charge holding portion wiring 160 in the figure shows an embodiment including a wiring connection portion 161. The wiring connection portion 161 has a shape protruding from the surface of the semiconductor substrate 130 and is connected to other wirings. Similarly, the wiring connection portion 166 is arranged on the embedded wiring 165.

[0362] [Structure of a cross section of a pixel]

[0363] Fig.40A and Fig.40B is a diagram showing a structural example of a pixel block according to a fourth modified example of the fifth embodiment of the present disclosure. Fig.23A is a cross-sectional view showing an example of a structure of a pixel block 100 in the pixel array section 90 .

[0364] Fig.40A is schematically shown along Fig.39 1 is a diagram showing the shape of a cross section taken along line QR in FIG. As shown in the figure, a through wire 260 is connected to the wiring connection portion 161 . Fig.40B Schematically shows the Fig.39 The shape of the cross section taken along the line ST in FIG. As shown in the figure, the through wiring 260 is connected to the wiring connection portion 166 .

[0365] [Fifth Modification]

[0366] Fig.411 is a diagram showing a structural example of a pixel block according to a fifth modification of the fifth embodiment of the present disclosure. 1 is a cross-sectional diagram showing a structural example of a pixel block 100 in a pixel array section 90. 1 Fig.39 The shape of the cross section taken along the line UV in FIG. As shown in the figure, the charge transfer portion 102 includes a gate electrode 148 configured as a vertical gate. In addition, the semiconductor region 134 included in the charge holding portion 103 in the figure shows an embodiment formed by thermal diffusion. Specifically, the semiconductor region 134 in the figure is formed by thermal diffusion of impurities contained in the charge holding portion common electrode 145 into the well region of the semiconductor substrate 130.

[0367] [Sixth Modification]

[0368] Fig.42 1 is a diagram showing a structural example of a pixel block according to a sixth modification of the fifth embodiment of the present disclosure. Fig. 23B 1 is a cross-sectional view showing a structural embodiment of a pixel block 100 in a pixel array section 90. The isolation section 142 in the figure shows an embodiment in which its bottom has a shape reaching near the back surface of the semiconductor substrate 130. The isolation section 170 is provided between the bottom of the isolation section 142 and the back surface of the semiconductor substrate 130. The isolation section 170 may be formed of a semiconductor region having a relatively high impurity concentration.

[0369] The configuration of the imaging element 1 other than the above is similar to that of the imaging element 1 in the fifth embodiment of the present disclosure, and therefore, description thereof is omitted.

[0370] (9. Other configuration embodiments)

[0371] Fig.43 1 is a diagram showing another configuration example of an imaging element. The imaging element 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging element 1 has a three-dimensional structure formed by bonding the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30). The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0372] The first substrate 10 includes a plurality of sensor pixels 12 that perform photoelectric conversion in a semiconductor substrate 11. The semiconductor substrate 11 corresponds to a specific embodiment of the “first semiconductor substrate” of the present disclosure. The plurality of sensor pixels 12 are arranged in a matrix shape in a pixel region 13 of the first substrate 10. The second substrate 20 includes a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixel 12 in a semiconductor substrate 21, each of the readout circuits 22 being provided for every four sensor pixels 12. The semiconductor substrate 21 corresponds to a specific embodiment of the “second semiconductor substrate” of the present disclosure. The second substrate 20 includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 includes a logic circuit 32 that processes a pixel signal in a semiconductor substrate 31. The semiconductor substrate 31 corresponds to a specific embodiment of the “third semiconductor substrate” of the present disclosure. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal driving circuit 35) outputs to the outside the output voltage Vout of each sensor pixel 12. In the logic circuit 32, for example, a low resistance region made of silicide formed using a self-aligned silicide process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0373] For example, the vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12 row by row. The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on the pixel signal output from each sensor pixel 12 of the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts the signal level of the pixel signal by performing, for example, CDS processing, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. For example, the horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. For example, the system control circuit 36 ​​controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0374] Fig.44 is a cross-sectional view showing another configuration example of an imaging element. Fig.43 An example of a cross-sectional structure in the vertical direction of the imaging element 1 in FIG. Fig.44 An embodiment of the cross-sectional structure of a portion of the imaging element 1 facing the sensor pixel 12 is shown. The imaging element 1 is constituted by sequentially stacking a first substrate 10, a second substrate 20, and a third substrate 30, and further has a color filter 40 and a light receiving lens 50 on the back side (light incident side) of the first substrate 10. For example, one color filter 40 and one light receiving lens 50 are provided for each sensor pixel 12. That is, the imaging element 1 is a back-illuminated type.

[0375] The first substrate 10 is formed by stacking an insulating layer 46 on a semiconductor substrate 11. The first substrate 10 includes the insulating layer 46 as a part of the interlayer insulating film 51. The insulating layer 46 is included in a gap between the semiconductor substrate 11 and a semiconductor substrate 21 to be described later. The semiconductor substrate 11 is formed of a silicon substrate. For example, the semiconductor substrate 11 has a p-well layer 42 in a part of the front surface and its vicinity and a PD 41 having a conductivity type different from that of the p-well layer 42 in other regions (regions deeper than the p-well layer 42). The p-well layer 42 is formed of a p-type semiconductor region. The PD 41 is formed of a semiconductor region of a conductivity type different from that of the p-well layer 42 (specifically, n-type). The semiconductor substrate 11 has a floating diffusion FD as a semiconductor region of a conductivity type different from that of the p-well layer 42 (specifically, n-type) in the p-well layer 42.

[0376] The first substrate 10 includes a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 has a structure in which the transfer transistor TR and the floating diffusion FD are included in a portion on the front surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 includes an element isolation portion 43 that isolates each sensor pixel 12. The element isolation portion 43 is formed to extend in the normal direction of the semiconductor substrate 11 (the direction perpendicular to the surface of the semiconductor substrate 11). The element isolation portion 43 is included between two sensor pixels 12 adjacent to each other. The element isolation portion 43 electrically isolates the sensor pixels 12 adjacent to each other from each other. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates the semiconductor substrate 11, for example. For example, the first substrate 10 further includes a p-well layer 44, that is, a side surface of the element isolation portion 43 and in contact with the surface on the photodiode PD side. The p-well layer 44 is formed by a semiconductor region of a conductivity type different from that of the photodiode PD (specifically, a p-type). For example, the first substrate 10 further includes a fixed charge film 45 in contact with the back side of the semiconductor substrate 11. In order to suppress the generation of dark current caused by the interface state on the light receiving surface side of the semiconductor substrate 11, the fixed charge film 45 is negatively charged. The fixed charge film 45 is formed of, for example, an insulating film having a negative fixed charge. Examples of the material of such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light receiving surface side of the semiconductor substrate 11 by the electric field induced by the fixed charge film 45. The hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the rear surface side of the semiconductor substrate 11. The color filter 40 is in contact with the fixed charge film 45, for example, and is included at a position facing the sensor pixel 12 via the fixed charge film 45. The light receiving lens 50 is in contact with the color filter 40, for example, and is included at a position facing the sensor pixel 12 via the color filter 40 and the fixed charge film 45.

[0377] The second substrate 20 is formed by stacking an insulating layer 52 on a semiconductor substrate 21. The second substrate 20 includes the insulating layer 52 as a part of the interlayer insulating film 51. The insulating layer 52 is included in the gap between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is formed of a silicon substrate. The second substrate 20 includes one readout circuit 22 for every four sensor pixels 12. The second substrate 20 has a structure in which the readout circuit 22 is included in a portion on the front surface side (third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 in a manner that the back surface of the semiconductor substrate 11 faces the front surface side of the semiconductor substrate 21. That is, the second substrate 20 is bonded to the first substrate 10 in a face-to-back manner. The second substrate 20 further includes an insulating layer 53 that penetrates the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The second substrate 20 includes the insulating layer 53 as a part of the interlayer insulating film 51. The insulating layer 53 is included in a manner that covers the side of the through wiring 54 described later.

[0378] The stacked body including the first substrate 10 and the second substrate 20 includes an interlayer insulating film 51 and a through wiring 54 included in the interlayer insulating film 51. The stacked body has one through wiring 54 for each sensor pixel 12. The through wiring 54 extends in the normal direction of the semiconductor substrate 21, penetrating a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through wiring 54. Specifically, the through wiring 54 is electrically connected to the floating diffusion FD and a connection wiring 55 described later.

[0379] The laminated body including the first substrate 10 and the second substrate 20 further includes through-wires 47 and 48 included in the interlayer insulating film 51. The laminated body has one through-wire 47 and one through-wire 48 for each sensor pixel 12. The through-wires 47, 48 extend in the normal direction of the semiconductor substrate 21, penetrating a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through-wires 47 and 48. Specifically, the through-wire 47 is electrically connected to the P well layer 42 of the semiconductor substrate 11 and the wiring of the second substrate 20. The through-wire 48 is electrically connected to the transfer gate TG and the pixel drive line 23.

[0380] For example, the second substrate 20 includes a plurality of connection portions 59 electrically connected to the readout circuit 22 and the semiconductor substrate 21 in the insulating layer 52. For example, the second substrate 20 further includes a wiring layer 56 on the insulating layer 52. The wiring layer 56 includes, for example, an insulating layer 57 and a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 included in the insulating layer 57. The wiring layer 56 also includes, for example, a plurality of connection lines 55 in the insulating layer 57, wherein one connection line is provided for every four sensor pixels 12. The connection lines 55 are electrically connected to each other through the conductive wires 54, which are electrically connected to the floating diffusion FD in the four sensor pixels 12 included in the shared readout circuit 22. Here, the total number of through-wires 54 and 48 is greater than the total number of sensor pixels 12 included in the first substrate 10 and is twice the total number of sensor pixels 12 included in the first substrate 10. In addition, the total number of through-wires 54, 48, and 47 is greater than the total number of sensor pixels 12 included in the first substrate 10 and is three times the total number of sensor pixels 12 included in the first substrate 10.

[0381] The wiring layer 56 also includes, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each of the pad electrodes 58 is formed of a metal such as copper (Cu) or aluminum (Al). Each of the pad electrodes 58 is exposed on the front surface of the wiring layer 56. Each of the pad electrodes 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding between the second substrate 20 and the third substrate 30. For example, one pad electrode 58 is provided for each pair of pixel drive lines 23 and vertical signal lines 24. Here, the total number of pad electrodes 58 (or the total number of nodes between the pad electrodes 58 and the pad electrodes 64 (described later)) is less than the total number of sensor pixels 12 included in the first substrate 10.

[0382] For example, the third substrate 30 is formed by stacking an interlayer insulating film 61 on a semiconductor substrate 31. As will be described later, since the third substrate 30 is bonded to the second substrate 20 in a manner that its front surfaces face each other, when describing the structure in the third substrate 30, the description in the vertical direction is opposite to the vertical direction in the drawings. The semiconductor substrate 31 is formed of a silicon substrate. The third substrate 30 has a structure in which the logic circuit 32 is included in a portion on the front surface side of the semiconductor substrate 31. For example, the third substrate 30 further includes a wiring layer 62 located on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and a plurality of pad electrodes 64 included in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each of the pad electrodes 64 is formed of, for example, Cu (copper). Each of the pad electrodes 64 is exposed on the front surface of the wiring layer 62. Each pad electrode 64 is used for electrical connection between the second substrate 20 and the third substrate 30 and bonding between the second substrate 20 and the third substrate 30. In addition, the number of pad electrodes 64 is not necessarily plural, and even one pad electrode can realize electrical connection with the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other through the bonding between the pad electrodes 58 and 64. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the logic circuit 32 via the through wire 54 and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 in such a manner that the front surface of the semiconductor substrate 31 faces the front surface side of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 in a face-to-face manner.

[0383] Fig.43 and Fig.44 The first substrate 10 and the second substrate 20 in the embodiment correspond to the semiconductor substrate 130 and the semiconductor substrate 230 of the first embodiment, respectively. A semiconductor substrate corresponding to the third substrate 30 described above may also be stacked on the semiconductor substrate 230. In addition, four or more semiconductor substrates may be stacked. Such a configuration in which three or more layers of semiconductor substrates are stacked may be applied to each embodiment of the present disclosure.

[0384] It should be noted that the arrangement of the circuit elements constituting the pixel block 100 is not limited to Figure 5 For example, all elements of the pixel circuit 120 may be included in the semiconductor substrate 130. A pixel circuit formed of an analog circuit or a digital circuit, a signal processing circuit, a memory circuit, a logic circuit, etc. can be ideally disposed in the semiconductor substrate 230 or in a semiconductor substrate that is ideally further increased.

[0385] (10. Application Examples)

[0386] Fig.451 is a diagram showing an example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the embodiment and its modified example.

[0387] The imaging system 7 is an electronic device such as an imaging apparatus such as a digital still camera or a video camera, or a portable terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, the imaging device 1 according to the above-described embodiment and one of its modifications, a DSP circuit 743, a frame memory 744, a display unit 745, a storage unit 746, an operation unit 747, and a power supply unit 748. In the imaging system 7, according to the imaging device of one of the embodiments and its modifications, the DSP circuit 743, the frame memory 744, the display unit 745, the storage unit 746, the operation unit 747, and the power supply unit 748 are connected to each other via a bus 749.

[0388] The imaging device 1 according to one of the embodiments and its modified examples outputs image data corresponding to incident light. The DSP circuit 743 is a signal processing circuit that processes a signal (image data) output from the imaging device 1 according to one of the embodiments and its modified examples. The frame memory 744 temporarily holds the image data processed by the DSP circuit 743 for each frame. The display unit 745 includes a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays a moving image or a still image captured by the imaging device 1 according to one of the embodiments and its modified examples. The storage unit 746 records the image data of the moving image or the still image captured by the imaging device 1 according to the embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation unit 747 issues operation commands for various functions of the imaging system 7 based on the operation of the user. The power supply unit 748 appropriately supplies various power supplies as the operation power supply of the imaging device 1 according to one embodiment and its modified examples, the DSP circuit 743, the frame memory 744, the display unit 745, the storage unit 746, and the operation unit 747 to these supply targets.

[0389] Next, the imaging process in the imaging system 7 will be described.

[0390] Fig.46 7 is a diagram showing an embodiment of a flowchart of an imaging operation in the imaging system 7. The user instructs to start imaging by operating the operation unit 747 (step S101). Then, the operation unit 747 sends an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit 36) performs imaging according to a predetermined imaging scheme (step S103).

[0391] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 743. Incidentally, the image data refers to data of pixel signals generated based on the charge temporarily held in the floating diffusion FD based on all pixels. The DSP circuit 743 performs predetermined signal processing (for example, noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 743 causes the frame memory 744 to hold the image data that has been subjected to the predetermined signal processing, and the frame memory 744 causes the storage unit 746 to record the image data (step S105). In this way, imaging in the imaging system 7 is performed.

[0392] In the present application example, the imaging device 1 according to one of the above-described embodiments and their modified examples is applied to the imaging system 7. Therefore, the imaging device 1 can be downsized or have high definition, and thus, the downsized or high definition imaging system 7 can be provided.

[0393] (11. Application example of mobile object)

[0394] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device to be installed on any type of mobile body, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot.

[0395] Fig.47 is a block diagram describing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0396] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.47 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0397] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0398] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0399] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface, or detect their distances, based on the received image.

[0400] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0401] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0402] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0403] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0404] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030.

[0405] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.47 In the embodiment of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0406] Fig.48 This is a diagram describing an example of the installation position of the imaging unit 12031.

[0407] exist Fig.48 , the imaging unit 12031 includes imaging parts 12101 , 12102 , 12103 , 12104 and 12105 .

[0408] The imaging units 12101, 12102, 12103, 12104 and 12105 are, for example, disposed at positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at positions on the upper portion of the windshield inside the vehicle. The imaging unit 12101 disposed at the front nose inside the vehicle and the imaging unit 12105 disposed at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed to the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 disposed to the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0409] By the way, Fig.48 An embodiment of the shooting range of the imaging units 12101 to 12104 is described. The imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging parts 12102 and 12103 set to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0410] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0411] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting objects that exist on the driving path of the vehicle 12100 and are traveling in the same direction as the vehicle 12100 at a prescribed speed (e.g., equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can pre-set the following distance to keep ahead of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, coordinated control for automatic driving that allows the vehicle to travel automatically without relying on the driver's operation, etc., can be performed.

[0412] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0413] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the imaged images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0414] An embodiment of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The imaging element 1 in can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, degradation of the image quality of the imaging section 12031 can be prevented.

[0415] (12. Application examples of endoscopic surgery systems)

[0416] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0417] Fig.49 It is a view describing an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (the present technology) can be applied.

[0418] exist Fig.49 , a surgeon (doctor) 11131 is shown performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, a pneumoperitoneum tube 11111, other surgical tools 11110 such as an energy treatment device 11112, a support arm device 11120 supporting the endoscope 11100, and a trolley 11200 carrying various endoscopic surgery devices.

[0419] The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from a distal end thereof for insertion into a body cavity of a patient 11132, and a camera 11102 connected to a proximal end of the lens barrel 11101. In the depicted example, the endoscope 11100 is depicted as including a hard scope having a hard type lens barrel 11101. However, the endoscope 11100 may additionally be included as a soft scope having a soft type lens barrel 11101.

[0420] The lens barrel 11101 has an opening at its distal end, and the objective lens is mounted in the opening. The light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is introduced into the front end of the lens barrel 11101 by the light guide extending inside the lens barrel 11101, and irradiated toward the observation object in the body cavity of the patient 11132 via the objective lens. In addition, the endoscope 11100 can be either a direct-view mirror, a stereoscope, or a side-view mirror.

[0421] The optical system and the image pickup element are arranged inside the camera 11102 so that the reflected light (observation light) from the observation target is focused on the image pickup element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as RAW data.

[0422] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102 and performs various image processing for displaying an image based on the image signal, such as, for example, development processing (demosaic processing), on the image signal.

[0423] The display device 11202 displays an image thereon based on an image signal on which image processing has been performed under the control of the CCU 11201 .

[0424] The light source device 11203 is composed of a light source such as a light emitting diode (LED), and supplies irradiation light for imaging the surgical area to the endoscope 11100.

[0425] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user inputs instructions to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0426] The treatment tool control device 11205 controls the drive of the energy treatment tool 11112 to perform cauterization, incision, blood vessel sealing, etc. of tissue. In order to ensure the field of view of the endoscope 11100 and the operating space of the surgeon, the pneumoperitoneum device 11206 supplies gas to the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms (such as text, images, or graphics).

[0427] In addition, the light source device 11203 that supplies irradiation light when the surgical area is photographed to the endoscope 11100 may also include a white light source, which is composed of, for example, an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing can be controlled with high precision for each color (each wavelength), the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the laser beams from each RGB laser light source are irradiated on the observation target in a time-sharing manner and the drive of the image pickup element of the camera 11102 is controlled synchronously with the irradiation timing. Then, images corresponding to the R, G, and B colors, respectively, can also be captured in a time-sharing manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0428] In addition, the light source device 11203 can be controlled so that the intensity of the light to be output is changed every predetermined time. By controlling the drive of the image pickup element of the camera 11102 synchronously with the timing of the light intensity change to acquire images in time division and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0429] In addition, the light source device 11203 can be configured to provide light of a predetermined wavelength band prepared for special light observation. In special light observation, by utilizing the wavelength dependence of the absorption of light by the biological tissue to irradiate light of a narrower band than the irradiation light (i.e., white light) during normal observation, narrow-band light observation (narrow-band light observation) is performed to image a predetermined tissue such as blood vessels in the surface layer of the mucosa with high contrast. Alternatively, in special light observation, fluorescence observation can also be performed to obtain an image from the fluorescence generated by irradiation with excitation light. In fluorescence observation, it is possible to observe fluorescence from biological tissue by irradiating excitation light to the biological tissue (autofluorescence observation), or to obtain a fluorescence image by locally injecting a reagent such as indocyanine green (ICG) into the biological tissue and irradiating the biological tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for special light observation as described above.

[0430] Fig.50 It is a depiction Fig.49 A block diagram of an example of the functional configuration of the camera 11102 and CCU 11201 depicted in FIG.

[0431] The camera 11102 includes a lens unit 11401, an image pickup unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 for communication with each other.

[0432] The lens unit 11401 is an optical system, and is provided at a connection position with the lens barrel 11101. Observation light acquired from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0433] The number of image pickup elements included in the image pickup unit 11402 may be one (single-board type) or multiple (multi-board type). In the case where the image pickup unit 11402 is configured as a multi-board type image pickup unit, for example, image signals corresponding to each R, G, and B are generated by the image pickup element, and the image signals can be synthesized to obtain a color image. The image pickup unit 11402 may also be configured to have a pair of image pickup elements for acquiring corresponding image signals of the right eye and the left eye prepared for three-dimensional (3D) display. In the case of performing 3D display, the surgical operator 11131 can more accurately grasp the depth of the biological tissue in the surgical area. It should be noted that in the case where the image pickup unit 11402 is configured as a stereoscopic type image pickup unit, a plurality of systems of lens units 11401 are set corresponding to a single image pickup element.

[0434] In addition, the image pickup unit 11402 is not necessarily provided on the camera head 11102. For example, the image pickup unit 11402 may be provided inside the lens barrel 11101 just behind the objective lens.

[0435] The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. As a result, the magnification and focus of the image picked up by the image pickup unit 11402 can be appropriately adjusted.

[0436] The communication unit 11404 includes a communication device for sending and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the image pickup unit 11402 to the CCU 11201 through the transmission cable 11400 as RAW data.

[0437] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to image pickup conditions, such as information specifying a frame rate of a picked-up image, information specifying an exposure value at the time of image pickup, and / or information specifying a magnification and a focus of a picked-up image.

[0438] It should be noted that image pickup conditions such as frame rate, exposure value, magnification, or focus may be specified by a user or may be automatically set based on an acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated in the endoscope 11100.

[0439] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 11201 received through the communication unit 11404 .

[0440] The communication unit 11411 includes a communication device for sending and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera 11102 through the transmission cable 11400.

[0441] In addition, the communication unit 11411 sends a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0442] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data sent thereto from the camera 11102 .

[0443] The control unit 11413 performs various controls related to the imaging of the operation area, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the operation area, etc. For example, the control unit 11413 creates a control signal for controlling the driving of the camera head 11102 .

[0444] In addition, the control unit 11413 controls the display device 11202 to display a picked-up image of the surgical area, etc., based on the image signal processed by the image processing unit 11412. Thus, the control unit 11413 can use various image recognition technologies to recognize various objects in the picked-up image. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific living body areas, bleeding, and mist when the energy treatment instrument 11112 is used by detecting the shape, color, etc. of the edge of the subject contained in the camera image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical support information in a manner overlapping with the image of the surgical area. When the surgical support information is displayed in an overlapping manner and prompted to the surgical operator 11131, the burden of the surgical operator 11131 can be reduced, and the surgical operator 11131 can reliably perform the operation.

[0445] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable prepared for communication of electric signals, an optical fiber prepared for optical communication, or a composite cable prepared for both electric communication and optical communication.

[0446] Here, although in the depicted embodiment, communication is performed through wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed through wireless communication.

[0447] Embodiments of endoscopic surgery systems to which the technology of the present disclosure can be applied have been described above. The technology of the present disclosure can be applied to the image pickup unit 11402 of the endoscope 11100 or the camera 11102 in the above-mentioned components. Specifically, Figure 1 The imaging element 1 in can be applied to the image pickup unit 11402. By applying the technology according to the present disclosure to the image pickup unit 11402, it is possible to prevent the image quality of the image pickup unit 11402 from being deteriorated.

[0448] It should be noted that in this embodiment, an endoscopic surgery system has been described as an example, however, the technology according to the present disclosure can be applied to other systems, such as a microsurgery system.

[0449] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above embodiments, and various modifications may be made without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0450] It should be noted that the effects described herein are merely embodiments and are not limiting, and other effects may also be achieved.

[0451] It should be noted that the present technology can also have the following configurations.

[0452] (1) An imaging element comprising:

[0453] A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; and a charge holding portion that holds charges generated by the photoelectric conversion, the charge holding portion being provided by being embedded in the semiconductor substrate; and

[0454] The signal generating unit generates a pixel signal corresponding to the charge held in the charge holding unit.

[0455] (2) The imaging element according to (1), wherein the charge holding portion is configured by being embedded in a well region formed in a semiconductor substrate.

[0456] (3) The imaging element according to (2), further including a reset section that releases the retained charge, the reset section being configured by a MOS transistor formed near a surface of the semiconductor substrate.

[0457] (4) The imaging element according to (3), further including a charge holding portion connecting portion connecting the charge holding portion and the semiconductor region of the reset portion.

[0458] (5) The imaging element according to any one of (1) to (4), wherein the pixel further includes a charge transfer portion that transfers the charge generated by the photoelectric conversion to the charge holding portion, the charge transfer portion being arranged by being embedded in the semiconductor substrate.

[0459] (6) The imaging element according to (5), wherein the charge transfer section is arranged in a partition formed at a boundary of a pixel.

[0460] (7) The imaging element according to any one of (1) to (6), further including an embedded electrode provided by being embedded in the semiconductor substrate, the embedded electrode being connected to a well region of the semiconductor substrate.

[0461] (8) The imaging element according to any one of (1) to (7), further including a charge holding section common electrode commonly connected to the charge holding sections of a plurality of pixels adjacent to each other.

[0462] (9) The imaging element according to any one of (1) to (8), further including an element isolation region provided between the photoelectric conversion portion and the charge holding portion.

[0463] (10) The imaging element according to any one of (1) to (9), further including a second semiconductor substrate in which the signal generating section is provided, the second semiconductor substrate being stacked on the semiconductor substrate.

[0464] (11) The imaging element according to (1), further comprising:

[0465] A wiring region is disposed adjacent to the front surface of the semiconductor substrate,

[0466] Here, the charge holding portion has a shape adjacent to a side surface of an opening formed in the semiconductor substrate at a boundary of a pixel, and the charge holding portion is arranged to be separated from a surface of the semiconductor substrate in contact with the wiring region.

[0467] (12) The imaging element according to (11), further including an embedded electrode arranged in the opening and spaced apart from the surface of the semiconductor substrate in contact with the wiring region, the embedded electrode being connected to the charge holding portion.

[0468] (13) The imaging element according to (12),

[0469] wherein the charge holding portion is composed of a semiconductor region to which an impurity is added, the semiconductor region being formed in a semiconductor substrate, and

[0470] The embedded electrodes are added with impurities.

[0471] (14) The imaging element according to any one of (11) to (13),

[0472] wherein the pixel further includes a charge transfer portion that transfers the charge generated by the photoelectric conversion to the charge holding portion, and

[0473] The charge transfer section is constituted by a MOS transistor including a gate electrode having a shape not overlapping the opening when viewed from a normal direction of a surface of the semiconductor substrate.

[0474] (15) The imaging element according to any one of (11) to (14), wherein the charge holding portion has a shape adjacent to a bottom of a step formed in the opening.

[0475] (16) An imaging element comprising:

[0476] A pixel including a photoelectric conversion portion for photoelectrically converting incident light, the photoelectric conversion portion being formed in a semiconductor substrate having a wiring region disposed adjacent to the semiconductor substrate;

[0477] a pixel circuit that generates a signal based on the charge generated by photoelectric conversion;

[0478] a semiconductor region adjacent to a side surface of an opening formed in the semiconductor substrate at a boundary of the pixel, the semiconductor region being provided to be separated from a surface of the semiconductor substrate in contact with the wiring region; and

[0479] A second embedded electrode is provided in the opening and is spaced apart from the surface of the semiconductor substrate in contact with the wiring region, the second embedded electrode being connected to the semiconductor region.

[0480] (17) The imaging element according to (16), wherein the semiconductor region is a semiconductor region of an element of a pixel circuit.

[0481] (18) The imaging element according to (16), wherein the semiconductor region is a well region of a semiconductor substrate.

[0482] (19) The imaging element according to (16), wherein the second embedded electrode is doped with the same impurity as that of the semiconductor region.

[0483] (20) The imaging element according to (8), further comprising:

[0484] a plurality of charge holding portion common electrodes; and

[0485] The charge holding portion wiring connects the plurality of charge holding portions to each other, and the charge holding portion wiring is arranged at the boundary of the pixel by being embedded in the semiconductor substrate.

[0486] (21) The imaging element according to (20), wherein the charge holding portion wiring is arranged in a separation portion formed at a boundary of a pixel.

[0487] (22) The imaging element according to (21), wherein the isolation portion is constituted by an insulating member arranged in an opening formed on the front surface of the semiconductor substrate.

[0488] (23) The imaging element according to (22), wherein the isolation portion is arranged in an opening having a shape penetrating the semiconductor substrate.

[0489] (24) The imaging element according to any one of (20) to (23), wherein the pixel has a rectangular shape when viewed from a normal direction of a surface of the semiconductor substrate.

[0490] (25) The imaging element according to (24), wherein the pixel has a square shape when viewed from a normal direction of a surface of the semiconductor substrate.

[0491] (26) The imaging element according to any one of (20) to (25), wherein the charge holding portion wiring is composed of polycrystalline silicon containing impurities.

[0492] (27) The imaging element according to any one of (20) to (25), wherein the charge holding portion wiring is made of metal.

[0493] (28) The imaging element according to any one of (20) to (27), further comprising

[0494] A wiring region is disposed adjacent to the front surface of the semiconductor substrate,

[0495] Here, the charge retention portion wiring is provided to be spaced apart from the wiring region and the surface of the semiconductor substrate.

[0496] (29) The imaging element according to (28), wherein the charge holding portion wiring includes a wiring connection portion for connection with another wiring, the wiring connection portion having a shape protruding from the front surface of the semiconductor substrate.

[0497] (30) The imaging element according to (16), further comprising:

[0498] a plurality of second embedded electrodes; and

[0499] The embedded wiring connects the plurality of second embedded electrodes to each other, and the embedded wiring is provided at a boundary of the pixel by being embedded in the semiconductor substrate.

[0500] (31) The imaging element according to (16), further including a second semiconductor substrate stacked on the semiconductor substrate, and a part of the pixel circuit is arranged in the second semiconductor substrate.

[0501] (32) An electronic device comprising:

[0502] A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; and a charge holding portion that holds charges generated by the photoelectric conversion, the charge holding portion being provided by being embedded in the semiconductor substrate;

[0503] a signal generating section that generates a pixel signal corresponding to the charge held in the charge holding section; and

[0504] The processing circuit processes the generated pixel signal.

[0505] Reference Numbers List

[0506] 1 Imaging element

[0507] 90 Pixel array section

[0508] 94 columns signal processing unit

[0509] 100 pixel blocks

[0510] 101, 101a, 101b, 101c, 101d photoelectric conversion unit

[0511] 102, 102a, 102b, 102c, 102d charge transfer unit

[0512] 103, 103a, 103b, 103c, 103d charge holding unit

[0513] 110, 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h PIXEL

[0514] 120 pixel circuit

[0515] 121 Amplifier transistor

[0516] 122 Select transistor

[0517] 123, 123a, 123b, 123c, 123d reset transistor

[0518] 124 Coupling transistor

[0519] 129 Signal Generation Department

[0520] 130, 230 semiconductor substrate

[0521] 131 to 134, 137, 138, 138a, 138b, 139, 181, 186, 231, 232 semiconductor regions

[0522] 135 Charge retention portion connecting portion

[0523] 136 Component Isolation Area

[0524] 142, 144, 144', 170 isolation

[0525] 143 Embedded Electrode

[0526] 146, 147 Electrode

[0527] 145, 145a, 145b common electrode of charge holding portion

[0528] 148, 149, 248 gate electrode

[0529] 150, 250 wiring area

[0530] 160 Charge retention unit wiring

[0531] 161, 166 Wiring connection part

[0532] 165 Embedded wiring

[0533] 179, 179a, 179b embedded electrodes

[0534] 182, 184 side wall

[0535] 185 steps

[0536] 260 Through-wire.

Claims

1. An imaging element, comprising: A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; and a charge holding portion that holds charges generated by the photoelectric conversion, the charge holding portion being provided by being embedded in the semiconductor substrate; and The signal generating unit generates a pixel signal corresponding to the charge held in the charge holding unit.

2. The imaging element according to claim 1, wherein The charge holding portion is provided by being embedded in a well region formed in the semiconductor substrate. 3 . The imaging element according to claim 2 , further comprising a reset section that releases the retained charge, the reset section being configured by a MOS transistor formed near a surface of the semiconductor substrate. 4 . The imaging element according to claim 3 , further comprising a charge holding portion connecting portion connecting a semiconductor region of the reset portion and the charge holding portion.

5. The imaging element according to claim 1, wherein The pixel further includes a charge transfer portion that transfers the charge generated by the photoelectric conversion to the charge holding portion, the charge transfer portion being provided by being embedded in the semiconductor substrate.

6. The imaging element according to claim 5, wherein: The charge transfer section is provided in a partition formed at a boundary of the pixel. 7 . The imaging element according to claim 1 , further comprising an embedded electrode provided by being embedded in the semiconductor substrate, the embedded electrode being connected to a well region of the semiconductor substrate. 8 . The imaging element according to claim 1 , further comprising a charge holding portion common electrode connected in common to the charge holding portions of a plurality of pixels adjacent to each other. 9 . The imaging element according to claim 1 , further comprising an element isolation region provided between the photoelectric conversion portion and the charge holding portion. 10 . The imaging element according to claim 1 , further comprising a second semiconductor substrate in which the signal generating section is provided, the second semiconductor substrate being stacked on the semiconductor substrate.

11. The imaging element according to claim 1, further comprising: a wiring region disposed adjacent to the front surface of the semiconductor substrate, The charge holding portion has a shape adjacent to a side surface of an opening formed in the semiconductor substrate at a boundary of the pixel, and the charge holding portion is provided to be separated from a surface of the semiconductor substrate in contact with the wiring region. 12 . The imaging element according to claim 11 , further comprising an embedded electrode provided in the opening and spaced apart from a surface of the semiconductor substrate in contact with the wiring region, the embedded electrode being connected to the charge holding portion.

13. The imaging element according to claim 12, in, The charge holding portion is configured by a semiconductor region to which an impurity is added, the semiconductor region being formed in the semiconductor substrate, and The embedded electrode is added with impurities.

14. The imaging element according to claim 11, in, The pixel further includes a charge transfer portion that transfers the charge generated by the photoelectric conversion to the charge holding portion, and The charge transfer section is configured by a MOS transistor including a gate electrode having a shape that does not overlap with the opening when viewed from a normal direction of a surface of the semiconductor substrate.

15. The imaging element according to claim 11, wherein The charge holding portion has a shape adjacent to a bottom of a step formed in the opening.

16. An imaging element, comprising: a pixel including a photoelectric conversion portion that performs photoelectric conversion on incident light, the photoelectric conversion portion being formed in a semiconductor substrate having a wiring region disposed adjacent to the semiconductor substrate; a pixel circuit that generates a signal based on the charge generated by the photoelectric conversion; a semiconductor region adjacent to a side surface of an opening formed in the semiconductor substrate at a boundary of the pixel, the semiconductor region being disposed to be spaced apart from a surface of the semiconductor substrate in contact with the wiring region; as well as A second embedded electrode is provided in the opening and is spaced apart from a surface of the semiconductor substrate in contact with the wiring region, the second embedded electrode being connected to the semiconductor region.

17. The imaging element according to claim 16, wherein: The semiconductor region is a semiconductor region of an element of the pixel circuit.

18. The imaging element according to claim 16, wherein: The semiconductor region is a well region of the semiconductor substrate.

19. The imaging element according to claim 16, wherein: The second embedded electrode is added with the same impurity as that of the semiconductor region.

20. The imaging element according to claim 8, further comprising: A plurality of charge holding portion common electrodes; as well as A charge holding portion wiring connects the plurality of charge holding portions to each other, and the charge holding portion wiring is provided at a boundary of the pixel by being embedded in the semiconductor substrate.

21. The imaging element according to claim 20, wherein The charge retention portion wiring is provided in a separation portion formed at a boundary of the pixel.

22. The imaging element according to claim 21, wherein The isolation portion is configured by an insulating member provided in an opening formed on the front surface of the semiconductor substrate.

23. The imaging element according to claim 22, wherein: The isolation portion is provided in the opening having a shape penetrating the semiconductor substrate.

24. The imaging element according to claim 20, wherein The pixel has a rectangular shape when viewed from a normal direction to a surface of the semiconductor substrate.

25. The imaging element according to claim 24, wherein The pixel has a square shape when viewed from a normal direction to a surface of the semiconductor substrate.

26. The imaging element according to claim 20, wherein The charge retention unit wiring is made of polysilicon containing impurities.

27. The imaging element according to claim 20, wherein The charge retention portion wiring is made of metal.

28. The imaging element according to claim 20, further comprising: a wiring region disposed adjacent to the front surface of the semiconductor substrate, The charge retention portion wiring is provided to be spaced apart from a surface of the semiconductor substrate in contact with the wiring region.

29. The imaging element according to claim 28, wherein The charge holding portion wiring includes a wiring connection portion for connection with another wiring, the wiring connection portion having a shape protruding from the front surface of the semiconductor substrate.

30. The imaging element according to claim 16, further comprising: a plurality of said second embedded electrodes; as well as An embedded wiring connects the plurality of second embedded electrodes to each other, and the embedded wiring is provided at a boundary of the pixel by being embedded in the semiconductor substrate. 31 . The imaging element according to claim 16 , further comprising a second semiconductor substrate which is stacked on the semiconductor substrate and in which a part of the pixel circuit is provided.

32. An electronic device comprising: A pixel including: a photoelectric conversion portion that performs photoelectric conversion of incident light, the photoelectric conversion portion being formed in a semiconductor substrate; and a charge holding portion that holds charges generated by the photoelectric conversion, the charge holding portion being provided by being embedded in the semiconductor substrate; a signal generating section that generates a pixel signal corresponding to the charge held in the charge holding section; and The processing circuit processes the generated pixel signal.

Images