A clock chip ATE test circuit and test method

Abstract

The present invention provides a clock chip ATE test circuit and test method, wherein the clock chip has a first differential output terminal and a second differential output terminal, and the ATE test circuit includes a first impedance matching circuit, a second impedance matching circuit, a first matching resistor access circuit, a second matching resistor access circuit, a terminal matching resistor access circuit, and a reference voltage and reference ground access circuit; wherein matching resistors, reference voltages, reference grounds, and matching impedance access are provided respectively. The present invention directly satisfies the test of different output types of the clock chip by controlling the access combination of matching resistors, reference voltages, reference grounds, and matching impedances in the test circuit, thereby reducing the matching circuit, and at the same time adopts a software switching method in the circuit, thereby reducing the time of manual physical switching, and generally achieving improved test efficiency and reduced test costs.

Description

Technical Field

[0001] The present invention relates to the field of clock chip testing, and in particular to a clock chip ATE testing circuit and a testing method. Background Art

[0002] Clock chips are core components in electronic devices, and their stability and accuracy directly affect the performance of the entire system. Therefore, developing efficient and accurate clock chip testing circuits and methods is of great significance to ensure product quality.

[0003] With the rapid development of integrated circuit technology, the performance indicators of clock chips are increasing day by day, and the requirements for testing technology are also increasing. Traditional testing methods often have problems such as long test cycles, low accuracy, and high costs, which are difficult to meet the rapid iteration and high quality requirements of modern electronic products. ATE (Automatic Test Equipment) is an important tool in the field of semiconductor testing. It can automatically complete a variety of test tasks and improve test efficiency and accuracy. However, for the specific testing requirements of clock chips, there is still room for optimization of existing ATE test circuits and methods.

[0004] Clock chips usually have two output modes, as follows:

[0005] 1. Single-Ended Output

[0006] (1) Features: Single-ended output mode means that the clock signal is output through a single pin, usually a signal in a differential pair (such as CLKOUTp or a similarly marked pin). In this mode, the integrity of the clock signal may be affected by noise and interference in the transmission line.

[0007] (2) Application: Suitable for occasions where the quality requirements for clock signals are not particularly high, such as some low-speed or medium-speed digital systems.

[0008] 2. Differential Output

[0009] (1) Features: The differential output mode outputs clock signals through a pair of pins (such as CLKOUT_p and CLKOUT_n). The two signals are equal in amplitude but opposite in polarity. Differential signals have better resistance to noise and interference because common-mode noise is canceled out at the differential receiving end.

[0010] (2) Application: Widely used in digital systems with high-speed and high-precision requirements, such as high-speed data transmission interfaces, high-speed memory interfaces, etc.

[0011] For differential clock output, in order to meet the needs of clock signals in different application scenarios, different output types have been derived, such as 1. LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor), a low-voltage complementary metal oxide semiconductor logic level standard; 2. LVPECL (Low Voltage Positive Emitter Coupled Logic), a high-speed, low-voltage differential output with faster signal rise and fall times; 3. LVDS (Low Voltage Differential Signaling), a low-power, low-noise differential signal transmission; 4. HCSL (High-Speed ​​Current Steering Logic), a high-speed, low-power differential output; 5. CML (Current Mode Logic), a logic level standard based on current control, with the characteristics of high speed, low noise and strong anti-interference ability.

[0012] Usually, clock chips should be compatible with the above clock output types, and ATE testing also needs to cover all output types. At present, when testing a pair of clock chip differential output signals, different matching circuits are used for testing, that is, to test two differential clock signals, multiple sets of test circuits are used, and different test circuits correspond to different output types. During the test process, different matching circuits need to be switched for testing different output types. Since the same clock chip usually has 10-20 pairs of differential outputs, the circuit switching time (hardware physical switching), the test time is long (low test efficiency), and there are many test hardware (multiple matching circuits for each pair of outputs), and the test cost is high. Summary of the invention

[0013] In view of the problems existing in the prior art, a clock chip ATE test circuit and test method are provided, which meet the test of different output types of clock chips by adopting a set of compatible circuits.

[0014] A first aspect of the present invention provides a clock chip ATE test circuit, wherein the clock chip has a first differential output terminal and a second differential output terminal, including:

[0015] a first impedance matching circuit;

[0016] a second impedance matching circuit;

[0017] A first matching resistor access circuit is used to control the access of the first matching resistor; a first end of the first matching resistor access circuit is connected to the first differential output end of the clock chip, and a second end of the first matching resistor access circuit is connected to the first test end via the first impedance matching circuit;

[0018] A second matching resistor access circuit is used to control the access of the second matching resistor; a first end of the second matching resistor access circuit is connected to the second differential output end of the clock chip, and a second end of the second matching resistor access circuit is connected to the second test end via the second impedance matching circuit;

[0019] A terminal matching resistor access circuit, used to control the access of the terminal matching resistor; the first end of the terminal matching resistor access circuit is connected to the second end of the first matching resistor access circuit, and the second end of the terminal matching resistor access circuit is connected to the second end of the second matching resistor access circuit;

[0020] A reference voltage and reference ground access circuit is connected to a terminal matching resistor access circuit and is used to control the access of the reference voltage and the reference ground.

[0021] As a preferred solution, the first matching resistor access circuit includes a first switch, a second switch and a first matching resistor; wherein,

[0022] A first end of the first switch is connected to a first end of the first matching resistor access circuit, and a second end of the first switch is connected to a second end of the first matching resistor access circuit;

[0023] A first end of the second switch is connected to a first end of the first matching resistor access circuit, and a second end of the second switch is connected to a second end of the first matching resistor access circuit via a first matching resistor.

[0024] As a preferred solution, the second matching resistor access circuit includes a third switch, a fourth switch and a second matching resistor; wherein,

[0025] A first end of the third switch is connected to a first end of the second matching resistor access circuit, and a second end of the third switch is connected to a second end of the second matching resistor access circuit via a second matching resistor;

[0026] A first end of the fourth switch is connected to a first end of the second matching resistor access circuit, and a second end of the fourth switch is connected to a second end of the second matching resistor access circuit.

[0027] As a preferred solution, the terminal matching resistor access circuit includes a fifth switch, a sixth switch, a first terminal matching resistor and a second terminal matching resistor; wherein,

[0028] The first end of the fifth switch is connected to the second end of the first matching resistor access circuit, and the second end of the fifth switch is connected to the second end of the second matching resistor access circuit via the first terminal matching resistor, the second terminal matching resistor and the sixth switch in sequence.

[0029] As a preferred solution, the reference voltage and reference ground access circuit includes a reference voltage source, a reference ground, a seventh switch and an eighth switch; wherein,

[0030] The output end of the reference voltage source is connected to a common node between the first terminal matching resistor and the second terminal matching resistor via a seventh switch;

[0031] The reference ground is connected to a common node between the first terminal matching resistor and the second terminal matching resistor via an eighth switch.

[0032] As a preferred solution, the reference voltage source is controlled by ATE to achieve output voltage variation.

[0033] As a preferred solution, in the test circuit, all switches are high-speed control switches that meet the bandwidth requirements of high-speed signals, and the closing and opening control of the high-speed control switches is achieved by ATE.

[0034] As a preferred solution, in the test circuit, all switches are implemented using radio frequency switches.

[0035] The second aspect of the present invention proposes a clock chip ATE test method, which is implemented based on the clock chip ATE test circuit described in the first aspect, including: controlling the combined access of a first matching resistor, a second matching resistor, a terminal matching resistor, a reference voltage, and a reference ground to achieve testing of different types of differential output signals of the clock chip.

[0036] As a preferred solution, the test of different types of differential output signals of the clock chip includes LVCMOS, LVPECL, LVDS, HCSL, and CML types.

[0037] Compared with the prior art, the beneficial effects of adopting the above technical solution are as follows: the present invention directly satisfies the test of different output types through one test circuit, thereby reducing the matching circuit, and at the same time adopts software switching in the compatible circuit, thereby reducing the time of manual physical switching, and overall achieving the goal of improving test efficiency and reducing test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a principle block diagram of the clock chip ATE test circuit proposed in an embodiment of the present invention.

[0039] Figure 2 The present invention is a schematic diagram of a clock chip ATE test circuit implementation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] To make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily. In addition, although the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in an order different from that here.

[0041] The terms "first" and "second" in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any variation thereof are intended to cover non-exclusive protection. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0042] In order to reduce the testing cost of a clock chip, an embodiment of the present invention proposes a clock chip ATE testing circuit, through which different types of output signals of the clock chip can be tested.

[0043] When introducing the specific composition of the clock chip ATE test circuit, it should be noted that the clock chip has a first differential output terminal Clock-out-1 and a second differential output terminal Clock-out-2, which output a pair of differential data signals. The test circuit receives a pair of differential data signals from the clock chip, and after selection and matching processing inside the test circuit, outputs test signals from the two test terminals, and the ATE completes the characteristic test of the test signal.

[0044] For details, please refer to Figure 1 The clock chip ATE test circuit mainly includes a first impedance matching circuit, a second impedance matching circuit, a first matching resistor access circuit, a second matching resistor access circuit, a terminal matching resistor access circuit, and a reference voltage and reference ground access circuit. Through the control of each circuit, the matching mode of the test circuit can be adjusted to meet the test of different types of differential outputs of the clock chip. Among them,

[0045] The first matching resistor access circuit is mainly used to control the access of the first matching resistor R1; the first end of the first matching resistor access circuit is connected to the first differential output terminal Clock-out-1 of the clock chip, and the second end of the first matching resistor access circuit is connected to the first test terminal Test-1 via the first impedance matching circuit, and the first test terminal Test-1 is connected to ATE to complete the test.

[0046] Similarly, the second matching resistor access circuit is used to control the access of the second matching resistor R2; the first end of the second matching resistor access circuit is connected to the second differential output terminal Clock-out-2 of the clock chip, and the second end of the second matching resistor access circuit is connected to the second test terminal Test-2 via the second impedance matching circuit, and the second test terminal Test-2 is also connected to ATE to complete the test.

[0047] In this embodiment, whether to connect the first matching resistor R1 and the second matching resistor R2 can be controlled respectively by the first matching resistor access circuit and the second matching resistor access circuit. In practical applications, the first end of the first matching resistor access circuit can be connected to the negative output end of the clock chip, and the first end of the second matching resistor access circuit can be connected to the positive output end of the clock chip. In other embodiments, the first end of the first matching resistor access circuit and the first end of the second matching resistor access circuit can also be exchanged with the output end of the clock chip.

[0048] Furthermore, the terminal matching resistor access circuit is mainly used to control the access of the terminal matching resistor. In this embodiment, the first end of the terminal matching resistor access circuit is connected to the second end of the first matching resistor access circuit, and the second end of the terminal matching resistor access circuit is connected to the second end of the second matching resistor access circuit.

[0049] The reference voltage and reference ground access circuit is mainly used to control the access of the reference voltage and the reference ground GND. The reference voltage and reference ground access circuit provides the reference voltage and the reference ground GND by connecting to the terminal matching resistor access circuit.

[0050] For a clearer description, specific implementation methods of various resistors are also provided in this embodiment.

[0051] Please refer to Figure 2, the first matching resistor access circuit includes a first switch K1, a second switch K2 and a first matching resistor R1. Among them, the first end of the first switch K1 is connected to the first end of the first matching resistor access circuit, and the second end of the first switch K1 is connected to the second end of the first matching resistor access circuit; the first end of the second switch K2 is connected to the first end of the first matching resistor access circuit, and the second end of the second switch K2 is connected to the second end of the first matching resistor access circuit via the first matching resistor R1. In practical applications, the access of the first matching resistor R1 can be achieved by controlling the on and off of the first switch K1 and the second switch K2.

[0052] Please continue to refer to Figure 2 , the second matching resistor access circuit includes a third switch K3, a fourth switch K4 and a second matching resistor R2; wherein the first end of the third switch K3 is connected to the first end of the second matching resistor access circuit, and the second end of the third switch K3 is connected to the second end of the second matching resistor access circuit via the second matching resistor R2; the first end of the fourth switch K4 is connected to the first end of the second matching resistor access circuit, and the second end of the fourth switch K4 is connected to the second end of the second matching resistor access circuit. In practical applications, the access of the second matching resistor R2 can be achieved by controlling the on and off of the third switch K3 and the fourth switch K4.

[0053] Through the cooperation of the first matching resistor access circuit and the second matching resistor access circuit, the direct connection characteristics and LVCMOS mode characteristics of the clock chip differential output can be realized. For the direct connection characteristics, the test can be completed by closing the first switch K1 and the third switch K3, and disconnecting the second switch K2 and the fourth switch K4. For the LVCMOS mode characteristics, the test can be completed by closing the second switch K2 and the fourth switch K4, and disconnecting the first switch K1 and the third switch K3.

[0054] In one embodiment, the first matching resistor R1 and the second matching resistor R2 provided by the first matching resistor access circuit and the second matching resistor access circuit are equal, and the setting of the resistance values ​​thereof is related to the chip being tested.

[0055] Please continue to refer to Figure 2 The terminal matching resistor access circuit includes a fifth switch K5, a sixth switch K6, a first terminal matching resistor R3 and a second terminal matching resistor R4. The first end of the fifth switch K5 is connected to the second end of the first matching resistor access circuit, and the second end of the fifth switch K5 is connected to the second end of the second matching resistor access circuit via the first terminal matching resistor R3, the second terminal matching resistor R4 and the sixth switch K6 in sequence.

[0056] In this embodiment, by designing the terminal matching resistor circuit, the control of the first matching resistor access circuit and the second matching resistor access circuit can be coordinated to achieve the test of the LVPECL mode characteristics of the differential output of the clock chip, that is, by closing the second switch K2, the fourth switch K4, the fifth switch K5, and the sixth switch K6, and opening the first switch K1 and the third switch K3, the test is completed.

[0057] In one embodiment, the first terminal matching resistor R3 and the second terminal matching resistor R4 in the terminal matching resistor circuit have the same resistance value, for example, both are 50 ohms.

[0058] Please continue to refer to Figure 2 The reference voltage and reference ground access circuit includes a reference voltage source VT, a reference ground GND, a seventh switch K7 and an eighth switch K8; wherein the output end of the reference voltage source VT is connected to a common node between the first terminal matching resistor R3 and the second terminal matching resistor R4 via the seventh switch K7; the reference ground GND is connected to a common node between the first terminal matching resistor R3 and the second terminal matching resistor R4 via the eighth switch K8.

[0059] In this embodiment, by designing the reference voltage and reference ground access circuit, and coordinating the control of the first matching resistor access circuit, the second matching resistor access circuit, and the terminal matching resistor circuit, the test of the LVDS, HCSL, and CML mode characteristics of the clock chip differential output can be realized. For the LVDS and CML mode characteristics, the test can be completed by closing the first switch K1, the fourth switch K4, the fifth switch K5, the sixth switch K6, and the seventh switch K7, and disconnecting the second switch K2, the third switch K3, and the eighth switch K8. For the HCLS mode characteristics, the test can be completed by closing the second switch K2, the third switch K3, the fifth switch K5, the sixth switch K6, and the eighth switch K8, and disconnecting the first switch K1, the fourth switch K4, and the seventh switch K7. It should be noted that, for the test of LVDS and CML mode characteristics, the closing control of the switch is the same, and the only difference is the output control of the reference voltage source VT, that is, under the LVDS mode characteristic test, the reference voltage source VT provides a voltage equal to the power supply voltage VDD0-2, and under the CML mode characteristic test, the reference voltage source VT provides a voltage equal to the power supply voltage VDD0.

[0060] The switches in the test circuit proposed in the embodiment of the present invention need to meet the bandwidth requirements of high-speed signals (depending on the clock frequency, such as 3Ghz). While ensuring signal integrity, they also need to meet requirements such as small size and good stability. In this embodiment, all switches in the test circuit can be implemented by RF switches (Radio Frequency) in wireless communications. Since the test is ultimately completed by ATE, in this embodiment, the closing and opening of the RF switch is controlled by ATE software. In other embodiments, switches that meet the requirements can also be used.

[0061] Since the test circuit needs to complete the test of the LVDS and CML mode characteristics of the clock chip differential output, and the difference between the two during the test is only the different reference voltage input, therefore, in this embodiment, the reference voltage source VT is an adjustable reference voltage source VT, and its output voltage needs to meet two voltage conditions, including the power supply voltage VDD0 and the power supply voltage VDD0-2. In practical applications, the output voltage of the reference voltage source VT can also be controlled by ATE software.

[0062] It should be noted that due to different chip scenarios, the impedance matching adopted is also different. Therefore, in this embodiment, the first impedance matching circuit and the second impedance matching circuit can be adjusted according to demand. In one embodiment, the first impedance matching circuit and the second impedance matching circuit are both 50 ohms to reduce signal reflection and distortion. In practical applications, the impedance matching of the first impedance matching circuit and the second impedance matching circuit can be achieved through the routing of the PCB board.

[0063] Through the clock chip ATE test circuit proposed in the present invention, different output types of tests can be satisfied through a compatible circuit, thereby reducing the matching circuit. At the same time, software switching is adopted in the compatible circuit to reduce the time of manual physical switching, thereby generally improving test efficiency and reducing test costs.

[0064] An embodiment of the present invention also proposes a clock chip ATE test method, which is implemented based on the aforementioned clock chip ATE test circuit, and realizes LVCMOS, LVPECL, LVDS, HCSL, and CML mode characteristic testing of the clock chip differential output signal by controlling the combined access of the first matching resistor R1, the second matching resistor R2, the terminal matching resistor, the reference voltage, and the reference ground GND.

[0065] Combine the following Figure 2 The specific process of each type of test is explained.

[0066] (1) Direct connection characteristics

[0067] The first switch K1 and the third switch K3 are closed, and the second switch K2 and the fourth switch K4 are opened; at this time, the differential output of the clock chip passes through the first impedance matching circuit and the second impedance matching circuit to reach the first test terminal Test-1 and the second test terminal Test-2 respectively, completing the direct connection characteristic test.

[0068] (2) LVCMOS mode characteristics

[0069] The second switch K2 and the fourth switch K4 are closed, and the first switch K1 and the third switch K3 are opened; at this time, the first path of the differential output of the clock chip passes through the first matching resistor R1 and the first impedance matching circuit to reach the first test terminal Test-1; the other path passes through the second matching resistor R2 and the second impedance matching circuit to reach the second test terminal Test-2, completing the test of the LVCMOS mode characteristics.

[0070] (3) LVPECL mode characteristics

[0071] The second switch K2, the fourth switch K4, the fifth switch K5, and the sixth switch K6 are closed, and the first switch K1 and the third switch K3 are opened; at this time, the differential output of the clock chip passes through the first impedance matching circuit and the second impedance matching circuit respectively, and is connected in parallel with the first terminal matching resistor R3 and the second terminal matching resistor R4, and then passes through the first impedance matching circuit and the second impedance matching circuit to reach the first test terminal Test-1 and the second test terminal Test-2, completing the test of the LVPECL mode characteristics.

[0072] (4) LVDS mode characteristics

[0073] The first switch K1, the fourth switch K4, the fifth switch K5, the sixth switch K6 and the seventh switch K7 are closed, and the second switch K2, the third switch K3 and the eighth switch K8 are opened; at this time, the differential output of the clock chip is connected to the reference voltage source VT in the reference voltage and reference ground access circuit through the first terminal matching resistor R3 and the second terminal matching resistor R4 respectively (in this test mode, the output voltage of the reference voltage source VT = VDD0-2), and then reaches the first test terminal Test-1 and the second test terminal Test-2 through the first impedance matching circuit and the second impedance matching circuit, completing the test of the LVDS mode characteristics.

[0074] (5) HCSL mode characteristics

[0075] The second switch K2, the third switch K3, the fifth switch K5, the sixth switch K6, and the eighth switch K8 are closed, and the first switch K1, the fourth switch K4, and the seventh switch K7 are opened; at this time, the differential output first terminal matching resistor R3 and the second terminal matching resistor R4 of the clock chip are connected to the reference ground GND in the reference voltage and reference ground access circuit, and then reach the first test terminal Test-1 and the second test terminal Test-2 through the first impedance matching circuit and the second impedance matching circuit, completing the test of the HCSL mode characteristics.

[0076] (6) CML mode characteristics

[0077] The first switch K1, the fourth switch K4, the fifth switch K5, the sixth switch K6 and the seventh switch K7 are closed, and the second switch K2, the third switch K3 and the eighth switch K8 are opened; at this time, the differential output of the clock chip is connected to the reference voltage source VT in the reference voltage and reference ground access circuit through the first terminal matching resistor R3 and the second terminal matching resistor R4 respectively (in this test mode, the reference voltage source VT outputs the voltage VT=VDD0, and then reaches the first test terminal Test-1 and the second test terminal Test-2 through the first impedance matching circuit and the second impedance matching circuit, completing the test of the CML mode characteristics.

[0078] In the test method proposed in the present invention, different output modes can be switched by controlling different switch combinations and reference voltage source output voltage combinations by ATE. The first test terminal and the second test terminal are connected to the ATE test machine to complete the performance test of different output modes of the clock chip, such as the frequency, duty cycle, amplitude and other parameters of the output clock.

[0079] For those skilled in the art, the specific meanings of the above terms in the present invention can be understood in specific situations; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0080] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A clock chip ATE test circuit, wherein the clock chip has a first differential output terminal and a second differential output terminal, characterized in that: include: a first impedance matching circuit; a second impedance matching circuit; A first matching resistor access circuit is used to control the access of the first matching resistor; The first end of the first matching resistor access circuit is connected to the first differential output end of the clock chip, and the second end of the first matching resistor access circuit is connected to the first test end via the first impedance matching circuit; the first matching resistor access circuit includes a first switch, a second switch and a first matching resistor, the first end of the first switch is connected to the first end of the first matching resistor access circuit, and the second end of the first switch is connected to the second end of the first matching resistor access circuit; the first end of the second switch is connected to the first end of the first matching resistor access circuit, and the second end of the second switch is connected to the second end of the first matching resistor access circuit via the first matching resistor; A second matching resistor access circuit is used to control the access of the second matching resistor; The first end of the second matching resistor access circuit is connected to the second differential output end of the clock chip, and the second end of the second matching resistor access circuit is connected to the second test end via the second impedance matching circuit; the second matching resistor access circuit includes a third switch, a fourth switch and a second matching resistor, the first end of the third switch is connected to the first end of the second matching resistor access circuit, and the second end of the third switch is connected to the second end of the second matching resistor access circuit via the second matching resistor; the first end of the fourth switch is connected to the first end of the second matching resistor access circuit, and the second end of the fourth switch is connected to the second end of the second matching resistor access circuit; wherein the first test end and the second test end are both used to provide a test signal for ATE; A terminal matching resistor access circuit, used to control the access of a terminal matching resistor; the first end of the terminal matching resistor access circuit is connected to the second end of the first matching resistor access circuit, and the second end of the terminal matching resistor access circuit is connected to the second end of the second matching resistor access circuit; the terminal matching resistor access circuit includes a fifth switch, a sixth switch, a first terminal matching resistor and a second terminal matching resistor, the first end of the fifth switch is connected to the second end of the first matching resistor access circuit, and the second end of the fifth switch is connected to the second end of the second matching resistor access circuit via the first terminal matching resistor, the second terminal matching resistor and the sixth switch in sequence; A reference voltage and reference ground access circuit is connected to a terminal matching resistor access circuit and is used to control the access of the reference voltage and the reference ground.

2. The clock chip ATE test circuit according to claim 1, characterized in that: The reference voltage and reference ground access circuit includes a reference voltage source, a reference ground, a seventh switch and an eighth switch; wherein, The output end of the reference voltage source is connected to a common node between the first terminal matching resistor and the second terminal matching resistor via a seventh switch; The reference ground is connected to a common node between the first terminal matching resistor and the second terminal matching resistor via an eighth switch.

3. The clock chip ATE test circuit according to claim 2, characterized in that: The reference voltage source is controlled by ATE to achieve output voltage change.

4. The clock chip ATE test circuit according to any one of claims 1 to 3, characterized in that: In the test circuit, all switches are high-speed control switches that meet the bandwidth requirements of high-speed signals, and the closing and opening control of the high-speed control switches is achieved by ATE.

5. The clock chip ATE test circuit according to claim 4, characterized in that: In the test circuit, all switches are implemented using radio frequency switches.

6. A clock chip ATE test method, characterized in that: The clock chip ATE test circuit is implemented based on any one of claims 1 to 5, including: testing of different types of differential output signals of the clock chip by controlling the combined access of the first matching resistor, the second matching resistor, the terminal matching resistor, the reference voltage and the reference ground.

7. The clock chip ATE testing method according to claim 6, characterized in that: The test of implementing different types of differential output signals of the clock chip includes LVCMOS, LVPECL, LVDS, HCSL, and CML types.

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