Controller and system for state compression in memory cells

Abstract

The invention discloses a controller and a system for state compression in a storage unit. The controller includes a processor. In one embodiment, a processor is configured to set a value of D bits based on a value of M bits. M is an integer greater than 0, and D is an integer greater than 0. The controller is configured to write a value of D bits and a value of M bits into a memory cell of the non-volatile memory. In another embodiment, the controller is configured to read a value of M bits and a value of D bits from a memory cell of the non-volatile memory, and the controller includes a processor configured to determine the value of M bits based on the value of D bits.

Description

Technical Field

[0001] The present disclosure relates to state compression in a storage unit. Background Art

[0002] As solid-state drive (SSD) technology continues to develop, different types of memory cells have been developed to store data, including single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and even penta-level cells (PLC).

[0003] For the memory cells of the SSD, different states are defined by a read reference voltage Vth. For example, in the case of SLC, a single read reference voltage Vth is used to define one bit (or one level) with two states "1" and "0". In the case of MLC, three read reference voltages Vth0, Vth1, and Vth2 are used to define two bits (or two levels) with four states "11", "10", "01", and "00". In the case of TLC, seven read reference voltages are used to define three bits (or three levels) with eight states "111", "110", "101", "100", "011", "010", "001", and "000". And, in the case of QLC, four bits (or four levels) having sixteen states "1111", "1110", "1101", "1100", "1011", "1010", "1001", "1000", "0111", "0110", "0101", "0100", "0011", "0010", "0001", and "0000" are defined by using fifteen read reference voltages. The case of PLC follows a similar pattern.

[0004] SLC cells store one bit of data per cell, providing high performance, durability, and reliability. They have faster read and write speeds, but are more expensive and have lower capacity than other cell types.

[0005] In SSDs, static data such as log files, system configuration data, and firmware are stored in SLC cells. These data are written once, rarely change, and require high reliability. Therefore, they are stored in SLC cells to reduce wear and maintain reliability.

[0006] In addition to these static data, a mapping table of logical addresses to physical addresses can be written into the SLC cell when a power outage occurs. When power is restored, the firmware will read the mapping table from the SLC cell to rebuild the table.

[0007] SLC cells can be used as program data buffers. In this usage scenario, the data to be programmed is first written to the SLC cells and then moved to the TLC cells in a background programming operation.

[0008] Since SLC cells have a lower raw bit error rate and are more reliable than MLC / TLC / QLC cells, SLC cells are often used to save the above critical data.

[0009] TLC / QLC can be used as SLC cells or TLC / QLC cells. For example, 20% of all cells in an SSD can be used as SLC cells.

[0010] If the number of SLC cells (including TLC / QLC cells used as SLC cells) can be reduced, the supply of TLC / QLC cells will increase. Therefore, the write amplification factor can be reduced, and the performance and life of the SSD can be improved.

[0011] Reducing SLC cells while meeting data storage requirements previously met by SLC cells may help.

[0012] Although this disclosure uses SSD to explain state compression, state compression may be applicable to other memories. Summary of the invention

[0013] In one embodiment, the controller has a processor configured to set a value of a D bit based on a value of an M bit. M is an integer greater than 0, and D is an integer greater than 0. The controller is configured to write the value of the D bit and the value of the M bit into a storage unit of the non-volatile memory.

[0014] In another embodiment, the controller is configured to read an M-bit value and a D-bit value from a storage unit of the non-volatile memory. M is an integer greater than 0, and D is an integer greater than 0. The controller has a processor configured to determine the M-bit value based on the D-bit value.

[0015] In yet another embodiment, the system includes a controller. The system is a solid state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

[0016] The foregoing is provided by way of general introduction and is not intended to limit the scope of the present invention as claimed.The described embodiments together with further advantages will be best understood by reference to the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A system according to one embodiment is schematically shown.

[0018] Figure 2 An example of state compression of a TLC cell is schematically shown.

[0019] Figure 3 An example of state compression of a QLC cell is schematically shown.

[0020] Figure 4 Gray code state representation in normal TLC mode is shown.

[0021] Figure 5 An 8 to 4 compressed state representation of TLC Example 1 is shown.

[0022] Figure 6 The status representation in normal TLC mode is shown.

[0023] Figure 7 The shift of the read reference voltage for the read retry of UP is schematically shown.

[0024] Figure 8 An 8 to 4 compression state representation of TLC Example 2 is shown.

[0025] Fig. 9 Another Gray code state representation in normal TLC mode is shown.

[0026] Figure 10-13 Four 8-to-4 TLC state compression schemes are shown.

[0027] Fig.14 Gray code state representation in normal QLC mode is shown.

[0028] Fig.15 A 16 to 8 compressed state representation of QLC Example 1 is shown.

[0029] Fig.16 A 16-to-4 compressed state representation of QLC Example 2 is shown.

[0030] Fig.17 is a schematic flow chart of a programming operation of a word line with a fully protected state compression scheme of the present disclosure.

[0031] Fig.18 is a schematic flow chart of a read operation of a word line with a fully protected state compression scheme of the present disclosure.

[0032] Fig.19 Schematically illustrates partial page usage of a state compression scheme in a TLC block. DETAILED DESCRIPTION

[0033] Now, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. In various drawings, the same elements are represented by the same reference numerals to maintain consistency.

[0034] The present disclosure proposes a state compression scheme that can provide better reliability of data storage in an SSD. The state compression scheme can be used to reduce the number of SLC blocks in an SSD to increase the life of the SSD.

[0035] Relative to the number of states that a storage cell of a non-volatile memory (NVM) physically has, a state compression scheme uses a smaller number of states for data storage. For example, a TLC cell physically has 8 states, but under a state compression scheme, only 2 or 4 states are used for data storage. That is, under a state compression scheme, a TLC cell is used as an SLC cell or an MLC cell. Similarly, a QLC cell physically has 16 states, but under a state compression scheme, only 2 or 4 or 8 states are used for data storage. That is, under a state compression scheme, a QLC cell is used as an SLC cell, an MLC cell, or a TLC cell.

[0036] In other words, although there are 8 states in TLC and 16 states in QLC, by applying an encoding scheme to the programming data, state compression can be achieved so that the number of states of a word line in TLC or QLC is reduced, and due to the fine programming operation, the margin between two adjacent states is larger than that of a normal TLC / QLC word line. Therefore, the state-compressed word line may have better reliability and lower raw bit error rate (BER).

[0037] Similarly, the proposed scheme can also be applied to MLC and PLC.

[0038] Figure 1 A system according to one embodiment is schematically shown.

[0039] In some embodiments, the system is a solid state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

[0040] System 100 may include a controller 102 and a non-volatile memory device (NVM) 104. In some embodiments, system 100 may be used as a storage system and provide data storage and / or access to stored data to a host when connected to the host.

[0041] The storage device 104 may be a non-volatile memory (NVM), such as a NAND device. The system 100 may include multiple non-volatile storage devices, and the storage device 104 may be shown as a representative of the multiple non-volatile storage devices.

[0042] The controller 102 includes a processor 106. The processor 106 may be a computer processor such as, but not limited to, a microprocessor or a microcontroller.

[0043] The controller 102 may write data to the storage device 104 and read data from the storage device 104. The processor 106 may perform some processing on some data to be written to the storage cells of the storage device 104 or some data to be read from the storage cells of the storage device 104.

[0044] A memory cell is the smallest physical storage unit in the storage device 104. In some embodiments, the memory cell may be a NAND cell. In the case of SLC, MLC, TLC, QLC, and PLC, one memory cell is configured to store 1, 2, 3, 4, and 5 bits of data by defining 2, 4, 8, 16, and 32 states using 1, 3, 7, 15, and 31 read reference voltages, respectively. Data is written to a memory cell by programming a voltage within a range corresponding to the bit value of the data into the memory cell, and data is read from the memory cell by comparing the threshold voltage of the memory cell with the read reference voltage.

[0045] The term "bit" refers to a binary digit, which is the basic unit of information in computing and digital communication, as well as data storage. It is usually represented as 0 or 1, corresponding to the two possible states of a digital signal or two values ​​in binary code.

[0046] Assume that the memory cell is initially configured to store N bits of data with 2 N states. Here, N is an integer greater than 1. For example, N=2 represents the MLC mode; N=3 represents the TLC mode; N=4 represents the QLC mode; and N=5 represents the PLC mode.

[0047] The MLC cell is configured to store 2 bits of data, which can be mapped to 2 pages, namely a lower page "LP" and an upper page "UP". The TLC cell is configured to store 3 bits of data, which can be mapped to 3 pages, namely a lower page "LP", an upper page "UP" and an extra page "XP". The QLC cell is configured to store 4 bits of data, which can be mapped to 4 pages, namely a lower page "LP", a middle page "MP", an upper page "UP" and a top page "TP".

[0048] Under the state compression scheme, 2 N The states can be compressed into 2 M states, corresponding to M bits. In other words, the data desired to be written into the memory cell has M bits. Here, M is an integer greater than 0, for example, M=1, M=2, M=3 or M=4. The M-bit data may be the data desired to be written into the memory cell.

[0049] Since the memory cell is originally designed and configured for N bits, for example, in the TLC mode with N=3 or in the QLC mode with N=4, the word lines connected to the memory cell are configured for N bits (or N pages). Under the state compression scheme, there are still D=NM bits (pages) of data that need to be programmed, which can be called "redundant bits" or "redundant pages". Here, D is an integer greater than 0. For example, D=1 or D=2.

[0050] When D=1, for the MLC mode, M=1; for the TLC mode, M=2; for the QLC mode, M=3; and for the PLC mode, M=4.

[0051] When D=2, for the TLC mode, M=1; for the QLC mode, M=2; and for the PLC mode, M=3.

[0052] The controller 102 may perform write operations and / or read operations on storage cells of the non-volatile memory (NVM) 104, which may be referred to as a “write embodiment” or a “read embodiment”. It should be understood that when the controller 102 is configured to read data from the non-volatile memory (NVM) 104, this does not mean that the data in the non-volatile memory (NVM) 104 is written by the controller 102.

[0053] In the embodiment written, the processor 106 is configured to set the value of the D bit based on the value of the M bit. For example, the processor 106 is configured to set the value of the D bit using one or more results of performing one or more logical operations (e.g., AND, DIS, INVERSE, XOR) on one or more values ​​of the M bit.

[0054] In some embodiments, processor 106 is configured to set a value of at least one of the D bits based on a value of only one of the M bits.

[0055] In some other embodiments, the processor 106 is configured to set the value of at least one of the D bits based on the value of only two of the M bits.

[0056] The controller 102 is configured to write the D-bit value and the M-bit value into a storage cell of a non-volatile memory (NVM) 104 .

[0057] In some cases, the D bits of data derived from the value of the M bits can be used to recover or correct one or more lost or erroneous bits in the M bits. This can be performed when checking, recovering or correcting one or more bits in the M bits.

[0058] In the read embodiment, the controller 102 is configured to read the value of the M bit and the value of the D bit from a memory cell of the non-volatile memory (NVM) 104, and the processor 106 is configured to determine the value of the M bit based on the value of the D bit.

[0059] In some embodiments, processor 106 is configured to determine the value of at least one of the M bits based on the value of only one of the D bits.

[0060] In some other embodiments, the processor 106 is configured to determine the value of at least one of the M bits based on the value of only two of the D bits.

[0061] In the above embodiments and examples, N=M+D. It should be understood that in some other embodiments, N=M+D+E is also possible. Here, E is an integer greater than 0. The D redundant bits are set based on the value of the M-bit data expected to be written to the storage cell, and the further E bit can be set in any other suitable scheme. The controller 102 is configured to write the value of the E bit, the value of the D bit, and the value of the M bit into the storage cell of the non-volatile memory (NVM) 104.

[0062] Hereinafter, some schemes for setting the value of the D bit or determining the value of the M bit will be described. In the setting scheme, logical operations such as "invert", "disjunction" and "exclusive or" will be used.

[0063] The "negation" of a bit value, also known as the logical "NOT" operation, is sometimes represented by a simple "~" and is used to flip or invert the state of a bit value. For example, the negation of a bit value of 0 is 1, and the negation of a bit value of 1 is 0.

[0064] The "disjunction" of two bits, also called the logical "OR" operation, sometimes represented by the symbol "|", returns 1 if at least one bit is 1. Otherwise, it returns 0.

[0065] Following is the truth table for the disjunction operation: Position A Position B A OR B 0 0 0 0 1 1 1 0 1 1 1 1

[0066] As the truth table shows, if either bit A or bit B (or both) is 1, the result of the disjunction operation will be 1. The result will only be 0 if both bits are 0.

[0067] The "exclusive OR" of two bits, also known as the logical "XOR" (exclusive OR) operation, returns 1 if the two bits have different values. Otherwise, it returns 0.

[0068] Following is the truth table for the XOR operation: Position A Position B A XOR B 0 0 0 0 1 1 1 0 1 1 1 0

[0069] As the truth table shows, when the two bits have different values ​​(one is 0 and the other is 1), the result of the XOR operation is 1. If the two bits are the same (either both are 0 or both are 1), the result is 0.

[0070] In a written embodiment, the processor is configured to set the value of at least one of the D bits to the value of one of the M bits.

[0071] For example, for a TLC cell, if LP and UP are designed to store M (here M=2) bits of data, and XP is designed to store one of D (here D=1) bits, the value of XP can be set to the value of UP or LP, that is, XP=UP or XP=LP.

[0072] Accordingly, in the read embodiment, the processor is configured to determine the value of one of the D bits as the value of at least one of the M bits.

[0073] For example, for a TLC cell, LP and UP are designed to store M (here M=2) bits of data, and XP is designed to store one of D (here D=1) bits, and the value of XP is set to the value of UP (or LP), that is, when writing data to the memory cell, XP=UP (or XP=LP). If UP (or LP) cannot be decoded when reading the value of the bit written in the memory cell, but XP can be decoded, the value of UP (or LP) can be determined as the value of XP.

[0074] In another written embodiment, the processor is configured to set the value of at least one of the D bits to the exclusive-OR-negation of the values ​​of two of the M bits.

[0075] For example, for a TLC cell, if LP and UP are designed to store M (here M=2) bits of data, and XP is designed to store one of D (here D=1) bits, the value of XP can be set to XP=NOT(UP XOR LP).

[0076] Alternatively, if LP and XP are designed to store M (here M=2) bits of data, and UP is designed to store one of D (here D=1) bits, the value of UP may be set to UP=NOT(XP XOR LP).

[0077] Accordingly, in the read embodiment, the processor is configured to determine the value of at least one of the M bits as the XOR of the value of another of the M bits and the inverse of the value of one of the D bits, or is configured to determine the value of at least one of the M bits as the XOR of the value of one of the D bits and the inverse of the value of another of the M bits.

[0078] For example, for a TLC cell, LP and UP are designed to store M (here M=2) bits of data, and XP is designed to store one of D (here D=1) bits, and the value of XP is set to XP=NOT (UP XOR LP). If XP and UP can be decoded from the storage cell, but LP cannot be decoded, LP can be determined based on LP=(NOT XP) XOR UP. If XP and LP can be decoded, but UP cannot be decoded, UP can be determined based on UP=(NOT XP) XOR LP.

[0079] In another example, LP and XP are designed to store M (here M=2) bits of data, and UP is designed to store one of D (here D=1) bits, and the value of UP is set to UP=NOT(XP XOR LP). If UP and LP can be decoded from the storage unit, but XP cannot be decoded, XP can be determined based on XP=(NOT UP)XOR LP. If UP and XP can be decoded, but LP cannot be decoded, LP can be determined based on LP=(NOT UP)XOR XP.

[0080] In another example, UP and XP are designed to store M (here M=2) bits of data, and LP is designed to store one of D (here D=1) bits, and the value of LP is set to LP=NOT(XP XOR UP). If LP and UP can be decoded from the storage unit, but XP cannot be decoded, XP can be determined based on XP=(NOT LP)XOR UP. If LP and XP can be decoded, but UP cannot be decoded, UP can be determined based on UP=(NOT LP)XOR XP.

[0081] In another written embodiment, the processor is configured to set the value of at least one of the D bits to the disjunction of the inverse of a value of one of the M bits and the inverse of a value of another of the M bits.

[0082] For example, for a TLC cell, if LP and UP are designed to store (here M=2) bits of data, and XP is designed to store (here D=1) bits of one, the value of XP can be set to XP=(~LP)|(~UP), that is, XP=(NOT LP)OR(NOT UP).

[0083] In another written embodiment, the processor is configured to set the value of at least one of the D bits to the disjunction of a value of one of the M bits and the inverse of a value of another of the M bits.

[0084] For example, for a TLC cell, if LP and UP are designed to store (here M=2) bits of data, and XP is designed to store (here D=1) bits of data, the value of XP can be set to XP=LP|(~UP), that is, XP=(LP)OR(NOT UP).

[0085] In another written embodiment, the processor is configured to set the value of at least one of the D bits to be an exclusive OR of the values ​​of two of the M bits.

[0086] For example, for a TLC cell, if LP and XP are designed to store (here M=2) bits of data, and UP is designed to store (here D=1) bits of one, the value of UP may be set to UP=XP XOR LP.

[0087] In another written embodiment, the processor is configured to set the value of at least one of the D bits to the exclusive OR result of the value of the second bit and the value of the third bit and the value of the first bit, wherein the first bit, the second bit and the third bit are certain three bits of the M bits.

[0088] For example, for a QLC cell, if LP, MP, and UP are designed to store (here M=3) bits of data, and TP is designed to store (here D=1) bits of one, the value of TP can be set to TP=LP XOR MP XOR UP.

[0089] It should be understood that if M is greater than 3, the first, second and third bits can be any three bits of M. The first, second and third bits do not imply any particular bits. For example, the first bit is not necessarily the most significant bit.

[0090] Hereinafter, the state compression effect produced by the scheme of the present disclosure will be described through some examples.

[0091] According to the scheme of the present disclosure, although there are 8 states in TLC and 16 states in QLC, by applying an encoding scheme to programming data, state compression can be achieved, so that the number of states of a word line in TLC or QLC is reduced, and due to the fine programming operation, the margin between two adjacent states is greater than that of a normal TLC / QLC word line. Therefore, the state-compressed word line has better reliability and lower original BER.

[0092] Similarly, the proposed scheme can also be applied to MLC and PLC.

[0093] Figure 2 An example of state compression of a TLC cell is schematically shown.

[0094] like Figure 2As shown, in the normal TLC mode, 7 read reference voltages Vth (as shown by 7 upward arrows) are used to define 8 states T0, T1, T2, T3, T4, T5, T6 and T7. Each word line has 3 data pages and 0 redundant pages.

[0095] When the 8-to-4 state compression scheme is applied to the TLC cell, the four non-adjacent states (eg, T0, T2, T5, T7) in the original 8-state list are retained. Each word line has 2 data pages and 1 redundant page.

[0096] When the 8-to-2 state compression scheme is applied to the TLC cell, the 2 non-adjacent states (eg, T0 and T7) in the original 8-state list are retained. Each word line has 1 data page and 2 redundant pages.

[0097] Figure 3 An example of state compression of a QLC cell is schematically shown.

[0098] like Figure 3 As shown, in normal QLC mode, 15 read reference voltages Vth (as shown by 15 upward arrows) are used to define 16 states Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14 and Q15. Each word line has 4 data pages and 0 redundant pages.

[0099] When the QLC cell applies a 16-to-8 state compression scheme, the non-adjacent 8 states (e.g., Q0, Q2, Q4, Q6, Q8, Q10, Q12, and Q15) in the original 16-state list are retained. Each word line has 3 data pages and 1 redundant page.

[0100] When the QLC cell applies a 16-to-4 state compression scheme, the non-adjacent 4 states (eg, Q0, Q5, Q10, Q15) in the original 16-state list are retained. Each word line has 2 data pages and 2 redundant pages.

[0101] When the QLC cell applies a 16-to-2 state compression scheme, 2 non-adjacent states (eg, Q0 and Q15) are retained in the original 16-state list. Each word line has 1 data page and 3 redundant pages.

[0102] From the above description, it can be seen that the state compression scheme provides a trade-off between data reliability and the overhead of SSD storing critical data.

[0103] In a conventional SSD with TLC flash NAND that does not adopt a state compression scheme, the block used as the SLC area occupies about 20% of the entire flash NAND block. If we use 4-state compression TLC to replace the SLC area, only 10% of the entire block is required. The other 10% of the block can be used as a TLC area to provide more reserved space. Therefore, the overhead of storing critical data and the overhead of the data buffer are half of those of conventional SSDs.

[0104] In some embodiments, state-compressed MLCs may be used to store critical data instead of using SLCs to store critical data.

[0105] The TLC cell stores 8 states, which can be represented by 8 three-bit binary codes. The correspondence between the 8 three-bit binary codes and the 8 states can be established using different sorting methods.

[0106] Gray code is a binary numeral system that represents consecutive values ​​in such a way that only one bit changes between consecutive values.

[0107] In Gray code state representation, each state is encoded using a binary code where adjacent states differ by only one bit. This helps reduce the possibility of errors due to noise or signal distortion during transmission or processing.

[0108] For a given Gray code state representation, there are multiple state compression schemes, some of which (which may be referred to as "fully protected state compression schemes") provide better data protection than others.

[0109] Several examples of state compression schemes are described in more detail below.

[0110] TLC Example 1

[0111] This is an example of compressing the 8 states of a TLC cell into 4 states.

[0112] Figure 4 A Gray code state representation in normal TLC mode that can be used for this example is shown.

[0113] like Figure 4 As shown, in this Gray coding rule, the eight states T0, T1, T2, T3, T4, T5, T6 and T7 are respectively mapped to eight three-bit binary codes 111, 011, 001, 101, 100, 000, 010 and 110. As mentioned above, the first bit (left) corresponds to XP (extra page), the middle bit corresponds to UP (upper page), and the last bit (right) corresponds to LP (lower page).

[0114] The eight states are defined by seven read reference voltages V1 to V7.

[0115] LP may be determined by only one read reference voltage V4, as indicated by the longest upward arrow.

[0116] UP can be determined by two read reference voltages V2 and V6, as shown by the medium length upward arrow. If the threshold voltage of the cell is between V2 and V6, UP = 0. If the threshold voltage of the cell is not between V2 and V6, UP = 1.

[0117] XP may be determined by four read reference voltages V1 , V3 , V5 , and V7 , as indicated by the shortest upward arrow.

[0118] By setting XP=LP, only four states remain, namely 111, 001, 000 and 110. Therefore, the 8 states of the normal TLC mode are compressed into 4 states.

[0119] In this example, the extra page (XP) data is encoded to be consistent with the upper page (UP) data (XP=LP), which results in state compression.

[0120] Figure 5 An 8 to 4 compressed state representation of TLC Example 1 is shown.

[0121] With state compression, TLC mode memory cells can now be used in MLC mode.

[0122] In TLC Example 1, the UP bit is protected. If UP cannot be decoded but XP can be decoded when reading the value of the bit written to the memory cell, UP can be restored by UP=XP.

[0123] Figure 6 The status representation in normal MLC mode is shown.

[0124] Compare Figure 5 and Figure 6 The difference between TLC 8 to 4 state compression and normal MLC can be seen. Figure 5 and Figure 6 Each cell has 4 states, but MLC states are closer to each other, while TLC 8 to 4 state compression has wider valley windows between states. Wider valley windows can provide lower RBER (raw bit error rate).

[0125] The distribution of dual-coded units in TLC mode (such as Figure 5 than MLC mode (as shown) Figure 6 The NAND memory is much better than the NAND memory shown in Figure 1 because the NAND memory applies the fine-grained programming mode of TLC operation instead of MLC programming operation. This will ensure more reliable data and lower RBER, thus providing another way to store critical data and reduce the number of SLC blocks required.

[0126] In addition, the extra page (XP) provides another layer of protection for the upper page (UP).

[0127] If the upper page (UP) cannot be decoded but the extra page (XP) can be decoded, data of the upper page (UP) can be restored by decoding the extra page (XP).

[0128] However, the data of the lower page (LP) is not protected by the XP and UP data. Therefore, this scheme is not a fully protected state compression scheme.

[0129] Use as Figure 5 With the state compression scheme shown, the UP bit can be read using either a voltage between V1 and V2 or V2 (preferred) or V1.

[0130] In TLC Example 1, the probability of a lower page (LP) error is very low for the following reasons.

[0131] First, unlike the upper page (UP) and extra page (XP) which apply two internal reads, the lower page (LP) applies only a single read, which has a lower error rate.

[0132] Secondly, since the proposed scheme does not have T3 and T4 states, the margin of the read reference voltage Vref4 (V4) relative to the adjacent states is greatly increased and the RBER is greatly reduced.

[0133] On the other hand, while the read margin of the lower page (LP) Vref is improved on both sides of the adjacent states, the read margin of the UP and XP Vref is improved only on one side.

[0134] For example, XP Vref (V1, V3, V5, and V7) obtains increased read margin to the right of states T1 and T3 and to the left of states T4 and T6.

[0135] UP Vref (V2 and V6) obtains increased read margin to the right of state T6 and to the left of state T1.

[0136] like Figure 5 As shown, the default Vref for UP and XP in Example 1 is no longer aligned with the center of the new valley window.

[0137] Now that the narrow margin point is known, the read retry during UECC can apply Vref shifted to the center of the new valley window to obtain a smaller RBER and a higher probability of successful decoding, such as Figure 5 shown.

[0138] Figure 7 The shift of the read reference voltage for the read retry of UP is schematically shown.

[0139] like Figure 7As shown, the read reference voltage V2 for reading UP can be shifted from the right side of the valley window between T0 and T2 to the middle of the valley window, i.e., V'2, and the read reference voltage V6 for reading UP can be shifted from the left side of the valley window between T5 and T7 to the middle of the valley window, i.e., V'6.

[0140] TLC Example 2

[0141] In TLC Example 2, use Figure 4 The same Gray coding rules are shown for normal TLC mode.

[0142] In this example, the XP page is set to XP=NOT (UP XOR LP).

[0143] Figure 8 An 8 to 4 compression state representation of TLC Example 2 is shown.

[0144] like Figure 8 As shown, the remaining four states are T0 (111), T2 (001), T4 (100) and T6 (010).

[0145] When reading from a memory cell, if only one page cannot be decoded, the data of the other two pages can be used to recover it.

[0146] Therefore, the extra page (XP) provides another layer of protection for the upper page (UP) and the lower page (LP).

[0147] Therefore, the state compression scheme of this example is a fully protected state compression scheme.

[0148] It should be noted that for the 8-to-4 state compression TLC scheme, although there are only four states after programming, representing two pages of user data. Since the word line is in TLC mode, three pages of data are still required for programming. The remaining pages are used as redundant pages.

[0149] In some embodiments, any two of the three pages may be used for user data, and the remaining one may be used for a redundant page. In some embodiments, some of the three pages may be allocated to data pages and redundant pages, preferably or not.

[0150] For based on Figure 4 The 8-to-4-state compression scheme shown in TLC Example 1 with Gray coding rule for the states shown can use (UP, LP) or (XP, LP) to store two pages of user data, but using (XP, UP) is not preferred.

[0151] For the (UP, LP) representation, XP will be a redundant page and provide another copy of UP.

[0152] Similarly, if the (XP, LP) representation is used, UP will be a redundant page and provide another copy of XP.

[0153] However, since LP has a lower decoding failure probability compared to UP and XP, it is not preferable to use LP as a redundant page. One of UP and XP may be used as a redundant page to protect the other page.

[0154] For the 8-to-4 state compression scheme shown in TLC Example 2, the data pages can be any two pages: (LP, UP), (LP, XP), or (UP, XP). The remaining pages are redundant pages.

[0155] To reduce read latency, (LP, UP) will be used as data pages and XP will be used as redundant pages because LP only requires one read reference voltage Vref (V4), UP requires two read reference voltages Vref (V2, V6), and XP requires four read reference voltages Vref (V1, V3, V5, V7).

[0156] TLC Example 3

[0157] The Gray code state representation used for TLC in this example is different from TLC Examples 1 and 2.

[0158] Fig. 9 Another Gray code state representation in normal TLC mode used in TLC Example 3 is shown.

[0159] like Fig. 9 As shown, in this Gray coding rule, the eight states T0, T1, T2, T3, T4, T5, T6 and T7 are mapped to eight three-bit binary codes 111, 110, 100, 000, 010, 011, 001 and 101 respectively.

[0160] The eight states are defined by seven read reference voltages V1 to V7.

[0161] Specifically, LP requires two read reference voltages Vref (V1, V5); XP requires two read reference voltages Vref (V3, V7); UP requires three read reference voltages Vref (V2, V4, V6). The read reference voltages of each page are schematically indicated by upward arrows of different lengths.

[0162] and Figure 4 Gray code state representation is similar for Fig. 9 The Gray code state representation shown, there are multiple ways to achieve 8 to 4 TLC state compression.

[0163] Figure 10-13 Four 8-to-4 TLC state compression schemes are shown.

[0164] Fig.10 The first solution is achieved by setting XP = (~LP) | (~UP), that is, XP = (NOT LP) OR (NOT UP). The remaining 4 states are T1 (110), T2 (100), T5 (011) and T7 (101).

[0165] Fig.11 The second solution is achieved by setting XP=LP|(~UP), that is, XP=LP OR (NOT UP). The remaining 4 states are T0 (111), T2 (100), T4 (010) and T7 (101).

[0166] Fig.12 The third solution is achieved by setting XP = NOT (UP XOR LP). The remaining 4 states are T0 (111), T2 (100), T4 (010) and T6 (001).

[0167] exist Figure 10-12 Of the solutions shown, only Fig.12 The third scheme shown provides protection for the extra page (XP) and the lower page (LP) while providing a large margin between two adjacent states. Fig.12 The third scheme shown is a fully protected 8-to-4 state compression scheme and provides a Fig.10 and Fig.11 The first and second schemes shown are better 8 to 4 state compression schemes.

[0168] for Fig.12 In the third scheme, in order to reduce the read latency, XP and LP are used for data pages; UP is used for redundant pages. This is because, as mentioned above, Fig. 9 In the Gray code state representation shown, UP uses 3 read reference voltages, while XP and LP use 2 read reference voltages.

[0169] If one of the data pages cannot be decoded, the redundant page is read and decoded. If the redundant page can be decoded, the other data page and the redundant page can be used to recover the data page that failed to decode.

[0170] Specifically, if Fig.12 In the third solution shown, data is written into the storage unit, LP and UP can be decoded, but XP cannot be decoded. Then XP can be determined by XP=(NOT UP) XOR LP.

[0171] Similarly, Fig.13 based on Fig. 9 The same Gray code state representation shown provides another fully protected 8-to-4 state compression scheme. Fig.13This is achieved by setting UP = (XP XOR LP). The remaining 4 states are T1 (110), T3 (000), T5 (011) and T7 (101).

[0172] QLC Example 1

[0173] This is an example of compressing the 16 states of a QLC cell into 8 states.

[0174] Fig.14 A Gray code state representation in normal QLC mode that can be used for this example is shown.

[0175] like Fig.14 As shown, in this Gray coding rule, 16 states T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14 and T15 are respectively mapped to 16 four-bit binary codes 1111, 1110, 1100, 1101, 1001, 0001, 0000, 1000, 1010, 0010, 0110, 0100, 0101, 0111, 0011 and 1011. As mentioned above, the first bit (left) corresponds to TP (top page), the second bit corresponds to UP (upper page), the third bit corresponds to MP (middle page), and the last bit (right) corresponds to LP (lower page).

[0176] 16 states are read by 15 reference voltages V1 to V 15 definition.

[0177] Specifically, LP requires four read reference voltages Vref (V1, V3, V6, V 12 ); MP requires four read reference voltages Vref (V2, V8, V 11 、V 13 ); UP requires three read reference voltages Vref (V4, V 10 、V 14 );TP requires four read reference voltages Vref (V5, V7, V9, V 15 ). The read reference voltages of the various pages are schematically indicated by upward arrows of different lengths.

[0178] In this example, LP, MP, and UP may be used as three data pages to store user data, and TP may be used as a redundant page.

[0179] The 16 to 8 full protection state compression scheme of QLC is implemented by setting TP=LP XOR MP XOR UP.

[0180] Fig.15 A 16 to 8 compressed state representation of QLC Example 1 is shown.

[0181] like Fig.15 As shown, the remaining 8 states are T0 (1111), T2 (1100), T4 (1001), T6 (0000), T8 (1010), T10 (0110), T12 (0101) and T14 (0011).

[0182] When reading data from a memory cell, if any one of the data pages LP, MP, and UP cannot be decoded, the successfully decoded TP may be used to recover the failed page.

[0183] QLC Example 2

[0184] Fig.16 A 16-to-4 compressed state representation of QLC Example 2 is shown. QLC Example 2 is based on Fig.14 The same Gray code state representation is shown.

[0185] For Gray code state representation, there may not be a completely protected 16-to-4 state compression scheme. For example, for Fig.14 The Gray code states shown indicate that there is no 16 to 4 state compression for complete protection.

[0186] For this state compression scheme, (T0, T5, T10, T15) will be selected to expand the margin between any two adjacent states.

[0187] Furthermore, in this example, TP and UP will be used as data pages. For this state compression scheme, LP and MP can be used as redundant pages to provide additional data protection for the data in TP.

[0188] Several examples of state compression schemes for TLC and QLC are described above.

[0189] In a TLC cell, if the 8-to-4 state compression scheme does not have any two adjacent states that satisfy one of the following two fully protected 8-to-4 state compression scheme encoding rules: XP=NOT(UP XOR LP), XP=UP XOR LP. One page among LP, UP and XP with the largest number of Vref can be used as a redundant page, and the other two pages can be used as data pages.

[0190] In a QLC cell, a 16-to-8 state compression scheme is fully protected if no two adjacent states of the scheme satisfy one of the following two encoding rules: TP=NOT(UP XOR MP XOR LP), TP=UPXOR MP XOR LP,. One page with the largest number of Vrefs among LP, MP, UP, and TP can be used as a redundant page, and the other three pages can be used as data pages.

[0191] Fig.17is a schematic flow chart of a programming operation of a word line with the state compression scheme of the present disclosure.

[0192] Programming operations can be performed by Figure 1 The controller 102 of the illustrated system 100 executes.

[0193] like Fig.17 As shown, in step S110, a data page is prepared.

[0194] Then, in step S120, redundant pages are generated (or set) based on corresponding encoding rules.

[0195] As described in this disclosure, a redundant page may be based on at least one of the data pages.

[0196] Then, in step S130 , the data page and the redundancy page are all programmed to the word lines to write into the memory cells.

[0197] If the data stored in the state compression memory cell is programmed with a fully protected state compression scheme, then when reading the data stored in the memory cell, a failed data page decode can be recovered with the help of a redundant page.

[0198] Fig.18 is a schematic flow chart of a read operation of a word line with a fully protected state compression scheme of the present disclosure.

[0199] Read operations can be performed by Figure 1 The controller 102 of the illustrated system 100 executes.

[0200] Fig.18 An example of reading a page of data from a state-compressed storage unit having multiple pages is shown.

[0201] like Fig.18 As shown, in step S210, a data page is read from a memory cell, for example, by using a read reference voltage corresponding to the data page.

[0202] In step S220, it is checked whether the data page can be decoded. For example, the page can be decoded by an ECC decoder.

[0203] If the decoding can be successfully performed, the process goes to step S230, the page data is output as a result, and the process ends.

[0204] If the decoding cannot be successfully performed, the process goes to step S240 to read all other pages from the memory cell.

[0205] In step S250 , it is checked whether all other pages in the same word line can be decoded.

[0206] If all other pages in the same word line can be decoded, the process goes to step S260, data from all these other pages are used to recover the page data and output the page data as a result, and the process ends.

[0207] If any of the other pages cannot be successfully decoded, the process goes to step S270 and another advanced error recovery scheme may be further tried.

[0208] The state compression scheme proposed in this disclosure may be used by portions of a word line.

[0209] Fig.19 Schematically illustrates partial page usage of a state compression scheme in a TLC block.

[0210] like Fig.19 As shown, a portion of a TLC block (e.g., the first four bytes of three pages (LP, UP, and XP) of a TLC word line) is encoded using a state compression scheme. The remainder of the TLC block (e.g., the remaining bytes of the word line) is programmed in a normal manner.

[0211] Some attribute data of 64 bits (such as the programming temperature of the current word line) can be stored in the state compression portion (e.g., the first four bytes of three pages) by using a fully protected 8-to-4 state compression scheme. Other space in the word line reserved in normal mode can be used to store uncompressed main data.

[0212] Even if a wordline decoding attempt using the default Vref fails, the attribute data stored using the 8-to-4 state compression scheme can still be correctly retrieved and used to select the optimal Vref for the next read retry because of its greater reliability and additional protection.

[0213] If one wishes to further improve the reliability of the attribute data, an 8-to-2 state compression scheme may be used by providing a trade-off between data size and reliability.

[0214] Using the new optimal Vref, the uncompressed main data can be successfully decoded.

[0215] Therefore, the state compression scheme proposed in the present disclosure provides better reliability than the normal TLC or QLC mode. Some critical data previously stored in SLC blocks can now be stored in state compressed TLC or QLC storage cells.

[0216] Therefore, the state compression scheme can be used to reduce the number of blocks used for SLC in the SSD, thereby increasing the life of the SSD.

[0217] As described above, for the 8-to-4 TLC state compression scheme and the 16-to-8 QLC state compression scheme, a fully protected state compression scheme can be found and used to provide additional data protection.

[0218] For the 16 to 4 QLC state compression scheme, the (T0, T5, T10, T15) state compression scheme will be used to provide better reliability.

[0219] In order to use the state compression scheme proposed in this disclosure, the data randomizer after the ECC encoding engine should be disabled.

[0220] Furthermore, the state compression scheme proposed in the present disclosure can be used by the entire word line or a portion of the word line.

[0221] The state compression scheme proposed in the present disclosure can be dynamically applied to a portion of the block without converting the entire block to a more reliable state (such as SLC). An example is that when the host notifies the SSD of data with important properties (for example, using a write FUA (forced unit access) command), the device can write this data to the word line using the state compression scheme.

[0222] Although various aspects and embodiments have been disclosed, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for illustrative purposes only and are not intended to be limiting, with the true scope and spirit being indicated by the claims.

Claims

1. A controller, characterized in that: include: a processor configured to set a value of a D bit based on a value of an M bit, wherein M is an integer greater than 0 and D is an integer greater than 0; The controller is configured to write the D-bit value and the M-bit value into a storage unit of a non-volatile memory.

2. The controller according to claim 1, characterized in that: The processor is configured to set the value of the D bits using one or more results of one or more logical operations on one or more values ​​of the M bits.

3. The controller according to claim 1, characterized in that: D=1, D=2 or D=3.

4. The controller according to claim 1, characterized in that: M=1, M=2, M=3 or M=4.

5. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits to a value of one of the M bits.

6. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits to an exclusive-OR-negation of values ​​of two of the M bits.

7. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits to a disjunction of an inverse of a value of one of the M bits and an inverse of a value of another of the M bits.

8. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits to a disjunction of a value of one of the M bits and an inverse of a value of another of the M bits.

9. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits to be an exclusive OR of values ​​of two of the M bits.

10. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits to an exclusive OR result of a value of a second bit and a value of a third bit and a value of a first bit, wherein the first bit, the second bit and the third bit are any three bits of the M bits.

11. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits based on a value of only one of the M bits.

12. The controller according to claim 1, characterized in that: The processor is configured to set a value of at least one of the D bits based on a value of only two of the M bits.

13. A system, characterized in that: The controller of claim 1, wherein the system is a solid state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

14. A controller configured to read an M-bit value and a D-bit value from a storage unit of a non-volatile memory, wherein M is an integer greater than 0 and D is an integer greater than 0; in, The controller includes a processor configured to determine a value of the M bit based on a value of the D bit.

15. The controller according to claim 14, characterized in that: D=1, D=2 or D=3.

16. The controller according to claim 14, characterized in that: M=1, M=2, M=3 or M=4.

17. The controller according to claim 14, characterized in that: The processor is configured to determine a value of at least one of the M bits as a value of one of the D bits.

18. The controller according to claim 14, characterized in that: The processor is configured to determine the value of at least one of the M bits as the exclusive OR of the inverse of the value of one of the D bits and the value of another of the M bits, or to determine the value of at least one of the M bits as the exclusive OR of the inverse of the value of another of the M bits and the value of one of the D bits.

19. The controller according to claim 14, characterized in that: The processor is configured to determine a value of at least one of the M bits based on a value of only one of the D bits.

20. The controller according to claim 14, characterized in that The processor is configured to determine a value of at least one of the M bits based on a value of only two of the D bits.

21. A system comprising the controller of claim 14, wherein the system is a solid state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

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