Individual core for media management of memory subsystems

Abstract

The invention relates to a separate core for media management of a memory subsystem. A controller of a memory subsystem may include a first processing core and a second processing core for a garbage collection program. The first processing core may perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory subsystem. The second processing core may execute a second set of one or more operations associated with a write process of the first stage of the garbage collection program, wherein the second set of one or more operations is simultaneous with the first set of one or more operations.

Description

[0001] Cross-references

[0002] This application is a divisional application of an invention patent application with an application date of December 24, 2020, application number “202011550335.2”, and invention name “SEPARATE CORES FOR MEDIA MANAGEMENT OF A MEMORY SUB-SYSTEM”. The parent case claims priority to U.S. Patent Application No. 16 / 730,886, entitled “SEPARATE CORES FOR MEDIA MANAGEMENT OF A MEMORY SUB-SYSTEM” filed by Bianco et al. on December 30, 2019, which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to separate cores for media management of memory subsystems. Background Art

[0004] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0005] A method is described. The method may include performing, by a first processing core of a controller for a memory subsystem, a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory subsystem, and performing, by a second processing core of the controller for the memory subsystem and concurrently with the first set of one or more operations, a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure.

[0006] A system is described. The system may include a plurality of memory components and a processing device operatively coupled to the plurality of memory components to: perform, by a first processing core of the processing device, one or more read operations associated with a first stage of a garbage collection procedure for the plurality of memory components, and perform, by a second processing core of the processing device and concurrently with the one or more read operations, one or more write operations associated with the first stage of the garbage collection procedure.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may include instructions that, when executed by a processor, cause the processor to: perform, by a first processing core of a controller for a memory subsystem, a first set of one or more operations associated with a read process of a first phase of a garbage collection procedure for a plurality of transfer units of the memory subsystem; and perform, by a second processing core of the controller for the memory subsystem and concurrently with the first set of one or more operations, a second set of one or more operations associated with a write process of the first phase of the garbage collection procedure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0009] Figure 1 An example of a computing system including a memory subsystem according to some examples of the present disclosure is described.

[0010] Figure 2 is a method diagram of an example method for a separate core for media management of a memory subsystem according to some examples of the present disclosure.

[0011] Figure 3 is a block diagram of an example system in which a separate processing core is operable for garbage collection.

[0012] Figure 4 is a method diagram of an example method for a separate core for media management of a memory subsystem according to some examples of the present disclosure.

[0013] Figure 5 is a block diagram of an example computer system in which examples of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to a separate core for media management of a memory subsystem according to some examples of the present disclosure. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0015] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells that store data bits. For some memory devices, such as NAND devices, a block is the smallest erasable area, and pages within a block cannot be erased individually. For such devices, erase operations are performed one block at a time. Pages of a block may contain valid data, invalid data, or no data. Invalid data is data that is marked as obsolete because a new version of the data is stored on the memory device. Invalid data includes data that was previously written but is no longer associated with a valid logical address (e.g., a logical address referenced by a host system in a physical to logical (P2L) mapping table). Valid data is the latest version of such data being stored on the memory device. The memory subsystem may mark data as invalid based on information received, for example, from an operating system. Pages that do not contain data include pages that were previously erased and have not yet been written to.

[0016] The memory subsystem controller may perform operations for media management algorithms such as wear leveling, refresh, garbage collection, erasure, etc. A block may have some pages with valid data and some pages with invalid data. To avoid waiting for all pages in a block to have invalid data in order to erase and reuse the block, an algorithm referred to below as "garbage collection" may be invoked to allow the block to be erased and released as a free block for subsequent write operations. Garbage collection is a set of media management operations that include, for example: selecting a block containing valid and invalid data; selecting a page in the block containing valid data; copying the valid data to a new location (e.g., a free page in another block); marking the data in a previously selected page as invalid; and erasing the selected block.

[0017] "Garbage collection" hereinafter refers to selecting a block; rewriting valid data from the selected block to another block; and erasing all invalid data and valid data stored at the selected block. Valid data from multiple selected blocks may be copied to a smaller number of other blocks, and the selected blocks may then be erased. Thus, the number of blocks that have been erased may be increased, making more blocks available for storing subsequent data from the host system.

[0018] During garbage collection, valid data to be erased of the block is initially read into and stored by the buffer based on one or more read commands issued by the memory device controller, and the corresponding page (e.g., a page containing valid data thereon) is erased. The valid data may be written (e.g., rewritten) to the memory device (e.g., to a different page of the memory device) before the page containing valid data thereon is erased. To write valid data to a location (e.g., a different page of the memory device), the memory subsystem controller issues write commands, each of which indicates a memory address (e.g., a destination memory address) to which the valid data is written. In some garbage collection programs, a write command is issued once the corresponding read command has been completed. That is, a read command for data at a source memory address (e.g., a memory address on a page to be erased).

[0019] In a conventional memory subsystem, a controller may include a single processing core. The single processing core may perform operations associated with a read process of a garbage collector and a write process of a garbage collector. In such cases, the memory subsystem may include an increased amount of overhead such that a single processing core of the controller performs each operation of the garbage collector. That is, the algorithm of the single processing core of the controller may increase processing time due to the single processing core utilizing processor cycles of multiple processes of the garbage collector, such as identifying a memory address for garbage collection and determining whether the data is dirty data or invalid data. In some cases, finding valid data, reading valid data, and preparing valid data to be written may utilize multiple processor cycles.

[0020] Such techniques (e.g., utilizing a single processing core) may cause the memory subsystem to experience a performance penalty during the garbage collection process, which may increase latency for other operations and the time used for garbage collection. A memory subsystem containing a single-core processor may reduce the overall performance of the memory subsystem, which may cause it to experience impaired read, write, and erase speeds (e.g., due to delays in read, write, or erase operations).

[0021] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that includes a separate processing core for a garbage collection program, thereby sharing responsibilities between multiple cores to improve the performance of the memory subsystem during the garbage collection program. For example, the memory subsystem may include two (or more than two) processing cores in a controller. In such a situation, adding a second processing core can enable the controller to handle multiple operations associated with the garbage collection program by dividing the operations between the two processing cores. For example, the two processing cores can each perform different operations for the garbage collection program in parallel (e.g., simultaneously). That is, one processing core can perform operations associated with the read process of the garbage collection program, and another processing core can perform the write process of the garbage collection program.

[0022] By offloading computational processes to a separate core (e.g., a second processing core), the memory subsystem can perform operations in parallel, thereby improving the performance of the memory subsystem, improving quality of service, and increasing read, write, and erase speeds. Implementing a separate core for a garbage collector can improve the overall efficiency of the memory subsystem, thereby allowing the memory subsystem to experience improved processing times.

[0023] First, in reference Figure 1 The features of the present disclosure are described in the context of the computing environment described. Figures 2 to 4 The features of the present disclosure are described in the context of the described methods and block diagrams. These and other features of the present disclosure are also illustrated by and described with reference to a computer system that is used to reference Figure 5 Consider the separate core for media management of the memory subsystem described.

[0024] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more non-volatile memory devices (such as memory device 130), one or more volatile memory devices (such as memory device 140), or a combination thereof.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile DIMMs (NVDIMMs).

[0026] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0027] Computing system 100 can include a host system 105 coupled with one or more memory subsystems 110. In some examples, host system 105 is coupled with memory subsystems 110 of different types. Figure 1An example of a host system 105 coupled to a memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0028] The host system 105 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0029] The host system 105 may be coupled to the memory subsystem 110 using a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a USB interface, a Fibre Channel, a small computer system interface (SCSI), a serial attached SCSI (SAS), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting double data rate (DDR)), an open NAND flash interface (ONFI), a double data rate (DDR), a low power double data rate (LPDDR), or any other interface. The physical host interface may be used to transmit data between the host system 105 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 105 through a PCIe interface, the host system 105 may further utilize a non-volatile memory express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 105.

[0030] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM) such as dynamic RAM (DRAM) and synchronous DRAM (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although a nonvolatile memory device such as a NAND-type flash memory is described, the memory device 130 may be based on any other type of nonvolatile memory such as a read-only memory (ROM), a phase change memory (PCM), a self-selecting memory, other chalcogenide-based memories, a ferroelectric transistor random access memory (FeTRAM), a ferroelectric RAM (FeRAM), a magnetic RAM (MRAM), or a non-(NOR) flash memory, a spin transfer torque (STT)-MRAM, a conductive bridge RAM (CBRAM), a resistive random access memory (RRAM), an oxide-based RRAM (OxRAM), and an electrically erasable programmable ROM (EEPROM).

[0034] The memory subsystem controller 115 (or simply controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125. In the illustrated example, the local memory 125 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 105.

[0036] In some examples, local memory 125 may include memory registers that store memory pointers, fetched data, etc. Local memory 125 may also include ROM for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another example of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] In general, the memory subsystem controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 105 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 105.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some examples, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some examples, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The memory subsystem 110 includes a plurality of processors 120, such as processor A 150 and processor B 155. Processor A 150 includes an input / output (I / O) core, and processor B 155 may include a flash translation layer (FTL) core 160. Processor A 150 may perform operations associated with one process (e.g., a read process) of a garbage collection program for a data block (e.g., a transfer unit (TU)) of the memory subsystem. Processor B 155 may perform operations associated with another process (e.g., a write process) of the garbage collection program, such that the operations associated with the write process may be performed simultaneously with the operations associated with the read process. By dividing the garbage collection program between the two processing cores, processor A 150 and processor B 155 may perform operations in parallel.

[0041] In some examples, the memory subsystem controller 115 includes at least a portion of a processor A 150 and a processor B 155. For example, the memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125 for performing the operations described herein. In some examples, the processor A 150 and the processor B 155 are part of a host system 105, an application, or an operating system.

[0042] In conventional systems, the increase in processing time may be attributed to the overhead associated with identifying data blocks for the garbage collection routine. For example, the memory subsystem controller 115 may repeatedly scan multiple data blocks multiple times, thereby increasing the processing time of the memory subsystem 110. By implementing processor A 150 and processor B 155, processor B 155 may perform operations associated with a portion of the garbage collection routine (e.g., the write process of the garbage collection routine) without the overhead caused by operations waiting for other portions of the garbage collection routine (e.g., the read process of the garbage collection routine) to complete. Additional details regarding the operation of processor A 150 and processor B 155 are described below.

[0043] Figure 2 is a method diagram of an example method 200 utilizing a separate core for media management of a memory subsystem according to some examples of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some examples, the method 200 is performed by Figure 1 The processes described herein are performed by processor A 150 and processor B 155. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated examples should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various examples. Therefore, not all processes are required in each example. Other process flows are possible.

[0044] At operation 205, the processing device may perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a set of TUs of the memory subsystem by a first processing core of a controller of the memory subsystem. In some instances, the first set of one or more operations may include identifying a corresponding source address for a set of TUs of the memory subsystem, wherein each TU in the set of TUs includes valid data. In some instances, the first set of one or more operations may include issuing a set of read commands associated with the garbage collection procedure, each read command including an instruction to read one TU in the set of TUs at a corresponding source address of the memory subsystem. In some instances, the set of TUs may correspond to a data set, and the first set of one or more operations may include assigning the data set to a clean state based at least in part on the data set containing invalid data.

[0045] In some examples, method 200 may include performing, by a first processing core of a processing device, one or more read operations associated with a first stage of a garbage collection procedure for a set of memory components. In some examples, method 200 may include sending a write request for a first TU in the set of TUs to a first write request queue in the set of write request queues, the first write request queue being associated with a first priority level that is different from a second priority level of a second write request queue in the set of write request queues as part of the one or more read operations.

[0046] At operation 210, the processing device may execute a second set of one or more operations associated with the write process of the first stage of the garbage collection program through a second processing core of a controller for the memory subsystem and simultaneously with the first set of one or more operations. In some instances, the second set of one or more operations may include allocating a data set in a clean state to an erase pool based at least in part on completing all read commands for the data set. In some instances, the second set of one or more operations may include issuing a set of write commands related to the garbage collection program, each write command including an instruction to write one TU in a set of TUs to a corresponding destination address of the memory subsystem. In some instances, the set of write commands may be issued according to a write rate of the garbage collection program. In some instances, the set of write commands may be issued based at least in part on a corresponding priority for each write command in the set of write commands.

[0047] In some examples, method 200 may include performing, by a second processing core of the processing device and concurrently with the one or more read operations, one or more write operations associated with a first phase of a garbage collection procedure. In some examples, method 200 may include performing a purge operation for one or more TUs in the set of TUs as part of the one or more write operations, the purge operation for the one or more TUs being associated with a first write request queue having a higher priority than a second write request queue.

[0048] In some examples, method 200 may include using a portion of data from at least one TU in the set of TUs to fill one or more TUs (e.g., memory pages or data blocks) for a flush operation as part of one or more write operations, where the one or more TUs are associated with corresponding write requests in the first or second write request queues.

[0049] Figure 33 is a block diagram 300 of an example system in which a separate processing core for garbage collection is operable. Block diagram 300 may include a memory controller 305. Memory controller 305 may include a core manager 310, which may include an I / O core 315 and an FTL core 320. In some examples, I / O core 315 may correspond to reference Figure 1 In some examples, the FTL core 320 may correspond to the processor A150 described in reference Figure 1 The block diagram 300 may also include a host system 335 and a backend manager 340 .

[0050] In some examples, the core manager 310 may include multiple processing cores. For example, the core manager may include an I / O core 315 and an FTL core 320. The I / O core 315 may perform operations 325 associated with a read process of a garbage collector in parallel (e.g., simultaneously or overlapping in time), and the FTL core 320 may perform operations 330 associated with a write process of a garbage collector. In some cases, the I / O core 315 may communicate with the FTL core 320.

[0051] In some cases, the I / O core 315 or the FTL core 320 may enable or disable the garbage collector during operation 325. For example, the I / O core 315 may maintain a threshold number of data blocks that are subject to the garbage collector. The threshold may include the number of data blocks for which the garbage collector may be enabled. The enabling of the garbage collector may be communicated between the I / O core 315 and the FTL core 320. For example, the enabling may be communicated via notifying the current garbage collection write rate from the I / O core 315 to the FTL core 320.

[0052] The operation 325 of the I / O core 315 may select a garbage collector mode. For example, the mode may indicate a data set that can be identified for the garbage collector (e.g., an operating mode) and a rate at which the garbage collector can be performed on the data set (e.g., an operating mode). In some examples, static wear leveling may be communicated by notifying the current operating mode from the I / O core 315 to the FTL core 320. In such cases, the I / O core 315 may control the rate of garbage collection without controlling the identification of data sets, thereby allowing the FTL core 320 to perform other operations at the same time. In other examples, the I / O core 315 or the FTL core 320 may predict the workload of performing a garbage collector on valid data. The prediction may be used for resource balancing and rate control.

[0053] In some examples, the rate (e.g., run mode) at which garbage collection procedures may be performed for a data set may be calculated by the I / O core 315. While the rate may be calculated for a host write domain (e.g., host system 335) and based on the frequency of the host write domain, the overhead to perform this calculation may be kept outside the write data path. In some cases, P2L discards may be read from the media into a buffer to find valid data within a data set.

[0054] Operation 325 of I / O core 315 may include a trigger to select a data block for a garbage collection procedure. The algorithm to select the data block may be included in a data set management module within I / O core 315. I / O core 315 may also identify when a new data set may be selected for a garbage collection procedure. For example, a new data set may be identified when a valid TU count (VTC) of a current data set is zero. A VTU may be an example of the number of TUs in a data set that may be mapped as valid data that may be referenced by host system 335. In some cases, a new data set may be identified when a garbage collection procedure is repeated for each P2L entry of a data set.

[0055] In some examples, the I / O core 315 may locate valid data (e.g., identify a source address). The source address of the valid data may be found on the media, and a valid data count for the data set may be available. In some examples, the I / O core 315 may read the valid data. For example, once the source address of the valid data can be identified, a read process may be issued to copy the data from the media into an intermediate buffer. In such a case, the I / O core 315 may issue a read command associated with the garbage collector to read the data set at the source address.

[0056] The operation 325 of the I / O core 315 can issue a write request. When the read process is completed, the write process of the data set can be issued to move the data set to a different location on the media. The write request can be queued in advance so that the FTL core 320 does not have to wait when the garbage collector is needed. In some cases, the write request can be inserted into the queue based on the priority of the write request. In such a case, the I / O core 315 can send the write request for the data set to the write request queue. The write request can be associated with a priority that is different from the priority of the different write requests. The complete write request queue can generate back pressure that limits the garbage collector to read the pipeline stage. The location on the media can be included with the write request to allow conditional mapping table updates, such as logical to physical (L2P) / VTC updates with garbage collection write requests.

[0057] In some examples, the operation 325 of the I / O core 315 may maintain a stream of write requests. For example, the write requests received to move the data sets may be issued in the order in which the data sets were originally written by the host system 335, so that the performance is similar between data blocks in the garbage collection process and data blocks without garbage collection. In some cases, the I / O core 315 may detect data blocks with invalid data. In such cases, the data blocks with invalid data are not subject to the garbage collection process, the garbage collection process for the blocks with invalid data may be stopped, or both. If the data set contains invalid data, the I / O core 315 may assign the data set to a clean state.

[0058] The core manager 310 may include a second processing core. For example, the core manager 310 may include an FTL core 320, which may perform operation 330. Operation 330 may include ensuring that the garbage collection write rate relative to the host system 335 write rate is on a low priority garbage collection write request queue. In some cases, the write command may be issued by the FTL core 320. In such cases, the write command may be issued based on the garbage collection write rate. In other examples, the write command may be issued based on the priority of the write command compared to the priority of other write commands.

[0059] In some cases, there may be one or more request queues between cores, and the receiving core may pull requests from the cores in a prioritized order. For example, the FTL core 320 may facilitate a purge request from a client on a high priority garbage collection write request queue. In such cases, the FTL core 320 may perform a purge operation for a data set, where the purge operation may be associated with a write request queue (e.g., a high priority garbage collection write request queue) having a higher priority than a different write request queue (e.g., a low priority garbage collection write request queue). The FTL core 320 may fill the data set for the purge operation with data from other data blocks.

[0060] In an example including two write request queues (e.g., a high priority garbage collection write request queue and a low priority garbage collection write request queue), a garbage collector purge may be inserted or assigned to the lowest priority queue so that all work (e.g., commands, requests, host operations) prior to the purge request may be completed before the processor of the core manager 310 performing the write sees and processes the purge request. In some cases, a purge request may be added to the high priority request queue when a write is requested by a client (e.g., garbage collection or other internal write) and all data for the purge is also submitted to the high priority request queue.

[0061] If user data is available, then clearing can use fill data or fill with additional user data from one of the garbage collection write request queues. If there is no available additional user data, then using fill data may be acceptable. Fill data may be garbage data added to the back-end command to meet the aggregation criteria of the operation. Garbage data may be fixed patterns, invalid data from other buffers, or both. In some cases, fill data may not be user data. In some cases, if asynchronous power loss (APL) security is requested, a completion response for clearing may be sent. For example, if the host system does not notify the drive of an impending power loss or if there is not enough uptime after this notification, power is removed, so it is referred to as an APL event. In other instances, after the garbage collector is written, the FTL core 320 may facilitate conditional L2P / VTC / log updates.

[0062] The backend manager 340 may communicate with the memory controller 305. For example, the backend manager 340 may send a read response to the memory controller 305. In such a case, the backend manager 340 may transmit a message indicating that the entire data set is read, and invalid data may be erased. For example, the backend manager 340 may communicate with the FTL core 320 to allocate a data set in a purged state to an erase pool based on completing all read commands for the data set.

[0063] Figure 4 is a method diagram of an example method 400 for a separate core for media management of a memory subsystem according to some examples of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some examples, the method 400 may be performed by Figure 1 processor A 150 and processor B 155 or Figure 3 The core manager 310 of . Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated examples should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various examples. Therefore, not all processes are required in every example. Other process flows are possible.

[0064] The core manager may enable a garbage collector at operation 405. The I / O core of the core manager and the FTL core of the core manager may operate in parallel, thereby reducing processing time and improving overall performance of the memory subsystem.

[0065] At operation 410, the I / O core of the core manager may perform operations associated with a read process of a garbage collector. For example, the I / O core may perform one or more operations associated with a read process of a garbage collector for a data block of a memory subsystem.

[0066] At operation 415, the FTL core of the core manager may perform operations associated with the write process of the garbage collector. For example, the I / O FTL core may perform one or more operations associated with the write process of the garbage collector for the data blocks of the memory subsystem. The execution of the operations associated with the write process may be performed simultaneously with (e.g., at least partially overlapping in time) operation 410. In some cases, the execution of the operations associated with the write process may be performed after operation 410.

[0067] At operation 420, the I / O core of the core manager may identify a source address for the garbage collector, for example, the I / O core may identify a corresponding source address for a data block of the memory subsystem. In such a case, the data block contains valid data. One or more operations associated with the read process may include identifying the source address.

[0068] At operation 425, the I / O core of the core manager may issue a read command. For example, the I / O core may issue a read command associated with a garbage collector. In such a case, each read command may include an instruction to read one of the data blocks at a corresponding source address of the memory subsystem. One or more operations associated with the read process may include issuing a read command.

[0069] At operation 430, the FTL core of the core manager may issue a write command. For example, the FTL core may issue a write command related to a garbage collector. In such cases, each write command may include an instruction to write one of the data blocks to a corresponding destination address of the memory subsystem. In some cases, the write command may be issued according to a write rate for the garbage collector. In other examples, the write command may be issued based on a priority of the write command relative to other write commands. In some cases, issuing the write command may be performed in parallel with operation 425. In other examples, issuing the write command may be performed after operation 425.

[0070] At operation 435, the I / O core of the core manager may assign the data to a purge state. For example, the I / O core may assign the data set to a purge state based on the data set containing invalid data. One or more operations associated with the read process may include assigning the data to a purge state.

[0071] At operation 440, the FTL core of the core manager may allocate the data to the erase pool. For example, the FTL core may allocate the data set in a purged state to the erase pool based on completing all read commands for the data set. One or more operations associated with the write process may include allocating the data to the erase pool. In some cases, allocating the data to the erase pool may be performed in parallel with operation 435. In other examples, allocating the data to the erase pool may be performed after operation 435.

[0072] At operation 445, the FTL core of the core manager may perform a purge operation. For example, an FTL write may perform a purge operation as part of a write command. The purge operation may be associated with a data set where a write request queue has a higher priority (e.g., a high priority garbage collection write request queue) than a priority of a different write request queue (e.g., a low priority garbage collection write request queue). In some cases, at operation 445, the FTL core may populate the data set for the purge operation with data from the data block. The populating of the data set for the purge operation may be part of the write operation.

[0073] Figure 5 An example machine of a computer system 500 supporting a separate core for media management of a memory subsystem according to examples disclosed herein is illustrated. The computer system 500 may include a set of instructions for causing the machine to perform any one or more of the techniques described herein. In some examples, the computer system 500 may correspond to a computer system including a memory subsystem (e.g., reference Figure 1 110 described above), a host system coupled to or utilizing the memory subsystem (e.g., reference Figure 1 The host system 105 described above may be used to perform operations of the controller (e.g., to execute an operating system to perform operations corresponding to the reference Figure 1 In some examples, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0074] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" may also include any collection of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0075] The example computer system 500 may include a processing device 505, a main memory 510 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM), etc.), a static memory 515 (e.g., flash memory, static RAM (SRAM), etc.), and a data storage system 525, which communicate with each other via a bus 545.

[0076] The processing device 505 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, and the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 505 may also be one or more special-purpose processing devices, such as an ASIC, an FPGA, a DSP, a network processor, and the like. The processing device 505 is configured to execute instructions 535 for implementing the operations and steps discussed herein. The computer system 500 may further include a network interface device 520 to communicate over a network 540.

[0077] The data storage system 525 may include a machine-readable storage medium 530 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 535 or software embodying any one or more of the methods or functions described herein. The instructions 535 may also reside completely or at least partially within the main memory 510 and / or within the processing device 505 during execution thereof by the computer system 500, the main memory 510 and the processing device 505 also constituting machine-readable storage media. The machine-readable storage medium 530, the data storage system 525, and / or the main memory 510 may correspond to a memory subsystem.

[0078] In one example, instructions 535 include instructions for implementing instructions corresponding to core manager 550 (eg, reference Figure 1The term "machine-readable storage medium" may include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0080] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0081] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), ROM, RAM, EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0083] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some examples, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, etc.

[0084] In the foregoing description, examples of the present disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the examples of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: performing, by one or more controllers of a memory system, a first set of one or more operations associated with a read process of a first phase of a garbage collection procedure of the memory system, wherein the first set of one or more operations includes issuing a plurality of read commands associated with the garbage collection procedure from the one or more controllers to one or more queues of the memory system; and A second set of one or more operations associated with the write process of the first stage of the garbage collection program is performed by the one or more controllers of the memory system, wherein the second set of one or more operations includes issuing a plurality of write commands related to the garbage collection program from the one or more controllers to the one or more queues, wherein issuing the plurality of read commands at least partially overlaps in time with issuing the plurality of write commands.

2. The method of claim 1 , wherein performing a first set of the one or more operations associated with the read process of the first phase of the garbage collection procedure of the memory system comprises: Respective source addresses of a plurality of transfer units of the memory system are identified, wherein each of the plurality of transfer units includes valid data.

3. The method of claim 2, wherein the plurality of transfer units correspond to data sets, and wherein the first set of one or more operations comprises: The data set is assigned to a sanitized state based at least in part on the data set containing invalid data.

4. The method of claim 3, wherein the second set of one or more operations comprises: The data set in the purge state is assigned to an erase pool based at least in part on completing all read commands for the data set. 5 . The method of claim 1 , wherein each read command comprises an instruction to read at least one of a plurality of transfer units at a corresponding source address of the memory system.

6. The method of claim 1, wherein each write command comprises instructions to write at least one of a plurality of transfer units to a respective destination address of the memory system. 7 . The method of claim 6 , wherein the plurality of write commands are issued based at least in part on a respective priority of each of the plurality of write commands.

8. A method comprising: performing, by one or more controllers of a memory system, a first set of one or more operations associated with a read process of a first phase of a garbage collection procedure of the memory system, wherein the first set of one or more operations includes issuing a plurality of read commands associated with the garbage collection procedure; and A second set of one or more operations associated with the write process of the first stage of the garbage collection program is performed by the one or more controllers of the memory system, wherein the second set of one or more operations includes issuing a plurality of write commands related to the garbage collection program, wherein each write command includes an instruction to write at least one of a plurality of transfer units to a corresponding destination address of the memory system, wherein the plurality of write commands are issued according to a write rate of the garbage collection program, and wherein at least one of the plurality of write commands is issued at the same time as the plurality of read commands are issued.

9. A method comprising: calculating, by one or more controllers of a memory system, a possible rate at which a garbage collection procedure is performed on the memory system, wherein the possible rate is calculated based at least in part on a number of write commands received from a host device over a duration of time; selecting, by the one or more controllers, a first operating mode for executing the garbage collection procedure on the memory system, wherein the first operating mode is associated with a rate associated with a number of the write commands received from the host device within the duration, wherein selecting the first operating mode is based at least in part on calculating the likely rate; identifying, by the one or more controllers, a triggering condition for initiating the garbage collection procedure on the memory system based at least in part on selecting the first operating mode; selecting, by the one or more controllers, one or more data blocks associated with the garbage collection procedure based at least in part on the number of valid data blocks; performing, by the one or more controllers, one or more first operations associated with a reading process of the garbage collector and the one or more data blocks according to the first operating mode based at least in part on identifying the trigger condition; and One or more second operations associated with a write process of the garbage collector and the one or more data blocks are performed according to the first operating mode by the one or more controllers based at least in part on performing the one or more first operations.

10. A method comprising: selecting, by one or more controllers of a memory system, a first operating mode for performing a garbage collection procedure on the memory system, wherein the first operating mode is associated with a rate at which the garbage collection procedure is performed; identifying, by the one or more controllers, a triggering condition for initiating the garbage collection procedure on the memory system based at least in part on selecting the first operating mode; performing, by the one or more controllers, one or more first operations associated with a read process of the garbage collection process according to the first operating mode based at least in part on identifying the triggering condition; performing, by the one or more controllers, one or more second operations associated with a write process of the garbage collection process according to the first operating mode based at least in part on performing the one or more first operations; generating, by the one or more controllers, a plurality of write requests prior to identifying the triggering condition for initiating the garbage collection procedure; and The plurality of write requests are stored, by the one or more controllers, to a queue of the memory system, wherein performing the one or more second operations associated with the write process of the garbage collection program is based at least in part on the plurality of write requests stored to the queue.

11. The method according to claim 10, further comprising: A priority is assigned to each of the plurality of write requests generated by the one or more controllers by the one or more controllers, wherein the plurality of write requests are stored to the queue of the memory system according to respective priorities, and wherein the one or more second operations associated with the write process of the garbage collection program are performed based on respective priorities of the plurality of write requests stored to the queue.

12. A memory system comprising: one or more controllers, wherein the one or more controllers are operable to cause the memory system to: performing a first set of one or more operations associated with a read process of a first phase of a garbage collection procedure of the memory system, wherein the first set of one or more operations includes issuing a plurality of read commands associated with the garbage collection procedure from the one or more controllers to one or more queues of the memory system; and Performing a second set of one or more operations associated with the write process of the first stage of the garbage collection program, wherein the second set of one or more operations includes issuing a plurality of write commands related to the garbage collection program, wherein issuing the plurality of read commands from the one or more controllers to the one or more queues overlaps in time at least partially with issuing the plurality of write commands.

13. The memory system of claim 12, wherein to perform the first set of the one or more operations associated with the read process of the first phase of the garbage collection procedure of the memory system, the one or more controllers are operable to cause the memory system to: Respective source addresses of a plurality of transfer units of the memory system are identified, wherein each of the plurality of transfer units includes valid data.

14. The memory system of claim 13, wherein the plurality of transfer units correspond to a data set, and wherein to perform the first set of the one or more operations, the one or more controllers are operable to cause the memory system to: The data set is assigned to a sanitized state based at least in part on the data set containing invalid data.

15. The memory system of claim 14, wherein to perform the second set of the one or more operations, the one or more controllers are operable to cause the memory system to: The data set in the purge state is assigned to an erase pool based at least in part on completing all read commands for the data set.

16. The memory system of claim 12, wherein each read command includes an instruction to read at least one of a plurality of transfer units at a corresponding source address of the memory system.

17. The memory system of claim 12, wherein each write command comprises an instruction to write at least one of a plurality of transfer units to a corresponding destination address of the memory system.

18. The memory system of claim 17, wherein the plurality of write commands are issued based at least in part on a respective priority of each of the plurality of write commands.

19. A memory system comprising: one or more controllers, wherein the one or more controllers are operable to cause the memory system to: performing a first set of one or more operations associated with a read process of a first phase of a garbage collection procedure of the memory system, wherein the first set of one or more operations includes issuing a plurality of read commands associated with the garbage collection procedure; as well as Executing a second set of one or more operations associated with the write process of the first stage of the garbage collection program, wherein the second set of one or more operations includes issuing a plurality of write commands related to the garbage collection program, wherein each write command includes an instruction to write at least one of a plurality of transfer units to a corresponding destination address of the memory system, wherein the plurality of write commands are issued according to a write rate of the garbage collection program, and wherein at least one of the plurality of write commands is issued at the same time as the plurality of read commands are issued.

Images