A dynamic instruction conversion optimization method based on write prefetch

Abstract

The present invention discloses a dynamic instruction conversion optimization method based on write prefetch. When an executable file is executed for the first time in a dynamic instruction conversion mode, an instruction combination related to a load instruction and a storage instruction is determined by semantic analysis of the instruction, and then a loop body where the instruction combination is located is determined based on an extended control flow graph. A write prefetch instruction adding method in a single-layer loop body is determined according to storage instructions of calculation results in the loop body, and a write prefetch instruction adding method in a multi-layer loop body is determined according to execution time. A write prefetch instruction insertion strategy list is formed by the write prefetch instruction adding method and the address of the storage instruction. Subsequently, the executable file can be executed again according to the write prefetch instruction insertion strategy list, thereby effectively improving the efficiency of code execution across instruction sets.

Description

Technical Field

[0001] The invention belongs to the technical field of computer software development, and in particular relates to a dynamic instruction conversion optimization method based on write prefetch. Background Art

[0002] Vectorized storage is the basis of vector databases. By converting data into vector form for storage, data reading and processing are made more efficient. The advantage of vectorized storage is that it reduces the number of I / O operations on data and improves data processing speed. In addition, vectorized storage also realizes compressed storage of data, saving storage space. Vector database is a system specifically used to store and manage vectorized data, mainly used in machine learning and other artificial intelligence-related scenarios. Among the existing SIMD-based instruction sets, AVX, SSE, Neon and other instruction sets all provide vectorized storage instructions. Among them, AVX and SSE instruction sets are instruction sets of the x86 architecture, and Neon is an instruction set of the ARM architecture.

[0003] The AVX instruction set allows the processor to process more data at a time to improve the parallelism and throughput of the processing process. The SSE instruction set is mainly used to process single-precision floating-point numbers. Neon is an instruction set extension introduced in the ARMv7 architecture and later versions, which is used to accelerate applications such as multimedia and signal processing that require large amounts of data processing, and provide support for high-performance computing.

[0004] In practice, when executing x86 architecture software on the ARM64 platform, it is necessary to use ARM64's SIMD instructions to simulate the execution of AVX instructions or SSE instructions. When converting load instructions and store instructions in a loop body, the frequent execution of data storage to memory and then loading from memory to registers usually increases the instruction conversion process and instruction execution time, thereby reducing the efficiency of AVX instruction or SSE instruction simulation execution. Summary of the invention

[0005] In view of this, the present invention provides a dynamic instruction conversion optimization method based on write prefetch, which determines the single-layer loop body or multi-layer loop body where the load instruction and the storage instruction are located through semantic analysis and loop dependency analysis, and determines the method of adding write prefetch instructions related to the storage instruction for different loop bodies.

[0006] The present invention provides a dynamic instruction conversion optimization method based on write prefetch, which specifically includes the following steps:

[0007] Step 1: If the executable file has a corresponding write prefetch instruction insertion strategy list, the execution of the executable file is completed according to the write prefetch instruction insertion strategy list, and this process ends; otherwise, the executable file is loaded through dynamic instruction conversion;

[0008] Step 2: parsing the executable file, extracting load instructions, store instructions and their respective target operands and source operands, and forming a first instruction set;

[0009] Step 3, forming a first instruction combination from adjacent load instructions in the first instruction set that have the same base address register, determining a traversal method for matrix elements according to a calculation method for an offset, if the offset is a fixed value and is the same as the element size, the traversal method is row traversal, otherwise it is column traversal; forming a first instruction combination set from a correspondence between the first instruction combination and the traversal method;

[0010] Step 4, identifying the single-layer loop in the executable file, and establishing a single-layer loop body set from the loop body of the single-layer loop; analyzing and determining the nested multi-layer loops in the single-layer loop body set, and forming a multi-layer loop body set from the loop bodies of these nested multi-layer loops;

[0011] Step 5: The loop bodies in the single-layer loop body set that include the first instruction combination in the first instruction combination set constitute a first single-layer loop body set, and the loop bodies in the multi-layer loop body set that include the first instruction combination in the first instruction combination set constitute a first multi-layer loop body set; execute step 6 for the first single-layer loop body set, and execute step 7 for the first multi-layer loop body set;

[0012] Step 6, traverse the first single-layer loop body set and take the arithmetic operation instruction related to the first instruction combination as the target arithmetic operation instruction, take the storage instruction of the operation result after the target arithmetic operation instruction as the target instruction, take the position after the target instruction as the address of the write prefetch instruction, take the memory address of the target instruction as the operand of the write prefetch instruction, add the correspondence between the write prefetch instruction name, address and operand and the address of the target instruction to the write prefetch instruction insertion strategy list, and execute step 9;

[0013] Step 7, traverse the first multi-layer loop body set and take the arithmetic operation instruction related to the first instruction combination as the target arithmetic operation instruction, take the storage instruction of the operation result after the target arithmetic operation instruction as the target instruction, if the target instruction is not unique, execute step 8; otherwise, take the position after the target instruction as the address of the write prefetch instruction, take the memory address of the target instruction as the operand of the write prefetch instruction, add the correspondence between the write prefetch instruction name, address and operand and the address of the target instruction to the write prefetch instruction insertion strategy list, and execute step 9;

[0014] Step 8, inserting the write prefetch instruction according to three methods: inserting the write prefetch instruction and the synchronization instruction after the target instructions of the inner and outer loops, inserting the write prefetch instruction and the synchronization instruction only after the target instruction of the inner loop, and inserting the write prefetch instruction and the synchronization instruction only after the target instruction of the outer loop, and adding the method with the shortest execution time to the write prefetch instruction insertion strategy list;

[0015] Step 9: Save the write prefetch instruction insertion strategy list of the executable file and end this process.

[0016] Furthermore, the method of parsing the executable file in step 2 is: parsing the executable file using a deep traversal algorithm based on an abstract syntax tree.

[0017] Furthermore, the memory unit corresponding to the target operand or the source operand is represented by a memory addressing method, including a base register and an offset.

[0018] Furthermore, the method of identifying the single-layer loop in the executable file in step 4 is: establishing an extended control flow graph for the executable file, and using a loop detection algorithm to parse the extended control flow graph to obtain the single-layer loop.

[0019] Furthermore, the method for analyzing and determining the nested multi-layer loops in the single-layer loop body set in step 4 is: traversing the extended control flow graph based on a depth-first search combined with a backtracking strategy to determine the nested multi-layer loops in the single-layer loop body set.

[0020] Furthermore, in step 6, the position after the target instruction is used as the address of the write prefetch instruction, and a DSB instruction is inserted before the target instruction, and a DSB instruction and an ISB instruction are inserted after the target instruction.

[0021] Furthermore, when the shortest execution time described in step 8 is greater than the execution time of the original executable file without inserting the write prefetch instruction, a second instruction set is formed by the instructions located between the target instruction and the loop end instruction, and the instructions in the second instruction set are traversed. For instructions that have no write dependency with the source operand of the target instruction and no read dependency with the target operand of the target instruction, their converted codes are moved before the converted code of the target instruction. When there are multiple such instructions, the order of the instructions is kept unchanged after the movement, and then step 8 is executed.

[0022] Furthermore, in step 7, the position after the target instruction is used as the address of the write prefetch instruction, and a DSB instruction is inserted before the target instruction, and a DSB instruction and an ISB instruction are inserted after the target instruction.

[0023] Furthermore, both the load instruction and the store instruction are MOV instructions.

[0024] Furthermore, the write prefetch instruction is a pldw instruction. Beneficial Effects

[0025] When the present invention executes the executable file for the first time in a dynamic instruction conversion manner, the instruction combination related to the load instruction and the storage instruction is determined through semantic analysis of the instructions, and then the loop body where the instruction combination is located is determined based on the extended control flow graph, and the write prefetch instruction adding method in the single-layer loop body is determined according to the storage instruction of the calculation result in the loop body, and the write prefetch instruction adding method in the multi-layer loop body is determined according to the execution time. A write prefetch instruction insertion strategy list is formed by the write prefetch instruction adding method and the address of the storage instruction. Subsequently, the executable file can be executed again according to the write prefetch instruction insertion strategy list, which effectively improves the efficiency of code execution across instruction sets. DETAILED DESCRIPTION

[0026] The present invention is described in detail with reference to the following embodiments.

[0027] In order to solve the problem of delay in reading or writing data from memory to register, existing processors provide a data prefetch mechanism, which can load data from memory into cache in advance, so that data can be obtained faster when it is actually used later, thus reducing waiting time. The CPU under the x86 architecture provides prefetch instructions, such as PREFETCHT0, PREFETCHT1, PREFETCHT2, PREFETCHNTA, etc. These instructions are mainly prefetch instructions related to data reading, rather than write prefetch instructions. The CPU under the ARM architecture provides both data prefetch instructions and write prefetch instructions. Therefore, when executing x86 architecture software on the ARM64 platform to dynamically convert load instructions and storage instructions, the ARM architecture write prefetch instructions can be introduced to preload data into the cache to improve the execution efficiency of the code. The write prefetch instructions provided under the ARM architecture are such as the pldw instruction.

[0028] The present invention provides a dynamic instruction conversion optimization method based on write prefetch, and its core idea is: when an executable file is executed for the first time in a dynamic instruction conversion mode, an instruction combination related to a load instruction and a storage instruction is determined by semantic analysis of the instructions, and then a loop body where the instruction combination is located is determined based on an extended control flow graph, a write prefetch instruction adding method in a single-layer loop body is determined according to storage instructions of calculation results in the loop body, and a write prefetch instruction adding method in a multi-layer loop body is determined according to execution time, and a write prefetch instruction insertion strategy list is formed by the write prefetch instruction adding method and the address of the storage instruction, and the executable file can be subsequently executed again according to the write prefetch instruction insertion strategy list.

[0029] The present invention provides a dynamic instruction conversion optimization method based on write prefetch, which specifically includes the following steps:

[0030] Step 1: If the executable file has a corresponding write prefetch instruction insertion strategy list, the execution of the executable file is completed by dynamic instruction conversion loading and execution according to the write prefetch instruction insertion strategy list, and this process ends; otherwise, the executable file is executed by dynamic instruction conversion loading and execution.

[0031] Step 2: parse the executable file using a deep traversal algorithm based on an abstract syntax tree (AST), extract the load instructions and store instructions, as well as the target operands and source operands of the load instructions and store instructions, and form a first instruction set from the load instructions, store instructions, and the corresponding target operands and source operands. The memory unit corresponding to the target operand or source operand can be represented by a memory addressing method, including a base register and an offset, and the memory unit is the memory unit pointed to by the sum of the value of the base register and the offset.

[0032] Among them, the load instruction is an instruction used to load data from a memory unit pointed to by a memory address into a register. The store instruction is an instruction used to store data into a memory or other storage device.

[0033] Step 3, the first instruction combination is composed of adjacent load instructions with the same base address register in the first instruction set, the first instruction combination is a load operation related to the matrix, and the traversal method of the matrix elements is determined according to the calculation method of the offset, if the offset is a fixed value and the same as the element size, the traversal method is row traversal, otherwise it is column traversal; the first instruction combination set is formed by the correspondence between the first instruction combination and the traversal method.

[0034] Step 4: Create an extended control flow graph (ECFG) for the executable file, use a loop detection algorithm to parse the extended control flow graph to identify single-layer loops, and create a single-layer loop body set from the loop bodies of the single-layer loops; traverse the extended control flow graph based on a depth-first search combined with a backtracking strategy, analyze and determine the nested multi-layer loops in the single-layer loop body set, and form a multi-layer loop body set from the loop bodies of these nested multi-layer loops.

[0035] Step 5: A first single-layer loop body set is formed by loop bodies in a single-layer loop body set that include the first instruction combination in the first instruction combination set, and a first multi-layer loop body set is formed by loop bodies in a multi-layer loop body set that include the first instruction combination in the first instruction combination set; execute step 6 for the first single-layer loop body set, and execute step 7 for the first multi-layer loop body set.

[0036] Step 6, traverse the loop bodies in the first single-layer loop body set, identify the arithmetic operation instruction related to the first instruction combination as the target arithmetic operation instruction, search for the storage instruction of the operation result from the target arithmetic operation instruction forward and use it as the target instruction, use the position after the target instruction as the address of the write prefetch instruction, use the memory address of the target instruction as the operand of the write prefetch instruction, add the correspondence between the write prefetch instruction name, address and operand and the address of the target instruction to the write prefetch instruction insertion strategy list, and execute step 10.

[0037] Furthermore, in the case where the executable file is a multi-threaded program and the processor is a multi-core processor, cache synchronization instructions are inserted before and after the target instruction, specifically: a DSB instruction is inserted before the target instruction as a data synchronization barrier to ensure that the current calculation and reading operations have been completed and the loading of data into the cache has been completed; a DSB instruction and an ISB instruction are inserted after the target instruction as data synchronization barriers, the DSB instruction can ensure that the written data has been completely written to the memory, and the ISB instruction can ensure that subsequent instructions can query the status of the latest written data.

[0038] Step 7, traverse the loop bodies in the first multi-layer loop body set, identify the arithmetic operation instruction related to the first instruction combination as the target arithmetic operation instruction, search for the storage instruction of the operation result from the target arithmetic operation instruction forward and use it as the target instruction. If the target instruction is not unique, that is, both the inner and outer loops contain the storage instruction of the operation result, then execute step 8; otherwise, use the position after the target instruction as the address of the write prefetch instruction, use the memory address of the target instruction as the operand of the write prefetch instruction, add the correspondence between the write prefetch instruction name, address and operand and the address of the target instruction to the write prefetch instruction insertion strategy list, and execute step 10.

[0039] Step 8. Establish the following three write prefetch instruction insertion strategies, including: inserting write prefetch instructions and synchronization instructions after the target instructions of both the inner and outer loops, inserting write prefetch instructions and synchronization instructions only after the target instructions of the inner loop, and inserting write prefetch instructions and synchronization instructions only after the target instructions of the outer loop. Complete the insertion of write prefetch instructions according to the three write prefetch instruction insertion strategies, and obtain the corresponding execution time. If the shortest execution time is greater than the execution time of the original executable file without the write prefetch instruction inserted, execute step 9; otherwise, add the write prefetch instruction insertion strategy with the shortest execution time to the write prefetch instruction insertion strategy list, and execute step 10.

[0040] Step 9. Form a second instruction set by the instructions located between the target instruction and the loop end instruction, traverse the instructions in the second instruction set, and for instructions that have no write dependency with the source operand of the target instruction and no read dependency with the target operand of the target instruction, move their converted codes to before the converted code of the target instruction. When there are multiple such instructions, the order of the instructions must be kept unchanged during the movement, and execute step 8.

[0041] Step 10: Save the write prefetch instruction insertion strategy list of the executable file and end this process. Example

[0042] In this embodiment, a dynamic instruction conversion optimization method based on write prefetch provided by the present invention is used to implement adding write prefetch instructions to load instructions and store instructions in a loop body, dynamically identifying vectorized load instructions and store instructions during the process of converting x86 instructions by an instruction conversion engine, and adding write prefetch instructions before store instructions, thereby completing the simulation execution of instructions of the x86 architecture on the ARM platform, including the following steps:

[0043] S1. Load and execute the executable file through dynamic instruction conversion. When the converted instruction is a MOV instruction, such as MOVEAX, [ESI + ESI_Index * 4], the detection of the matrix calculation mode is started and S2 is executed; otherwise, general instruction conversion is executed.

[0044] S2. Parse the base register, index register and element size of the MOV instruction in the executable file, such as EAX, EBX, ECX, ESI, EDI, etc.

[0045] For example, parsing MOV EAX, [ESI + ESI_Index * 4], we can infer that the element size is 32 bits based on the multiplication by 4.

[0046] S3. If the instruction after the current MOV instruction is MOV EBX, [ESI + (ESI_Index + 1) * 4], MOVECX, [ESI + (ESI_Index + 2) * 8], etc., if the index is increasing, the base address is constant, and the element size is uniform, it is determined to traverse the matrix elements by row; if the instruction after the current MOV instruction is MOV EAX, [EDI + EDI_ColIndex* 4 + RowOffset], EDI_ColIndex is the major column index, and RowOffset is an immediate value, it is determined to traverse the matrix elements by column.

[0047] S4. Based on the loop detection algorithm built on ECFG, decompile the subsequent code to identify the loop structure. Take the following code snippet as an example:

[0048] OuterLoop: ...

[0049] MOV ESI_Index, 0

[0050] InnerLoop: ...

[0051] INC ESI_Index

[0052] CMP ESI_Index, COLS_B

[0053] JNE InnerLoop ...

[0054] DEC EDI_Index

[0055] CMP EDI_Index, ROWS_A

[0056] JNE OuterLoop

[0057] Based on the depth-first search combined with the backtracking strategy, the ECFG is traversed and it is identified that the InnerLoop is nested inside the OuterLoop. Both layers are controlled by loop variables, which means it is a nested multi-layer loop.

[0058] S5. Identify arithmetic operations within the loop range analyzed in S4. Take the matrix multiplication core loop fragment as an example:

[0059] OuterLoop:

[0060] MOV EAX, [ESI + ESI_Index * 4] ; Get elements from matrix A

[0061] MOV EBX, [EDI + EDI_Index * 4] ; Get elements from matrix B

[0062] MUL EAX, EBX

[0063] MOV ESI_Index2, 0

[0064] InnerLoop:

[0065] MOV ECX, [EBX + ESI_Index2 * 4]

[0066] ADD ECX, EAX

[0067] MOV [EBX + ESI_Index2 * 4], ECX

[0068] INC ESI_Index2

[0069] CMP ESI_Index2, COLS_B

[0070] JNE InnerLoop

[0071] INC EDI_Index

[0072] CMP EDI_Index, ROWS_A

[0073] JNE OuterLoop

[0074] Specifically, using a deep backtracking algorithm based on the data dependency graph (DDG), it can be traced that the operands EAX and EBX of the MUL instruction originate from the previous load instruction, and the operand ECX of the ADD instruction originates from the inner loop memory access. EAX is used to store the result of the multiplication operation, so it conforms to the matrix multiplication operation logic chain and can be judged as a matrix multiplication operation.

[0075] S6. Identify the storage instruction related to the above arithmetic operation result, such as MOV [EBX + ESI_Index2 * 4], ECX.

[0076] S7. Insert a write prefetch instruction pldw after the ARM instruction (usually the str instruction) converted from the result storage instruction in the matrix calculation. The data address of the write prefetch instruction is the memory address in the storage instruction operand.

[0077] S8. If the current executable file is a multi-threaded program and the processor is a multi-core processor, in order to ensure write consistency when inserting the write prefetch instruction, a cache synchronization instruction needs to be inserted before and after the ARM calculation result storage instruction generated in the previous step.

[0078] Before storing the instruction str, use the DSB instruction as a data synchronization barrier to ensure that the previous prefetch and calculation operations have been completed and the data has been correctly loaded into the cache, such as:

[0079] DSB

[0080] str register, [address]

[0081] After the storage instruction str and before the prefetch instruction pldw, use the DSB and ISB instructions. DSB ensures that the written data has been written to the memory, and ISB ensures that subsequent instructions can read the latest written data status, such as:

[0082] DSB

[0083] ISB

[0084] pldw [register, address]

[0085] S9. If it is a nested multi-layer loop, optimize the loop structure performance, select the one with the shortest execution time from the three strategies, and end this process.

[0086] If the execution time of the executable file modified according to the selected write prefetch instruction insertion strategy is longer than the execution time of the executable file when the write prefetch instruction and the data synchronization barrier are not inserted, then the storage instruction corresponding to the insertion position of the write prefetch instruction is reversed, and it is recorded as insertTargetInstr. For all instructions between the loop end instruction, for instructions that have no write dependency on the source operand of insertTargetInstr (that is, the source operand of insertTargetInstr will not be written) and no read dependency on the target operand of insertTargetInstr (that is, the memory address of the write data of insertTargetInstr will not be read), their converted codes are moved before the converted code of insertTargetInstr, and the order of the previous and next instructions between the multiple codes moved before insertTargetInstr is ensured to remain unchanged; then execute S9.

[0087] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamic instruction conversion optimization method based on write prefetch, characterized in that: The specific steps include: Step 1: If the executable file has a corresponding write prefetch instruction insertion strategy list, the execution of the executable file is completed according to the write prefetch instruction insertion strategy list, and this process ends; otherwise, the executable file is loaded through dynamic instruction conversion; Step 2: parsing the executable file, extracting load instructions, store instructions and their respective target operands and source operands, and forming a first instruction set; Step 3, forming a first instruction combination from adjacent load instructions in the first instruction set that have the same base address register, determining a traversal method for matrix elements according to a calculation method for an offset, if the offset is a fixed value and is the same as the element size, the traversal method is row traversal, otherwise it is column traversal; forming a first instruction combination set from a correspondence between the first instruction combination and the traversal method; Step 4, identifying the single-layer loop in the executable file, and establishing a single-layer loop body set from the loop body of the single-layer loop; analyzing and determining the nested multi-layer loops in the single-layer loop body set, and forming a multi-layer loop body set from the loop bodies of these nested multi-layer loops; Step 5: The loop bodies in the single-layer loop body set that include the first instruction combination in the first instruction combination set constitute a first single-layer loop body set, and the loop bodies in the multi-layer loop body set that include the first instruction combination in the first instruction combination set constitute a first multi-layer loop body set; execute step 6 for the first single-layer loop body set, and execute step 7 for the first multi-layer loop body set; Step 6, traverse the first single-layer loop body set and take the arithmetic operation instruction related to the first instruction combination as the target arithmetic operation instruction, take the storage instruction of the operation result after the target arithmetic operation instruction as the target instruction, take the position after the target instruction as the address of the write prefetch instruction, take the memory address of the target instruction as the operand of the write prefetch instruction, add the correspondence between the write prefetch instruction name, address and operand and the address of the target instruction to the write prefetch instruction insertion strategy list, and execute step 9; Step 7, traverse the first multi-layer loop body set and take the arithmetic operation instruction related to the first instruction combination as the target arithmetic operation instruction, take the storage instruction of the operation result after the target arithmetic operation instruction as the target instruction, if the target instruction is not unique, execute step 8; otherwise, take the position after the target instruction as the address of the write prefetch instruction, take the memory address of the target instruction as the operand of the write prefetch instruction, add the correspondence between the write prefetch instruction name, address and operand and the address of the target instruction to the write prefetch instruction insertion strategy list, and execute step 9; Step 8, inserting the write prefetch instruction according to three methods: inserting the write prefetch instruction and the synchronization instruction after the target instructions of the inner and outer loops, inserting the write prefetch instruction and the synchronization instruction only after the target instruction of the inner loop, and inserting the write prefetch instruction and the synchronization instruction only after the target instruction of the outer loop, and adding the method with the shortest execution time to the write prefetch instruction insertion strategy list; Step 9: Save the write prefetch instruction insertion strategy list of the executable file and end this process.

2. The dynamic instruction conversion optimization method according to claim 1, characterized in that: The method of parsing the executable file in step 2 is: parsing the executable file using a deep traversal algorithm based on an abstract syntax tree.

3. The dynamic instruction conversion optimization method according to claim 1, characterized in that: The memory unit corresponding to the target operand or source operand is represented by a memory addressing method, including a base register and an offset.

4. The dynamic instruction conversion optimization method according to claim 1, characterized in that: The method of identifying the single-layer loop in the executable file in step 4 is: establishing an extended control flow graph for the executable file, and using a loop detection algorithm to parse the extended control flow graph to obtain the single-layer loop.

5. The dynamic instruction conversion optimization method according to claim 4, characterized in that: The method of analyzing and determining the nested multi-layer loops in the single-layer loop body set in step 4 is: traversing the extended control flow graph based on depth-first search combined with backtracking strategy to determine the nested multi-layer loops in the single-layer loop body set.

6. The dynamic instruction conversion optimization method according to claim 1, characterized in that: In step 6, the position after the target instruction is used as the address of the write prefetch instruction, and at the same time, a DSB instruction is inserted before the target instruction, and a DSB instruction and an ISB instruction are inserted after the target instruction.

7. The dynamic instruction conversion optimization method according to claim 1, characterized in that: When the shortest execution time described in step 8 is greater than the execution time of the original executable file without inserting the write prefetch instruction, a second instruction set is formed by the instructions located between the target instruction and the loop end instruction, and the instructions in the second instruction set are traversed. For instructions that have no write dependency with the source operand of the target instruction and no read dependency with the target operand of the target instruction, their converted codes are moved before the converted code of the target instruction. When there are multiple such instructions, the order of the instructions is kept unchanged after the movement, and then step 8 is executed.

8. The dynamic instruction conversion optimization method according to claim 1, characterized in that: In step 7, the position after the target instruction is used as the address of the write prefetch instruction, and at the same time, a DSB instruction is inserted before the target instruction, and a DSB instruction and an ISB instruction are inserted after the target instruction.

9. The dynamic instruction conversion optimization method according to claim 1, characterized in that: Both load instructions and store instructions are MOV instructions.

10. The dynamic instruction conversion optimization method according to claim 1, characterized in that: The write prefetch instruction is a pldw instruction.