Processor with non-invasive self-testing

Abstract

The invention relates to a processor with non-invasive self-testing. A processor (100) includes a central processing unit (CPU) (102) and a diagnostic monitoring circuit (112). The diagnostic monitoring circuit (112) is coupled to the CPU (102). The diagnostic monitoring circuit (112) includes a monitoring and cyclic redundancy check (CRC) calculation unit (106). The monitoring and CRC calculation unit (106) is configured to detect execution of a diagnostic program by the CPU (102) and calculate a plurality of CRC values. When the CPU (102) executes the diagnostic program, each of the CRC values corresponds to a processor value retrieved from a given register of the CPU (102) or from a bus coupling the CPU (102) to a memory and peripheral subsystem (108).

Description

[0001] Information about divisional applications

[0002] This case is a divisional application of the invention patent application with application date of August 1, 2018, application number 201810862842.6, and invention name “Processor with non-intrusive self-test”.

[0003] Related Applications

[0004] This application claims priority to Indian Provisional Application No. 201741027612 filed on August 3, 2017, which is incorporated herein by reference. Technical Field

[0005] The present application relates to a processor with non-intrusive self-test. Background Art

[0006] Microprocessors, microcontrollers, and similar electronic devices are used in a variety of applications. Various conditions and events can cause such devices to fail, adversely affecting device operation. The consequences of such failures are often more significant when the device in which the failure occurs is performing a critical task that affects user safety. To ensure that such applications operate correctly, the operating conditions of the device are continuously evaluated. The device may include a self-test feature that supports continuous evaluation of operation. Summary of the invention

[0007] Disclosed herein is an apparatus and method for monitoring processor operation. In one example, a processor includes a central processing unit (CPU) and a diagnostic monitoring circuit. The diagnostic monitoring circuit is coupled to the CPU. The diagnostic monitoring circuit includes a monitoring and cyclic redundancy check (CRC) calculation unit. The monitoring and CRC calculation unit is configured to detect the CPU's execution of a diagnostic program and calculate a plurality of CRC values. When the CPU executes the diagnostic program, each of the CRC values ​​corresponds to a processor value retrieved from a given register of the CPU or from a bus that couples the CPU to a memory and a peripheral subsystem. Each of the CRC values ​​corresponds to various aspects of the CPU, such as a register, a memory bus, or an internal state during the execution of the diagnostic program.

[0008] In another example, the processor diagnostic circuit includes a diagnostic monitoring circuit. The diagnostic monitoring circuit includes a monitoring and cyclic redundancy check (CRC) calculation unit. The monitoring and CRC calculation unit is configured to detect execution of a diagnostic program by a central processing unit (CPU) and calculate a plurality of CRC values. When the CPU executes the diagnostic program, each of the CRC values ​​corresponds to a processor value retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystems. Each of the CRC values ​​corresponds to various aspects of the CPU, such as a register, a memory bus, or an internal state during execution of the diagnostic program.

[0009] In another example, a method for monitoring a processor health state includes executing, by a processor, instructions of a diagnostic program during discontinuous processor idle time intervals. The method also includes detecting, by a diagnostic monitoring circuit, the execution of the diagnostic program in the discontinuous idle time intervals. The method further includes calculating a plurality of cyclic redundancy check (CRC) values, each of the CRC values ​​corresponding to a processor value retrieved from a given register of a central processing unit (CPU) of the processor when the diagnostic program is executed by the CPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To describe various examples in detail, reference is now made to the accompanying drawings, in which:

[0011] Figure 1 A block diagram illustrating a processor including a non-intrusive self-test according to various examples;

[0012] Figure 2 A block diagram showing a monitoring and cyclic redundancy check computation unit for non-intrusive self-testing according to various examples;

[0013] Figure 3 illustrates an example of a self-test execution time sequence in a processor including a non-intrusive self-test according to various examples;

[0014] Figure 4 A block diagram showing a pipeline extraction unit for non-intrusive self-testing according to various examples;

[0015] Figure 5 A flowchart illustrating a method for performing a non-intrusive self-test according to various examples; and

[0016] Figure 6 A flow chart of a method for non-intrusive self-testing according to various examples is shown. DETAILED DESCRIPTION

[0017] Certain terms are used throughout the following description and claims to refer to specific system components. As will be appreciated by those skilled in the art, different parties may refer to components by different names. It is not intended herein to distinguish between components that differ in name but not in function. In the following discussion and in the claims, the terms "include" and "comprise" are used in an open manner and should therefore be interpreted as meaning "including (but not limited to)...". Similarly, the term "coupled" is intended to mean an indirect or direct wired or wireless connection. Thus, if a first device is coupled to a second device, the connection may be by a direct connection, or by an indirect connection via other devices and connections. The statement "based on" means "based at least in part on". Thus, if X is based on Y, X may vary with Y and any number of other factors.

[0018] Periodic self-testing is important or required in a variety of applications (e.g., some embedded real-time applications, mission-critical applications, etc.). However, conventional techniques for self-testing can be intrusive or inefficient. For example, hardware built-in self-test (BIST) is intrusive because the central processing unit (CPU) being tested is not available to execute user applications while the hardware BIST is being performed. Alternatively, software-only self-testing is also inefficient because a large number of instructions must be executed to provide sufficient fault coverage.

[0019] The example processor of the present disclosure includes a non-intrusive and efficient self-test. The self-test can be completely interrupted to provide the fast response time required by the embedded real-time system. In some examples, the self-test programming can be performed only during the CPU idle time, so the application timing is usually not affected by the self-test. The disclosed processor may include a circuit for retrieving registers and state values ​​from the CPU, processor bus, peripheral devices, etc. During the execution of the self-test program, each given type of retrieval value is input to a cyclic redundancy check (CRC) circuit, which calculates the CRC value of the retrieval value for the given type within the self-test length. When the self-test program is executed, the CRC value is compared with the stored predetermined correct CRC value with the self-test program to determine whether the CPU and the associated system are operating correctly.

[0020] Figure 1A block diagram of a processor 100 including a non-intrusive self-test according to various examples is shown. The processor 100 may be a general purpose microprocessor, a microcontroller, a digital signal processor, or other instruction execution device. The processor 100 includes a central processing unit (CPU) 102, a memory and peripheral subsystem 108, and a diagnostic monitoring circuit 112. The CPU 102 includes circuitry to execute instructions retrieved from the memory. For example, the CPU 102 may include an execution pipeline including a fetch unit, a decode unit, and an execution unit. Some examples of the CPU 102 may include additional functional units, such as data and / or instruction caches, branch prediction circuits, etc. The fetch unit retrieves instructions from the instruction memory for execution by the processor 100. The instruction memory may be included in the processor 100, or external to the processor 100. The fetch unit provides the retrieved instructions to the decode unit.

[0021] The decode unit examines the instructions received from the fetch unit and translates each instruction into controls suitable for operating the execution unit, processor registers, and other components of the processor to perform operations that implement the instructions. The decode unit provides control signals to the execution unit and other units of the processor 100, causing the processor 100 to perform the operations required to execute each instruction.

[0022] The execution units include arithmetic circuits, shifters, multipliers, registers, logic operation circuits, etc., which are arranged to manipulate data values ​​specified by control signals generated by the decode units. Some implementations of processor 100 may include multiple execution units including the same or different data manipulation capabilities.

[0023] The memory and peripheral subsystem 108 includes various circuits that operate in conjunction with the CPU 102. For example, the memory and peripheral subsystem 108 may include memory for storing programs and data, communication circuits, interrupt control circuits, timer circuits, direct memory access control circuits, and / or various other circuits that provide services to the CPU 102. The memory and peripheral subsystem 108 is communicatively connected to the CPU 102 via one or more buses 114.

[0024] The diagnostic monitoring circuit 112 monitors the operation of the CPU 102 and / or the memory and peripheral subsystem 108 to determine whether the processor 100 is operating correctly. The diagnostic monitoring circuit 112 is coupled to the CPU 102, the memory and peripheral subsystem 108, and / or one or more buses 114 for communicating information about the operating status of the CPU 102 and / or the memory and peripheral subsystem 108 to the diagnostic monitoring circuit 112. The diagnostic monitoring circuit 112 includes the pipeline extraction unit 104, the monitoring and CRC calculation unit 106, and the monitoring circuit 110.

[0025] The pipeline extraction unit 104 is coupled to the CPU 102. The pipeline extraction unit 104 retrieves information from the CPU 102 that is not otherwise available to circuits external to the CPU 102. For example, the pipeline extraction unit 104 may obtain instruction register contents, pipeline state information, program counter values, and / or other information generated internally to the CPU 102 from the CPU 102. The pipeline extraction unit 104 may combine some of the information retrieved from the CPU 102 so that the amount of information provided to the monitoring and CRC calculation unit 106 may be reduced. For example, the pipeline extraction unit 104 may simultaneously obtain multiple different values ​​from the CPU 102 and combine the multiple values ​​using an exclusive-or function. The exclusive-or of the multiple values ​​may be provided to the monitoring and CRC calculation unit 106.

[0026] The monitoring and CRC calculation unit 106 is coupled to the pipeline extraction unit 104, the memory and peripheral subsystem 108, and the one or more buses 114. The monitoring and CRC calculation unit 106 captures information provided by the pipeline extraction unit 104, the memory and peripheral subsystem 108, and the one or more buses 114 and calculates CRC values ​​for each different type of information captured when the processor 100 executes a self-test program (also referred to herein as a diagnostic program). For example, the monitoring and CRC calculation unit 106 may calculate a first CRC value using a program counter value retrieved during the execution of the self-test program, calculate a second CRC value using an instruction register value retrieved during the execution of the self-test program, and so on.

[0027] The monitoring and CRC calculation unit 106 analyzes information received from the pipeline extraction unit 104, the memory and peripheral subsystem 108, and the one or more buses 114 to determine whether to update the CRC value using the received information. Because the CRC value is updated based on the execution of the self-test program, some embodiments of the monitoring and CRC calculation unit 106 check the program counter value to determine whether the self-test program is being executed. For example, the range of address values ​​at which the self-test program is stored can be pre-programmed into the monitoring and CRC calculation unit 106. If the program counter address value is within the range of address values, the monitoring and CRC calculation unit 106 can update the CRC value using the information retrieved from the pipeline extraction unit 104, the memory and peripheral subsystem 108, and the one or more buses 114.

[0028] When execution of the self-test program is complete, the CRC value calculated by the monitoring and CRC calculation unit 106 may be compared to a predetermined correct CRC value to determine whether the processor 100 passed or failed the self-test. For example, the predetermined expected CRC value may be stored as part of the self-test program, and the comparison of the calculated CRC value to the predetermined correct CRC value may be performed by the CPU 102 as part of the execution of the self-test program, or by the monitoring and CRC calculation unit 106. The results of the self-test may be stored for further processing and / or provided to a user.

[0029] The monitoring circuit 110 monitors the self-test to ensure that the execution of the self-test program is in accordance with the established specifications. For example, if the established specifications provide that the self-test program should execute for at least a first amount of time at predetermined time intervals, then the monitoring circuit 110 can measure the execution time of the self-test at predetermined time intervals and adjust the operating parameters of the processor 100 to change the execution time of the self-test based on the measured execution time. The adjustment can include enforcing a minimum execution time for the self-test program when the user program preempts.

[0030] Figure 2 A block diagram of a monitoring and CRC calculation unit 106 according to various examples is shown. The monitoring and CRC calculation unit 106 includes a CRC calculation circuit 202, a CRC control circuit 204, and a CRC register 206. The CRC register 206 includes a register 208 for each of a plurality of CRC values ​​calculated by the monitoring and CRC calculation unit 106. For example, the CRC register 206 may include a register 208 for storing each of a write data CRC value, a write address CRC value, a read data CRC value, a read address CRC value, an instruction register CRC value, a program counter CRC value, and an internal node CRC value. The number of bits provided in each CRC register 208 may be different in different implementations. In some implementations, the CRC register 208 may store a 32-bit CRC value.

[0031] CRC calculation circuit 202 is coupled to CRC register 206, pipeline extraction unit 104, memory and peripheral subsystem 108, and / or bus 114. CRC calculation circuit 202 includes circuitry to evaluate a CRC polynomial relative to a current value of CRC register 208 and a new information value received from pipeline extraction unit 104, memory and peripheral subsystem 108, and / or bus 114. Thus, CRC calculation circuit 202 retrieves a value from CRC register 206, calculates a CRC value based on the value retrieved from the CRC register and the new information value, and stores the result of the polynomial evaluation in CRC register 206. Some implementations of CRC calculation circuit 202 may include separate CRC evaluation circuitry for each CRC register 208.

[0032] CRC control circuit 204 checks information received from pipeline extraction unit 104, memory and peripheral subsystem 108, and / or bus 114 to determine whether a self-test is being performed and the CRC value stored in CRC register 206 should be updated based on the information received from pipeline extraction unit 104, memory and peripheral subsystem 108, and / or bus 114. For example, CRC control circuit 204 may store information defining a range of address values ​​at which the self-test program is stored. If the program counter address value received from pipeline extraction unit 104 is within the range, CRC control circuit 204 may determine that a self-test is being performed and, in turn, may select a CRC register 208 corresponding to the received information to be updated and enable CRC calculation circuit 202 to update the CRC value stored in the selected CRC register 208.

[0033] Figure 3 1 shows the execution of self-tests in the processor 100 according to various examples. In an embodiment of the processor 100, the execution of the self-test program is interspersed with the execution of the user program. Figure 3 , the execution of the self-test 304 is interspersed with the execution of the user task 302. For example, the processor 100 may execute the self-test 304 only when the user task 302 is not ready to be executed. That is, the processor 100 may execute the self-test 304 only when the CPU 102 is idle (i.e., CPU idle time). Therefore, the execution of the self-test 304 does not interfere with the execution timing of the user task 302. Because the execution of the self-test 304 is executed in any number of discontinuous execution time intervals from beginning to end, the monitoring and CRC calculation unit 106 identifies the execution of the self-test program. The monitoring and CRC calculation unit 106 enables the updating of the CRC register 206 within the entire discontinuous execution of the self-test program, and prohibits the updating of the CRC register 206 when the user task 302 is being executed.

[0034] Figure 4 1 shows a block diagram of a pipeline extraction unit 104 according to various examples. Figure 1 As shown, pipeline extraction unit 104 interfaces with CPU 102. Figure 4 , pipeline nodes 402, 404, 406, 408, and 410 may be registers or outputs of other circuits in CPU 102. Pipeline extraction unit 104 passes some of the information retrieved from the pipeline nodes to monitoring and CRC calculation unit 106 without modification. Thus, pipeline extraction unit 104 provides monitoring and CRC calculation unit 106 with direct access to information generated in CPU 102. Figure 4, the information retrieved from pipeline node 410 is passed unmodified to monitoring and CRC calculation unit 106 as raw output 416. Embodiments of pipeline extraction unit 104 may pass information retrieved from any number of pipeline nodes of CPU 102 unmodified.

[0035] The pipeline extraction unit 104 may also include circuitry to process or combine information retrieved from some of the pipeline nodes of the CPU 102. By combining information retrieved from multiple pipeline nodes of the CPU 102, the pipeline extraction unit 104 reduces the number of different data values ​​provided to the monitoring and CRC calculation unit 106, which in turn reduces the number of CRC values ​​maintained by the monitoring and CRC calculation unit 106. Figure 4 In the example of , pipeline extraction unit 104 includes XOR circuit 412. XOR circuit 412 combines the information retrieved from pipeline nodes 402, 404, 406, and 408 to produce a composite output 414 that is provided to monitoring and CRC calculation unit 106. Implementations of pipeline extraction unit 104 may combine information retrieved from any number of pipeline nodes of CPU 102 to produce a composite output, and implementations may produce any number of different composite outputs that combine different pipeline nodes of CPU 102.

[0036] Figure 5 A flow chart of a method for performing a non-intrusive self-test according to various examples is shown. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown. At least some of the operations of method 500 may be implemented by processor 100.

[0037] In block 502, processor 100 executes instructions retrieved from program storage (i.e., instructions retrieved from memory). Monitoring and CRC calculation unit 106 receives information from pipeline extraction unit, memory and peripheral subsystem 108, and / or bus 114. If the instructions being executed are part of a user program (i.e., user task 302), then monitoring of program execution continues at block 502.

[0038] On the other hand, if no user program is executing (ie, no user program is ready to execute) in block 502 , then in block 504 the processor 100 begins or resumes execution of instructions of the self-test program (ie, self-test 304 ).

[0039] In block 506, the processor 100 executes the self-test program started in block 504. The processor 100 determines whether a user program is ready to execute. If no user program is ready to execute, the processor 100 continues to execute the self-test program.

[0040] If the user program is ready to execute in block 506 , then in block 508 , the processor 100 suspends execution of the self-test program and starts / resumes execution of the user program.

[0041] Thus, the processor 100 executes the self-test procedure only when no user program is executing or ready to execute. In this way, embodiments of the processor 100 provide a self-test that is non-intrusive to the timing or functionality of the user program.

[0042] Figure 6 A flow chart of a method for non-intrusive self-test according to various examples is shown. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown. At least some of the operations of method 600 may be implemented by processor 100.

[0043] In block 602, processor 100 executes instructions retrieved from program storage (i.e., instructions retrieved from memory). Pipeline extraction unit 104 retrieves various information values ​​from CPU 102. The information values ​​may include program counter values, instruction values, read address values, read data values, write address values, and / or write data values, and / or various state / data values ​​provided in registers of CPU 102 and / or present in pipeline nodes of CPU 102.

[0044] In block 604, pipeline extraction unit 104 combines some of the information values ​​retrieved from CPU 102 to reduce the number of values ​​provided to monitoring and CRC calculation unit 106. Some embodiments of pipeline extraction unit 104 may apply an exclusive-or function to produce a composite value of the multiple values ​​retrieved from CPU 102.

[0045] In block 606, the monitoring and CRC calculation unit 106 evaluates the information received from the pipeline execution unit 104, the memory and peripheral subsystem 108, and / or the bus 114 to determine whether the CPU 102 is currently executing a self-test (i.e., self-test 304). For example, the monitoring and CRC calculation unit 106 may compare the address of the execution instruction received via the pipeline extraction unit 104 with the address range where the self-test program is stored to determine whether the self-test is being executed. If the self-test is not being executed, the method continues with block 602 to retrieve additional information from the CPU 102.

[0046] If, in block 606, the monitoring and CRC calculation unit 106 determines that a self-test is being performed, then in block 608, the monitoring and CRC calculation unit 106 calculates a CRC value for each of a plurality of information values ​​received from the pipeline extraction unit 104, the memory and peripheral subsystems 108, and / or the bus 114. Calculating the CRC value may include retrieving a current CRC value from a storage device (e.g., register 208) and applying the current CRC value and new information values ​​received from the pipeline extraction unit 104, the memory and peripheral subsystems 108, and / or the bus 114 to a predetermined polynomial.

[0047] In block 610, processor 100 determines whether self-test execution is completed. For example, the execution of self-test may include setting a state value specifying that self-test is completed. In various embodiments, the determination that self-test is completed may be performed by monitoring circuit 110, CPU 102, monitoring and CRC calculation unit 106 or other components of processor 100. If self-test is completed, then in block 616, processor 100 determines whether self-test fails or passes. Processor 100 may compare the CRC value calculated by monitoring and CRC calculation unit 106 during self-test execution with a predetermined correct CRC value. For example, for each CRC value calculated by monitoring and CRC calculation unit 106, a predetermined correct CRC value may be stored in a memory (e.g., as a part of a self-test program). If the CRC value calculated by monitoring and CRC calculation unit 106 during self-test execution is equal to a predetermined correct CRC value, processor 100 considers the self-test passed in block 618. On the other hand, if the CRC value calculated by the monitoring and CRC calculation unit 106 during the execution of the self-test is not equal to the predetermined correct CRC value, then the processor 100 considers the self-test to have failed in block 620 .

[0048] If, in block 610, the processor 100 determines that execution of the self-test is not complete, then in block 612, the monitoring circuit 110 determines whether the amount of time to execute the self-test is a minimum. The minimum amount of time may be at least a predetermined test execution time within a given time interval (e.g., 10 milliseconds in each second). If the time for self-test execution is low (e.g., the execution time of the user task allows too little time for self-test execution), then in block 614, the monitoring circuit 110 adjusts the operation of the processor 100 to ensure that the self-test executes for at least the minimum execution time. For example, the monitoring circuit 110 may prohibit the user task from preempting the self-test for at least a time selected to provide the required minimum execution time for the self-test.

[0049] The above discussion is intended to illustrate the principles and various examples of the present invention. For those skilled in the art, many variations and modifications will become apparent once the above disclosure is fully understood. It is intended that the appended claims be interpreted as including all such variations and modifications.

Claims

1. A processor, comprising: A central processing unit CPU, comprising a first register and a second register; as well as a monitoring circuit coupled to the CPU, the monitoring circuit being configured to: Detecting execution of a program by the CPU; retrieving a first processor value from said first register of said CPU; retrieving a second processor value from said second register of said CPU; combining the first processor value and the second processor value; calculating a cyclic redundancy check (CRC) value based on the combined first processor value and the second processor value; as well as The CRC value is compared to a predetermined CRC value for a match.

2. The processor of claim 1, wherein the CPU is configured to execute the program only during CPU idle time.

3. The processor of claim 1 , wherein: the monitoring circuit being configured to combine the first processor value and the second processor value into a single value; as well as The CRC value is based on the single value. 4 . The processor of claim 3 , wherein combining the first processor value and the second processor value into the single value comprises applying an exclusive-OR function to the first processor value and the second processor value.

5. The processor of claim 1 , wherein the first processor value comprises: Program counter value; Command value; Read address value; Read data value; Write the address value; and Write data value.

6. The processor of claim 1 , wherein the monitoring circuit is configured to: identifying completion of execution of the program; and Responsive to the completion, the CRC value is compared to the predetermined CRC value.

7. The processor of claim 1 , wherein the monitoring circuit is further configured to: monitoring the performance of said procedures; and Based on the time that the program is executed within the predetermined time interval being less than a minimum predetermined execution time, a time allocated for execution of the program is increased.

8. The processor of claim 1, wherein the monitoring circuit is configured to calculate the CRC value over discrete execution time intervals of the program.

9. A method for monitoring processor operation, comprising: The monitoring circuit detects the execution of the program by the central processing unit CPU; retrieving a first processor value from a first register of the CPU; retrieving a second processor value from a second register of the CPU; combining the first processor value and the second processor value; calculating a cyclic redundancy check (CRC) value based on the combined first processor value and the second processor value; as well as The CRC value is compared to a predetermined CRC value for a match.

10. The method according to claim 9, wherein combining the first processor value and the second processor value to produce a single value; and The CRC value is based on the single value.

11. The method of claim 9, wherein combining the first processor value and the second processor value into a single value comprises applying an exclusive-OR function to the first processor value and the second processor value.

12. The method of claim 10, further comprising identifying completion of execution of the program, wherein in response to the completion, the CRC value is compared to a predetermined CRC value.

13. The method according to claim 10, further comprising: monitor the implementation of said procedures; as well as Based on the time that the program is executed within the predetermined time interval being less than a minimum predetermined execution time, a time allocated for execution of the program is increased.

14. A circuit comprising: A monitoring circuit is configured to: Detect the execution of the program by the central processing unit CPU; calculating a plurality of cyclic redundancy check (CRC) values, wherein each of the CRC values ​​is a function of a processor value retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and a peripheral subsystem while the CPU executes the program; and pipeline extraction unit, which is configured as retrieving a processor value from a register of the CPU and providing the processor value to the monitoring circuit for use in a CRC calculation; and combining a plurality of processor values ​​retrieved from the CPU into a single value and providing the single value to the monitoring circuit for use in a CRC calculation; Wherein the monitoring circuit is further configured to compare each of the CRC values ​​to a corresponding predetermined CRC value.

15. The circuit of claim 14, further comprising a monitoring circuit configured to: monitoring the performance of said procedures; and Based on the time the program is executed within the predetermined time interval being less than a minimum predetermined diagnostic execution time, the CPU increases a time allocated for execution of the program.

16. The circuit of claim 14, wherein the monitoring circuit is further configured to identify completion of execution of the program; and Wherein the monitoring circuit is configured to compare each of the CRC values ​​to the corresponding predetermined CRC value in response to the completion.

17. The circuit of claim 14, wherein the processor value comprises: Program counter value; Command value; Read address value; Read data value; Write the address value; and Write data value.

18. The circuit of claim 14, wherein the pipeline extraction unit is further configured to combine the processor values ​​into the single value by applying an exclusive-OR function to the processor values.

19. The circuit of claim 14, wherein the monitoring circuit is further configured to calculate each of the CRC values ​​over discrete execution time intervals of the program.

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