Register protection method, system, device and product

Abstract

The present application provides a register protection method, system, device and product, the method comprising: obtaining the output value of each register in the module and the output value of the corresponding register protection module, the register protection module is obtained by copying the register or constructing it using an error detection algorithm; comparing the output value of the register with the output value of the register protection module to obtain a single-bit result; performing logical compression processing on the single-bit result through a full self-check fault comparator to obtain an output result; the output result includes a 2-bit level combination, when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or register protection mechanism is in an abnormal state; according to the output result, a pulse output signal is generated. This solution can accurately and effectively detect single-point faults and improve the coverage of latent fault detection.

Description

Technical Field

[0001] The present application relates to the field of chip security technology, and in particular, to a register protection method, system, device and product. Background Art

[0002] With the continuous development of modern electronic systems, especially in the fields of automotive electronics that have extremely high requirements for safety and reliability, registers, as key components for storing data and controlling information, have a direct impact on the operation of the entire system due to their stability and correctness. As system complexity continues to rise and the application environment becomes increasingly diverse, registers are also facing many threats and challenges. Among them, the Automotive Safety Integrity Level (ASIL), as an indicator for measuring the safety of automotive electronic systems or functions, has been increasingly used in the automotive industry to ensure the safety of electronic and electrical systems in vehicles during normal operation and when failures occur. Therefore, in order to improve the safety and reliability of automotive use, it is particularly important to study how to protect registers in the automotive field.

[0003] At present, the logic compression in the register protection scheme in the related technology mostly adopts the detection architecture based on OR logic (orreduction). However, this scheme has some faults caused by environmental factors that cannot be effectively detected. Environmental interference may cause the logic gate output to be abnormal but cannot be detected. The fault in this error detection mechanism is called a latent fault. In order to detect the latent fault, it is usually necessary to perform error injection detection on the logic compression. Summary of the invention

[0004] The embodiments of the present application provide a register protection method, system, device and product.

[0005] A first aspect of an embodiment of the present application provides a register protection method, comprising:

[0006] Acquire the output value of each register in the module and the output value of the corresponding register protection module, wherein the register protection module is obtained by copying the register or constructing it using an error detection algorithm;

[0007] Compare the output value of the register with the output value of the register protection module to obtain a single-bit result; when the single-bit result is a high level, it indicates that an error has occurred in the register in the module; when the single-bit result is a low level, it indicates that no error has occurred in the register in the module;

[0008] The single-bit result is logically compressed by a full self-check fault comparator to obtain an output result; the output result includes a 2-bit level combination, when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state;

[0009] A pulse output signal is generated according to the output result; the pulse output signal is used to indicate whether an error occurs in the system.

[0010] In an optional embodiment of the present application, the single-bit result is logically compressed by a full self-test fault comparator to obtain an output result, including:

[0011] Dividing the plurality of single-bit results into two parts, and performing inversion processing on one part of the single-bit results to obtain an inverted value;

[0012] The inverted value and the remaining single-bit results are subjected to logical compression processing to obtain the output result.

[0013] In an optional embodiment of the present application, the negated value and the remaining single-bit results are subjected to logical compression processing to obtain the output result, including:

[0014] Performing a first comparison logic compression process of the full self-detection fault on the two groups of the inverted value and the remaining single-bit results to obtain a plurality of compressed values;

[0015] The plurality of compressed values ​​are subjected to a second comparison logic compression process of full self-detection fault to obtain the output result.

[0016] In an optional embodiment of the present application, the two groups of the inverted value and the remaining single-bit results are subjected to a first comparison logic compression process of the full self-detection fault to obtain multiple compressed values, including:

[0017] The inverted value and each two of the remaining single-bit results are combined and logically processed to obtain a plurality of compressed values.

[0018] In an optional embodiment of the present application, generating a pulse output signal according to the output result includes:

[0019] When the output result indicates that the protected register or the register protection mechanism is in a normal state, the output result is processed by a pulse generating circuit, and the generated pulse output signal is a normal system signal;

[0020] When the output result indicates that the protected register or the register protection mechanism is in an abnormal state, the output result is processed by a pulse generating circuit, and the generated pulse output signal is a system error signal.

[0021] In an optional embodiment of the present application, comparing the output value of the register with the output value of the register protection module to obtain a single-bit result includes:

[0022] When the output value of the register and the output value of the register protection module are "compared and passed", a single-bit result is generated as a low level;

[0023] When the output value of the register “failed to pass the comparison” with the output value of the register protection module, a single-bit result of a high level was generated.

[0024] A second aspect of the embodiments of the present application provides a register protection system, including: a plurality of modules and a full self-check fault comparator, each module including a plurality of registers, a register protection module, and a comparison module;

[0025] The register protection module is obtained by copying the register or constructing it by using an error detection algorithm; the comparison module is used to compare the output value of the register with the output value of the register protection module to obtain a single-bit result; when the single-bit result is a high level, it indicates that an error has occurred in the register in the module; when the single-bit result is a low level, it indicates that no error has occurred in the register in the module;

[0026] The full self-check fault comparator is used to: perform logical compression processing on the single-bit result to obtain an output result; the output result includes a 2-bit level combination, and a pulse output signal is generated according to the output result; when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state; the pulse output signal is used to indicate whether an error occurs in the system.

[0027] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program or data, and the processor implements the steps of any of the above methods when executing the computer program.

[0028] A fourth aspect of the embodiments of the present application provides a computer hardware and program product, wherein the computer hardware and program product include instructions, and when the instructions are executed by the hardware, the steps of any of the above methods are implemented.

[0029] In the embodiment of the present application, the output value of each register in the module and the output value of the corresponding register protection module are obtained, and the output value of the register is compared with the output value of the register protection module to obtain a single-bit result. When the single-bit result is a high level, it indicates that an error has occurred in the register in the module; when the single-bit result is a low level, it indicates that no error has occurred in the register in the module; the single-bit result is logically compressed by a full self-check fault comparator to obtain an output result; the output result includes a 2-bit level combination, when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state; according to the output result, a pulse output signal is generated; the pulse output signal is used to indicate whether an error has occurred in the system. Compared with the prior art, the technical solution in the present application can determine a single-bit result by comparing the output value of the register with the output value of the register protection module, and because a full self-check fault comparator is used, the single-bit result of each module can be automatically logically compressed according to the level value. In particular, for situations where the output of the logic gate is abnormal due to environmental factors (such as electromagnetic interference, temperature changes, etc.), the full self-check fault comparator is used to perform logical compression processing, so as to more comprehensively and accurately determine the 2-bit level combination to detect whether an error occurs in the system, thereby effectively detecting single-point faults and improving the latent fault detection coverage; and part of the self-check logic of the register protection is moved to the TSC decode area, thereby increasing the effective area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0031] Figure 1 A schematic diagram of the error detection and processing logic structure of a physical device provided by an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the structure of a computer device provided in one embodiment of the present application;

[0033] Figure 3 A flowchart of a register protection method provided by an embodiment of the present application;

[0034] Figure 4 A schematic diagram of the structure of a register protection system provided by an embodiment of the present application;

[0035] Figure 5A schematic flow chart of a method for obtaining an output result by performing logic compression processing on a check signal according to a level value of the check signal through a full self-check fault comparator provided in another embodiment of the present application;

[0036] Figure 6 A schematic diagram of the logic principle of a full self-check fault comparator provided by an embodiment of the present application;

[0037] Figure 7 A schematic diagram of the logic operation of a full self-check fault comparator provided in one embodiment of the present application. DETAILED DESCRIPTION

[0038] In the process of implementing the present application, the inventors found that the traditional solution cannot effectively detect faults caused by environmental factors.

[0039] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0040] As mentioned in the background technology, ASIL is divided into five levels: Quality Management (QM), A, B, C, and D. Among them, QM means no specific safety requirements, while AD levels have different degrees of requirements for functional safety, and ASIL D is the highest level. Please refer to the following Table 1, which includes the failure degree requirements corresponding to different automotive safety levels of safety-related products:

[0041] Table 1

[0042]

[0043] For the safety protection of automotive grade ASIL B, it can be required to protect the registers in the entire CPU, and the single-point failure rate is required to reach 90% of the overall coverage, which can be understood as the failure in the original design logic. Register protection needs to cover 90% of the failure in the original design logic; the potential failure rate reaches 60%, and the potential failure here can be understood as the failure in the protection logic of register protection.

[0044] See also Figure 1 As shown, Figure 1A schematic diagram of the error detection and processing logic structure of a physical device provided in an embodiment of the present application, wherein the figure includes multiple modules, registers and logic gates. The multiple modules may include two, three, four or more modules, for example, Module A and Module B shown in the figure, which represent different functional units. The registers in Module A may include multiple ones, for example, Reg A and Reg B and more other registers, which are used to store data or status information. The above-mentioned module Module A also includes Reg Prot A, which is the protection part of register Reg A, and includes protection logic and check logic. The output of the check logic can be a check signal generated by a single-bit result, and the check signal can be represented by err, so err is used here to represent the single-bit result.

[0045] The originally designed register Reg A or Reg B includes data input and output ports.

[0046] In the entire processing logic process, multiple signals are included, including Check_enable, Err_pulse, etc. These signals are used to control the process of error detection and processing. The Error_injection enable signal is an enable flag for artificial error injection, which is used to enable the check mechanism of register protection for artificial error injection, and when the register is not an even number, it can be used to replace the register and register protection mechanism; the Err_pulse signal is an error pulse signal, which is used to indicate the detected error. For the error detection mechanism, when the Check_enable signal is received, it is used to start the error detection mechanism, and when the signal is activated, it will trigger the check of the register. If a submodule detects an error through the err interface, or injects an error through Error_injection, an Err_pulse signal will be generated, indicating that an error has occurred. It is used to ensure that the hardware module can detect and handle possible errors during operation, and to detect and report errors by enabling the check mechanism, injecting errors for testing, and processing errors through logic gates. This process detects and outputs register protection logic error reports through the TSCcomparator self-test module and the injection error test to ensure that there is no problem with the register protection logic itself. At the beginning of use, the register protection logic and TSC comparator self-check module automatically check for errors and report errors. The errors are errors in the original register logic that may be caused by environmental factors.

[0047] For Reg_Prot_A, each register is duplicated, for example, one copy of register A, or algorithms such as parity check and error detection and correction code (EDC) are used to ensure data correctness.

[0048] Register protection is the protection of all registers. Taking register A as an example, during the operation on register A, one aspect is the protection of the register by Reg Prot A (parity / EDC / duplicated can be used) in the figure and the checks contained therein. It also includes the collection of all the results after the check to confirm whether all the check results have errors, which can be done by using OR reduction logic or other logic (such as TSC logic). For example, the results of each register protection check are connected through an OR gate. If one register protection check has an error, an error will be reported after passing through the OR gate.

[0049] For the Error Injection mechanism, the purpose of error injection is to check the protection logic of register protection to ensure that the potential fault coverage requirement of 60% can be met.

[0050] However, the above scheme may cause faults due to environmental influences such as temperature and electromagnetic interference. For example, when the output of the OR reduction (or logic gate) is forced to be pulled low or high due to environmental factors such as electromagnetic interference, the circuit state changes and it may not be detected. Assuming that the system design considers that the OR logic output is 0 as a normal situation, then when environmental factors cause the output to be inappropriately pulled low, the error detection mechanism may not be able to detect a single-point abnormality of a protected register, resulting in the error detection mechanism being unable to detect faults caused by its own environmental factors.

[0051] Based on the above defects, the present application provides a register protection method. Compared with the prior art, by comparing the output value of the register with the output value of the register protection module, a single-bit result can be accurately determined. In addition, due to the use of a full self-check fault comparator, the check signal of each module can be automatically logically compressed according to the level value. In particular, for situations where the output of the logic gate is abnormal due to environmental factors (such as electromagnetic interference, temperature changes, etc.), logical compression processing is performed through the full self-check fault comparator, so as to more comprehensively and accurately determine the 2-bit level combination to detect whether an error occurs in the system, thereby effectively detecting single-point faults and improving the latent fault detection coverage; and the saved compressed logic area is used to implement the full self-check fault comparator, thereby increasing the effective area.

[0052] Among them, the solutions in the embodiments of the present application may include but are not limited to various computer language implementations, such as object-oriented programming language Java and interpreted scripting language JavaScript, etc. The solutions in the embodiments of the present application may also be used for non-programmable special circuits.

[0053] See also Figure 2 , a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 2 As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a register protection method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse.

[0054] See also Figure 3 The following embodiments take the above-mentioned computer device as the execution subject, and apply the register protection method provided in the embodiment of the present application to the above-mentioned computer device to perform instruction processing as an example for specific description. The register protection method provided in the embodiment of the present application includes the following steps 201-204:

[0055] Step 201 : Obtain the output value of each register in the module and the output value of the corresponding register protection module, where the register protection module is obtained by copying the register or constructing it using an error detection algorithm.

[0056] Step 202, compare the output value of the register with the output value of the register protection module to obtain a single-bit result; when the single-bit result is a high level, it indicates that an error has occurred in the register in the module; when the single-bit result is a low level, it indicates that no error has occurred in the register in the module.

[0057] It should be noted that the above modules are modules in the hardware system, and each module includes multiple registers. Error injection can be used to find out whether there is a problem with the register protection logic. For each module, the output value of each register and the output value of the corresponding register protection module are obtained. The register protection module can be obtained by copying the original designed register or by using an error detection algorithm. The error detection algorithm may include: parity / edc / duplicated.

[0058] After obtaining the output value of the register and the output value of the corresponding register protection module, the output value of the register can be compared with the output value of the register protection module to see whether they are equal. A single-bit result is generated based on the result of whether they are equal. The single-bit result can be packaged into a check signal. The check signal can be understood as Figure 4 The check signal can also be understood as the err injection enable in the error injection mechanism. Each bit corresponds to an error injection bit, and the self-check logic uses error injection to determine whether all hardware is normal. It should be noted that the reason why it is called a check signal is that it is the result of comparing the register output result with the register protection logic during normal use; the reason why it is called an err signal in the previous part is that if you want to determine whether there is an error in the register protection logic, you need to use error injection to determine whether the register protection logic can really determine the error, so the output is an err signal.

[0059] The check signal can be used as the input signal of the total self check compare (TSC_compare). When the single comparison result in the check signal is low level 0, it means there is no error; when the single comparison result is high level 1, it means an error has occurred. When an error occurs in the system, such as a single point error, the error bit corresponding to a check signal is pulled high, which will change the input combination of the TSC compare and trigger error detection.

[0060] The check signal is transmitted through a signal line in the hardware circuit to pass control information from one module to another, for example, to a full self-check fault comparator to start checking these registers.

[0061] Step 203, perform logic compression processing on the single-bit result through the full self-check fault comparator to obtain an output result; the output result includes a 2-bit level combination. When the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state.

[0062] It should be noted that the input of the above-mentioned full self-check fault comparator is a check signal, and the output is a 2-bit level combination; the full self-check fault comparator is used to perform logic compression processing according to the level value of the check signal to obtain a 2-bit level combination. The 2-bit level combination can include two level values. When the two level values ​​in the 2-bit level combination are both 0 or both 1, that is, when it is expressed as 00 or 11, it indicates that the protected register or the register protection mechanism is in an abnormal state; when the two level values ​​in the 2-bit level combination include 1 and 0, that is, when it is expressed as 01 or 10, it indicates that the protected register or the register protection mechanism is in a normal state.

[0063] See also Figure 4 As shown, Figure 4 This is a schematic diagram of the error detection and processing logic of the hardware system mentioned in the embodiment of the present application, which includes modules and registers. Module includes Module A and Module B, which are two main modules. Each module contains multiple different registers, wherein Module A contains registers Reg A, Reg B, and register protection modules Reg Prot A and Reg Prot B. Among them, Reg Prot A is the register protection module of Reg A, and Reg Prot B is the register protection module of Reg B, which is used to detect whether an error occurs in the register.

[0064] Each register has multiple modules with different functions, namely gen, reg, chk and err. The input of gen is the input data of the original register design, and the output is the result of the error detection algorithm or the same result after copying the original design; reg is a module of the original register design, with the input as input data and the output as the processed result; the input of check is the input of gen and the output of reg, and then the relationship between the two is used to confirm whether there is a random hardware failure problem in the original design or register protection logic. If so, an error is reported, otherwise no error is reported.

[0065] It also includes some logic signals of the original register, which may include: edc check_enable signal, edc_error_injection signal and ena nxt signal. Among them, edc_check_enable and edc_error_injection are signals related to error detection and injection, and ena nxt signal is used to control the operation of the register. There are multiple concatenate operations in the figure, which are used to splice multiple signals together to form a data structure or signal stream with a larger data bit width. Among them, the error_injection signal is used to artificially inject errors in order to test the effectiveness of the error handling mechanism.

[0066] During the error handling and injection process, for each module (including Module A and Module B), the corresponding signal can be output through the error flag port of each register in the multiple registers (including RegA and RegB), and a check signal can be formed through a concatenate operation. Then, the signals of each module are concatenated to obtain a check signal, which is then input into the full self-check fault comparator for logic compression processing to obtain an output result.

[0067] Step 204: Generate a pulse output signal according to the output result; the pulse output signal is used to indicate whether an error occurs in the system.

[0068] After obtaining the output result, the output result can be processed using a pulse generation circuit to form a pulse output signal. The pulse output signal can include an err_pulse (error pulse) signal, indicating a detected error; and can also include a correct pulse signal, indicating that no error is detected.

[0069] It is understandable that, when a machine generally starts working, it first performs a self-check and then starts. Among them, the self-check process is to ensure that there is no problem with the register protection mechanism, and the process is checked in an injection error manner. Then it starts working, and when it starts working, it ensures that there is no problem of random hardware failure, relying on the register protection mechanism. It’s just that this TSC compare is both a register protection mechanism and a mechanism to protect the register protection mechanism. Because it has a self-check function, once the logic of the TSC comparator itself has a problem (random hardware failure), even if the input check signals are all expected, an error will be reported. That is to say, the 2-bit level combination of the final output result is the same level value, so its effective area is large, and the compression logic in this application uses a full self-check fault comparator without the need for injection error detection, thereby saving the area of ​​the injection error logic.

[0070] In the embodiment of the present application, the output value of each register in the module and the output value of the corresponding register protection module are obtained, and the output value of the register is compared with the output value of the register protection module to obtain a single-bit result. When the single-bit result is a high level, it indicates that an error has occurred in the register in the module; when the single-bit result is a low level, it indicates that no error has occurred in the register in the module; the single-bit result is logically compressed by a full self-check fault comparator to obtain an output result; the output result includes a 2-bit level combination, when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state; according to the output result, a pulse output signal is generated; the pulse output signal is used to indicate whether an error has occurred in the system. Compared with the prior art, the technical solution in the present application can determine a single-bit result by comparing the output value of the register with the output value of the register protection module, and because a full self-check fault comparator is used, the single-bit result of each module can be automatically logically compressed according to the level value. In particular, for situations where the output of the logic gate is abnormal due to environmental factors (such as electromagnetic interference, temperature changes, etc.), the full self-check fault comparator is used to perform logical compression processing, so as to more comprehensively and accurately determine the 2-bit level combination to detect whether an error occurs in the system, thereby effectively detecting single-point faults and improving the latent fault detection coverage; and the saved compressed logic area is used to implement the full self-check fault comparator, thereby increasing the effective area.

[0071] In an optional embodiment of the present application, see Figure 5 As shown, the single-bit result is logically compressed by the full self-check fault comparator to obtain the output result, including:

[0072] Step 301: divide a plurality of single-bit results into two parts, and invert one part of the single-bit results to obtain an inverted value.

[0073] Step 302: Perform logical compression processing on the inverted value and the remaining single-bit results to obtain an output result.

[0074] It should be noted that the above-mentioned negated value is the level value obtained by negating some single-bit results, and the output result includes a 2-bit level combination. When the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state. The above-mentioned full self-check fault comparator may include AND logic and OR logic.

[0075] See also Figure 6 As shown, Figure 6 A schematic diagram of the logic principle of a full self-check fault comparator provided in an embodiment of the present application, including a TSC Comparer, which is the core of the entire logic. The input signal may include multiple check signals. Figure 6 In the example, four check signals are included, each of which includes a corresponding single-bit result. Two of the check signals are directly used as the input signals of the TSC Comparer, and the other two check signals are used as the input signals of the TSC Comparer after being inverted. Then, after being processed by the TSC Comparer, multiple self-test values ​​are output, including x0, x1, y0 and y1. Among them, y0 and y1 are the inverted results of the "check" operation.

[0076] Among them, multiple self-test values ​​(x0, x1, y0 and y1) are processed with AND logic to obtain corresponding compressed values. Then the compressed values ​​are processed with OR logic to obtain output results (x0&y1 | x1&y0) and (x0&x1 | y0&y1).

[0077] It can be understood that the above logic is that from the overall logic point of view, as long as one of the first part (x0&y1 | x1&y0) or the second part (x0&x1 | y0&y1) is true, the output is true. It is used to check whether two sets of input data (x0, y0) and (x1, y1) meet specific consistency or error detection conditions. For example, in the error detection circuit of hardware design, these inputs may come from different registers or modules, and this logical operation is used to determine whether there is an error.

[0078] In this embodiment, a full self-check fault comparator is used to generate an output result for detecting faults in the system, and can accurately detect logic gate output errors caused by environmental factors.

[0079] In an optional embodiment of the present application, the negated value and the remaining single-bit results are subjected to logical compression processing to obtain an output result, including the following method steps:

[0080] The two groups of multiple inverted values ​​and remaining single-bit results are subjected to first comparison logic compression processing of full self-detection fault to obtain multiple compressed values;

[0081] The plurality of compressed values ​​are subjected to a second comparison logic compression process of the full self-detection fault to obtain an output result.

[0082] It should be noted that after obtaining multiple inverted values, the multiple inverted values ​​and the remaining single-bit results can be processed through the TSC Comparer, and firstly processed by AND logic to obtain multiple compressed values. The compressed values ​​are processed by OR logic to obtain the output result.

[0083] After obtaining multiple negated values, the multiple negated values ​​and every two of the remaining single-bit results can be combined to obtain a combined value, which may include, for example: 01, 10, 11, 00, etc. When the full self-check fault comparator includes four AND gates, the output compression values ​​are also four.

[0084] For example, as shown in Table 2 below, the full self-check fault comparator includes four AND gates, namely AND gate 0, AND gate 1, AND gate 2, and AND gate 3. After obtaining the inverted value and the remaining single-bit results, every two of them are combined to obtain (x0, y0), (x1, y1), and then processed through four AND gates to obtain the corresponding four compressed values. The compressed values ​​are subjected to OR logic processing to obtain the output result, which is the result of the last column of the table.

[0085] Table 2

[0086]

[0087] In this embodiment, by performing AND logic and OR logic processing on two groups of multiple negated values ​​and remaining single-bit results, the output result can be accurately obtained, so that errors in the system can be detected through specific logical operations, thereby improving the system's fault tolerance and reliability.

[0088] In an optional embodiment of the present application, the inverted value and the remaining single-bit results are subjected to a first comparison logic compression process of the full self-detection fault to obtain multiple compressed values, including the following method steps:

[0089] After combining every two of the inverted value and the remaining single-bit results and performing AND logic processing, a plurality of compressed values ​​are obtained.

[0090] It should be noted that after obtaining multiple compressed values, every two compressed values ​​in the multiple compressed values ​​can be combined to obtain a combined value, such as 01, 10, 11, 00, etc. For example, if the full self-check fault comparator includes two OR gates, the output OR gate value is also two.

[0091] See also Figure 7 As shown, Figure 7A logical operation diagram of a full self-check fault comparator provided in an embodiment of the present application, the full self-check fault comparator may include multiple AND gates and multiple OR gates, for example, four, five AND gates, two or three OR gates, the small box on the right in the figure represents a unit on the left, when there are multiple registers, multiple single-bit results can be output accordingly, when designing the full self-check fault comparator TSC comparator, a similar binary division method can be used to form it, so that the area used is smaller, and this embodiment is not limited to binary division. Take the full self-check fault comparator including four AND gates and two OR gates as an example, the four AND gates are TSC C0, TSC C1, TSC C2, TSC C3 from top to bottom, the two OR gates are TSC C4, TSC C5 from top to bottom, and the result is input to TSC C6.

[0092] It can be understood that when the output result is 11 or 00, it indicates that the protected register or register protection mechanism is in an abnormal state; when the output result is 01 or 10, it indicates that the protected register or register protection mechanism is in a normal state. If a single point error occurs, causing any input to be 00 or 11, then the final output result must be (0, 0) or (1, 1), indicating that the protected register or register protection mechanism is in an abnormal state.

[0093] In this embodiment, multiple compressed values ​​are obtained by combining each two of the multiple inverted values ​​and the remaining single-bit results and performing AND logic processing, and each two of the multiple compressed values ​​are combined and then OR logic processing is performed, so that the output result can be accurately obtained.

[0094] In an optional embodiment of the present application, the above-mentioned generating a pulse output signal according to the output result includes the following method steps:

[0095] When the output result indicates that the protected register or the register protection mechanism is in a normal state, the output result is processed by a pulse generation circuit, and the generated pulse output signal is a normal signal of the system;

[0096] When the output result indicates that the protected register or the register protection mechanism is in an abnormal state, the output result is processed by a pulse generation circuit, and the generated pulse output signal is a system error signal.

[0097] It should be noted that the above-mentioned pulse output signal is used as an efficient error indication signal. When the system detects an error, a pulse output signal is immediately generated, which can quickly notify other parts of the system, such as the error handling module or the monitoring system, so that they can respond in time. Compared with continuous level signals, pulse signals are more immediate and can prevent error signals from occupying system resources for a long time or being misjudged.

[0098] Among them, whether this output is a pulse signal or a level signal can be determined according to actual specific needs. When the actual output is a pulse signal, if a level signal is required, the pulse signal can also be saved using a register. If the actual demand of the system is a pulse signal, a pulse signal is output; if the actual demand of the system is a level signal, a level signal is output.

[0099] Optionally, after generating a pulse output signal, when the generated pulse output signal is an error pulse signal (errpulse), a subsequent error handling mechanism may also be triggered, such as notifying the system that an error has occurred and allowing the system to take corresponding measures, such as reinitializing related modules, switching to a backup circuit, etc.

[0100] For complex hardware systems that include multiple modules, each module can generate a unique pulse output signal to indicate its own error condition. By monitoring and recording these pulse output signals, it is possible to quickly determine which submodule has a problem, facilitating subsequent troubleshooting and repair.

[0101] In an optional embodiment of the present application, the output value of the register is compared with the output value of the register protection module to obtain a single-bit result, including:

[0102] When the output value of the register "passes the comparison" with the output value of the register protection module, a single-bit result is generated as a high level; when the output value of the register "fails the comparison" with the output value of the register protection module, a single-bit result is generated as a low level.

[0103] Among them, if the comparison is passed, its output is actually 1, and 1 represents a high level. However, due to the logic of the wrong injection, when the injection is wrong, that is, when checking whether there is a problem with the logic of the register protection, because of the wrong injection, the comparison fails, and its output is 0, that is, a low level. When the injection is wrong, if the injection is done one by one, then the final TSC output is 00 or 11. Using comparators for logic compression allows parallel injection of all register protections, greatly reducing the number of injection errors. When the final output is sent to the TSC comparator, half are 0 and half are 1.

[0104] The high and low levels of the above-mentioned single-bit result can be pre-agreed and determined according to actual conditions. Both the high level and the low level can indicate whether an error has occurred. When the high level indicates that an error has occurred, the low level can indicate that no error has occurred; when the low level indicates that an error has occurred, the high level indicates that no error has occurred, as long as the other situation where no error has occurred is the opposite result of the situation where an error has occurred.

[0105] It should be noted that the above-mentioned register protection module can be obtained by copying the original register, or it can be constructed using an error detection algorithm, and then the output value of the register is compared with the output value of the register protection module. When the comparison result is that the output value of the register and the output value of the register protection module are the same, a single-bit result of low level 0 is generated; when the comparison result is that the output value of the register and the output value of the register protection module are different, a single-bit result of high level 1 is generated.

[0106] In this embodiment, the error flags of each register are combined and spliced, so that the error conditions of multiple modules or registers can be comprehensively considered, faults in the system can be detected more comprehensively, and scattered error signals can be integrated into a complete error information set to facilitate subsequent error handling logic to analyze and process, thereby improving the system's error detection capability and reliability.

[0107] On the other hand, an embodiment of the present application further provides a register protection system, the register protection system comprising: a plurality of modules and a full self-check fault comparator, each module comprising a plurality of registers, a register protection module, and a comparison module;

[0108] The register protection module is obtained by copying the register or constructing it by using an error detection algorithm; the comparison module is used to compare the output value of the register with the output value of the register protection module to obtain a single-bit result; when the single-bit result is a high level, an error occurs in the register in the characterization module; when the single-bit result is a low level, no error occurs in the register in the characterization module;

[0109] The full self-check fault comparator is used to: perform logic compression processing on all single-bit results to obtain output results; the output results include 2-bit level combinations, and a pulse output signal is generated according to the output results; when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state; the pulse output signal is used to indicate whether an error occurs in the system.

[0110] It should be noted that the above-mentioned multiple modules can be Module A and Module B respectively, each module Module includes multiple registers Registers, Module A includes registers Reg A and Reg B, and also includes register protection modules Reg Prot A and Module B for detecting whether errors occur in the original registers.

[0111] It can be understood that after obtaining the comparison result of the output value of the register and the output value of the register protection module, they can be connected through the concatenate operation to generate a check signal, which includes the corresponding single-bit result, and then the check signal is input into the full self-check fault comparator (such as TSC Comparator) for logical operation processing, so as to make a unified error judgment on the system, thereby obtaining the corresponding level combination value. The level combination value may include 11, 00, 10, 01, etc. When the two level values ​​in the 2-bit level combination are both 0 or both 1, that is, when it is expressed as 00 or 11, it indicates that the protected register or the register protection mechanism is in an abnormal state; when the two level values ​​in the 2-bit level combination include 1 and 0, that is, when it is expressed as 01 or 10, it indicates that the protected register or the register protection mechanism is in a normal state.

[0112] In this embodiment, due to the use of a full self-check fault comparator, the check signal of each module can be automatically subjected to logic compression processing according to the level value. In particular, for the situation where the logic gate output is abnormal due to environmental factors (such as electromagnetic interference, temperature change, etc.), the full self-check fault comparator is used to perform logic compression processing, so as to more comprehensively and accurately determine the 2-bit level combination to detect whether an error occurs in the system, thereby effectively detecting single-point faults and improving the latent fault detection coverage; and part of the area of ​​the existing TSC decode is transferred to the area of ​​the full self-check fault comparator TSC, thereby increasing the effective area.

[0113] In another embodiment of the present application, the full self-check fault comparator is specifically used to: divide a single-bit result into two parts, invert one part of the single-bit result to obtain an inverted value; and perform logical compression processing on the inverted value and the remaining single-bit results to obtain an output result.

[0114] It can be understood that after obtaining the single-bit result, it can be processed into a check signal, and then the input check signal is divided into two parts, one part is inverted and the other part remains unchanged, and then the two parts are logically compressed through a full self-check fault comparator to obtain the output result.

[0115] Exemplarily, taking four check signals and four AND gates and two OR gates included in the full self-check fault comparator as an example, after outputting the inverted value and the remaining single-bit results, every two are combined to obtain four first combination values, and then the four first combination values ​​are respectively subjected to AND logic processing through four AND gates to obtain four compressed values, and then the first two and the last two of the four compressed values ​​are combined to obtain two second combination values, and the two second combination values ​​are subjected to OR logic processing through an OR gate to obtain an output result, and then a pulse output signal is generated according to the output result.

[0116] In this embodiment, by setting up a full self-check fault comparator, it is possible to first perform preliminary level value and processing, and then perform or logic processing on it, so as to detect whether an error occurs in the system, thereby effectively detecting single point faults.

[0117] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0118] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 1 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a register protection method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program or data, and when the processor executes the computer program, any step in the register protection method as described above is implemented.

[0119] In one embodiment, a computer-readable storage medium is provided, on which a computer program or data is stored. When the computer program is executed by a processor, any step in the above register protection method can be implemented.

[0120] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0121] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0122] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0123] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0124] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0125] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A register protection method, characterized in that: The register protection method comprises: Acquire the output value of each register in the module and the output value of the corresponding register protection module, wherein the register protection module is obtained by copying the register or constructing it using an error detection algorithm; Compare the output value of the register with the output value of the register protection module to obtain a single-bit result; when the single-bit result is a high level, it indicates that an error has occurred in the register in the module; when the single-bit result is a low level, it indicates that no error has occurred in the register in the module; The single-bit result is logically compressed by a full self-check fault comparator to obtain an output result; the output result includes a 2-bit level combination, when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state; Generate a pulse output signal according to the output result; the pulse output signal is used to indicate whether an error occurs in the system; The single-bit result is logically compressed by a full self-check fault comparator to obtain an output result, including: Dividing the plurality of single-bit results into two parts, and performing inversion processing on one part of the single-bit results to obtain an inverted value; Performing logic compression processing on the inverted value and the remaining single-bit results to obtain the output result; The inverted value and the remaining single-bit results are logically compressed to obtain the output result, including: Performing a first comparison logic compression process of the full self-check fault on the two groups of the inverted value and the remaining single-bit results to obtain a plurality of compressed values; The plurality of compressed values ​​are subjected to a second comparison logic compression process of full self-detection fault to obtain the output result; The two groups of the inverted value and the remaining single-bit results are subjected to the first comparison logic compression processing of the full self-detection fault to obtain multiple compressed values, including: The inverted value and each two of the remaining single-bit results are combined and logically processed to obtain a plurality of compressed values.

2. The method according to claim 1, characterized in that Generating a pulse output signal according to the output result, including: When the output result indicates that the protected register or the register protection mechanism is in a normal state, the output result is processed by a pulse generating circuit, and the generated pulse output signal is a normal system signal; When the output result indicates that the protected register or the register protection mechanism is in an abnormal state, the output result is processed by a pulse generating circuit, and the generated pulse output signal is a system error signal.

3. The method according to claim 1, characterized in that Comparing the output value of the register with the output value of the register protection module to obtain a single-bit result, including: When the output value of the register and the output value of the register protection module "pass the comparison", a single-bit result is generated as a high level; When the output value of the register fails to pass the comparison with the output value of the register protection module, a single-bit result is generated as a low level.

4. A register protection system, characterized in that: The system comprises: a plurality of modules and a full self-check fault comparator, each module comprising a plurality of registers, a register protection module and a comparison module; The register protection module is obtained by copying the register or constructing it by using an error detection algorithm; the comparison module is used to compare the output value of the register with the output value of the register protection module to obtain a single-bit result; when the single-bit result is a high level, it indicates that an error has occurred in the register in the module; when the single-bit result is a low level, it indicates that no error has occurred in the register in the module; The full self-check fault comparator is used to: perform logic compression processing on the single-bit result to obtain an output result; the output result includes a 2-bit level combination, and a pulse output signal is generated according to the output result; when the level values ​​in the 2-bit level combination are different, it indicates that the protected register or the register protection mechanism is in a normal state; when the level values ​​in the 2-bit level combination are the same, it indicates that the protected register or the register protection mechanism is in an abnormal state; the pulse output signal is used to indicate whether an error occurs in the system; The full self-test fault comparator is specifically used for: Dividing the single-bit result into two parts, and performing inversion processing on one part of the single-bit result to obtain an inverted value; The inverted value and the remaining single-bit results are subjected to logical compression processing to obtain the output result, including: combining each two of the inverted value and the remaining single-bit results and performing AND logical processing to obtain multiple compressed values; The plurality of compressed values ​​are subjected to a second comparison logic compression process of full self-detection fault to obtain the output result.

5. A computer device comprising: A memory and a processor, wherein the memory stores a computer program or data, and wherein the processor implements the steps of the method according to any one of claims 1 to 3 when executing the computer program.

6. A computer hardware and program product, characterized in that The computer hardware and program product include instructions, and when the instructions are executed, the hardware implements the steps of any one of claims 1 to 3.

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