Protection circuit and protection method of protected module, storage medium and electronic equipment
By designing a protection circuit for chip modules, using the control signal bus and test input data for abnormal detection, the problem of module abnormal detection in chips is solved, and effective guarantee of chip reliability is achieved.
Patent Information
- Application Number
- CN202411549486.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-11
AI Technical Summary
How to effectively realize abnormal detection of modules in chips to ensure the reliability of the chips.
A protection circuit of a protected module is designed, including a first detection control module, a generation module and a second detection control module. The current state of the module is determined by determining the current state of the transmission signal based on the control signal bus, testing input data is generated, and the abnormality detection result is determined based on the actual test output data and the expected test output data.
Without affecting the normal operation of the protected module, abnormal detection of the protected module can be effectively realized, improving the reliability of the chip.
Smart Images
Figure CN119415347A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to functional safety technology, and in particular to a protection circuit, a protection method, a storage medium and an electronic device for a protected module. Background Art
[0002] At present, the application of chips is very extensive. In order to ensure the reliability of the chip, it is often necessary to perform abnormality detection on the modules in the chip. How to effectively implement abnormality detection on the modules in the chip is a problem worthy of attention for those skilled in the art. Summary of the invention
[0003] In order to solve the above technical problems, the present disclosure provides a protection circuit, a protection method, a storage medium and an electronic device for a protected module.
[0004] According to one aspect of an embodiment of the present disclosure, a protection circuit of a protected module is provided, including:
[0005] A first detection control module is configured to determine a current state of the protected module based on a transmission signal on a control signal bus between a real control signal source and the protected module;
[0006] A generating module, configured to generate test input data in response to the current state being an idle state;
[0007] The second detection control module is configured to determine an abnormality detection result of the protected module based on actual test output data output by the protected module in response to the test input data and expected test output data corresponding to the test input data.
[0008] According to another aspect of an embodiment of the present disclosure, a method for protecting a protected module is provided, including:
[0009] Determine the current state of the protected module based on the transmission signal on the control signal bus between the real control signal source and the protected module;
[0010] In response to the current state being an idle state, generating test input data;
[0011] Based on actual test output data output by the protected module in response to the test input data and expected test output data corresponding to the test input data, an abnormality detection result of the protected module is determined.
[0012] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the protection method of the protected module.
[0013] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device comprising:
[0014] processor;
[0015] a memory for storing instructions executable by the processor;
[0016] The processor is used to read the executable instructions from the memory and execute the instructions to implement the protection method of the protected module.
[0017] According to another aspect of the embodiments of the present disclosure, a computer program product is provided. When instructions in the computer program product are executed by a processor, the protection method of the protected module is executed.
[0018] Based on the protection circuit, protection method, storage medium, electronic device and program product of the protected module provided by the above embodiments of the present disclosure, the first detection control module can determine the current state of the protected module. When the current state of the protected module is an idle state, the generation module can generate test input data. The second detection control module can obtain the actual test output data output by the protected module for the test input data, and the second detection control module can also determine the expected test output data corresponding to the test input data. It should be noted that if there is no abnormality in the protected module, the expected test output data is usually consistent with the actual test output data. If there is an abnormality in the protected module, the expected test output data is usually inconsistent with the actual test output data. In view of this, it can be referred to the consistency of the expected test output data and the actual test output data to infer whether the protected module is abnormal, thereby obtaining the abnormal detection result of the protected module. It can be seen that, using the protection circuit, the protected module can be detected for abnormality during the intermittent period when the protected module is working normally. In this way, the abnormal detection of the protected module can be effectively realized without affecting the normal operation of the protected module. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 is a system architecture diagram applicable to some exemplary embodiments of the present disclosure.
[0020] Figure 2 It is a protection circuit of a protected module provided by some exemplary embodiments of the present disclosure.
[0021] Figure 3 It is a protection circuit of a protected module provided by some other exemplary embodiments of the present disclosure.
[0022] Figure 4 It is a flowchart of a protection method for a protected module provided by some exemplary embodiments of the present disclosure.
[0023] Figure 5 It is a flowchart of a protection method for a protected module provided by other exemplary embodiments of the present disclosure.
[0024] Figure 6 It is a flowchart of a method for generating signal conflict prompt information provided by some exemplary embodiments of the present disclosure.
[0025] Figure 7 It is a flowchart of a protection method for a protected module provided by some further exemplary embodiments of the present disclosure.
[0026] Figure 8 It is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION
[0027] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.
[0028] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
[0029] Application Overview
[0030] At present, the application of chips is very wide. For example, the chip can be applied to vehicles, in which case the chip can be a smart driving chip.
[0031] In order to ensure the reliability of the chip, it is often necessary to perform abnormal detection on the modules in the chip. For example, the chip may include a data path. In order to ensure the reliability of the chip, abnormal detection may be performed on the modules in the data path. Optionally, the data path may include but is not limited to an image path, a voice path, etc.
[0032] The module in the chip that has the need for abnormality detection can be called a protected module. How to effectively implement abnormality detection of the protected module is a problem worthy of attention for those skilled in the art.
[0033] Exemplary Systems
[0034] like Figure 1 As shown, in the embodiment of the present disclosure, a protection circuit of the protected module 10 can be arranged outside the protected module 10 .
[0035] Optionally, the protected module 10 may be a circuit or device with a storage function. For example, the protected module 10 may be a circuit or device with a storage function in a data path included in a chip. As an example, the protected module 10 may be a static random access memory (SRAM) in the data path. Alternatively, the protected module 10 may be a register group in the data path. In addition, based on the storage function of the protected module 10, the protected module 10 may be used to store image data, voice data, etc. Alternatively, based on the storage function of the protected module 10, the protected module 10 may be used to store computer executable instructions.
[0036] In the embodiment of the present disclosure, the protection circuit can be used to detect abnormalities of the protected module 10 during the intermittent period of normal operation of the protected module 10, for example, to perform permanent abnormality detection on the protected module 10. In this way, the abnormality detection of the protected module 10 can be effectively realized without affecting the normal operation of the protected module 10.
[0037] Example Circuit
[0038] Figure 2 Schematic diagram of the structure of the protection circuit of the protected module 10 provided in some exemplary embodiments of the present disclosure. Figure 3 It is a schematic diagram of the structure of the protection circuit of the protected module 10 provided by other exemplary embodiments of the present disclosure.
[0039] Optionally, the protected module 10 may be a circuit or device with a storage function in a data path included in the chip. Through the protection circuit, the entire storage space or part of the storage space of the protected module 10 may be detected for abnormalities. For ease of understanding, the following description will be given by taking the case where the entire storage space of the protected module 10 is detected for abnormalities through the protection circuit as an example.
[0040] like Figure 2 , Figure 3 As shown, the protection circuit may include:
[0041] The first detection control module 15 is configured to determine the current state of the protected module 10 based on the transmission signal on the control signal bus between the real control signal source and the protected module 10;
[0042] A generating module 20, configured to generate test input data in response to the current state being an idle state;
[0043] The second detection control module 30 is configured to determine the abnormality detection result of the protected module 10 based on the actual test output data output by the protected module 10 in response to the test input data and the expected test output data corresponding to the test input data.
[0044] Optionally, the real control signal source may be a module for providing a real input control signal to the protected module 10. The real control signal source may be located in the chip where the protected module 10 is located, or located outside the chip where the protected module 10 is located. The real input control signal may be a control signal required for the protected module 10 to work properly. The real input control signal may also be referred to as an external input control signal. As an example, the real input control signal may be Figure 3 Signal 1 in.
[0045] Optionally, the first detection control module 15 may be a module for detecting the state of the protected module 10 and having certain control functions. A control signal bus may be provided between the real control signal source and the protected module 10, and the first detection control module 15 may be electrically connected to the control signal bus. In this way, the first detection control module 15 may obtain the transmission signal on the control signal bus, and based on the obtained transmission signal, the current state of the protected module 10 may be determined. The current state of the protected module 10 may include two situations, namely, a working state and an idle state. The current state of the protected module 10 being a working state may be understood as: the protected module 10 currently has a real task to be executed, for example, the protected module 10 needs to execute a real data reading and writing task. The current state of the protected module 10 being an idle state may be understood as: the protected module 10 currently has no real task to be executed. If the current state of the protected module 10 is an idle state, it may be considered that the protected module 10 is currently in an intermittent period of normal operation.
[0046] Optionally, the generating module 20 may be a module for generating data and signals related to abnormality detection. The generating module 20 may be electrically connected to the first detection control module 15. The generating module 20 may also be electrically connected to the protected module 10. If the current state of the protected module 10 is an idle state, the first detection control module 15 may send a trigger signal to the generating module 20 to trigger the generating module 20 to generate test input data. As an example, the trigger signal may be Figure 3Signal 2 in. In addition, the entire storage space of the protected module 10 may include M bits, and the test input data may include input characters corresponding to each of the M bits. Any input character may be "0" or "1". The generation module 20 may transmit the generated test input data to the protected module 10. The test input data may be first written to the protected module 10 and then read from the protected module 10, and the read result may be used as the actual test output data output by the protected module 10 for the test input data. The actual test output data may include actual output characters corresponding to each of the M bits.
[0047] Optionally, the second detection control module 30 can be used to determine whether the protected module 10 has an abnormality, and is a module with certain control functions. The second detection control module 30 can be electrically connected to the protected module 10. In this way, the second detection control module 30 can obtain actual test output data. The second detection control module 30 can also determine the expected test output data corresponding to the test input data. The expected test output data can include the expected output characters corresponding to each of the M bits. If the protected module 10 is a module with a data storage function, the data input and output of the protected module 10 are theoretically consistent, then the expected test output data can be consistent with the test input data. Based on the actual test output data and the expected test output data, the second detection control module 30 can determine the abnormality detection result of the protected module 10. For example, if the actual test output data is consistent with the expected test output data, the abnormality detection result can indicate that the protected module 10 does not have an abnormality. If the actual test output data is inconsistent with the expected test output data, the abnormality detection result can indicate that the protected module 10 has an abnormality. If the abnormality detection result indicates that the protected module 10 has an abnormality, the second detection control module 30 can issue an abnormality alarm.
[0048] In one example, the abnormality detection of the protected module 10 can be implemented based on the memory built-in self-test (MBIST) algorithm. The memory built-in self-test algorithm may include but is not limited to the March C algorithm, the March C+ algorithm, the March C-algorithm, the MATS+ algorithm, etc. Taking the case where the memory built-in self-test algorithm is the March C algorithm as an example, the first round of data reading and writing operations can be performed first. The first round of data reading and writing can refer to: writing 0 to the M bits of the protected module 10 according to the rule of ascending address order, and after completing the write 0 operation, reading the M bits according to the rule of ascending address order. After the first round of data reading and writing operations are completed, the second round of data reading and writing operations can be performed. The second round of data reading and writing operations can refer to: writing 1 to the M bits of the protected module 10 according to the rule of ascending address order, and after completing the write 1 operation, reading the M bits according to the rule of ascending address order. After the second round of data reading and writing operations are completed, the third round of data reading and writing operations can be performed. The third round of data read and write operations may refer to: writing 0 to the M bits of the protected module 10 according to the rule of ascending address order, and after completing the write 0 operation, reading the M bits according to the rule of ascending address order. After the third round of data read and write operations are completed, the fourth round of data read and write operations may be performed. The fourth round of data read and write operations may refer to: writing 0 to the M bits of the protected module 10 according to the rule of descending address order, and after completing the write 0 operation, reading the M bits according to the rule of descending address order. After the fourth round of data read and write operations are completed, the fifth round of data read and write operations may be performed. The fifth round of data read and write operations may refer to: writing 1 to the M bits of the protected module 10 according to the rule of descending address order, and after completing the write 1 operation, reading the M bits according to the rule of descending address order. Several more rounds of data read and write operations may be performed subsequently, which are not listed one by one here. If in the first round of data reading and writing operations, M bits are read and M 0s are obtained in sequence, in the second round of data reading and writing operations, M bits are read and M 1s are obtained in sequence, in the third round of data reading and writing operations, M bits are read and M 0s are obtained in sequence, in the fourth round of data reading and writing operations, M bits are read and M 0s are obtained in sequence, in the fifth round of data reading and writing operations, M bits are read and M 1s are obtained in sequence, ..., it can be determined that the actual test output data is consistent with the expected test output data. Then, the abnormality detection result determined by the second detection control module 30 can indicate that there is no abnormality in the protected module 10.
[0049] In the embodiment of the present disclosure, the first detection control module 15 can determine the current state of the protected module 10. When the current state of the protected module 10 is an idle state, the generation module 20 can generate test input data. The second detection control module 30 can obtain the actual test output data output by the protected module 10 for the test input data, and the second detection control module 30 can also determine the expected test output data corresponding to the test input data. It should be noted that if there is no abnormality in the protected module 10, the expected test output data is usually consistent with the actual test output data. If there is an abnormality in the protected module 10, the expected test output data is usually inconsistent with the actual test output data. In view of this, it is possible to refer to the consistency of the expected test output data and the actual test output data to infer whether there is an abnormality in the protected module 10, thereby obtaining the abnormality detection result of the protected module 10. It can be seen that, by using the protection circuit, the protected module 10 can be detected for abnormality during the intermittent period when the protected module 10 is working normally. In this way, the abnormality detection of the protected module 10 can be effectively realized without affecting the normal operation of the protected module 10.
[0050] In some optional examples, such as Figure 3 As shown, the protection circuit may also include:
[0051] A first multiplexer 40 is configured to conduct a data signal bus between the generating module 20 and the protected module 10 in a first mode;
[0052] The first detection control module 15 is configured to place the first multiplexer 40 in the first mode in response to the current state being the idle state, so that the protected module 10 receives the test input data generated by the generation module 20 .
[0053] Optionally, each multiplexer involved in the embodiments of the present disclosure may also be referred to as a MUX.
[0054] Optionally, the first multiplexer 40 may be configured to include multiple modes. The multiple modes may include a first mode. In the first mode, the first multiplexer 40 may conduct the data signal bus between the generating module 20 and the protected module 10. In the remaining modes except the first mode, the first multiplexer 40 may not conduct the data signal bus between the generating module 20 and the protected module 10. The data signal bus between the generating module 20 and the protected module 10 may include Figure 3 Bus 42 and bus 44 in.
[0055] Optionally, the first detection control module 15 can be electrically connected to the first multiplexer 40. The first multiplexer 40 can be electrically connected to the protected module 10 and the generating module 20, respectively. If the current state of the protected module 10 is an idle state, the first detection control module 15 can place the first multiplexer 40 in the first mode. In this way, the data signal bus between the generating module 20 and the protected module 10 can be turned on, and accordingly, the test input data generated by the generating module 20 can be transmitted to the protected module 10 via the data signal bus, that is, the protected module 10 can receive the test input data, and on this basis, the protected module 10 can output actual test output data for determining the abnormal detection result of the protected module 10. As an example, the test input data can be carried on Figure 3 The signal in 3.
[0056] In an embodiment of the present disclosure, when the current state of the protected module 10 is an idle state, by placing the first multiplexer 40 in a first mode adapted to the idle state, the test input data generated by the generation module 20 can be successfully transmitted to the protected module 10, which is beneficial to utilizing the intermittent period of normal operation of the protected module 10 to realize abnormality detection of the protected module 10.
[0057] In some optional examples, such as Figure 3 As shown, the protection circuit may also include:
[0058] The first multiplexer 40 is configured to conduct the data signal bus between the real data source and the protected module 10 in the second mode;
[0059] The first detection control module 15 is configured to place the first multiplexer 40 in the second mode in response to the current state being the working state, so that the protected module 10 receives the real input data from the real data source.
[0060] Optionally, the real data source may be a module for providing real input data to the protected module 10. The real data source may be located in the chip where the protected module 10 is located, or located outside the chip where the protected module 10 is located. The real input data may be input data required for the normal operation of the protected module 10. The data type of the real input data may include but is not limited to image type, feature map type, weight type, etc. As an example, the real input data may be carried in Figure 3 The signal in 4.
[0061] Optionally, the first multiplexer 40 may be configured to include multiple modes. In addition to the first mode, the multiple modes may also include a second mode. In the second mode, the first multiplexer 40 may conduct the data signal bus between the real data source and the protected module 10. In the remaining modes except the second mode, the first multiplexer 40 may not conduct the data signal bus between the real data source and the protected module 10. The data signal bus between the real data source and the protected module 10 may include Figure 3 Bus 46 and bus 44 are shown.
[0062] If the current state of the protected module 10 is the working state, the first detection control module 15 can put the first multiplexer 40 into the second mode. In this way, the data signal bus between the real data source and the protected module 10 can be connected, and accordingly, the real input data at the real data source can be transmitted to the protected module 10 via the data signal bus, that is, the protected module 10 can receive the real input data. The real input data can be written to the protected module 10 first, and then read from the protected module 10, and the read result can be transmitted to the post-stage module of the protected module 10.
[0063] In an embodiment of the present disclosure, when the current state of the protected module 10 is a working state, by placing the first multiplexer 40 in a second mode adapted to the working state, the real input data at the real data source can be successfully transmitted to the protected module 10, which is beneficial to ensuring the normal operation of the protected module 10.
[0064] In an example, Figure 3 As shown, the first multiplexer 40 may include a first input terminal P1, a second input terminal P2, and an output terminal P3. The first input terminal P1 may be electrically connected to the generating module 20. The second input terminal P2 may be electrically connected to the real data source. The output terminal P3 may be electrically connected to the protected module 10. The first detection control module 15 may generate a signal for performing mode control on the first multiplexer 40, for example Figure 3 If the current state of the protected module 10 is the idle state, the signal 5 can be used to connect the first input terminal P1 with the output terminal P3, at which time, the bus 42 and the bus 44 can be turned on, and the first multiplexer 40 is placed in the first mode. If the current state of the protected module 10 is the working state, the signal 5 can be used to connect the second input terminal P2 with the output terminal P3, at which time, the bus 46 and the bus 44 can be turned on, and the first multiplexer 40 is placed in the second mode. In this way, the first multiplexer 40 can be placed in the corresponding mode efficiently and quickly according to actual needs.
[0065] The above paragraph introduces the principle of mode control for the first multiplexer 40 . The principle of mode control for the remaining multiplexers involved in the embodiments of the present disclosure is similar to this and will not be further introduced below.
[0066] In some optional examples, such as Figure 3 As shown, the protection circuit may also include:
[0067] The second multiplexer 50 is configured to conduct the control signal bus between the generating module 20 and the protected module 10 in the third mode;
[0068] The generating module 20 is configured to generate a test input control signal corresponding to the test input data in response to the current state being an idle state;
[0069] The first detection control module 15 is configured to place the second multiplexer 50 in the third mode in response to the current state being the idle state, so that the protected module 10 receives the test input control signal generated by the generation module 20 .
[0070] Optionally, the second multiplexer 50 may be configured to include multiple modes. The multiple modes may include a third mode. In the third mode, the second multiplexer 50 may conduct the control signal bus between the generating module 20 and the protected module 10. In the remaining modes except the third mode, the second multiplexer 50 may not conduct the control signal bus between the generating module 20 and the protected module 10. The control signal bus between the generating module 20 and the protected module 10 may include Figure 3 Bus 52 and bus 54 in.
[0071] Optionally, the first detection control module 15 can be electrically connected to the second multiplexer 50. The second multiplexer 50 can be electrically connected to the protected module 10 and the generating module 20 respectively. If the current state of the protected module 10 is an idle state, the first detection control module 15 can send a trigger signal to the generating module 20 to trigger the generating module 20 to generate test input data and a test input control signal. The test input control signal can be a control signal that matches the test input data. As an example, the test input control signal can include but is not limited to a control signal for indicating the start of transmitting the test input data, a control signal for indicating whether to use the address ascending rule or the address descending rule, etc. The test input control signal can be, for example, Figure 3 If the current state of the protected module 10 is an idle state, the first detection control module 15 may place the second multiplexer 50 in the third mode. For example, the first detection control module 15 may Figure 3The signal 7 in the second multiplexer 50 is placed in the third mode. In this way, the control signal bus between the generating module 20 and the protected module 10 can be connected, and accordingly, the test input control signal generated by the generating module 20 can be transmitted to the protected module 10 via the control signal bus, that is, the protected module 10 can receive the test input control signal, and the protected module 10 can operate according to the test input control signal, which is conducive to ensuring that the abnormality detection of the protected module 10 is carried out normally.
[0072] In some optional examples, such as Figure 3 As shown, the protection circuit may also include:
[0073] The second multiplexer 50 is configured to conduct the control signal bus between the real control signal source and the protected module 10 in the fourth mode;
[0074] The first detection control module 15 is configured to place the second multiplexer 50 in the fourth mode in response to the current state being the working state, so that the protected module 10 receives the real input control signal from the real control signal source.
[0075] Optionally, the second multiplexer 50 may be configured to include multiple modes. In addition to the third mode, the multiple modes may also include a fourth mode. In the fourth mode, the second multiplexer 50 may conduct the control signal bus between the real control signal source and the protected module 10. In the remaining modes except the fourth mode, the second multiplexer 50 may not conduct the control signal bus between the real control signal source and the protected module 10. The control signal bus between the real control signal source and the protected module 10 may include Figure 3 Bus 56 and bus 54 are shown.
[0076] If the current state of the protected module 10 is the working state, the first detection control module 15 can place the second multiplexer 50 in the fourth mode. For example, the first detection control module 15 can Figure 3 The signal 7 in the second multiplexer 50 is placed in the fourth mode. In this way, the control signal bus between the real control signal source and the protected module 10 can be connected, and accordingly, the real input control signal at the real control signal source can be transmitted to the protected module 10 via the control signal bus, that is, the protected module 10 can receive the real input control signal for the normal operation of the protected module 10.
[0077] In an embodiment of the present disclosure, when the current state of the protected module 10 is the working state, by placing the second multiplexer 40 in the fourth mode adapted to the working state, the real input control signal at the real control signal source can be successfully transmitted to the protected module 10, which is beneficial to ensuring the normal operation of the protected module 10.
[0078] In some optional examples, such as Figure 3 As shown, the protection circuit may also include:
[0079] The third multiplexer 60 is configured to conduct the control signal bus between the second detection control module 30 and the subsequent module of the protected module 10 in the fifth mode;
[0080] The second detection control module 30 is configured to generate an output shielding control signal. In response to the current state being an idle state, the third multiplexer 60 is placed in the fifth mode so that the subsequent module receives the output shielding control signal generated by the second detection control module 30. The subsequent module responds to the output shielding control signal to shield the actual test output data output by the protected module 10 for the test input data.
[0081] Optionally, the third multiplexer 60 may be configured to include multiple modes. The multiple modes may include a fifth mode. In the fifth mode, the third multiplexer 60 may conduct the control signal bus between the second detection control module 30 and the subsequent module of the protected module 10. In the remaining modes except the fifth mode, the third multiplexer 60 may not conduct the control signal bus between the second detection control module 30 and the subsequent module.
[0082] The control signal bus between the second detection control module 30 and the subsequent modules may include a bus 62 and a bus 64 .
[0083] Optionally, the second detection control module 30 may be electrically connected to the third multiplexer 60. The third multiplexer 60 may also be electrically connected to the protected module 10 and the subsequent module. If the current state of the protected module 10 is an idle state, the second detection control module 30 may generate an output shielding control signal, such as Figure 3 The output shielding control signal can be used to indicate shielding the actual test output data of the protected module 10. If the current state of the protected module 10 is an idle state, the second detection control module 30 can also put the third multiplexer 60 into the fifth mode. For example, the second detection control module 30 can Figure 3 The signal 9 in the third multiplexer 60 is placed in the fifth mode. In this way, the control signal bus between the second detection control module 30 and the subsequent module can be connected, and accordingly, the output shielding control signal generated by the second detection control module 30 can be transmitted to the subsequent module via the control signal bus. In response to receiving the output shielding control signal, the subsequent module can shield the actual test output data, for example, the subsequent module may not receive the actual test output data.
[0084] In an embodiment of the present disclosure, when the current state of the protected module 10 is an idle state, by placing the third multiplexer 60 in a fifth mode adapted to the idle state, the subsequent module can shield the actual test output data, thereby helping to avoid the resources and power consumption required to receive the actual test output data.
[0085] In some optional examples, such as Figure 3 As shown, the protection circuit may also include:
[0086] The third multiplexer 60 is configured to conduct the control signal bus between the protected module 10 and the subsequent module of the protected module 10 in the sixth mode;
[0087] The second detection control module 30 is configured to place the third multiplexer 60 in the sixth mode in response to the current state being the working state, so that the subsequent module receives the real output control signal output by the protected module 10 .
[0088] Optionally, the third multiplexer 60 may be configured to include multiple modes. In addition to the fifth mode, the multiple modes may include a sixth mode. In the sixth mode, the third multiplexer 60 may conduct the control signal bus between the protected module 10 and the subsequent module of the protected module 10. In the remaining modes except the sixth mode, the third multiplexer 60 may not conduct the control signal bus between the protected module 10 and the subsequent module. The control signal bus between the protected module 10 and the subsequent module may include a bus 64 and a bus 66.
[0089] If the current state of the protected mode 10 is the working state, the second detection control module 30 can place the third multiplexer 60 in the sixth mode. For example, the second detection control module 30 can Figure 3 The signal 9 in the third multiplexer 60 is placed in the sixth mode. In this way, the control signal bus between the protected module 10 and the subsequent module can be connected, and accordingly, the real output control signal output by the protected module 10 based on the real input control signal can be normally transmitted to the subsequent module. In response to receiving the real output control signal, the subsequent module can normally receive the data output by the protected module 10 in response to the real input data.
[0090] In an embodiment of the present disclosure, when the current state of the protected mode 10 is the working state, by placing the second multiplexer 50 in the sixth mode adapted to the working state, the data output by the protected module 10 for the real input data can be successfully transmitted to the subsequent module of the protected module 10, which is beneficial to ensure the normal operation of the chip where the subsequent module is located.
[0091] In some optional examples, such as Figure 3 As shown, the protection circuit may also include:
[0092] The conflict detection module 70 is configured to obtain a transmission signal on a control signal bus between a real control signal source and the protected module 10;
[0093] A first detection control module 15 is configured to generate a test characterization signal in response to the current state being an idle state;
[0094] The conflict detection module 70 is configured to determine the receiving state of the test characterization signal, determine the first existence attribute of the real input control signal generated by the real control signal source in the transmission signal, and generate signal conflict prompt information in response to the reception state indicating that the test characterization information is received and the first existence attribute indicating that the real input control signal exists in the transmission signal.
[0095] Optionally, the conflict detection module 70 may be a module for detecting whether there is a timing conflict between normal operation and abnormality detection of the protected module 10 .
[0096] Optionally, there may be a control signal bus between the real control signal source and the protected module 10, and the conflict detection module 70 may be electrically connected to the control signal bus. In this way, the conflict detection module 70 may obtain the transmission signal on the control signal bus. In addition, the first detection control module 15 may be electrically connected to the conflict detection module 70. If the current state of the protected module 10 is an idle state, the first detection control module 15 may generate a test characterization signal, and the test characterization signal may indicate that an abnormality detection is currently being performed on the protected module 10. As an example, the test characterization signal may be Figure 3 The first detection control module 15 may transmit the test characterization signal to the conflict detection module 70. If the current state of the protected module 10 is the working state, the first detection control module 15 may not generate and transmit the test characterization signal. The conflict detection module 70 may determine the reception state of the test characterization signal, and the reception state may indicate whether the test characterization signal is received. The conflict detection module 70 may also determine a first existence attribute of the real input control signal generated by the real control signal source in the transmission signal. The first existence attribute may indicate whether there is a real input control signal in the transmission signal. As an example, the real input control signal may be Figure 3 Signal 1 in.
[0097] If the receiving state indicates that the test characterization information is received, and the first existence attribute indicates that the real input control signal exists in the transmission signal, both of these conditions are met, it can be determined that the normal operation and abnormality detection of the protected module 10 are being performed synchronously, that is, there is a timing conflict between the normal operation and abnormality detection of the protected module 10, then the conflict detection module 70 can generate signal conflict prompt information. The conflict detection module 70 can report the signal conflict prompt information to the upper-layer abnormality collection module.
[0098] If the receiving state indicates that the test characterization information is received, and the first existence attribute indicates that there is a real input control signal in the transmission signal, at least one of the two conditions is not met, it can be determined that the normal operation and abnormality detection of the protected module 10 are not carried out synchronously, then the conflict detection module 70 may not generate signal conflict prompt information.
[0099] In the embodiments of the present disclosure, through the collaborative work of the conflict detection module 70 and the first detection control module 15, etc., it is possible to effectively identify the situation where there is a timing conflict between the normal operation and abnormal detection of the protected module 10, and give a prompt for this situation, which is beneficial to avoid the adverse effects caused by the timing conflict between the normal operation and abnormal detection of the protection module 10, for example, it is beneficial to avoid the timing conflict from affecting the correctness of the data received by the subsequent module.
[0100] In some optional examples, the number of protected modules 10 may be multiple;
[0101] A first detection control module 15 is configured to determine a fault detection order of a plurality of protected modules 10;
[0102] The generating module 20 is configured to generate test input data in response to the current state being an idle state, including:
[0103] The generating module 20 is configured to generate test input data corresponding to each of the plurality of protected modules 10 in response to the current state being an idle state;
[0104] The second detection control module 30 is configured to determine the abnormality detection result of the protected module 10 based on the actual test output data output by the protected module 10 for the test input data and the expected test output data corresponding to the test input data, including:
[0105] The second detection control module 30 is configured to determine the abnormal detection results corresponding to the plurality of protected modules 10 respectively according to the fault detection order based on the actual test output data corresponding to the plurality of protected modules 10 respectively and the expected test output data corresponding to the plurality of protected modules 10 respectively;
[0106] The sum of the abnormality detection durations corresponding to the plurality of protected modules 10 and the preset fault tolerance time interval satisfy a preset numerical relationship.
[0107] It should be noted that the functional safety-related standards specify the maximum tolerance time interval for detecting anomalies and reporting them, which can be used as a preset fault tolerance time interval. The preset fault tolerance time interval can also be called FTTI. As an example, the functional safety-related standard can be ISO26262, and the preset fault tolerance time interval can be 132 milliseconds.
[0108] Optionally, the number of the protected modules 10 may be two, three, four or more than four, which are not listed one by one here.
[0109] Taking the case where the number of protection modules 10 is N as an example, if the current states of the N protected modules 10 are all idle states, the generation module 20 can generate test input data corresponding to each of the N protected modules 10. The test input data corresponding to any two protected modules 10 can be the same or different.
[0110] The first detection control module 15 can determine the fault detection order of the N protected modules 10. The fault detection order of the N protected modules 10 can be randomly determined to ensure that the abnormality detection of the N protected modules 10 is performed in different time periods.
[0111] The second detection control module 30 can determine the abnormal detection results corresponding to each of the N protected modules 10 based on the actual test output data corresponding to each of the N protected modules 10 and the expected test output data corresponding to each of the N protected modules 10 in accordance with the fault detection order. For example, the N protected modules 10 are represented as module 1, module 2, ..., module N, then the module 1 can be firstly detected for abnormality to obtain the abnormal detection result corresponding to the module 1, and then the module 2 can be detected for abnormality to obtain the abnormal detection result corresponding to the module 2, ..., finally the module N can be detected for abnormality to obtain the abnormal detection result corresponding to the module N, and it is ensured that the sum of the abnormal detection durations corresponding to each of the modules 1, module 2, ..., and module 6 satisfies the preset numerical relationship with the preset fault tolerance time interval. The sum and the preset fault tolerance time interval satisfying the preset numerical relationship may mean that the difference between the preset fault tolerance time interval and the sum is less than the preset time difference. Alternatively, the sum and the preset fault tolerance time interval satisfying the preset numerical relationship may mean that the ratio of the sum to the preset fault tolerance time interval is less than or equal to the preset ratio. As an example, the preset time difference may be 20 milliseconds, 25 millimeters, etc., and the preset ratio may be 0.6, 0.7, etc., which are not listed here one by one.
[0112] In the embodiment of the present disclosure, the same set of protection circuits can be reused by N protected modules 10. During the intermittent period when the protected modules 10 are working normally, the same set of protection circuits can be reused in time division to realize abnormality detection of the N protected modules 10, which is conducive to reducing the hardware cost of abnormality detection.
[0113] In some optional examples, the first detection control module 15 is configured to determine the current state of the protected module 10 based on the transmission signal on the control signal bus between the real control signal source and the protected module 10, including:
[0114] The first detection control module 15 is configured to determine a second existence attribute of a data frame end signal in a transmission signal on a control signal bus between a real control signal source and the protected module 10, and determine a current state of the protected module 10 based on the second existence attribute.
[0115] Optionally, there may be a control signal bus between the real control signal source and the protected module 10, and the first detection control module 15 may be electrically connected to the control signal bus. In this way, the first detection control module 15 can obtain the transmission signal on the control signal bus. The first detection control module 15 can determine the second existence attribute of the data frame end signal in the transmission signal. The second existence attribute can indicate whether there is a data frame end signal in the transmission signal. If the second existence attribute indicates that there is a data frame end signal in the transmission signal, this indicates that the normal operation of the protected module 10 has ended, then it can be determined that the current state of the protected module 10 is an idle state. If the second existence attribute indicates that there is no data frame end signal in the transmission signal, this indicates that the protected module 10 is working normally, then it can be determined that the current state of the protected module 10 is a working state.
[0116] In the embodiment of the present disclosure, the current state of the protected module 10 can be determined efficiently and quickly by referring to the second existence attribute of the data frame end signal in the transmission signal on the control signal bus between the real control signal source and the protected module 10.
[0117] In some optional examples, such as Figure 3 As shown, the protection circuit may include a first detection control module 15 , a generation module 20 , a second detection control module 30 , a first multiplexer 40 , a second multiplexer 50 , a third multiplexer 60 and a conflict detection module 70 .
[0118] The first detection control module 15 can obtain the transmission signal on the control signal bus between the real control signal source and the protected module 10, and can determine the current state of the protected module 10 based on whether there is a data frame end signal in the obtained transmission signal. For example, if it is detected that there is a data frame end signal in the obtained transmission signal, it can be determined that the current state of the protected module 10 is an idle state, and then the abnormality detection of the protected module 10 can be started. After the abnormality detection is completed, the next data frame end signal can be waited for, so that the next abnormality detection of the protected module 10 can be started when the next data frame end signal arrives.
[0119] The first detection control module 15 can be used to generate signal 5, signal 7, signal 2, signal 10 and signal 11. Signal 2 can be a signal for triggering the generation module 20 to generate test input data and test input control signals. Signal 5 can be a signal for performing mode control on the first multiplexer 40. Signal 7 can be a signal for performing mode control on the second multiplexer 50. If the current state of the protected module 10 is an idle state, signal 5 can be used to place the first multiplexer 40 in the first mode, and signal 7 can be used to place the second multiplexer 50 in the third mode, so that the test input data can be transmitted to the protected module 10 via the first multiplexer 40, and the test input control signal can be transmitted to the protected module 10 via the second multiplexer 50. If the current state of the protected module 10 is the working state, signal 5 can be used to place the first multiplexer 40 in the second mode, and signal 7 can be used to place the second multiplexer 50 in the fourth mode, so that the real input data can be transmitted to the protected module 10 via the first multiplexer 40, and the real input control signal can be transmitted to the protected module 10 via the second multiplexer 50. Signal 10 can be a signal used to indicate that an abnormality detection is currently being performed on the protected module 10, that is, the test characterization signal mentioned above. Signal 11 can be a signal used to indicate the consistency of the actual test output data and the expected test output data of the protected module 10.
[0120] If the conflict detection module 70 receives both signal 1 and signal 10, this indicates that a timing conflict occurs between the normal operation and abnormality detection of the protected module 10, and the conflict detection module 70 may generate signal conflict prompt information.
[0121] The second detection control module 30 can be used to receive signal 11, signal 12, and signal 13, and also to generate signal 8 and signal 9. Signal 12 can be a signal carrying data output by the protected module 10. Signal 13 is a control signal output by the protected module 10. Signal 8 is an output shielding control signal. Signal 9 is a signal for mode control of the third multiplexer 60. If the current state of the protected module 10 is an idle state, signal 9 can be used to place the third multiplexer 60 in the fifth mode, so that the actual test output data will not be transmitted to the subsequent module of the protected module 10. If the current state of the protected module 10 is a working state, signal 9 can be used to place the third multiplexer 60 in the sixth mode so that the data output by the protected module 10 for the real input data can be transmitted to the subsequent module of the protected module 10.
[0122] It should be noted that if N protected modules 10 use time-division multiplexing protection circuits, a corresponding first multiplexer 40 and a second multiplexer 50 need to be provided for each of the N protected modules 10 .
[0123] In summary, by adopting the embodiments of the present disclosure, it is possible to effectively implement abnormality detection of the protected module 10 with a relatively simple circuit structure and a relatively small cost, which is beneficial to ensuring the reliability of the chip.
[0124] Exemplary Methods
[0125] Figure 4 It is a flowchart of a protection method for a protected module provided by some exemplary embodiments of the present disclosure. Figure 4 The illustrated method may include step 410 , step 420 , and step 430 .
[0126] Step 410: Determine the current state of the protected module based on the transmission signal on the control signal bus between the real control signal source and the protected module.
[0127] Step 420: In response to the current state being an idle state, generate test input data.
[0128] Step 430 , determining an abnormality detection result of the protected module based on actual test output data output by the protected module in response to the test input data and expected test output data corresponding to the test input data.
[0129] In some optional examples, the method provided by the embodiments of the present disclosure may also include: Figure 5 At least one of the following: step 510, step 520, step 530.
[0130] Step 510: Based on the current state, a mode control is performed on a first multiplexer in a protection circuit of the protected module.
[0131] In some optional implementations of the present disclosure, step 510 may include:
[0132] In response to the current state being the idle state, the first multiplexer is placed in the first mode. The first multiplexer in the first mode turns on the data signal bus between the generation module and the protected module in the protection circuit so that the protected module receives the test input data generated by the generation module.
[0133] In some other optional implementations of the present disclosure, step 510 may include:
[0134] In response to the current state being the working state, the first multiplexer is placed in the second mode. The first multiplexer in the second mode conducts the data signal bus between the real data source and the protected module, so that the protected module receives the real input data from the real data source.
[0135] Step 520: Based on the current state, the mode of the second multiplexer in the protection circuit of the protected module is controlled.
[0136] In some optional implementations of the present disclosure, step 520 may include:
[0137] In response to the current state being the idle state, the second multiplexer is placed in the third mode. The second multiplexer in the third mode turns on the control signal bus between the generation module and the protected module in the protection circuit so that the protected module receives the test input control signal generated by the generation module.
[0138] In some other optional implementations of the present disclosure, step 520 may include:
[0139] In response to the current state being the working state, the second multiplexer is placed in the fourth mode. The second multiplexer in the fourth mode conducts the control signal bus between the real control signal source and the protected module, so that the protected module receives the real input control signal from the real control signal source.
[0140] Step 530: Based on the current state, the mode of the third multiplexer in the protection circuit of the protected module is controlled.
[0141] In some optional implementations of the present disclosure, step 530 may include:
[0142] In response to the current state being an idle state, the third multiplexer is placed in a fifth mode. The third multiplexer in the fifth mode turns on the control signal bus between the second detection control module in the protection circuit and the subsequent module of the protected module, so that the subsequent module receives the output shielding control signal generated by the second detection control module. The subsequent module responds to the output shielding control signal to shield the actual test output data output by the protected module for the test input data.
[0143] In some other optional implementations of the present disclosure, step 530 may include:
[0144] In response to the current state being the working state, the third multiplexer is placed in the sixth mode. The third multiplexer in the sixth mode turns on the control signal bus between the protected module and the subsequent module of the protected module, so that the subsequent module receives the real output control signal output by the protected module.
[0145] In some optional examples, such as Figure 6 As shown, the method provided by the embodiment of the present disclosure may include step 610, step 620 and step 630.
[0146] Step 610: Acquire the transmission signal on the control signal bus between the real control signal source and the protected module.
[0147] Step 620: In response to the current state being an idle state, generate a test characterization signal.
[0148] Step 630, determine the receiving state of the conflict detection module in the protection circuit for the test characterization signal, determine the first existence attribute of the real input control signal generated by the real control signal source in the transmission signal, and generate signal conflict prompt information in response to the reception state indicating that the test characterization information is received and the first existence attribute indicating that the real input control signal exists in the transmission signal.
[0149] In some optional examples, such as Figure 7 As shown, the method provided by the embodiment of the present disclosure may include step 710, step 720 and step 730. Optionally, step 720 may be used as an optional implementation of step 420 of the present disclosure. In addition, step 730 may be used as an optional implementation of step 430 of the present disclosure.
[0150] Step 710: determine the fault detection order of multiple protected modules.
[0151] Step 720: In response to the current state being an idle state, generate test input data corresponding to each of the plurality of protected modules.
[0152] Step 730 , based on the actual test output data corresponding to each of the multiple protected modules and the expected test output data corresponding to each of the multiple protected modules, determine the abnormality detection results corresponding to each of the multiple protected modules in accordance with the fault detection order.
[0153] In some optional examples, step 410 may include:
[0154] A second existence attribute of a data frame end signal in a transmission signal on a control signal bus between a real control signal source and a protected module is determined, and a current state of the protected module is determined based on the second existence attribute.
[0155] In the method disclosed in the present invention, various optional embodiments, optional implementation methods and optional examples disclosed in the above exemplary circuit part can be flexibly selected and combined as needed to achieve corresponding functions and effects, and the present invention does not list them one by one.
[0156] The beneficial technical effects corresponding to the exemplary embodiment of the method can be found in the corresponding beneficial technical effects of the above exemplary circuit part, which will not be repeated here.
[0157] Exemplary Electronic Devices
[0158] Figure 8 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. The electronic device 800 includes one or more processors 810 and a memory 820 .
[0159] The processor 810 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 800 to perform desired functions.
[0160] The memory 820 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 810 may execute one or more computer program instructions to implement the methods of the various embodiments of the present disclosure described above and / or other desired functions.
[0161] In one example, the electronic device 800 may further include: an input device 830 and an output device 840 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).
[0162] The input device 830 may also include, for example, a keyboard, a mouse, etc.
[0163] The output device 840 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output device, etc.
[0164] Of course, to simplify, Figure 8 Only some of the components related to the present disclosure in the electronic device 800 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 800 may also include any other appropriate components.
[0165] Exemplary computer program products and computer-readable storage media
[0166] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.
[0167] The computer program product may be written in any combination of one or more programming languages to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0168] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.
[0169] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.
[0170] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present disclosure. The specific details disclosed above are only for the purpose of illustration and ease of understanding, not limitation. The above details do not limit the present disclosure to being implemented by adopting the above specific details.
[0171] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.
Claims
1. A protection circuit for a protected module, comprising: A first detection control module is configured to determine a current state of the protected module based on a transmission signal on a control signal bus between a real control signal source and the protected module; A generating module, configured to generate test input data in response to the current state being an idle state; The second detection control module is configured to determine an abnormality detection result of the protected module based on actual test output data output by the protected module in response to the test input data and expected test output data corresponding to the test input data.
2. The protection circuit according to claim 1, further comprising: A first multiplexer, configured to conduct a data signal bus between the generating module and the protected module in a first mode; The first detection control module is configured to place the first multiplexer in the first mode in response to the current state being an idle state, so that the protected module receives the test input data generated by the generation module.
3. The protection circuit according to claim 1, further comprising: a first multiplexer, configured to conduct a data signal bus between a real data source and the protected module in a second mode; The first detection control module is configured to place the first multiplexer in the second mode in response to the current state being the working state, so that the protected module receives the real input data from the real data source.
4. The protection circuit according to claim 1, further comprising: a second multiplexer, configured to conduct a control signal bus between the generating module and the protected module in a third mode; The generating module is configured to generate a test input control signal corresponding to the test input data in response to the current state being an idle state; The first detection control module is configured to place the second multiplexer in the third mode in response to the current state being an idle state, so that the protected module receives the test input control signal generated by the generation module.
5. The protection circuit according to claim 1, further comprising: a second multiplexer, configured to conduct a control signal bus between the real control signal source and the protected module in a fourth mode; The first detection control module is configured to place the second multiplexer in the fourth mode in response to the current state being the working state, so that the protected module receives the real input control signal from the real control signal source.
6. The protection circuit according to claim 1, further comprising: a third multiplexer, configured to conduct a control signal bus between the second detection control module and a subsequent module of the protected module in a fifth mode; The second detection control module is configured to generate an output shielding control signal, and in response to the current state being an idle state, places the third multiplexer in the fifth mode so that the subsequent module receives the output shielding control signal generated by the second detection control module, and the subsequent module shields the actual test output data output by the protected module for the test input data in response to the output shielding control signal.
7. The protection circuit according to claim 1, further comprising: a third multiplexer, configured to conduct a control signal bus between the protected module and a subsequent module of the protected module in a sixth mode; The second detection control module is configured to place the third multiplexer in the sixth mode in response to the current state being the working state, so that the subsequent module receives the real output control signal output by the protected module.
8. The protection circuit according to any one of claims 1 to 7, further comprising: a conflict detection module, configured to obtain a transmission signal on a control signal bus between the real control signal source and the protected module; The first detection control module is configured to generate a test characterization signal in response to the current state being an idle state; The conflict detection module is configured to determine the reception status of the test characterization signal, determine the first existence attribute of the real input control signal generated by the real control signal source in the transmission signal, and generate signal conflict prompt information in response to the reception status indicating that the test characterization information is received and the first existence attribute indicating that the real input control signal exists in the transmission signal.
9. The protection circuit according to any one of claims 1 to 7, wherein: The first detection control module is configured to determine a fault detection order of the plurality of protected modules; The generating module is configured to generate test input data in response to the current state being an idle state, including: The generating module is configured to generate the test input data corresponding to each of the plurality of protected modules in response to the current state being an idle state; The second detection control module is configured to determine an abnormality detection result of the protected module based on actual test output data output by the protected module in response to the test input data and expected test output data corresponding to the test input data, including: The second detection control module is configured to determine the abnormal detection results corresponding to each of the plurality of protected modules according to the fault detection order based on the actual test output data corresponding to each of the plurality of protected modules and the expected test output data corresponding to each of the plurality of protected modules; The sum of the abnormality detection durations corresponding to each of the plurality of protected modules and the preset fault tolerance time interval satisfy a preset numerical relationship.
10. The protection circuit according to any one of claims 1 to 7, wherein: The first detection control module is configured to determine the current state of the protected module based on the transmission signal on the control signal bus between the real control signal source and the protected module, including: The first detection control module is configured to determine a second existence attribute of a data frame end signal in a transmission signal on a control signal bus between the real control signal source and the protected module, and to determine a current state of the protected module based on the second existence attribute.
11. A method for protecting a protected module, comprising: Determine the current state of the protected module based on the transmission signal on the control signal bus between the real control signal source and the protected module; In response to the current state being an idle state, generating test input data; Based on actual test output data output by the protected module in response to the test input data and expected test output data corresponding to the test input data, an abnormality detection result of the protected module is determined.
12. The protection method according to claim 11, further comprising at least one of the following: Based on the current state, performing mode control on a first multiplexer in a protection circuit of the protected module; Based on the current state, performing mode control on a second multiplexer in the protection circuit of the protected module; Based on the current state, a mode control is performed on a third multiplexer in the protection circuit of the protected module.
13. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the protection method for a protected module according to any one of claims 11 to 12.
14. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the protection method of the protected module described in any one of claims 11-12.