High-speed data sending system
By using FPGA devices and buffer technology in embedded real-time systems, the data loss problem of embedded real-time systems when sending large amounts of data at high speed is solved, and reliable data transmission and sequential recovery are achieved.
Patent Information
- Application Number
- CN202411499821.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-02-11
AI Technical Summary
When the embedded real-time system sends a large amount of data at a high rate through interfaces such as Can, 485, 1553B, 422, etc., the external device does not receive it in time or is stuttered, resulting in data loss.
The FPGA device is combined with an embedded real-time system to establish two buffers A and B, subcontract data and add sequence numbers and write to the buffers. The FPGA device reads the data and sends it to the external device through the forwarding communication interface.
It effectively solves the problem of data loss when sending high-speed and large-scale data, ensuring that external devices can correctly receive and restore data sequence.
Smart Images
Figure CN119415453A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of communication technology, and in particular to a high-speed data sending system for an embedded real-time system. Background Art
[0002] When the embedded real-time system CAN, 485, 1553B, 422 and other interfaces send hundreds of MByte or several GByte of large amounts of data to external devices at high-speed intervals at the same time, after the external device receives the data, due to untimely processing or external device freezes, a certain packet of data may not be received, which can easily cause data loss and affect the entire data interaction function.
[0003] It can be seen that in many application scenarios, embedded real-time systems cannot send large amounts of data of hundreds of M Bytes or several G Bytes at high-speed intervals at the same time through interfaces such as CAN, 485, 1553B, 422, etc. Even if large amounts of data can be sent at high speed intervals at the same time, the receiving device cannot guarantee that all the large amounts of data sent by the embedded real-time system will be received, resulting in data loss. Summary of the invention
[0004] In view of the above problems, the present invention provides a high-speed data transmission system for overcoming the above problems or at least partially solving the above problems. The system solves the problem of data loss or data packet loss when interfaces such as CAN, 485, 1553B, 422, etc. simultaneously transmit a large amount of data of several hundred MByte or several GByte at high-speed intervals in an embedded real-time system.
[0005] The present invention provides the following scheme:
[0006] A high-rate data transmission system, comprising:
[0007] The invention comprises an embedded real-time system and an FPGA device, wherein the embedded real-time system is connected to the FPGA device via a communication bus; the embedded real-time system comprises a plurality of original communication interfaces of different types for realizing communication connection with an external device, wherein the original communication interface comprises at least one or more of a Can interface, a 485 interface, a 1553B interface, and a 422 interface; the FPGA device is provided with a plurality of forwarding communication interfaces for connecting with an external device, and the plurality of forwarding communication interfaces correspond one to one with the plurality of original communication interfaces;
[0008] The FPGA device is used to perform the following operations:
[0009] A corresponding first buffer area and a corresponding second buffer area are created for each type of the original communication interface, so that the embedded real-time system performs packet processing on the data to be sent by each type of the original communication interface, and writes the data into the corresponding first buffer area and the second buffer area after adding sequence numbers;
[0010] After determining that data needs to be sent through a target communication interface, the target communication interface includes one or more of the forwarding communication interfaces; the data in the first cache area and the second cache area corresponding to the target communication interface are sent to the external device through the target communication interface, so that the external device restores the data order according to the sequence number after receiving the data.
[0011] Preferably: after determining that the sending is completed, the data sending status is changed to sending completion, and the sending status is sent to the embedded real-time system, so that the embedded real-time system can write the subsequent subpackaging and the required data into the first buffer area and the second buffer area in the idle state.
[0012] Preferably: the sending is determined to be completed after the current packet data sent by the external device is received.
[0013] Preferably, the storage capacity units of the first cache area and the second cache area are both kilobytes.
[0014] Preferably, the communication bus includes any one of a PCIE bus and an AXI bus.
[0015] Preferably: after detecting that the length of data written by the embedded real-time operating system and the completion of the writing status are completed, it is determined that the data needs to be sent through the target communication interface.
[0016] Preferably: after receiving the data read request sent through the target communication interface, it is determined that data needs to be sent through the target communication interface.
[0017] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0018] The embodiment of the present application provides a high-speed data transmission system, which is combined with an embedded real-time system and an FPGA device to establish A and B buffers on the FPGA device. The system first writes data into the A and B buffers and writes a flag. The FPGA device reads the data in the buffer and sends it to the external device, and interacts with the real-time system to complete the transmission of high-speed and large data. It solves the problem that when interfaces such as CAN, 485, 1553B, and 422 simultaneously send a large amount of data of several hundred MByte or several GByte at high-speed intervals, when the external device receives the data, due to untimely processing or external device jamming, a certain packet of data cannot be received, resulting in the phenomenon of lost data packets.
[0019] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0021] Figure 1 The present invention provides a data processing flow chart of a high-speed data transmission system. DETAILED DESCRIPTION
[0022] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.
[0023] See also Figure 1 , is a high-speed data transmission system provided by an embodiment of the present invention, such as Figure 1 As shown, the system may include:
[0024] An embedded real-time system and an FPGA device, wherein the embedded real-time system is connected to the FPGA device via a communication bus; the embedded real-time system comprises a plurality of original communication interfaces of different types for realizing communication connection with an external device, wherein the original communication interface comprises at least one or more of a Can interface, a 485 interface, a 1553B interface, and a 422 interface; the FPGA device is provided with a plurality of forwarding communication interfaces for connecting with an external device, and the plurality of forwarding communication interfaces correspond one to one with the plurality of original communication interfaces;
[0025] The FPGA device is used to perform the following operations:
[0026] A corresponding first buffer area and a corresponding second buffer area are created for each type of the original communication interface, so that the embedded real-time system performs packet processing on the data to be sent by each type of the original communication interface, and writes the data into the corresponding first buffer area and the second buffer area after adding sequence numbers;
[0027] After determining that data needs to be sent through a target communication interface, the target communication interface includes one or more of the forwarding communication interfaces; the data in the first cache area and the second cache area corresponding to the target communication interface are sent to the external device through the target communication interface, so that the external device restores the data order according to the sequence number after receiving the data.
[0028] Furthermore, in order to achieve continuous data transmission, the embodiment of the present application can also provide a method of changing the data transmission status to transmission completion after determining that the transmission is completed, and sending the transmission status to the embedded real-time system, so that the embedded real-time system can write the subsequent subpackaging and the required data into the first cache area and the second cache area in the idle state.
[0029] Further, the sending is determined to be completed after the current packet data sent by the external device is received.
[0030] In order to ensure that the cache capacities of the two cache areas are large enough to cope with the transmission requirements of large amounts of data, the embodiment of the present application may provide that the storage capacity units of the first cache area and the second cache area are both kilobytes.
[0031] The system provided in the embodiment of the present application adds an FPGA device for caching and forwarding data compared to a common embedded real-time operating system. In order to achieve communication between the two, the embodiment of the present application can provide that the communication bus includes any one of a PCIE bus and an AXI bus.
[0032] In order to facilitate the determination of the timing of sending data to an external device, the embodiment of the present application can also provide a method of determining the need to send data through a target communication interface after detecting the length of data written by the embedded real-time operating system and the completion of the writing status. In this way, the FPGA device can send the cached data to the external device after determining that a data packet has been sent.
[0033] In another implementation, the embodiment of the present application can provide that after receiving a data read request sent through the target communication interface, it is determined that data needs to be sent through the target communication interface. In this way, selective data transmission can be achieved, and data will only be read and sent when the external device needs it.
[0034] After the system provided in the embodiment of the present application is connected to the FPGA device through an embedded real-time system, two buffers A and B corresponding to each type of interface are established in the FPGA device. The system first writes the data that needs to be sent through the original communication interface into the corresponding A and B buffers, and writes a flag. The FPGA device reads the data in the buffer, sends it to the external device through the configured forwarding communication interface, and interacts with the real-time system to complete the transmission of high-speed and large data. It solves the problem that when the interfaces such as the Can interface, 485 interface, 1553B interface, and 422 interface simultaneously send a large amount of data of several hundred MByte or several GByte at high-speed intervals, when the external device receives the data, due to untimely processing or the external device jamming, a certain packet of data cannot be received, resulting in the phenomenon of lost data packets.
[0035] The system provided by this application is introduced in detail below.
[0036] In order to solve the problem that when an embedded real-time system CAN, 485, 1553B, 422 and other interfaces simultaneously send a large amount of data of several hundred M Bytes or several G Bytes at a high-speed rate interval, when an external device receives data, a certain packet of data cannot be received or a data packet is lost due to untimely processing or external device freeze. The embodiment of the present application provides a high-speed data transmission system.
[0037] When implementing:
[0038] 1. Create two FIFO spaces for data cache A / B.
[0039] In an embedded real-time operating system, when the original communication interfaces such as the Can interface, 485 interface, 1553B interface, and 422 interface need to send a large amount of data of several hundred M Bytes or several G Bytes, through the configured FPGA device, each interface corresponds to establishing two m Kbyte FIFO data spaces A and B on the FPGA device for the embedded real-time operating system to implement data packet processing, increase the sequence number of the data after packet processing, and write the data crosswise into the corresponding FIFO space.
[0040] After the data is cached in the two cache areas established by the FPGA device, the subsequent outbound data is sent through the forwarding interface of the FPGA device to communicate with external devices. Therefore, when selecting the FPGA device to be configured, the FPGA device needs to have the same type and number of forwarding communication interfaces as the embedded real-time operating system, and each forwarding communication interface is arranged one-to-one with each original communication interface.
[0041] For example, if the original communication interface includes 1 Can interface, 2 485 interfaces, 1 1553B interface, and 1 422 interface, the FPGA device needs to set up 1 Can forwarding communication interface, 2 485 forwarding communication interfaces, 1 1553B forwarding communication interface, and 1 422 forwarding communication interface. Then, two corresponding buffers are established for 1 Can interface, four corresponding buffers are established for 2 485 interfaces, two corresponding buffers are established for 1 1553B interface, and two corresponding buffers are established for 1 422 interface.
[0042] 2. The real-time operating system writes data to the FIFO space.
[0043] Under the embedded real-time operating system, the data to be sent by the corresponding interfaces such as Can, 485, 1553B, 422 are packetized, and the packet sequence number is added to the data packet header. The packetized and numbered data is written into the A / B FIFO space of the corresponding interface established in the first step through the PCIE or AXI bus, and the corresponding register is changed to notify the FPGA device of the completion of the written data length and write status.
[0044] 3. FPGA device obtains and sends data.
[0045] When the FPGA device detects that the data length and writing status written by the embedded real-time operating system are complete, the FPGA device can obtain data from the FIFO of the corresponding Can, 485, 1553B, 422 and other interfaces, and send data to the external device. The external device receives the data and restores the data sequence according to the sequence number, notifying the FPGA device that the current packet data reception is complete. The FPGA device changes the data sending status to sending completion, and the real-time operating system monitors the FPGA data sending status in real time.
[0046] 4. Repeat detection, writing data, and sending data.
[0047] When the embedded real-time system detects that the state is the data transmission completion state, the embedded real-time operating system immediately writes the subsequent sub-packet number and the data with the increased sequence number into the FIFO A / B area of the corresponding Can, 485, 1553B, 422 and other interfaces. The FPGA device detects that the data length and writing status written by the embedded real-time operating system are completed, and the FPGA device obtains data from the FIFO of the corresponding Can, 485, 1553B, 422 and other interfaces, and sends data to the external device. The external device receives the data and restores the data order according to the sequence number, notifying the FPGA device that the current packet data reception is completed, and the FPGA device changes the data transmission state to transmission completion. The real-time operating system monitors the data transmission state of the FPGFPGA device in real time, and repeats this process until all data packets are sent.
[0048] In summary, the high-speed data transmission system provided by the present application is a combination of an embedded real-time system and an FPGA device. A and B buffers are established on the FPGA device. The system first writes data into the A and B buffers and writes a flag. The FPGA device reads the data in the buffer and sends it to the external device, and interacts with the real-time system to complete the transmission of high-speed and large data. This solves the problem that when interfaces such as CAN, 485, 1553B, and 422 simultaneously send a large amount of data of several hundred M Bytes or several G Bytes at high-speed intervals, when the external device receives the data, due to untimely processing or external device jamming, a certain packet of data cannot be received, resulting in the phenomenon of lost data packets.
[0049] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0050] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.
[0051] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.
[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A high-rate data transmission system, characterized in that: The invention comprises an embedded real-time system and an FPGA device, wherein the embedded real-time system is connected to the FPGA device via a communication bus; the embedded real-time system comprises a plurality of original communication interfaces of different types for realizing communication connection with external devices, wherein the original communication interfaces at least comprise one or more of a Can interface, a 485 interface, a 1553B interface, and a 422 interface; the FPGA device is provided with a plurality of forwarding communication interfaces for connecting with external devices, and the plurality of forwarding communication interfaces correspond one to one with the plurality of original communication interfaces; The FPGA device is used to perform the following operations: A corresponding first buffer area and a corresponding second buffer area are created for each type of the original communication interface, so that the embedded real-time system performs packet processing on the data to be sent by each type of the original communication interface, and writes the data into the corresponding first buffer area and the second buffer area after adding sequence numbers; After determining that data needs to be sent through a target communication interface, the target communication interface includes one or more of the forwarding communication interfaces; the data in the first cache area and the second cache area corresponding to the target communication interface are sent to the external device through the target communication interface, so that the external device restores the data order according to the sequence number after receiving the data.
2. The high-rate data transmission system according to claim 1, characterized in that: After determining that the sending is completed, the data sending status is changed to sending completion, and the sending status is sent to the embedded real-time system so that the embedded real-time system can write the subsequent subpackaging and the required data into the first buffer area and the second buffer area in the idle state.
3. The high-rate data transmission system according to claim 2, characterized in that: The sending is determined to be completed after the current packet data sent by the external device is received.
4. The high-rate data transmission system according to claim 1, characterized in that: The storage capacity units of each of the first cache area and the second cache area are kilobytes.
5. The high-rate data transmission system according to claim 1, characterized in that: The communication bus includes any one of a PCIE bus and an AXI bus.
6. The high-rate data transmission system according to claim 1, characterized in that: After detecting that the length of the data written by the embedded real-time operating system and the completion of the writing status are completed, it is determined that the data needs to be sent through the target communication interface.
7. The high-rate data transmission system according to claim 1, characterized in that: After receiving the data read request sent through the target communication interface, it is determined that data needs to be sent through the target communication interface.