FLASH controller compatible with SPI bus and LPC bus

Abstract

According to the FLASH controller compatible with the SPI bus and the LPC bus, the SPI main controller module is selected by default to work, and the SPI main controller module judges whether the ID number of FLASH equipment is received within the set time so as to judge whether the default SPI main controller module is matched with the FLASH equipment in type or not; and the arbiter module determines whether to start the pin multiplexing module to cancel the pin control right of the SPI main controller module so as to be compatible with an LPC protocol and an SPI protocol.

Description

Technical Field

[0001] The invention relates to the technical field of communications, and in particular to a FLASH controller compatible with SPI and LPC buses. Background Art

[0002] LPC technology is a product of history. Because of its low pin count, flexibility, support for multiple device connections, it is also suitable for certain microcontrollers based on the LPC interface. It has the characteristics of high speed, high energy efficiency and high performance. The LPC interface supports larger memory space access and has strong scalability. It also has certain compatibility with other bus standards such as the PCI bus, making system upgrades and expansions easier, so its ecosystem remains stable.

[0003] Nowadays, people are more likely to use SPI FLASH as a storage chip. SPI flash has the following characteristics:

[0004] (1) Serial communication interface: SPI flash communicates with the host controller through a serial interface, usually using the SPI protocol for data transmission.

[0005] (2) Low power consumption: SPI flash usually has low power consumption characteristics and is suitable for use in mobile and portable devices, which can extend the battery life of the device.

[0006] (3) Random access speed: Compared with traditional parallel flash, SPI flash has a faster random access speed and can read and write data faster.

[0007] (4) Small size: SPI flash is usually small in size and takes up less space when integrated on a circuit board, making it suitable for use in space-constrained devices.

[0008] (5) Easy to integrate: SPI flash communicates with the host controller through a simple serial interface, making it easy to integrate into various devices.

[0009] (6) Low cost: Since SPI flash uses a serial communication interface, its production cost is relatively low and suitable for large-scale applications. Summary of the invention

[0010] The technical problem to be solved by the technical solution of the present invention is: the mainstream FLASH on the market is mainly divided into SPI, NOR and NAND, but some old BMC chips still support the server to access their storage through the LPC interface, and the BMC chip as the main device to access other FLASH storage devices. This requires a module that is compatible with the LPC protocol and the SPI protocol, and can access both LPC FLASH and SPI FLASH.

[0011] In order to solve the above technical problems, the technical solution of the present invention provides a FLASH controller compatible with SPI and LPC buses, including an arbitrator module, an LPC master controller module, an SPI master controller module and a pin multiplexing module;

[0012] The arbiter module selects the SPI master controller module by default to work, configures the pin multiplexing module to SPI mode, and enables the SPI master controller module;

[0013] The SPI master controller module sends an operation to read the ID number to the FLASH device. If the FLASH device is of SPI type, the ID number of the FLASH device is returned.

[0014] If the FLASH device is of LPC type, the ID number of the FLASH device will not be returned in response;

[0015] If the SPI master controller module receives the ID number of the FLASH device within the specified time, it notifies the arbiter module that the FLASH device type connected at this time is the SPI type, and the SPI master controller will continue to use the pins to initiate read, write, and erase operations on the FLASH device;

[0016] If the SPI master controller module does not receive the ID number of the FLASH device within the specified time, it sends a FLASH device type mismatch to the arbitrator module, notifying the arbitrator module that the FLASH device type connected at this time is the LPC type;

[0017] After the arbiter module receives that the FLASH device type is the LPC type, it terminates the SPI master controller module's right to use the pin, starts the LPC master controller module, and configures the pin multiplexing module to switch from the SPI mode to the LPC mode;

[0018] The LPC main controller module initiates MEMORY read and write operations on the FLASH device.

[0019] Preferably, the pins configured by the LPC main controller module include an LCLK pin, an LFRAME pin, an LRESET pin and a LAD[3:0] pin.

[0020] Preferably, the pins configured by the SPI master controller module include a CLK pin, a CS pin, a DQ3[1:0] pin, a WP (DQ2) pin and a HOLD (DQ3) pin.

[0021] Preferably, in the pin multiplexing module, the LCLK pin is multiplexed with the CLK pin, the LFRAME pin is multiplexed with the CS pin, the LAD[3:0] pin is multiplexed with the DQ[3:0] pin, and the LRESET pin is multiplexed with DQ3.

[0022] The technical solution of the present invention proposes a FLASH controller compatible with SPI and LPC buses. The SPI main controller module is selected by default to work. The SPI main controller module determines whether the ID number of the FLASH device is received within a specified time to determine whether the default SPI main controller module matches the FLASH device type. Then the arbitrator module decides whether to enable the pin multiplexing module to cancel the pin control right of the SPI main controller module to be compatible with the LPC protocol and the SPI protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a FLASH controller compatible with SPI and LPC buses provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0025] The relevant terms and concepts in this invention are as follows:

[0026] Low pin count Bus (LPC): Introduced by Intel into PC products in 1998. Compared with the ISA bus, LPC has fewer pins and faster speed.

[0027] Serial Peripheral Interface (SPI): Proposed by Motorola, it is a high-speed, full-duplex, synchronous communication bus. It is generally used for communication between MCU and peripheral devices, and is widely used in the communication between peripheral chips or modules such as Flash, analog-to-digital converters, and communication modules and MCU.

[0028] The embodiment of the present invention provides a FLASH controller compatible with SPI and LPC buses, including: an arbitrator module, an LPC master controller module, an SPI master controller module and a pin multiplexing module. The LPC bus includes: an LCLK pin, an LFRAME pin, an LRESET pin and a LAD[3:0] pin. The SPI chip includes a CLK pin, a CS pin, a DQ3[1:0] pin, a WP (DQ2) pin and a HOLD (DQ3) pin, wherein HOLD and WP are also used for data transmission in a four-wire mode.

[0029] Among them, the LPC master controller module is used to initiate read and write access operations to the LPC FLASH; the SPI master controller module is used to initiate read and write access and erase operations to the SPI FLASH; and the arbiter module is used to determine the type of FLASH device connected. Depending on the type of connection, it chooses whether to use the LPC master controller or the SPI master controller for access, and enables different pin multiplexing functions. The pin multiplexing module multiplexes the two groups of pins and selects which type of pin to use according to the control of the arbiter. The LCLK pin of the LPC bus is multiplexed with the CLK pin of the SPI bus, the LFRAME pin is multiplexed with the CS pin, the LAD[3:0] pin is multiplexed with the DQ[3:0] pin, and the LRESET pin is multiplexed with DQ3.

[0030] The working process of the embodiment of the present invention is as follows:

[0031] Step S1: The arbiter selects the SPI master controller by default to work, configures the pin multiplexing to SPI mode, and the SPI master controller first sends an operation of reading the ID number to the FLASH device;

[0032] Step S2: If the FLASH device is of SPI type, the device ID number is returned; if the FLASH device is of LPC type, the operation is not responded to;

[0033] Step S3: If the SPI master controller receives the ID number within the specified time, it notifies the arbitrator that the FLASH type connected at this time is the SPI type, and the SPI master controller will continue to use the interface pins;

[0034] Step S4: The SPI master controller normally initiates erase, program, read, etc. operations on the FLASH;

[0035] Step S5: If the SPI master controller does not receive the ID number within the specified time, it will send a type mismatch status message to the arbitrator, notifying the arbitrator that the FLASH type connected at this time is the LPC type;

[0036] Step S6: After receiving the type mismatch status information, the arbitrator terminates the SPI master controller's right to use the pin, enables the LPC master controller, and switches the pin multiplexing to the LPC mode;

[0037] Step S7: The LPC main controller initiates MEMORY read and write operations on FLASH normally.

[0038] The embodiment of the present invention can fill the demand for LPC FLASH storage in the market, and can meet both SPI type FLASH storage and LPC type FLASH storage.

Claims

1. A FLASH controller compatible with SPI and LPC buses, characterized in that: include: Arbiter module, LPC master controller module, SPI master controller module and pin multiplexing module; The arbiter module selects the SPI master controller module by default to work, configures the pin multiplexing module to SPI mode, and enables the SPI master controller module; The SPI master controller module sends an operation to read the ID number to the FLASH device. If the FLASH device is of SPI type, the ID number of the FLASH device is returned. If the FLASH device is of LPC type, the ID number of the FLASH device will not be returned in response; If the SPI master controller module receives the ID number of the FLASH device within the specified time, it notifies the arbiter module that the FLASH device type connected at this time is the SPI type, and the SPI master controller will continue to use the pins to initiate read, write, and erase operations on the FLASH device; If the SPI master controller module does not receive the ID number of the FLASH device within the specified time, it sends a FLASH device type mismatch to the arbitrator module, notifying the arbitrator module that the FLASH device type connected at this time is the LPC type; After the arbiter module receives that the FLASH device type is the LPC type, it terminates the SPI master controller module's right to use the pin, starts the LPC master controller module, and configures the pin multiplexing module to switch from the SPI mode to the LPC mode; The LPC main controller module initiates MEMORY read and write operations on the FLASH device.

2. A FLASH controller compatible with SPI and LPC buses as claimed in claim 1, characterized in that: The pins configured by the LPC main controller module include LCLK pin, LFRAME pin, LRESET pin and LAD[3:0] pin.

3. A FLASH controller compatible with SPI and LPC buses as claimed in claim 2, characterized in that: The pins configured by the SPI master controller module include a CLK pin, a CS pin, a DQ3[1:0] pin, a WP (DQ2) pin and a HOLD (DQ3) pin.

4. A FLASH controller compatible with SPI and LPC buses as claimed in claim 3, characterized in that: In the pin multiplexing module, the LCLK pin is multiplexed with the CLK pin, the LFRAME pin is multiplexed with the CS pin, the LAD[3:0] pin is multiplexed with the DQ[3:0] pin, and the LRESET pin is multiplexed with DQ3.

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