Data receiving system, data receiving method and core particle

Abstract

The invention provides a data receiving system, a data receiving method and a core grain, and the data receiving system comprises a synchronous serial-to-parallel receiving module which converts received serial data into parallel data under a serial clock, and the parallel data are stored in a parallel data packet mode; the asynchronous-to-synchronous processing module is used for receiving the parallel data and converting the parallel data from a serial clock domain to a local clock domain; wherein the asynchronous-to-synchronous processing module detects the number of clock cycles needed during conversion of each parallel data packet, and when the number of clock cycles needed during conversion of the parallel data packets is not within a preset range, it is judged that the process of converting the serial data into the parallel data is abnormal, and asynchronous reset is carried out. According to the data receiving system, the data receiving method and the core particle provided by the invention, the reliability of the received data is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of data processing, and in particular relates to a data receiving system, a data receiving method and a core particle. Background Art

[0002] Chiplets are modular chips made with different processes that are integrated together using packaging technology like Lego blocks, improving performance while achieving low cost and high yield. How to interconnect chiplets at high speed is the key to the implementation of chiplet technology. The established Universal Chiplet Interconnect Express (UCIe) protocol covers the physical layer, communication electrical signal standards, number of channels, contact spacing, and so on. When the input interface of the chiplet receives data, it is necessary to convert the input parallel data into serial data and complete cross-time domain processing. However, when an abnormality occurs in the serial line, it is impossible to correct and recover in time, affecting data transmission. Summary of the invention

[0003] The object of the present invention is to provide a data receiving system, a data receiving method and a core particle, which can solve the problem that when an abnormality occurs in a serial line, it is impossible to correct errors and recover in time.

[0004] To achieve the above object, the present invention provides a data receiving system, which at least comprises:

[0005] A synchronous serial conversion and receiving module converts the received serial data into parallel data under the serial clock, and the parallel data is stored in the form of parallel data packets; and

[0006] An asynchronous-to-synchronous processing module receives the parallel data and converts the parallel data from a serial clock domain to a local clock domain;

[0007] Among them, the asynchronous to synchronous processing module detects the number of clock cycles required for the conversion of each parallel data packet. When the number of clock cycles required for the conversion of the parallel data packet is not within a preset range, it is determined that an abnormality occurs in the process of converting the serial data to the parallel data, and an asynchronous reset is performed.

[0008] In one embodiment of the present invention, the synchronous serial conversion and receiving module samples the serial data under a serial clock signal to form the parallel data packet.

[0009] In one embodiment of the present invention, the synchronous serial-to-parallel receiving module generates a serial-to-parallel start signal, which becomes a high level when the synchronous serial-to-parallel receiving module receives the serial data and becomes a low level when the serial data is not received.

[0010] In one embodiment of the present invention, the asynchronous-to-synchronous processing module includes a data clock domain conversion unit, which generates a clock domain conversion start signal, and the clock domain conversion start signal is a level signal obtained by the serial-to-parallel start signal after clock domain conversion.

[0011] In an embodiment of the present invention, the data clock domain conversion unit generates a data packet transfer end signal after detecting a falling edge of the clock domain conversion start signal.

[0012] In one embodiment of the present invention, the data clock domain conversion unit generates a data clock domain conversion valid signal within the next clock of generating the data packet transfer end signal if the clock domain conversion start signal is at a low level;

[0013] And while generating the data clock domain conversion valid signal, the data value of the parallel data packet signal is sampled and assigned to the local parallel data packet signal to complete the cross-time domain processing of the parallel data.

[0014] In an embodiment of the present invention, the asynchronous-to-synchronous processing module includes a receiving error detection unit, which generates a data packet counting signal, and the data packet counting signal counts the clock cycle of the clock domain conversion start signal.

[0015] In one embodiment of the present invention, when the number of clock cycles required for the parallel data packet conversion is not within a preset range, the reception error detection unit generates an error signal and reports the error signal to the physical layer to complete the error cause analysis.

[0016] In one embodiment of the present invention, after the receiving error detection unit generates the error signal, the receiving error detection unit generates an asynchronous clear signal and sends the asynchronous clear signal to the synchronous serial conversion and receiving module to asynchronously reset the signal in the serial clock domain.

[0017] In one embodiment of the present invention, the lower limit value of the preset range is equal to the length of the parallel data packet minus the first preset value, and the range of the first preset value is 2 to 3, and the upper limit value of the preset range is equal to the length of the parallel data packet plus the second preset value, and the range of the second preset value is 3 to 5.

[0018] The present invention also provides a data receiving method, which at least comprises the following steps:

[0019] Using a synchronous serial conversion and receiving module to convert the received serial data into parallel data under a serial clock, and the parallel data is stored in the form of parallel data packets; and

[0020] Using an asynchronous to synchronous processing module to receive the parallel data, and converting the parallel data from a serial clock domain to a local clock domain;

[0021] Among them, the asynchronous to synchronous processing module detects the number of clock cycles required for the conversion of each parallel data packet. When the number of clock cycles required for the conversion of the parallel data packet is not within a preset range, it is determined that an abnormality occurs in the process of converting the serial data to the parallel data, and an asynchronous reset is performed.

[0022] The present invention further provides a core particle, wherein any one of the data receiving systems described above is arranged in a receiving interface of the core particle.

[0023] In summary, the data receiving system, data receiving method and core particle provided by the present invention can complete the serial-to-parallel processing of the data receiving end when the core particle receives data, complete the cross-clock domain processing of parallel data, detect errors and report them, and can recover from errors in time to increase the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0025] Figure 1 It is a schematic diagram of a universal core particle interconnection structure according to an embodiment of the present application.

[0026] Figure 2 It is a structural block diagram of a data receiving system in one embodiment of the present application.

[0027] Figure 3 It is a timing diagram of some signals of the synchronous serial conversion and receiving module when receiving data in one embodiment of the present application.

[0028] Figure 4 This is a timing diagram of signals when a data receiving system receives data in a normal state in an embodiment of the present application.

[0029] Figure 5 This is a timing diagram of signals when a data receiving system receives data after the serial clock signal has several more cycles in an embodiment of the present application.

[0030] Figure 6 This is a timing diagram of signals when a data receiving system receives data after the serial clock signal loses several cycles in one embodiment of the present application.

[0031] Description of labels:

[0032] 101, synchronous serial conversion and receiving module; 102, asynchronous to synchronous processing module; 1021, data clock domain conversion unit; 1022, receiving error detection unit; 103, post-stage data analysis and processing module. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0036] Chiplets are modular chips made with different processes that are integrated together using packaging technology like Lego blocks, improving performance while achieving low cost and high yield. How to connect chiplets at high speed is the key to the implementation of chiplet technology. The established Universal Chiplet Interconnect Express (UCIe) protocol is a standard based on a layered protocol. Each protocol layer has its own functions, which is convenient for general use and reuse, and clarifies the functions that each layer must support.

[0037] See also Figure 1As shown, in one embodiment of the present invention, high-frequency data interaction is required between core particles Die0 and Die1 to complete related calculations. Since the amount of calculation of high-performance computing is large, the amount of data transmission between the two core particles is huge. In order to prevent data transmission from becoming a bottleneck for high-performance computing, the high-speed data interface between the two core particles needs to meet the two requirements of high bandwidth and low latency. In order to meet the demand for high bandwidth between core particles, the high-speed data interface needs to transmit data at a higher rate on the interconnection line between the core particles. In order to meet the transmission requirements of management messages between core particles without reducing the high-bandwidth performance of the high-speed data interface to transmit data, the management messages between core particles need to be transmitted through the sideband interconnection line. Therefore, after the receiving interface RX of the high-speed data interface receives the serial sideband data, the received sideband data needs to be deserialized from the serial data to parallel data before being transmitted to the system side. And because the serial clock and the system working clock are usually not synchronized, it is necessary to perform cross-clock domain processing on the data path to synchronize the data from the serial clock domain to the local clock domain.

[0038] See also Figure 1 and Figure 2 As shown, the present invention provides a data receiving system, which is arranged in the receiving interface RX of the core particle to complete the deserialization and cross-time domain processing of the data. Specifically, the data receiving system includes a synchronous serial conversion and receiving module 101 and an asynchronous to synchronous processing module 102. Among them, the synchronous serial conversion and receiving module 101 converts the received serial data into parallel data under the serial clock, and stores the parallel data in the form of parallel data packets, and the length of each parallel data packet is within a preset range. The asynchronous to synchronous processing module 102 is electrically connected to the output end of the synchronous serial conversion and receiving module 101, receives the parallel data output by the synchronous serial conversion and receiving module 101, and converts the parallel data from the serial clock domain to the local clock domain. At the same time, the asynchronous to synchronous processing module 102 also detects the number of clock cycles required for the conversion of each parallel data packet. When the number of clock cycles required for the conversion of the parallel data packet is not within the preset range, it is determined that the process of converting the serial data into the parallel data is abnormal, and an asynchronous reset is performed. The data receiving system provided in the present application detects anomalies that occur during the process of converting serial data to parallel data while completing data serial to parallel conversion and clock domain conversion, and reports and recovers in a timely manner after the anomaly occurs, thereby increasing the reliability of the system.

[0039] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the application takes the sideband data transmitted between the core particles as an example to realize the conversion of serial data to parallel data, and the cross-time domain processing of the sideband data packet. According to the general core particle interconnection technology protocol, the sideband data transmitted between the two core particles is transmitted in the form of a sideband data packet. Each sideband data packet is a complete sequence of 64-bit data. And after completing the transmission of a sideband data packet, before the next sideband data packet comes, there will be 32 or more idle cycles between the two sideband data packets, and the sideband data and sideband clock will not be transmitted, so there will be an idle window between the serial to parallel conversion to do error checking of the clock domain conversion.

[0040] It should be noted that the present invention can also realize serial-to-parallel conversion and cross-time domain processing of other data transmitted in the form of data packets between cores, and is not limited to sideband data.

[0041] For details, please refer to Figure 2 and Figure 3 As shown, the synchronous serial conversion and receiving module 101 samples the serial data sb_ser_data under the serial clock signal sb_ser_clk. The serial clock signal sb_ser_clk is synchronized with the serial data sb_ser_data, and one bit of serial data sb_ser_data is sampled at the falling edge of each serial clock signal sb_ser_clk to form a parallel data packet signal sb_packet. For sideband data, 64 bits of parallel data packet signals sb_packet constitute a parallel data packet, and one sideband data information includes one or two parallel data packets.

[0042] See also Figure 2 and Figure 4As shown, in one embodiment of the present invention, the synchronous serial-to-parallel receiving module 101 is input with a serial clock signal sb_ser_clk and serial data sb_ser_data, and the synchronous serial-to-parallel receiving module 101 generates a serial-to-parallel start signal sb_s2p_start, a serial-to-parallel count signal sb_s2p_cnt, and a parallel data packet signal sb_packet. The serial clock signal sb_ser_clk input by the synchronous serial-to-parallel receiving module 101 is synchronized with the serial data sb_ser_data, and the serial data sb_ser_data completes the conversion of the serial data sb_ser_data into parallel data under the serial clock domain, that is, forms a parallel data packet signal sb_packet. The serial-to-parallel count signal sb_s2p_cnt counts when each serial data sb_ser_data flips, and when the count value of the serial-to-parallel count signal sb_s2p_cnt reaches 63, it returns to 0, indicating that a 64-bit data has been received, forming a parallel data packet. At this time, the serial-to-parallel count signal sb_s2p_cnt is re-counted. When the synchronous serial-to-receive module 101 receives the serial data sb_ser_data, the serial-to-parallel start signal sb_s2p_start becomes high, indicating that the current serial data is being received. When the last bit of the serial data sb_ser_data is received and the synchronous serial-to-receive module 101 does not receive the serial data sb_ser_data, the serial-to-parallel start signal sb_s2p_start becomes low. When waiting for the next serial clock signal sb_ser_clk and serial data sb_ser_data to arrive, the reception of the next parallel data packet is completed again.

[0043] See also Figure 2 and Figure 4 As shown, in one embodiment of the present invention, the asynchronous to synchronous processing module 102 includes a data clock domain conversion unit 1021 and a receiving error detection unit 1022. The data clock domain conversion unit 1021 receives the parallel data output by the synchronous serial conversion and receiving module 101, and converts the parallel data from the serial clock domain to the local clock domain. The receiving error detection unit 1022 detects the length of each data packet of the parallel data. When the length of the data packet exceeds the preset length, it is determined that the process of converting the serial data to the parallel data is abnormal, and an asynchronous reset is performed.

[0044] See also Figure 2 and Figure 4 As shown, it should be noted that the parallel data output by the serial conversion and receiving module 101 is the parallel data packet signal sb_packet, and each data packet of the parallel data is a parallel data packet.

[0045] See also Figure 2and Figure 4 As shown, in one embodiment of the present invention, the synchronous serial conversion and receiving module 101 is input into the data clock domain conversion unit 1021 to generate a serial-to-parallel start signal sb_s2p_start and a parallel data packet signal sb_packet, as well as a local clock signal sbclk generated by the core grain. The data clock domain conversion unit 1021 generates a clock domain conversion start signal rx_start, a data packet transfer end signal rx_end, a data clock domain conversion valid signal rx_valid, and a local parallel data packet signal rx_packet. Among them, the local clock signal sbclk and the serial clock signal sb_ser_clk have the same frequency but different phases, and then through a simple cross-time domain conversion, the single-bit signal of the serial clock signal sb_ser_clk clock domain is converted into a single-bit signal of the local clock signal sbclk clock domain. Then, the parallel data packet signal sb_packet under the serial clock signal sb_ser_clk can be converted into a local parallel data packet signal rx_packet under the local clock signal sbclk, completing the conversion of parallel data from the serial clock domain to the local clock domain.

[0046] See also Figure 2 and Figure 4 As shown, in one embodiment of the present invention, the clock domain conversion start signal rx_start is a level signal obtained by the serial-to-parallel start signal sb_s2p_start after the clock domain conversion. That is, relative to the serial-to-parallel start signal sb_s2p_start, the clock domain conversion start signal rx_start has a fixed relationship with the high level duration of the serial-to-parallel start signal sb_s2p_start, so the clock domain conversion start signal rx_start is a delayed signal of the serial-to-parallel start signal sb_s2p_start in the local clock domain. Among them, during the clock conversion, there will be a preset deviation between the high level duration of the clock domain conversion start signal rx_start and the serial-to-parallel start signal sb_s2p_start, and the preset deviation is within plus or minus 2 clock cycles. In this embodiment, the serial-to-parallel start signal sb_s2p_start can be converted from the serial clock domain to the local clock domain by tapping, and the clock domain conversion start signal rx_start can be obtained.

[0047] See also Figure 2 and Figure 4As shown, in one embodiment of the present invention, when a parallel data packet is converted, the serial-to-parallel start signal sb_s2p_start becomes low. After the time delayed by the clock domain conversion, it is also detected that the clock domain conversion start signal rx_start becomes low. After detecting the falling edge of the clock domain conversion start signal rx_start, the data clock domain conversion unit 1021 generates a data packet transfer end signal rx_end. The generation of the data packet transfer end signal rx_end indicates that the parallel data packet formed by the synchronous serial conversion and receiving module 101 is ready, and the parallel data packet can be converted in the clock domain. And the data packet transfer end signal rx_end is a high-level signal, and the time of the high-level signal is equal to one clock cycle of the local clock signal sbclk. In the next clock cycle of generating the data packet transfer end signal rx_end, if the clock domain conversion start signal rx_start is a low-level signal, the data clock domain conversion unit 1021 generates a data clock domain conversion valid signal rx_valid. While generating the data clock domain conversion valid signal rx_valid, the data value of the parallel data packet signal sb_packet is sampled and assigned to the local parallel data packet signal rx_packet to complete the cross-time domain processing of parallel data. Among them, the data clock domain conversion valid signal rx_valid is a high-level signal, and the time of the high-level signal is equal to one clock cycle of the local clock signal sbclk.

[0048] See also Figure 2 , Figure 5 and Figure 6As shown, in one embodiment of the present invention, the receiving error detection unit 1022 generates a data packet counting signal rx_cnt, an error signal rx_err, and an asynchronous clear signal rx_clr. The data packet counting signal rx_cnt starts counting at the rising edge of the clock domain conversion start signal rx_start, and is incremented by one at each rising edge of a clock cycle when the clock domain conversion start signal rx_start is at a high level, and the number of clock cycles of the clock domain conversion start signal rx_start is obtained, and then the number of clock cycles of the serial-to-parallel start signal sb_s2p_start is indirectly counted, and then the number of clock cycles required for parallel data packet conversion is counted. When the number of clock cycles of the clock domain conversion start signal rx_start is not within a preset range, the receiving error detection unit 1022 generates an error signal rx_err, and reports the error signal rx_err to the post-stage data parsing and processing module 103 in the physical layer, and the post-stage data parsing and processing module 103 records the cause of the error and completes the cause analysis of the error. After the receiving error detection unit 1022 generates an error signal rx_err, the receiving error detection unit 1022 generates an asynchronous clear signal rx_clr, and sends the asynchronous clear signal rx_clr to the synchronous serial conversion and receiving module 101, and asynchronously resets the signal in the serial clock domain, so that the serial-to-parallel module can recover from the error. The error signal rx_err is a high-level signal, and the time of the high-level signal is equal to one clock cycle of the local clock signal sbclk. In the next clock cycle of the error signal rx_err, an asynchronous clear signal rx_clr is formed. And the asynchronous clear signal rx_clr is also a high-level signal, and the time of the high-level signal is equal to one clock cycle of the local clock signal sbclk.

[0049] See also Figure 2 , Figure 5 and Figure 6 As shown, in one embodiment of the present invention, in monitoring whether the number of clock cycles of the clock domain conversion start signal rx_start is not within a preset range, the lower limit of the preset range is equal to the length of the parallel data packet minus the first preset value, and the first preset value is, for example, 2 to 3, then the preset value is specifically, for example, equal to 2 or 3. The upper limit of the preset range is equal to the length of the parallel data packet plus the second preset value, and the second preset value is, for example, 3 to 5, then the preset value is specifically, for example, equal to 3, 4 or 5.

[0050] See also Figure 2 , Figure 5 and Figure 6As shown, in one embodiment of the present invention, the lower limit value of the preset range is equal to 61-62, and the upper limit value of the preset range is equal to 66-68. This embodiment is described with the upper limit value of the preset range being equal to 67 and the lower limit value being equal to 62. The data packet counting signal rx_cnt starts counting from 0. When the value of the data packet counting signal rx_cnt reaches 63, the counting of a parallel data packet is completed. At this time, if the level of the clock domain conversion start signal rx_start continues to be high, the data packet counting signal rx_cnt starts counting from 0 again. When the value of the data packet counting signal rx_cnt rises to 3, it indicates that the clock cycle of the clock domain conversion start signal rx_start is not within the upper limit value of the preset range. If the value of the data packet counting signal rx_cnt does not reach 62, the level of the clock domain conversion start signal rx_start becomes a low level, and the value of rx_cnt will also decrease by 0. At this time, the clock domain conversion start signal rx_start is not within the lower limit value of the preset range.

[0051] Therefore, when using the data receiving system provided by the present invention for data transmission, if unexpected errors occur, such as interference from the working environment, when an abnormal situation occurs, the number of parallel data packets may not be 64 bits, resulting in abnormal reception of the serial-to-parallel module, affecting the reception of subsequent data. The present invention can make the system more stable and can easily locate the cause of the error by adding an error detection and recovery mechanism.

[0052] For details, please refer to Figure 2 and Figure 5 As shown, in one embodiment of the present invention, when the line is interfered, resulting in one, two or more narrow pulses in the serial clock signal sb_ser_clk, it will cause the serial-to-parallel mechanism to fail when the synchronous serial-to-receiving module 101 converts the serial data sb_ser_data into a parallel data packet signal sb_packet, thereby causing the serial data sb_ser_data to be unable to be received normally afterwards.

[0053] See also Figure 2 and Figure 5As shown, in one embodiment of the present invention, since the data packet counting signal rx_cnt counts the number of clock cycles of the clock domain conversion start signal rx_start of the local clock domain, and the clock domain conversion start signal rx_start is a signal of the serial-to-parallel start signal sb_s2p_start converted from the serial clock domain to the local clock domain, the data packet counting signal rx_cnt is equivalent to indirectly counting the number of clock cycles of the serial-to-parallel start signal sb_s2p_start. When the line is interfered, causing the serial clock signal sb_ser_clk to have one, two or more narrow pulses, it will cause two situations of the serial-to-parallel start signal sb_s2p_star. The first situation is that the serial clock signal sb_ser_clk has one, two or more narrow pulses, and the narrow pulses are detected, causing the serial-to-parallel start signal sb_s2p_cnt to be unable to remain at 0 after being cleared to 0, causing the number of clock cycles of the serial-to-parallel start signal sb_s2p_start to be greater than the preset range and have a low level of 1 clock cycle, and remain at a high level after the low level. After the clock domain conversion, the local clock domain signal rx_start also has a low level of 1 clock cycle, and remains at a high level after the low level, which causes the number of clock cycles of the clock domain conversion start signal rx_start to be outside the preset range. The second situation is that the serial clock signal sb_ser_clk has one, two or more narrow pulses, and the narrow pulses are detected, causing the serial-to-parallel start signal sb_s2p_cnt to be unable to remain at 0 after being cleared to 0, causing the number of clock cycles of the serial-to-parallel start signal sb_s2p_start to be greater than the preset range and have a low level of 1 clock cycle, and remain at a high level after the low level. After the clock domain conversion, the local clock domain signal rx_start does not have a low level of 1 clock cycle, and continues to be a high level, which causes the number of clock cycles of the clock domain conversion start signal rx_start to be outside the preset range. In these two cases, the serial clock signal sb_ser_clk has one, two or more narrow pulses, which causes the number of clock cycles of the clock domain conversion start signal rx_start to be out of the preset range. At this time, the receiving error detection unit 1022 generates an error signal rx_err, reports the error signal rx_err to the physical layer, and records the cause of the error. After the receiving error detection unit 1022 generates an error signal rx_err, the receiving error detection unit 1022 generates an asynchronous clear signal rx_clr to asynchronously reset the signal in the serial clock domain, so that the serial-to-parallel module can recover from the error.

[0054] See also Figure 2 and Figure 5As shown, in one embodiment of the present invention, in the first case, due to the detection of one, two or more narrow pulses in the serial clock signal sb_ser_clk, the serial-to-parallel start signal sb_s2p_start will generate a low level of 1 clock cycle when it reaches 64 clock cycles, and will remain at a high level in the future. At this time, the low level of the rx_start signal will generate a data packet transfer end signal rx_end, but since the data packet transfer end signal rx_end is a high level signal, and the high level time is equal to one clock cycle of the local clock signal sbclk. Therefore, in the next clock cycle when the serial clock signal sb_ser_clk has a narrow pulse, the serial clock signal sb_ser_clk has been restored, resulting in the serial-to-parallel start signal sb_s2p_start also restoring a high level, and then in the next clock cycle when the data packet transfer end signal rx_end is generated, the clock domain conversion start signal rx_start will be restored to a high level signal. Therefore, in the next clock cycle when the data packet transfer end signal rx_end is generated, the data clock domain conversion valid signal rx_valid cannot be generated. At this time, the data value of the parallel data packet signal sb_packet is not sampled and assigned to the local parallel data packet signal rx_packet, and no cross-time domain processing of the parallel data is performed.

[0055] See also Figure 2 and Figure 5 As shown, in one embodiment of the present invention, in the second case, since the local clock domain does not detect a low level of one cycle of the serial-to-parallel start signal sb_s2p_start, the number of clock cycles of the clock domain conversion start signal rx_start is not within the preset range. In this case, since the clock domain conversion start signal rx_start is always at a high level and no falling edge is generated, the data packet transfer end signal rx_end will not be generated, and thus the data clock domain conversion valid signal rx_valid will not be generated. At this time, the data value of the parallel data packet signal sb_packet will not be sampled and assigned to the local parallel data packet signal rx_packet, and no cross-time domain processing of parallel data is performed.

[0056] See also Figure 2 and Figure 6 As shown, in one embodiment of the present invention, when the line is interfered, resulting in the serial clock signal sb_ser_clk lacking one, two or more period signals, it will cause the serial-to-parallel mechanism to fail when the synchronous serial-to-receiving module 101 converts the serial data sb_ser_data into a parallel data packet signal sb_packe, thereby causing the serial data sb_ser_data to be unable to be received normally afterwards.

[0057] See also Figure 2 and Figure 6 As shown, in one embodiment of the present invention, since the data packet counting signal rx_cnt counts the number of clock cycles of the clock domain conversion start signal rx_start of the local clock domain, and the clock domain conversion start signal rx_start is a signal of the serial-to-parallel start signal sb_s2p_start converted from the serial clock domain to the local clock domain, the data packet counting signal rx_cnt is equivalent to indirectly counting the number of clock cycles of the serial-to-parallel start signal sb_s2p_start. When the line is interfered, resulting in one, two or more cycle signals missing from the serial clock signal sb_ser_clk, it will cause the serial data sb_ser_data to be unable to be received, then the serial-to-parallel start signal sb_s2p_cnt will not flip after the last serial clock signal sb_ser_clk ends, and the serial-to-parallel counting signal sb_s2p_cnt will not increase the count, and the flip from 63 to 0 cannot be achieved. The serial-to-parallel start signal sb_s2p_start is always at a high level. At this time, the clock domain conversion start signal rx_start is also always at a high level, resulting in the number of clock cycles of the serial-to-parallel start signal sb_s2p_start being greater than the preset range, which in turn results in the number of clock cycles of the clock domain conversion start signal rx_start being outside the preset range. Since the number of clock cycles of the clock domain conversion start signal rx_start is outside the preset range, the receiving error detection unit 1022 generates an error signal rx_err, reports the error signal rx_err to the physical layer, and records the cause of the error. After the receiving error detection unit 1022 generates an error signal rx_err, the receiving error detection unit 1022 generates an asynchronous clear signal rx_clr, asynchronously resets the signal in the serial clock domain, and enables the serial-to-parallel module to recover from the error.

[0058] See also Figure 2 and Figure 6 As shown, in one embodiment of the present invention, during this process, since the clock domain conversion start signal rx_start is always at a high level and no falling edge is generated, the data packet transfer end signal rx_end will not be generated, and thus the data clock domain conversion valid signal rx_valid will not be generated. At this time, the data value of the parallel data packet signal sb_packet will not be sampled and assigned to the local parallel data packet signal rx_packet, and no cross-time domain processing of parallel data is performed.

[0059] In summary, the present invention provides a data receiving system, a data receiving method and a core particle, wherein the data receiving system includes a synchronous serial conversion and receiving module, which converts the received serial data into parallel data under a serial clock, and the parallel data is stored in the form of parallel data packets; and an asynchronous to synchronous processing module, which receives the parallel data and converts the parallel data from a serial clock domain to a local clock domain; wherein the asynchronous to synchronous processing module detects the number of clock cycles required for the conversion of each parallel data packet, and when the number of clock cycles required for the conversion of the parallel data packet is not within a preset range, it is determined that the process of converting the serial data into the parallel data is abnormal, and an asynchronous reset is performed. Through the data receiving system, data receiving method and core particle provided by the present invention, the reliability of the received data is increased.

[0060] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A data receiving system, characterized in that: At least: A synchronous serial conversion and receiving module converts the received serial data into parallel data under the serial clock, and the parallel data is stored in the form of parallel data packets; as well as An asynchronous-to-synchronous processing module receives the parallel data and converts the parallel data from a serial clock domain to a local clock domain; Among them, the asynchronous to synchronous processing module detects the number of clock cycles required for the conversion of each parallel data packet. When the number of clock cycles required for the conversion of the parallel data packet is not within a preset range, it is determined that an abnormality occurs in the process of converting the serial data to the parallel data, and an asynchronous reset is performed.

2. A data receiving system according to claim 1, characterized in that: The synchronous serial conversion and receiving module samples the serial data under the serial clock signal to form the parallel data packet.

3. A data receiving system according to claim 1, characterized in that: The synchronous serial-to-parallel receiving module generates a serial-to-parallel start signal, which becomes a high level when the synchronous serial-to-parallel receiving module receives the serial data and becomes a low level when the serial data is not received.

4. A data receiving system according to claim 3, characterized in that: The asynchronous-to-synchronous processing module includes a data clock domain conversion unit, which generates a clock domain conversion start signal. The clock domain conversion start signal is a level signal obtained by the serial-to-parallel start signal after clock domain conversion.

5. A data receiving system according to claim 4, characterized in that: The data clock domain conversion unit generates a data packet transfer end signal after detecting the falling edge of the clock domain conversion start signal.

6. A data receiving system according to claim 5, characterized in that: The data clock domain conversion unit generates a data clock domain conversion valid signal within the next clock of generating the data packet transfer end signal if the clock domain conversion start signal is at a low level; And while generating the data clock domain conversion valid signal, the data value sampling of the parallel data packet signal is assigned to the local parallel data packet signal to complete the cross-time domain processing of the parallel data.

7. A data receiving system according to claim 4, characterized in that: The asynchronous-to-synchronous processing module includes a receiving error detection unit, which generates a data packet counting signal, and the data packet counting signal counts the clock cycle of the clock domain conversion start signal.

8. A data receiving system according to claim 7, characterized in that: When the number of clock cycles required for the parallel data packet conversion is not within a preset range, the receiving error detection unit generates an error signal and reports the error signal to the physical layer to complete the error cause analysis.

9. A data receiving system according to claim 8, characterized in that: After the receiving error detection unit generates the error signal, the receiving error detection unit generates an asynchronous clear signal and sends the asynchronous clear signal to the synchronous serial transfer and receiving module to asynchronously reset the signal in the serial clock domain.

10. A data receiving system according to claim 1, characterized in that: The lower limit value of the preset range is equal to the length of the parallel data packet minus the first preset value, and the range of the first preset value is 2 to 3. The upper limit value of the preset range is equal to the length of the parallel data packet plus the second preset value, and the range of the second preset value is 3 to 5.

11. A data receiving method, characterized in that: At least the following steps are included: Using a synchronous serial conversion and receiving module to convert the received serial data into parallel data under a serial clock, and the parallel data is stored in the form of parallel data packets; as well as Using an asynchronous to synchronous processing module to receive the parallel data, and converting the parallel data from a serial clock domain to a local clock domain; Among them, the asynchronous to synchronous processing module detects the number of clock cycles required for the conversion of each parallel data packet. When the number of clock cycles required for the conversion of the parallel data packet is not within a preset range, it is determined that an abnormality occurs in the process of converting the serial data to the parallel data, and an asynchronous reset is performed.

12. A core particle, characterized in that: The data receiving system as described in any one of claims 1 to 10 is arranged in the receiving interface of the core particle.

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