Equipment driving device

Abstract

Provided is a device driving apparatus capable of transmitting and receiving a command to operate without separately setting an address when connected to the same bus interface. The device comprises a master device and at least one slave device, wherein the master device is connected with a bus interface with a clock signal line and a data signal line; each slave device includes a first terminal connected to one of the clock signal line and the data signal line, and a second terminal connected to the other of the clock signal line and the data signal line; and according to the signals of the master device input from the first terminal and the second terminal, the connection orientation of the clock signal line is judged, and an independent address is allocated to the slave device which is reversely connected.

Description

Technical Field

[0001] The present invention relates to the technical field of device driving devices, and in particular to a device driving device which enables a device to receive and send commands and perform operations through the same bus interface without setting addresses separately.

[0002] This application claims priority, and its priority date is May 21, 2024, and the priority number is 10-2024-0065749. This application refers to the above priority document. Background Art

[0003] Generally, in electrical systems, interconnects are often used when information or signals are transmitted between components of the system. This interconnect consists of one or more signal lines, also known as a bus.

[0004] For example, some systems use the I2C bus as an Inter-Integrated Circuit (I2C) bus, i.e., a bus protocol, to provide an environment in which multiple ICs communicate using fewer communication lines. The I2C bus consists of a serial clock line (SCL) for transmitting a clock and a serial data line (SDA) for serially transmitting data, and data is sent and received according to the clock.

[0005] The I2C bus uses two wires to exchange data between IC chips, and devices connected to the I2C bus communicate through master devices and slave devices. Figure 1 As shown, the I2C bus is a serial bus protocol that can communicate with multiple slave devices. Multiple slave devices 21, 22, 23, 24 are connected to the master device 10 through the power line VDD and the two-strand wires SCL and SDA to send and receive data. In this way, the I2C bus can control multiple chips in parallel with two lines.

[0006] The master device generates a clock signal to control the data transfer between the master device and the slave device. Then, the master device specifies the slave address assigned to each slave device to communicate with the desired slave device. The master device specifies the address of the slave device by sending multiple bits (usually 1 byte) of information on the bus, including specifying the N-bit slave device bus address and the command bit for specifying the read or write operation. In this case, if two or more slave devices with the same address are connected to the bus, these slave devices will not be accessible individually by the master device. Therefore, each device connected to the bus must have its own unique bus address to ensure the normal operation of the bus. That is, the master device and the slave device each have an independent address. The master device sends the specified address through the data line (SDA) to call a specific slave device.

[0007] For example, after the master device creates a start condition on the bus, it outputs the slave device address of the communication object. The slave device with the corresponding address responds with an acknowledgement signal (ACK), thereby starting communication. During the communication process, the device receiving the data replies with an ACK signal. The master device terminates the communication with the slave device by constructing a stop condition on the bus. Therefore, the master device can communicate with a specific slave device by the slave device address assigned to each slave device. However, when individual slave devices composed of different chips communicate data through the I2C bus, they are assigned different addresses so that they can communicate with the master device. However, if two or more slave devices composed of chips of the same manufacture are connected to the bus, they may be assigned the same slave device address, resulting in a conflict.

[0008] In addition, slave devices usually use the data signal line SDA, which can be used for both input and output, while the clock signal line SCL is mainly used as an input. However, if these signal lines are mistakenly connected crosswise due to operator error, etc., the data transmitted from the master device may not be received normally. In other words, since the characteristics of the I2C protocol require that the clock terminal (SCL terminal) and the data terminal (SDA terminal) must be connected in a clearly defined direction in order to communicate, in I2C communication, the SCL terminal and SDA terminal of all slave devices must be connected in the same way.

[0009] If the SCL terminal of the slave device is connected to the data line SDA, and the SDA terminal is connected to the clock line SCL, the clock and data signals will be connected incorrectly. Because the SCL terminal needs an output line to generate a clock signal, this incorrect connection will result in the inability to correctly perform both data input and output operations in I2C communication. Therefore, traditionally, IC chips with different addresses need to be used, or if IC chips with the same structure are used, there will be difficulties in connection and address allocation, and the address needs to be modified with the help of internal memory so that it can be used correctly. Especially when driving multiple slave devices, the choice of using IC chips with the same structure at the same time is limited, so multiple chips need to be prepared, which also causes problems in inventory management. In addition, although the circuit configuration can be changed at the manufacturing stage to set the address, it is very difficult to implement structural modifications for the circuit structure that has already been manufactured, so there are manufacturing restrictions. Summary of the invention

[0010] The present invention is proposed to solve the above technical problems. The purpose of the present invention is to provide a device driver that can individually allocate addresses for reversely connected slave devices.

[0011] In one embodiment, the present invention aims to provide a device driver that can easily perform address allocation even when multiple slave devices with the same configuration are used simultaneously.

[0012] To achieve the above-mentioned purpose, the device driving device provided by the present invention is a system, comprising a master device and at least one slave device connected to a bus interface having a clock signal line and a data signal line; each of the slave devices comprises a first terminal connected to one of the clock signal line and the data signal line, and a second terminal connected to the other of the clock signal line and the data signal line; based on the signal of the master device input from the first terminal and the second terminal, the connection direction of the clock signal line is judged, and a separate address is assigned to the reversely connected slave device.

[0013] Optionally, the slave device is set according to the following characteristics: if the first terminal is connected to the clock signal line and the second terminal is connected to the data signal line, the slave device is set as a normally connected slave device;

[0014] If the first terminal is connected to the data signal line and the second terminal is connected to the clock signal line, the slave device is set as a reversely connected slave device.

[0015] Optionally, the slave device is equipped with an input line and an output line at the first terminal and the second terminal respectively, and the input and output of data signals are carried out normally in a normal connection state or a reverse connection state.

[0016] Optionally, the slave device further includes an input / output exchange decision module, and the input / output exchange decision module determines the reverse connection state of the slave device by identifying a specific pattern within a given holding time.

[0017] Compared with the prior art, the device driving device provided by the present invention has the following beneficial effects:

[0018] The device driver provided by the present invention can allocate a separate address to a slave device connected in reverse. In addition, by adopting the device driver provided by the present invention, even if multiple slave devices with the same configuration are used at the same time, address allocation can be easily performed, so it has advantages in inventory management. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural block diagram of a general device driver;

[0020] Figure 2 A structural block diagram of a device driver provided by an embodiment of the present invention;

[0021] Figure 3 A structural diagram of an integrated circuit constituting a slave device in a device driving apparatus provided by an embodiment of the present invention;

[0022] Figure 4 A working diagram of a device driver provided by an embodiment of the present invention;

[0023] Figure 5 This is the timing diagram of the I2C protocol.

[0024] Description of reference numerals:

[0025] 100-device driver;

[0026] 110-main device;

[0027] 120- slave device;

[0028] 121a, 123a-first terminals;

[0029] 121b, 123b-second terminals. DETAILED DESCRIPTION

[0030] The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms.

[0031] The terms used in this specification are intended to describe various embodiments and are not intended to restrict the present invention. In this specification, unless otherwise specified, the singular includes the plural. The terms "include" and / or "comprise" used in this specification do not exclude the existence or addition of one or more other components other than the components described. Throughout the specification, the same figure numbers refer to the same components, and "and / or" covers each of the components and any combination thereof. Although terms such as "first" and "second" are used to describe different components, these components are not limited by these terms, and these terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component in the technical concept of the present invention.

[0032] In this specification, the word "exemplary" is used to mean "used as an example or evidence". Any embodiment described as "exemplary" in this specification should not be interpreted as necessarily ideal or having advantages over other embodiments. In addition, in the terms used in this specification, "part" refers to a hardware element, such as software, FPGA or ASIC, and a "part" can play a variety of different roles. However, a "part" is not limited to software or hardware. It can be configured in an addressable storage medium, and can also be configured to regenerate one or more processors. So, for example, a "part" can cover software elements, object-oriented software elements, class elements, and task elements, as well as processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided to a "part" can be integrated into a smaller number of elements and "parts", or disassembled into a larger number of elements and "parts". (For example, in actual applications, a complex software system may contain multiple "sections" that work together to realize the functions of the entire system. For example, in a large e-commerce platform, the user management module can be regarded as one "section", and the order processing module is another "section". Sometimes, in order to improve system performance, some originally scattered functions may be integrated into one "section"; and when the system is upgraded or optimized, the functions of a "section" may also be separated for more refined management and optimization. For another example, in the hardware design of electronic equipment, different circuit components can also be regarded as different "sections". For example, the power management circuit is one "section", and the signal processing circuit is another "section". With the development of technology, some originally independent circuits may be integrated into a more integrated "section", or a complex circuit "section" may be separated into several simpler parts for easy maintenance.)

[0033] In this specification, all "units" can be controlled by at least one processor, and the operations performed by the "units" in the present invention can be performed by at least one processor. The embodiments in this specification can be described from the perspective of modules that perform functions or operations. Modules referred to as "units" or "modules" in this specification can be physically implemented by analog or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memories, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be selectively driven by firmware and software. For example, in an advanced communication device, the module responsible for signal processing may be composed of a high-performance microprocessor and a dedicated integrated circuit, and driven by optimized firmware and software to achieve efficient data transmission and processing. For another example, in the control system of a smart home appliance, the module that controls temperature adjustment may be implemented by a digital circuit composed of logic gates and a microcontroller, and precise temperature control functions are achieved with the help of specific software and firmware.

[0034] The embodiments herein may be executed on at least one hardware device using at least one software program, and may perform network management functions to control components. Unless otherwise defined, all terms (including technical and scientific terms) used in this specification can be understood to be consistent with the common understanding of ordinary technicians in the field of the present invention. In addition, terms that are usually defined in dictionaries should not be over-interpreted or exceed their reasonable scope in the absence of clear and specific definitions.

[0035] Hereinafter, the technical features of the present invention will be described in detail with reference to the accompanying drawings.

[0036] The present invention aims to provide a device driver capable of assigning individual addresses to slave devices connected in reverse. In one embodiment, even if multiple slave devices with the same configuration are used at the same time, the present invention can easily complete the address assignment. Specifically, Figure 2 FIG. 1 is a structural block diagram of a device driver provided by an embodiment of the present invention. Figure 2 As shown, the device driving apparatus provided by the present invention is a device connected to a bus interface having a clock signal line SCL and a data signal line SDA, and can also be composed of an I2C communication system.

[0037] The device driver 100 may include a master device 110 and at least one slave device 120 connected via a serial bus. In this embodiment, the slave device 120 is composed of four devices, but is not limited thereto.

[0038] Among them, the master device and the slave device are respectively composed of independent integrated circuits (IC chips), and each device is equipped with a serial clock terminal and a serial data terminal. These devices can be connected to the clock signal line SCL and the data signal line SDA, respectively, and access the I2C bus interface. For example, in a complex industrial automation control system, such a device driver that can assign individual addresses to slave devices is particularly important. Multiple sensors with the same configuration as slave devices can be accurately assigned addresses through the device driver, thereby ensuring stable and efficient operation of the system. For another example, in the network of a smart home, various smart home appliances are used as slave devices. With the help of such a device driver, even if there are multiple appliances of the same type at the same time, address allocation and effective communication control can be smoothly achieved.

[0039] In this case, the device driver provided by the present invention can configure each device with respective terminals that can be connected to the clock signal line SCL and the data signal line SDA. Each terminal can have the functions of a clock terminal and a data terminal. In other words, each device can have a first terminal connected to one of the clock signal line SCL and the data signal line SDA, and a second terminal connected to the other of the clock signal line SCL and the data signal line SDA.

[0040] Generally speaking, the first terminal can be connected to the clock signal line SCL, and the second terminal can be connected to the data signal line SDA. This connection method can be called a normal connection. Conversely, the structure in which the first terminal is connected to the data signal line SDA and the second terminal is connected to the clock signal line SCL can be called a cross connection (or reverse connection). In a conventional system, if the terminals are cross-connected without the intervention of other devices or structures, the system may not operate normally. In other words, the clock signal line SCL is responsible for transmitting the clock signal and synchronizing the data, while the data signal line SDA is responsible for transmitting the actual data. If these two terminals are cross-connected, errors will occur in the flow of clock signals and data signals, which may greatly increase the risk of communication failure. Therefore, operators need to pay attention to ensure the correctness of the normal connection method.

[0041] As an embodiment, the device driver provided by the present invention enables some slave devices to operate normally even if they are connected to each signal line in a cross-connection manner. The relevant content will be described in detail later. Therefore, each terminal is connected to its own signal line, so that the master device 110 and multiple slave devices 120 can interact through I2C bus communication. In addition, the clock signal line SCL and the data signal line SDA can be connected to the power supply voltage VDD through the pull-up resistor Rpu.

[0042] The device driver provided by the present invention sends a clock signal on the clock signal line SCL, and sends and receives a data signal on the data signal line SDA. In other words, the master device 110 and the slave device 120 can send and receive the clock signal and the data signal through the clock signal line SCL and the data signal line SDA. Therefore, the master device 110 and the plurality of slave devices 120 can operate according to the I2C bus.

[0043] The master device 110 can control multiple slave devices 120 by means of I2C bus communication, and the multiple slave devices 120 controlled by the master device 110 can act as drivers for external devices. However, if two or more slave devices are composed of the same IC chip (same model), then these devices may have the same address. Therefore, when the device driver is started, it is necessary to assign a different address to each device.

[0044] As an embodiment, the design feature of the device driver provided by the present invention is that even if connected to the same bus interface, the device can be assigned different addresses without setting addresses separately, and can send and receive commands to operate. Figure 2 As shown, the first terminal and the second terminal of the first slave device 121 and the second slave device 122 of the plurality of slave devices 120 are normally connected to each signal line, while the connection positions of the first terminal and the second terminal of the third slave device 123 and the fourth slave device 124 are crossed and connected to each signal line. The following description will focus on the first slave device 121 and the third slave device 123 as examples.

[0045] First, the first terminal 121a of the first slave device 121 can be connected to the clock signal line SCL, and the second terminal 121b can be connected to the data signal line SDA. On the contrary, the first terminal 123a of the third slave device 123 can be connected to the data signal line SDA, and the second terminal 123b can be connected to the clock signal line SCL. In this way, the terminals can be connected by pin swapping in a cross manner. The second slave device 122 and the fourth slave device 124 can also be connected in the same manner. Subsequently, the device driver provided by the present invention can determine which of the first terminal and the second terminal the clock signal line SCL is connected to based on the signal of the master device 110 input from the first terminal and the second terminal, and assign separate addresses to the slave devices (the third slave device 123 and the fourth slave device 124) connected in reverse.

[0046] According to the device driving apparatus provided by the present invention, when it is determined that the first terminal 121a of the first slave device 121 is connected to the clock signal line SCL and the second terminal 121b is connected to the data signal line SDA, the first address can be automatically set as the address of the first slave device 121.

[0047] On the contrary, if it is determined that the first terminal 121a of the first slave device 121 is connected to the data signal line SDA and the second terminal 121b is connected to the clock signal line SCL, the device driver provided by the present invention can automatically set the second address as the address of the first slave device 121. If there is an allocated address, other user address values ​​can be automatically allocated.

[0048] These first addresses, second addresses and other user addresses can be stored in the address registers in the interface module of each slave device. Figure 2 As shown, the first terminal 121a of the first slave device 121 is connected to the clock signal line SCL, and the second terminal 121b is connected to the data signal line SDA, so the first address can be assigned as a normal connection configuration. Next, similar to the first slave device 121, the device driver provided by the present invention can assign an address to the third slave device 123. That is, if it is determined that the first terminal 123a of the third slave device 123 is connected to the clock signal line SCL, and the second terminal 123b is connected to the data signal line SDA, the device driver provided by the present invention can automatically assign the first address to the third slave device 123.

[0049] On the contrary, if it is determined that the first terminal 123a of the third slave device 123 is connected to the data signal line SDA and the second terminal 123b is connected to the clock signal line SCL, the device driving apparatus of the present invention can automatically assign the second address to the third slave device 123. Figure 2 As shown, the first terminal 123a of the third slave device 123 is connected to the data signal line SDA, and the second terminal 123b is connected to the clock signal line SCL, so as a cross-connection configuration, a second address can be assigned. If there is an assigned address, other user address values ​​can be automatically assigned.

[0050] Here, the first slave device 121 and the third slave device 123 are different in whether each terminal is normally connected or cross-connected, but they are both composed of the same IC chip. Similarly, the device driver provided by the present invention can assign different addresses to each of the first slave device 121, the second slave device 122, the third slave device 123 and the fourth slave device 124. That is, by cross-connecting the signal lines connected to the terminals of the device in a conventional connection mode, forming the reversely connected third slave device 123 and the fourth slave device 124, and identifying them, the reversely connected third slave device 123 and the fourth slave device 124 can be assigned separate addresses.

[0051] Therefore, the device driving apparatus provided by the present invention can allocate respective addresses to a plurality of slave devices using the same IC chip, thereby avoiding address conflicts and ensuring stable transmission of control signals.

[0052] Figure 3 The integrated circuit structure diagram of the slave device of the device driver provided by the present invention. In other words, it shows the configuration of the device for address control. As an embodiment, the device driver provided by the present invention can be configured so that each terminal connected to the clock signal line SCL and the data signal line SDA can be connected to the input line and the output line. Generally speaking, the clock terminal (or pin) connected to the clock signal line SCL is used to receive the clock signal of the master device 110, so that the clock terminal of the slave device 120 does not need to generate an independent clock signal. The clock terminal of the slave device 120 only receives the clock signal generated and controlled by the master device 110, so the design is relatively simple. Therefore, in most devices, the clock terminal connected to the clock signal line SCL usually does not need an output line, which can simplify the hardware design.

[0053] As an embodiment, the device driver provided by the present invention allows the existing clock terminal to be used as a data terminal during cross-connection, so both terminals are equipped with input lines and output lines. Figure 3As shown, each first terminal P1 and second terminal P2 connected to the clock signal line SCL and the data signal line SDA can connect to the input line IL and the output line OL. In this case, the first terminal P1 functions as a clock terminal connected to the clock signal line SCL, and the second terminal P2 functions as a data terminal connected to the data signal line SDA. When the slave device is cross-connected, the connection of the signal line becomes a reverse connection, so the first terminal P1 can be used as a data terminal, and the second terminal P2 can be used as a clock terminal. Since the device driver provided by the present invention is configured with an input line IL and an output line OL on the first terminal P1 and the second terminal P2, it is possible to perform input of output signals and input and output of data signals. Therefore, by adding connection lines to the terminals, the present invention can achieve normal operation of the device with the help of the normal signal input and output of the slave device 120 even in the case of reverse connection, rather than being limited to the position of normal connection.

[0054] At the same time, the present invention connects the connection line to each terminal on the integrated circuit, so that the clock signal and the data signal can be transmitted normally even in the reverse connection state, even if the initial terminal is connected to other signal lines. Figure 3 As shown, the integrated circuit is connected to the signal lines SCL and SDA through the first terminal P1 and the second terminal P2, and can be connected to the host device. A noise filter (Glltch Filter) F, a multiplexer MUX and an interface module IB can also be connected in the circuit. The noise filter F can be designed as a pulse filter for detecting and handling signal anomalies such as power supply or signal noise.

[0055] A multiplexer MUX is a device that can selectively switch multiple input signals to a single output, and it can work like a switch. This multiplexer can be set to connect to a specific device as required, and disconnect from other devices to control the communication path. The interface module IB can act as an I2C slave device controller, manage communication between devices, control clock and timing signals, and manage status and control registers. As an embodiment, the interface module IB can include an I2C slave device engine (I2C Slave Engine) and an input and output swap decision module (IO Swap Decision Block).

[0056] The I2C slave device engine is mainly responsible for receiving commands from the master device and providing data. In other words, it can detect the slave device address and maintain the required state to transmit or receive data signals. Some I2C slave device engines can include a data shift register, an address comparator, and multiple address registers, and can send and receive data with the memory part. The data shift register can store data transmitted or received in I2C communication. It is used to cache data received from the master device or retain data to be transmitted in the slave device. The address comparator can detect the address and compare the address from the master device with the address of the slave device to determine whether they match. It is used for the slave device to receive the address sent by the master device and determine whether the slave device is called.

[0057] The address register can store the address of the slave device. When receiving the address from the master device, it uses the address stored in the register to compare with the received address to confirm whether it is called. When assigning addresses, the newly assigned addresses can be stored. These addresses are stored in the user-defined address register area. In this embodiment, the input-output exchange decision module can make a decision to exchange data signals in I2C communication. This input-output exchange decision module can determine the IO configuration, that is, determine whether the input-output direction needs to be exchanged. For example, the input-output exchange decision block can play a role in the following situation: when the connection mode of the third slave device 123 is cross-connected, that is, its terminals are cross-connected to each signal line, the input-output exchange decision module can decide to perform input-output exchange to ensure that the signal is normally transmitted and received through each terminal when the signal line is cross-connected. The input-output exchange decision module can cover the input-output management register (IO Config Register). The input-output management register is used to manage the input-output direction and can set and manage the operation of the input-output terminals.

[0058] Data may be stored in memory.

[0059] As an embodiment, the device driver provided by the present invention can identify and assign separate addresses to slave devices whose terminals are in a cross-connection state rather than a normal connection state. In this case, the device driver provided by the present invention can send and receive signals normally even in a terminal exchange state, because the first terminal and the second terminal each have an input and output line, by connecting the clock terminal to the data signal line and the data terminal to the clock signal line. Finally, the present invention enables the device to be driven normally even when it is in a cross-connection state.

[0060] According to the present invention, even if multiple IC chips of the same configuration are used as slave devices, different addresses can be assigned to each device. In this way, when the driver needs it, the same chip can be used instead of different chips. Compared with the traditional inventory method that requires owning and managing various forms of chips, inventory management can be performed more easily. In addition, according to the present invention, even in the case of cross-connected IC chip terminals, clock signals and data signals can be normally transmitted and received. Therefore, it can be ensured that the equipment can operate normally regardless of whether it is due to operator error or intentional, thereby improving work efficiency.

[0061] The present invention relates to a method for easily identifying devices and assigning independent addresses in a two-wire system sharing an I2C clock signal and a data signal, even in the case of a cross connection (that is, the address is inserted inverted), thereby making the previous normal connection mode and operation possible, and the terminals of the slave device are connected to the signal line. Figure 4 A flowchart of a device driver provided by an embodiment of the present invention. Figure 5 The following is a sequence diagram of the operation of the I2C protocol. Referring to these diagrams, the following describes the process of setting the input / output configuration change condition by the device of the present invention.

[0062] First, after identifying the start signal, wait (hold) for a period of time. At this time, if it is confirmed that the holding time exceeds a certain target, it is identified as an IO configuration exchange. At this time, when 1 to N start, hold, stop operations are performed, and when 1 to N start, hold, reload start, hold, stop operations are performed, it is identified as an address exchange state, and the input / output direction is changed by changing the function of the terminal, so as to achieve normal communication in the reverse connection state. Therefore, the device driver device provided by the present invention can identify a specific mode, and by allocating a certain length of holding time, it determines whether to perform operations such as IO exchange. It will access the input and output management register of the relevant slave device, request to change the input and output direction, and write a value to the register to save and apply the changed settings. Here, the device driver provided by the present invention is equipped with an input and output line for each slave device terminal, so that normal operation can be performed even if the input and output configuration changes. In other words, generally speaking, if the terminal function changes, it is likely that normal communication cannot be achieved. However, the present invention configures an input and output line for each terminal, so normal operation can be achieved in the reverse connection state. Therefore, according to the present invention, for a cross-connected slave device, the I / O configuration can be changed and can work normally in a cross-connected state. In some embodiments, when the IO Config settings have been swapped, different addresses will be assigned, so no matter how the address is, normal operation can be performed in the case of a reverse connection.

[0063] As described above, the device driver provided by the present invention can allocate a separate address to the slave devices connected in reverse. In addition, by adopting the device driver provided by the present invention, even if the slave devices with the same configuration are used at the same time, the address allocation can be easily performed, thus solving the inventory management problem of needing to prepare multiple chips in the past, making it advantageous in terms of inventory management.

[0064] Various embodiments of the present invention can be implemented in the form of a software, including one or more instructions stored in a storage medium (e.g., a memory) read by a processor of a device (e.g., a vehicle-generated data recording device or a computer). For example, the processor of the device can call and execute at least one instruction stored in the storage medium. This enables the device to perform at least one function in accordance with the at least one instruction called. These one or more instructions can cover code generated by a compiler or code executable by an interpreter. The readable device storage medium can be provided in the form of a non-volatile storage medium. Here, "non-volatile storage medium" refers to an actual existing device, which only indicates that it does not contain signals (e.g., electromagnetic waves), and does not distinguish whether the data is permanently stored or temporarily stored in the storage medium. For example, a "non-volatile storage medium" can include a buffer for temporarily storing data.

[0065] The methods according to various embodiments disclosed in this specification can be included in a computer program product and can be traded as a commodity between a seller and a buyer. The computer program product can be distributed in the form of a device-readable storage medium (such as a compact disc read-only memory (CD-ROM)), or can be distributed through an application store (such as PlayStore). TM ) directly between two user devices (e.g., smartphones) or online (e.g., downloading or uploading). For online distribution, at least a portion of the computer program product (e.g., a downloadable application) can be stored or temporarily generated in a device-readable storage medium (e.g., memory) of a manufacturer's server, an application store's server, or a relay server.

[0066] The above description is merely an example of the technical concept of the present invention, and within the scope of common knowledge in the technical field to which the present invention relates, a person with ordinary technical level can make various modifications and variations without departing from the essential features of the present invention. Therefore, the embodiments disclosed according to the present invention are not intended to limit the technical concept of the present invention, but to illustrate. These embodiments do not limit the scope of the technical concept of the present invention.

Claims

1. A device driving apparatus, characterized in that: A master device and at least one slave device connected to a bus interface having a clock signal line and a data signal line; each of the slave devices comprises a first terminal connected to one of the clock signal line and the data signal line, and a second terminal connected to the other of the clock signal line and the data signal line; The connection direction of the clock signal line is determined based on the signal of the master device input from the first terminal and the second terminal, and an individual address is allocated to the slave device connected in reverse.

2. The device driving apparatus according to claim 1, characterized in that: The slave device is set according to the following characteristics: If the first terminal is connected to the clock signal line and the second terminal is connected to the data signal line, the slave device is set as a normally connected slave device; If the first terminal is connected to the data signal line and the second terminal is connected to the clock signal line, the slave device is set as a reversely connected slave device.

3. The device driving apparatus according to claim 1, characterized in that: The slave device further includes an input-output exchange decision module, which determines the reverse connection state of the slave device by identifying a specific pattern within a given holding time.

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