Dual bank attribute adjustment method and system, terminal and readable storage medium

Abstract

The application is suitable for the chip field, and provides a double-Bank attribute adjustment method, system, terminal and readable storage medium, wherein the method comprises the following steps: determining a target address of a target Bank and an associated reference address based on attribute adjustment information; checking whether the target address and the reference address exist address conflicts; in the case that the address conflicts do not exist, adjusting a target Bank space length address of the target Bank into the target address based on the attribute adjustment information, or adjusting a target space operation permission corresponding to the target address. The scheme provides a safe and efficient double-Bank attribute adjustment method, and solves the technical problem that there is no attribute adjustment scheme in the double-Bank use process.

Description

Technical Field

[0001] This application belongs to the field of chips, and in particular relates to a dual-bank attribute adjustment method, system, terminal and readable storage medium. Background Technology

[0002] A dual-core chip refers to a chip that contains two Central Processing Unit (CPU) cores. To support the efficient operation of a dual-core chip, embedded flash memory is typically integrated inside the chip. This flash memory is a crucial component of the chip, responsible for storing programs and data. To ensure the independence and security of data processing between the two CPU cores in a dual-core architecture, the flash memory is partitioned to ensure that each CPU core has its own dedicated storage space, or bank. This means that the flash memory contains a first bank corresponding to the first CPU core and a second bank corresponding to the second CPU core; this is called dual-bank.

[0003] The spatial length address of each dual bank and the spatial operation permissions of each address segment within the spatial length address are predefined during the chip design stage, and once configured, they are usually fixed. In subsequent use, there is a lack of dual bank attribute adjustment schemes. Summary of the Invention

[0004] This application provides a method, system, terminal, and readable storage medium for adjusting dual-bank attributes, in order to solve the problem of the lack of dual-bank attribute adjustment schemes in the use of dual-bank technology.

[0005] The first aspect of this application provides a dual-Bank attribute adjustment method, including:

[0006] Based on attribute adjustment information, the target address and associated reference address of the target bank are determined; the target bank is the first bank corresponding to the first CPU core or the second bank corresponding to the second CPU core in a dual-core chip, and both the first bank and the second bank correspond to a bank space length address and space operation permissions corresponding to each address segment within the bank space length address; the target address is the expected bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the bank space length address of the first bank and / or the second bank used for address verification with the target address;

[0007] Check whether there is an address conflict between the target address and the reference address;

[0008] In the absence of address conflicts, based on the attribute adjustment information, the target Bank space length address of the target Bank is adjusted to the target address, or the operation permissions of the target space corresponding to the target address are adjusted.

[0009] A second aspect of this application provides a dual-bank attribute adjustment system, including:

[0010] The determination module is used to determine the target address and associated reference address of the target Bank based on attribute adjustment information; the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in a dual-core chip, and both the first Bank and the second Bank correspond to a Bank space length address and the space operation permissions corresponding to each address segment within the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the Bank space length address of the first Bank and / or the second Bank used for address verification with the target address;

[0011] The verification module is used to verify whether there is an address conflict between the target address and the reference address;

[0012] The adjustment module is used to adjust the target Bank space length address of the target Bank to the target address based on the attribute adjustment information when there is no address conflict, or to adjust the target space operation permissions corresponding to the target address.

[0013] A third aspect of this application provides a terminal including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described in the first aspect.

[0014] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0015] The fifth aspect of this application provides a computer program product that, when run on a terminal, causes the terminal to perform the steps of the method described in the first aspect.

[0016] As can be seen from the above, when handling the dual-bank attribute adjustment problem, this application first determines the target bank, its target address, and associated reference address based on the attribute adjustment information. The target bank is either the first bank corresponding to the first CPU core or the second bank corresponding to the second CPU core in a dual-core chip. Both the first and second banks have corresponding bank space length addresses and space operation permissions corresponding to each address segment within those bank space length addresses. The target address is the expected bank space length address given by the attribute adjustment information, or it can be one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information. The reference address is the bank space length address of the first bank and / or the second bank used for address verification with the target address. Subsequently, address comparison is used to check for address conflicts between the target address and the reference address, promptly detecting such conflicts to prevent data loss and other problems caused by them, thus ensuring the stability and security of the bank space. After confirming no address conflicts, attribute adjustment is performed based on the attribute adjustment information. If the attribute adjustment information indicates that the target bank's bank space length address is to be adjusted, then the target bank space length address of the target bank is adjusted to the target address. If the attribute adjustment information indicates that the target bank's space operation permissions are to be adjusted, then the target space operation permissions corresponding to the target address will be adjusted. This series of steps provides a complete, secure, and efficient method for adjusting dual-bank attributes, effectively solving the problem of the lack of attribute adjustment schemes in the use of dual banks, and providing strong support for the flexible use and management of dual banks. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a dual-Bank attribute adjustment method provided in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of a dual-bank Flash storage space provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram illustrating the interaction between a CPU core and Flash storage space under a dual-bank architecture, provided in an embodiment of this application.

[0021] Figure 4This is a schematic diagram of a circuit interaction for executing a read command, provided in an embodiment of this application;

[0022] Figure 5 This is a flowchart of a read command execution provided in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of a circuit interaction for executing erase / programming commands, provided in an embodiment of this application.

[0024] Figure 7 This is a flowchart illustrating the execution of an erase / programming command according to an embodiment of this application;

[0025] Figure 8 This is a structural diagram of a dual-Bank attribute adjustment system provided in an embodiment of this application;

[0026] Figure 9 This is a structural diagram of a terminal provided in an embodiment of this application. Detailed Implementation

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0029] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0031] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0032] In specific implementations, the terminals described in the embodiments of this application include, but are not limited to, other portable devices such as mobile phones, laptop computers, or tablet computers with touch-sensitive surfaces (e.g., touchscreen displays and / or touchpads). It should also be understood that in some embodiments, the device is not a portable communication device, but a desktop computer with touch-sensitive surfaces (e.g., touchscreen displays and / or touchpads).

[0033] The following discussion describes terminals that include displays and touch-sensitive surfaces. However, it should be understood that terminals may include one or more other physical user interface devices such as physical keyboards, mice, and / or joysticks.

[0034] The terminal supports a variety of applications, such as one or more of the following: drawing applications, presentation applications, word processing applications, website creation applications, disc burning applications, spreadsheet applications, game applications, telephone applications, video conferencing applications, email applications, instant messaging applications, exercise support applications, photo management applications, digital camera applications, digital camcorder applications, web browsing applications, digital music player applications, and / or digital video player applications.

[0035] Various applications that can run on a terminal can use at least one common physical user interface device, such as a touch-sensitive surface. One or more functions of the touch-sensitive surface and the corresponding information displayed on the terminal can be adjusted and / or changed between and / or within applications. In this way, the terminal's common physical architecture (e.g., the touch-sensitive surface) can support various applications with user interfaces that are intuitive and transparent to the user.

[0036] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0037] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0038] See Figure 1 , Figure 1 This is a flowchart of a dual-Bank attribute adjustment method provided in an embodiment of this application. Figure 1 As shown, a method for adjusting dual-bank attributes includes the following steps:

[0039] Step 101: Based on attribute adjustment information, determine the target address and associated reference address of the target Bank; the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in a dual-core chip, and both the first Bank and the second Bank correspond to a Bank space length address and the space operation permissions corresponding to each address segment within the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the Bank space length address of the first Bank and / or the second Bank used for address verification with the target address.

[0040] Dual-core chips, such as dual-core electricity meter chips, have two CPU cores: a first CPU core and a second CPU core. The first CPU core corresponds to a first bank, and the second CPU core corresponds to a second bank. The first bank has access to the address space of the first bank and the spatial operation permissions for each address segment within that address space. The second bank has access to the address space of the second bank and the spatial operation permissions for each address segment within that address space.

[0041] The first bank space length address refers to the space address and size of the first bank in Flash, and the second bank space length address refers to the space address and size of the second bank.

[0042] In some embodiments, when the Bank attribute, namely the Bank space length address, is adjusted, the Bank space address changes, and the Bank space size increases, decreases, or remains unchanged.

[0043] In this application, before the dual-core chip is officially put into operation, the space length address of the first bank corresponding to the first CPU core and the space operation permissions of each address segment within the first bank space length address are pre-configured, as well as the space operation permissions of the second bank space length address of the second CPU core corresponding to the second bank and each address segment within the second bank space length address.

[0044] In some embodiments, this configured attribute information is stored in a register. Therefore, before determining the target address and associated reference address of the target Bank based on the attribute adjustment information, the method further includes: creating a register for storing the Bank space length addresses corresponding to the first Bank and the second Bank, respectively, and the space operation permissions corresponding to each address segment within the Bank space length address.

[0045] In some embodiments, registers are created in the Flash controller to store the first Bank space length address of the first Bank, the second Bank space length address of the second Bank, and the space operation permissions corresponding to each address segment within the space length address of each Bank.

[0046] In some embodiments, two types of registers are created: one is a zone management register for storing the Bank space length address, and the other is a permission management register for storing space operation permission configuration information.

[0047] In some embodiments, the first CPU core is designated as a secure CPU core. In response to the secure CPU core's region management register creation instruction, the Flash controller creates a region management register to store the first Bank space length address and the second Bank space length address. In response to the first CPU core's permission management register creation instruction, the Flash controller creates a first permission management register to store the space operation permissions corresponding to each address segment within the first Bank space length address, i.e., the first space operation permissions. In response to the second CPU core's permission management register creation instruction, the Flash controller creates a second permission management register to store the space operation permissions corresponding to each address segment within the second Bank space length address, i.e., the second space operation permissions.

[0048] In some embodiments, according to the usage requirements of each CPU core, the Flash storage space in the dual-core chip is pre-divided, and a Bank space is configured for each CPU core. The starting address of the first Bank, CPU1_start_addr, and the ending address of the first Bank, CPU1_end_addr, are defined in the Flash storage space. The starting address of the second Bank, CPU2_start_addr, and the ending address of the second Bank, CPU2_end_addr, are also defined, thus obtaining the first Bank corresponding to the first CPU core and the second Bank corresponding to the second CPU core. The first Bank is a spatially contiguous Bank, and the second Bank is also a spatially contiguous Bank. Specifically, CPU1_start_addr - CPU1_end_addr is the spatial length address of the first Bank, and CPU2_start_addr - CPU2_end_addr is the spatial length address of the second Bank.

[0049] In some embodiments, the first bank and the second bank are banks with contiguous addresses but non-overlapping spaces, or the first bank and the second bank are banks with non-contiguous addresses and non-overlapping spaces.

[0050] In some implementations, bank space is partitioned according to a set granularity, such as 8KB. This set granularity is determined by considering customer requirements and circuit costs. The size of each bank is a positive integer multiple of the set granularity. Partitioning space based on this set granularity improves the finer detail of chip management.

[0051] In some embodiments, the first bank space length address of the first bank and the second bank space length address of the second bank are stored in a region management register, which provides support for bank region management. Address comparison is performed during attribute adjustments and read / write operations. During attribute adjustments, the space length address attribute can be adjusted simply by modifying the predefined attribute information stored in the register.

[0052] After determining the Bank corresponding to each CPU core, the space operation permissions for each address segment in each Bank are configured. The space operation permissions include read, write, erase, and program permissions.

[0053] In some embodiments, the first space operation permissions of each address segment within the first Bank space length address of the first Bank are stored in the first permission management register, and the second space operation permissions of each address segment within the second Bank space length address of the second Bank are stored in the second permission management register. Independent permission management registers allow for independent configuration and management of the address segments of each Bank. By storing the space operation permissions of different Banks in separate permission management registers, partitioned permission control is achieved. During dual-core chip upgrades, expansions, or modifications, permission adjustments can be made more flexibly without affecting the normal operation of the other Bank, effectively preventing potential permission leaks or out-of-bounds access and improving security. Simultaneously, storing permission information in registers can accelerate the permission check process, reduce delays caused by permission checks, optimize access control logic, and improve overall chip performance.

[0054] By configuring the Bank space and the permissions of each address range in the Bank space, we can achieve scientific and efficient management of Flash storage space and Bank resources.

[0055] like Figure 2 As shown, Figure 2 This is a schematic diagram of a dual-bank Flash storage space provided in an embodiment of this application. Figure 2 It can be seen that the Flash storage space includes the first Bank, the second Bank, and free space.

[0056] also, Figure 2 The document also shows the starting address of the first bank (CPU1_start_addr) and the ending address of the first bank (CPU1_end_addr), the starting address of the second bank (CPU2_start_addr) and the ending address of the second bank (CPU2_end_addr), as well as the space operation permissions for each address segment in the first and second banks. Figure 2 In the diagram, CPU1_start_addr-CPU1_end_addr represents the address space length of the first bank (first bank), and CPU2_start_addr-CPU2_end_addr represents the address space length of the second bank (second bank). This diagram only shows the configuration of erase and programmable permissions. "Erasable / Programmable" means that the corresponding address range can be erased and programmed, i.e., it has erase and programmable permissions configured. "Non-erasable / Programmable" means that the corresponding address range cannot be erased and programmed, i.e., it does not have erase and programmable permissions configured.

[0057] in, Figure 2The first Bank's start address CPU1_start_addr and end address CPU1_end_addr, the second Bank's start address CPU2_start_addr and end address CPU2_end_addr, and the erase programming permissions for each address segment in the first and second banks are all stored in registers.

[0058] like Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the interaction between a CPU core and Flash storage space under a dual-bank architecture, as provided in an embodiment of this application. Each CPU core has its corresponding registers and Bank space. Figure 3 In the first bank, the start address (CPU1_start_addr) and end address (CPU1_end_addr) of the first bank, and the start address (CPU2_start_addr) and end address (CPU2_end_addr) of the second bank, are stored in the region management register. The erase programming permission configuration information for each address segment in the first bank is stored in the first permission management register. The erase programming permission configuration information for each address segment in the second bank is stored in the second permission management register. The Flash controller manages the attributes of the first and second banks in the Flash storage space through these registers.

[0059] When adjusting the attributes later, you can directly modify the relevant attribute configuration information in the register.

[0060] When executing commands such as read and erase / program commands, the attribute configuration information in the registers is required. The following sections will introduce two example scenarios.

[0061] First example scenario: Read command scenario. In the following example scenario, the read permissions for each address range of the Bank are the inherent configured permissions for each address range of the Bank. No read permission check is required when responding to a read command.

[0062] like Figure 4 As shown, Figure 4 This is a schematic diagram of a circuit interaction for executing a read command, provided in an embodiment of this application.

[0063] When the Flash controller receives a read command from either the first or second CPU core, it decodes the command to obtain a read command signal and an address signal, the latter containing the access address. The read command signal is then sent to the address comparison unit and the command generation unit. The address comparison unit, activated by the read command signal, performs an address comparison, comparing the received address signal with the address transmitted by the region management register. If the read command originates from the first CPU core, the comparison is made with the address of the first bank space length in the region management register; if the read command originates from the second CPU core, the comparison is made with the address of the second bank space length in the region management register. Additionally, the address signal is also simultaneously sent to the Flash signal control unit.

[0064] When the address signal is within the Bank space length address corresponding to the source CPU core, the address signal is deemed valid, and a valid address signal is sent to the command generation unit and the output data generation unit. At this time, the command generation unit determines that the read command signal is valid and transmits the valid read command signal to the Flash signal control unit.

[0065] At this point, the Flash signal control unit receives the address signal and the valid read command signal from the command generation unit. It then controls the corresponding signal circuit via the Flash control signal to read the data corresponding to the access address from the Flash memory space, thus obtaining the Flash output data. This Flash output data is then transmitted to the output data generation unit. Finally, the output data generation unit sends the Flash output data as output data to the corresponding source CPU core—either the first CPU core or the second CPU core—thus completing the read command.

[0066] When the address signal is not within the Bank space length address corresponding to the source CPU core, it indicates that the address signal is invalid, and the command generation unit and output data generation unit will not receive a valid address signal. In this case, the command generation unit cannot generate and output a valid read command signal to the Flash signal control unit. The Flash signal control unit receives the address signal but does not receive a valid read command signal; therefore, the Flash signal control unit does not start and does not execute the read command operation. The output data generation unit generates spurious data, such as all zeros, and sends it as output data to the corresponding source CPU core, thus avoiding erroneous operations and ensuring the complete execution of the read command.

[0067] like Figure 5 As shown, Figure 5 This is a flowchart of a read command execution provided in an embodiment of this application. Figure 5The execution process of the read command is clearly demonstrated. The access address is the address indicated by the address signal, the specified area is the Bank space length address of the Bank corresponding to the source CPU sending the read command—either the first CPU core or the second CPU core, and the data corresponding to the address signal is the Flash output data.

[0068] By managing the Bank space length addresses corresponding to the first and second CPU cores separately through region management registers, fine-grained partitioning and efficient management of Flash storage space are achieved. This management method enables CPU cores to accurately and quickly access their corresponding storage regions, improving data access efficiency.

[0069] The design of the address comparison unit and registers effectively prevents illegal or out-of-bounds data reading, enhancing the security and stability of the bank.

[0070] The second example scenario: erase / programming commands.

[0071] like Figure 6 As shown, Figure 6 This is a schematic diagram of a circuit interaction for executing erase / programming commands, provided in an embodiment of this application.

[0072] When the Flash controller receives an erase / program command from either the first or second CPU core, it decomposes the erase / program command to obtain an erase / program command signal and an address signal. The erase / program command signal is then sent to the address comparison unit and the command generation unit. The address comparison unit, activated by the erase / program command signal, performs an address comparison function, comparing the received address signal with the address transmitted by the region management register. Similarly, if the erase / program command originates from the first CPU core, the comparison is made with the address of the first bank space length in the information transmitted by the region management register; if the erase / program command originates from the second CPU core, the comparison is made with the address of the second bank space length in the information transmitted by the region management register. Simultaneously, the address signal is also sent to the Flash signal control unit. If the command is specifically a programming command, decomposing the programming command will also yield a data signal, which is sent to the Flash signal control unit along with the address signal.

[0073] When the address signal is within the Bank space length address corresponding to the Bank of its source CPU core, the address signal is deemed valid, and a valid address signal is sent to the permission check unit. The permission check unit, upon receiving the address signal and the valid address signal, checks whether the access address indicated by the address signal has erase / programming permissions based on the space operation permission configuration information transmitted by the permission management register corresponding to the source CPU. If it does, a valid permission signal is sent to the command generation unit. In this case, the command generation unit determines that the erase / programming command signal is valid and transmits it to the Flash signal control unit. The Flash signal control unit receives the address signal and the valid erase / programming command signal from the command generation unit, indicating that the erase / programming command is valid. The Flash signal control unit controls the corresponding signal circuits via Flash control signals to perform programming / erasing operations on the address segment corresponding to the address signal in the Flash memory space. This means erasing the data in the address segment corresponding to the address signal in the Flash memory space, or writing data signals into the address segment corresponding to the address signal in the Flash memory space through programming operations.

[0074] When the address signal is not within the Bank space length address corresponding to the source CPU core, the address signal is invalid, that is, the erase / program command is invalid, and the permission check unit, command generation unit and Flash signal control unit will not be enabled.

[0075] If the address range corresponding to the address signal does not have erase / programming permissions, the erase / programming permission signal is invalid, that is, the erase / programming command is invalid, and the command generation unit and the Flash signal control unit will not be enabled.

[0076] like Figure 7 As shown, Figure 7 This is a flowchart of an erase / programming command execution provided in an embodiment of this application. Figure 7 The execution process of erase / programming commands is demonstrated. The access address is the address indicated by the address signal, and the defined area is the length of the Bank space corresponding to the Bank of the source CPU that sent the erase / programming command—either the first CPU core or the second CPU core.

[0077] Through a rigorous address verification and permission check mechanism, problems such as operation failure or system crashes caused by address errors or insufficient permissions are effectively avoided, thereby improving the reliability and stability of chip operation.

[0078] This application allows for the adjustment of Bank attributes during the use of the first Bank and the second Bank.

[0079] Upon receiving attribute adjustment information, the target bank to be adjusted is determined based on the source of the attribute adjustment information. The target address corresponding to the attribute to be adjusted in the target bank is determined from the attribute adjustment information, and the reference address required for verification is determined based on the attribute to be adjusted in the target bank.

[0080] Different attributes to be adjusted correspond to different types of target addresses. If the current attribute to be adjusted is a space length address, then the target address is the expected Bank space length address given in the attribute adjustment information. If the current attribute to be adjusted is a space operation permission, then the target address is one or more address ranges corresponding to the target space operation permission given in the attribute adjustment information.

[0081] Different attributes to be adjusted correspond to different reference addresses. If the attribute to be adjusted is a space length address, the reference addresses are the used space length address of the target bank and the bank space length address of another bank. If the attribute to be adjusted is a space operation permission, the reference address is the bank space length address of the target bank. The address segment corresponding to the used space length address stores data information.

[0082] In some embodiments, the target Bank is the first Bank, and determining the target address and associated reference address of the target Bank based on attribute adjustment information includes: if the attribute adjustment information indicates that the first Bank space length address of the first Bank is adjusted, then extracting the desired Bank space length address from the attribute adjustment information, and obtaining the used first space length address of the first Bank and the second Bank space length address of the second Bank as the reference address.

[0083] In some embodiments, the target Bank is the second Bank, and determining the target address and associated reference address of the target Bank based on attribute adjustment information includes: if the attribute adjustment information indicates that the second Bank space length address of the second Bank is adjusted, then the desired Bank space length address is extracted from the attribute adjustment information, and the used second space length address of the second Bank and the first Bank space length address of the first Bank are obtained as the reference address.

[0084] In some embodiments, the target Bank is the first Bank, and determining the target address and associated reference address of the target Bank based on attribute adjustment information includes: if the attribute adjustment information indicates that the first space operation permission of the first Bank is adjusted, then extracting the one or more address segments from the attribute adjustment information and determining the first Bank space length address of the first Bank as the reference address.

[0085] In some embodiments, the target Bank is the second Bank, and determining the target address and associated reference address of the target Bank based on attribute adjustment information includes: if the attribute adjustment information indicates that the second space operation permissions of the second Bank are adjusted, then extracting the one or more address segments from the attribute adjustment information and determining the second Bank space length address of the second Bank as the reference address.

[0086] In some embodiments, the attribute adjustment information may contain two different attributes to be adjusted simultaneously. The adjustment priority of the target bank space length address of the target bank is higher than the adjustment priority of the target space operation permission. The step of determining the target address and associated reference address of the target bank based on attribute adjustment information includes: upon first receiving the attribute adjustment information, if the attribute adjustment information indicates adjustment of the target bank space length address of the target bank and adjustment of the target space operation permission of the target bank, then the desired bank space length address in the attribute adjustment information is determined as the first target address, and the used space length address of the target bank and the bank space length address of another bank are determined as the first reference address; if the target bank space length address of the target bank is adjusted to the first target address, the one or more address segments corresponding to the target space operation permission in the attribute adjustment information are determined as the second target address, and the first target address is determined as the second reference address; or, if there is an address conflict between the first target address and the first reference address, the one or more address segments corresponding to the target space operation permission in the attribute adjustment information are determined as the second target address, and the target bank space length address of the target bank is determined as the second reference address.

[0087] Wherein, when the target bank is the first bank, the other bank is the second bank; when the target bank is the second bank, the other bank is the first bank.

[0088] After receiving the attribute adjustment information for the first time, when it is detected that the attribute adjustment information requires adjustment of the Bank space length address of the target Bank and the space operation permissions of certain address segments, the principle that the adjustment priority of the target Bank space length address is higher than the adjustment priority of the target space operation permissions must be followed. At this time, the adjustment confirmation of the Bank space length address attribute of the target Bank is performed first, that is, the target address and reference address under this attribute are determined, the first target address, namely the expected Bank space length address and the first reference address, are obtained, and step 102 is executed. If there is no address conflict, step 103 is executed; if there is an address conflict, no adjustment is made.

[0089] When the target Bank's space length address is adjusted to the first target address, or when there is an address conflict between the first target address and the first reference address, the adjustment and confirmation of the target Bank's space operation permission attribute is performed. That is, the target address and reference address under the space operation permission attribute are determined. For ease of distinction, these are referred to as the second target address and the second reference address. The second target address is one or more address segments, and the second reference address is the target Bank's current Bank space length address.

[0090] When there is an address conflict between the first target address and the first reference address, the Bank space length address of the target Bank remains unchanged. In this case, the current Bank space length address of the target Bank is still the target Bank space length address, meaning the second reference address is the target Bank space length address. When the target Bank space length address is adjusted to the first target address, the Bank space length address of the target Bank changes from the original target Bank space length address to the desired Bank space length address. In this case, the current Bank space length address of the target Bank is the desired Bank space length address, meaning the second reference address is the desired Bank space length address.

[0091] When attribute adjustment information involves adjusting both attributes of the target Bank, the adjustment and confirmation of the Bank space length address are performed first. This provides the correct reference address for the subsequent space operation permission adjustment and confirmation process. Then, the space operation permission adjustment and confirmation are performed promptly to ensure data security and improve chip operating efficiency. Through a clear operation sequence and timely confirmation mechanism, operational confusion or data errors caused by improper attribute adjustment order are avoided, enhancing the stability and reliability of attribute adjustment.

[0092] Step 102: Check whether there is an address conflict between the target address and the reference address.

[0093] After obtaining the target address and the reference address, an address comparison is performed to check for address conflicts, i.e., to check whether the attribute adjustment operation is compliant.

[0094] Before adjusting the Bank space length address attribute, it is necessary to check whether the adjustment operation will cause the loss of data in the original Bank space of the target Bank, and whether it will encroach on the Bank space of another Bank. The attribute adjustment operation can only be performed if there is no data loss and no space encroachment.

[0095] In some embodiments, the target bank is a first bank, and the attribute to be adjusted is the bank space length address of the target bank. The step of checking whether there is an address conflict between the target address and the reference address includes: checking whether the expected bank space length address contains the used first space length address of the first bank, and checking whether the expected bank space length address is located within the second bank space length address of the second bank. If the expected bank space length address contains the used first space length address of the first bank, and the expected bank space length address is not located within the second bank space length address of the second bank, then it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0096] In some embodiments, the target bank is a second bank, and the attribute to be adjusted is the bank space length address of the target bank. The step of checking whether there is an address conflict between the target address and the reference address includes: checking whether the expected bank space length address contains the used second space length address of the second bank, and checking whether the expected bank space length address is located within the first bank space length address of the first bank. If the expected bank space length address contains the used second space length address of the second bank, and the expected bank space length address is not located within the first bank space length address of the first bank, then it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0097] The address ranges involved in configuring and adjusting the space operation permissions of a bank must not exceed the address range limited by the bank's space length address. Before adjusting this attribute, it is necessary to verify that the address range to be adjusted is within the target bank's space length address range.

[0098] In some embodiments, the target Bank is a first Bank, and the attribute to be adjusted is the spatial operation permission of the target Bank. The step of checking whether there is an address conflict between the target address and the reference address includes: checking whether one or more address segments are located within the first Bank's spatial length address; if they are, then it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0099] In some embodiments, the target bank is a second bank, and the attribute to be adjusted is the spatial operation permission of the target bank. The step of checking whether there is an address conflict between the target address and the reference address includes: checking whether one or more address segments are located within the second bank's spatial length address; if they are, then it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0100] Step 103: If there is no address conflict, adjust the target Bank space length address of the target Bank to the target address based on the attribute adjustment information, or adjust the target space operation permissions corresponding to the target address.

[0101] In the absence of address conflicts, the target Bank can be adjusted by making the corresponding attributes, thus realizing the dynamic adjustment of the Bank space length address and the Bank space operation permissions.

[0102] If the instruction is to adjust the Bank space length address of the target Bank, and there is no conflict between the target address and the reference address, then the Bank space length address will be adjusted. For example, if the target Bank space length address is address1-address332, and the desired Bank space length address is address64-address490, then the target Bank's Bank space length address will be adjusted from address1-address332 to address64-address490.

[0103] If the instruction is to adjust the space operation permissions of the target bank, and there is no conflict between the target address and the reference address, then the space operation permissions for the corresponding address range will be adjusted. The space operation permission adjustment is either enabling or disabling the permission. For example, "0" indicates disabled permission, and "1" indicates enabled permission. If the target addresses are address ranges A and B, and the erase / programming permissions for address ranges A and B are changed to disabled, then the erase / programming permissions for address ranges A and B will be changed from "1" to "0". In practical applications, when the permissions for certain address ranges are disabled (i.e., changed to non-erasable programming), the data in these address ranges in the Flash memory cannot be erased or programmed; that is, the data stored in these address ranges cannot be modified, ensuring data security.

[0104] In some embodiments, the configuration information of the Bank space length address and space operation permissions is stored in a register. The step of adjusting the target Bank space length address of the target Bank to the target address based on the attribute adjustment information when there is no address conflict, or adjusting the target space operation permissions corresponding to the target address, includes: changing the target Bank space length address of the target Bank in the register to the desired Bank space length address when there is no address conflict, or modifying the target space operation permissions corresponding to one or more address segments of the target Bank in the register.

[0105] Adjusting the dual-bank attribute configuration information in the registers makes attribute adjustment more convenient. After the dual-bank attributes are adjusted, the registers send the updated attribute configuration information to the address comparison unit, enabling more precise or efficient memory access control based on the new configuration, thus improving the flexibility and responsiveness of chip applications.

[0106] This application provides a method for adjusting the attributes of dual banks, which allows for the adjustment of dual bank attributes during the use of dual-core chips, greatly improving the flexibility and security of dual-core chip applications.

[0107] In this embodiment, when handling the dual-bank attribute adjustment problem, the target bank, its target address, and associated reference address are first determined based on the attribute adjustment information. The target bank is either the first bank corresponding to the first CPU core or the second bank corresponding to the second CPU core in a dual-core chip. Both the first and second banks have corresponding bank space length addresses and space operation permissions corresponding to each address segment within those bank space length addresses. The target address is the expected bank space length address given by the attribute adjustment information, or it can be one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information. The reference address is the bank space length address of the first bank and / or the second bank used for address verification with the target address. Subsequently, address comparison is used to check for address conflicts between the target address and the reference address, promptly detecting such conflicts to prevent data loss and other problems caused by them, thus ensuring the stability and security of the bank space. After confirming no address conflicts, attribute adjustments are performed based on the attribute adjustment information. If the attribute adjustment information indicates that the target bank's bank space length address is to be adjusted, then the target bank space length address of the target bank is adjusted to the target address. If the attribute adjustment information indicates that the target bank's space operation permissions are to be adjusted, then the target space operation permissions corresponding to the target address will be adjusted. This series of steps provides a complete, secure, and efficient method for adjusting dual-bank attributes, effectively solving the problem of the lack of attribute adjustment schemes in the use of dual banks, and providing strong support for the flexible use and management of dual banks.

[0108] See Figure 8 , Figure 8 This is a structural diagram of a dual-bank attribute adjustment system provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0109] The dual-Bank attribute adjustment system 800 includes: a determination module 801, a verification module 802, and an adjustment module 803.

[0110] The determining module 801 is used to determine the target address and associated reference address of the target Bank based on attribute adjustment information; the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in a dual-core chip, and both the first Bank and the second Bank correspond to a Bank space length address and the space operation permissions corresponding to each address segment within the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the Bank space length address of the first Bank and / or the second Bank used for address verification with the target address.

[0111] The verification module 802 is used to verify whether there is an address conflict between the target address and the reference address.

[0112] The adjustment module 803 is used to adjust the target Bank space length address of the target Bank to the target address based on the attribute adjustment information when there is no address conflict, or to adjust the target space operation permissions corresponding to the target address.

[0113] In some embodiments, the target Bank is the first Bank, and the determining module is specifically used for:

[0114] If the attribute adjustment information indicates that the first bank space length address of the first bank should be adjusted, then the desired bank space length address is extracted from the attribute adjustment information, and the used first space length address of the first bank and the second bank space length address of the second bank are obtained as the reference address.

[0115] In some embodiments, the inspection module is specifically used for:

[0116] Check whether the expected Bank space length address contains the used first space length address of the first Bank, and check whether the expected Bank space length address is located within the second Bank space length address of the second Bank;

[0117] If the expected Bank space length address includes the used first space length address of the first Bank, and the expected Bank space length address is not located within the second Bank space length address of the second Bank, then it is determined that there is no address conflict.

[0118] In some embodiments, the target Bank is the first Bank, and the determining module is further configured to:

[0119] If the attribute adjustment information indicates that the first space operation permission of the first Bank is adjusted, then the one or more address segments are extracted from the attribute adjustment information, and the first Bank space length address of the first Bank is determined as the reference address.

[0120] In some embodiments, the inspection module is further configured to:

[0121] Verify whether the one or more address segments are located within the first Bank space length address of the first Bank;

[0122] If it is located, then it is determined that there is no address conflict.

[0123] In some embodiments, the adjustment priority of the target Bank space length address of the target Bank is higher than the adjustment priority of the target space operation permission, and the determining module is further configured to:

[0124] Upon first receiving the attribute adjustment information, if the attribute adjustment information indicates that the target bank space length address of the target bank is adjusted, and the target space operation permission of the target bank is adjusted, then the desired bank space length address in the attribute adjustment information is determined as the first target address, and the used space length address of the target bank and the bank space length address of another bank are determined as the first reference address;

[0125] When the target Bank space length address of the target Bank is adjusted to the first target address, the one or more address segments corresponding to the target space operation permission in the attribute adjustment information are determined as the second target address, and the first target address is determined as the second reference address; or, when there is an address conflict between the first target address and the first reference address, the one or more address segments corresponding to the target space operation permission in the attribute adjustment information are determined as the second target address, and the target Bank space length address of the target Bank is determined as the second reference address.

[0126] In some embodiments, the dual-bank attribute adjustment system further includes a creation module, the creation module being used for:

[0127] Create a register for storing the Bank space length addresses corresponding to the first Bank and the second Bank respectively, and the space operation permissions corresponding to each address segment within the Bank space length address;

[0128] In some embodiments, the adjustment module is specifically used for:

[0129] In the absence of address conflict, change the target Bank space length address in the register to the desired Bank space length address, or modify the target space operation permissions corresponding to one or more address segments of the target Bank in the register.

[0130] The dual-Bank attribute adjustment system provided in this application can implement all the processes of the above-described dual-Bank attribute adjustment method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0131] Figure 9 This is a structural diagram of a terminal provided in an embodiment of this application. As shown in the figure, the terminal 9 of this embodiment includes: at least one processor 90 ( Figure 9 (Only one is shown in the diagram), memory 91, and computer program 92 stored in said memory 91 and executable on said at least one processor 90, which, when executed, implements the steps in any of the above method embodiments.

[0132] The terminal 9 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. The terminal 9 may include, but is not limited to, a processor 90 and a memory 91. Those skilled in the art will understand that... Figure 9 This is merely an example of terminal 9 and does not constitute a limitation on terminal 9. It may include more or fewer components than shown, or combine certain components, or different components. For example, the terminal may also include input / output devices, network access devices, buses, etc.

[0133] The processor 90 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0134] The memory 91 can be an internal storage unit of the terminal 9, such as a hard disk or memory of the terminal 9. The memory 91 can also be an external storage device of the terminal 9, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the terminal 9. Furthermore, the memory 91 can include both internal storage units and external storage devices of the terminal 9. The memory 91 is used to store the computer program and other programs and data required by the terminal. The memory 91 can also be used to temporarily store data that has been output or will be output.

[0135] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0136] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0137] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0138] In the embodiments provided in this application, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0139] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0140] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0141] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0142] The methods described in this application can be implemented in whole or in part by a computer program product. When the computer program product is run on a terminal, the terminal executes the steps in the various method embodiments described above.

[0143] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for adjusting dual-Bank attributes, characterized in that, The method includes: Based on attribute adjustment information, the target address and associated reference address of the target bank are determined; the target bank is the first bank corresponding to the first CPU core or the second bank corresponding to the second CPU core in a dual-core chip, and both the first bank and the second bank correspond to a bank space length address and space operation permissions corresponding to each address segment within the bank space length address; the target address is the expected bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the bank space length address of the first bank and / or the second bank used for address verification with the target address; Check whether there is an address conflict between the target address and the reference address; the check whether there is an address conflict between the target address and the reference address includes: checking whether the target address causes data loss in the Bank space of the target Bank, and whether it encroaches on the Bank space of another Bank; or, checking whether the target address is located within the target Bank space length address of the target Bank; In the absence of address conflicts, based on the attribute adjustment information, the target Bank space length address of the target Bank is adjusted to the target address, or the operation permissions of the target space corresponding to the target address are adjusted.

2. The method according to claim 1, characterized in that, The target bank is the first bank, and the step of determining the target address and associated reference address of the target bank based on attribute adjustment information includes: If the attribute adjustment information indicates that the first bank space length address of the first bank should be adjusted, then the desired bank space length address is extracted from the attribute adjustment information, and the used first space length address of the first bank and the second bank space length address of the second bank are obtained as the reference address.

3. The method according to claim 2, characterized in that, The step of checking whether there is an address conflict between the target address and the reference address includes: Check whether the expected Bank space length address contains the used first space length address of the first Bank, and check whether the expected Bank space length address is located within the second Bank space length address of the second Bank; If the expected Bank space length address includes the used first space length address of the first Bank, and the expected Bank space length address is not located within the second Bank space length address of the second Bank, then it is determined that there is no address conflict.

4. The method according to claim 1, characterized in that, The target bank is the first bank, and the step of determining the target address and associated reference address of the target bank based on attribute adjustment information includes: If the attribute adjustment information indicates that the first space operation permission of the first Bank is adjusted, then the one or more address segments are extracted from the attribute adjustment information, and the first Bank space length address of the first Bank is determined as the reference address.

5. The method according to claim 4, characterized in that, The step of checking whether there is an address conflict between the target address and the reference address includes: Verify whether the one or more address segments are located within the first Bank space length address of the first Bank; If it is located, then it is determined that there is no address conflict.

6. The method according to claim 1, characterized in that, The adjustment priority of the target bank's space length address is higher than the adjustment priority of the target space operation permissions. The step of determining the target address and associated reference address of the target bank based on attribute adjustment information includes: Upon first receiving the attribute adjustment information, if the attribute adjustment information indicates that the target bank space length address of the target bank is adjusted, and the target space operation permission of the target bank is adjusted, then the desired bank space length address in the attribute adjustment information is determined as the first target address, and the used space length address of the target bank and the bank space length address of another bank are determined as the first reference address; When the target Bank space length address of the target Bank is adjusted to the first target address, the one or more address segments corresponding to the target space operation permission in the attribute adjustment information are determined as the second target address, and the first target address is determined as the second reference address; or, when there is an address conflict between the first target address and the first reference address, the one or more address segments corresponding to the target space operation permission in the attribute adjustment information are determined as the second target address, and the target Bank space length address of the target Bank is determined as the second reference address.

7. The method according to claim 1, characterized in that, Before determining the target address and associated reference address of the target bank based on attribute adjustment information, the process also includes: Create a register for storing the Bank space length addresses corresponding to the first Bank and the second Bank respectively, and the space operation permissions corresponding to each address segment within the Bank space length address; In the absence of address conflicts, the method of adjusting the target Bank space length address of the target Bank to the target address based on the attribute adjustment information, or adjusting the target space operation permissions corresponding to the target address, includes: In the absence of address conflict, change the target Bank space length address in the register to the desired Bank space length address, or modify the target space operation permissions corresponding to one or more address segments of the target Bank in the register.

8. A dual-Bank attribute adjustment system, characterized in that, include: The determination module is used to determine the target address and associated reference address of the target bank based on attribute adjustment information; The target Bank is either the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in a dual-core chip. Both the first Bank and the second Bank have a corresponding Bank space length address and space operation permissions corresponding to each address segment within the Bank space length address. The target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information. The reference address is the Bank space length address of the first Bank and / or the second Bank used for address verification with the target address. The verification module is used to verify whether there is an address conflict between the target address and the reference address; The step of checking whether there is an address conflict between the target address and the reference address includes: checking whether the target address causes data loss in the Bank space of the target Bank, and whether it encroaches on the Bank space of another Bank; or, checking whether the target address is located within the target Bank space length address of the target Bank. The adjustment module is used to adjust the target Bank space length address of the target Bank to the target address based on the attribute adjustment information when there is no address conflict, or to adjust the target space operation permissions corresponding to the target address.

9. A terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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