Memory management communication interface and method oriented to network-on-chip and SRIO protocol

Abstract

The invention relates to a memory management communication interface and method oriented to a network-on-chip and an SRIO protocol. The memory management communication interface comprises a main interface module, a slave interface module and an output control module. On one hand, the memory management communication interface can receive a request in an AXI bus form from the SRIO, package the request into a request packet oriented to a network-on-chip form, send the request packet to the storage particles through the network-on-chip, control the storage particles to perform memory management and read-write operation, receive a response packet indicating whether the operation is successful through the network-on-chip after the operation is completed, and send the response packet to the SRIO; unpacking the response into a response in an AXI bus form, and sending the response to the SRIO; on one hand, a read-write request packet sent by a host through a network-on-chip can be received, a request in an AXI bus form is unpacked and sent to the SRIO, after completion, a response in the AXI bus form from the SRIO is received, the response packet is converted into a response packet oriented to the network-on-chip type, and the response packet is sent to the host initiating the request through the network-on-chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit communication technology, and in particular to a memory management communication interface and method oriented to an on-chip network and SRIO protocol. Background Art

[0002] In recent years, the development cost of integrated circuit chips has increased dramatically due to Moore's Law. In certain fields, the emergence of chiplet technology has greatly shortened the chip design and manufacturing cycle. This technology relies on the on-chip network to interconnect and integrate different bare chips. SRIO accesses remote storage particles through the communication interface and the on-chip network for read and write operations.

[0003] However, this type of communication interface currently has the problem of low storage resource utilization when accessing remote storage particles. When multiple hosts access storage particles through the on-chip network, the data that has been written is easily illegally accessed and changed. Therefore, there is an urgent need to provide a memory management communication interface for the on-chip network and SRIO protocol to solve this problem. When the on-chip network transmits multiple host requests, the storage resource utilization can be improved, thereby improving the performance of the multi-chip interconnection network system. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a memory management communication interface for on-chip network and SRIO protocol, wherein the memory management communication interface is connected to SRIO, and is connected to storage particles and a host respectively through the on-chip network. The memory management communication interface includes:

[0005] Slave interface module; the slave interface module includes a slave logic judgment unit and a slave data conversion unit. The slave data conversion unit receives application, sharing, release, read and write requests through AW and W channels in the form of AXI bus, parses out the necessary information of a request event such as event type, event code, event address and write data, and encapsulates it into a specified format and writes it to the slave logic judgment unit; the slave data conversion unit will initiate a request acceptance notification after completely receiving a write-related request;

[0006] Main interface module; the main interface module includes a main logic judgment unit and a main data conversion unit. The main data conversion unit receives the necessary information of the write request from the main logic judgment unit, initiates transmission to the write request address through the AXImAW channel, and writes the write data to SRIO through the AXImW channel; when the write request is completed, initiates transmission to the AXI address of the write request information notification given during the initial configuration through the AXImAW channel, and sends the content of the write request information notification to SRIO through the AXImW channel;

[0007] Output control module; for request packets from the slave interface module, including application, sharing, release, write, and read request packets, for confirmation packets from the master interface module, including application response packets, memory access response packets, write response packets, and read confirmation packets, and for read response packets from the master interface module, multiplexing is performed to resolve output conflicts.

[0008] In one embodiment of the present invention, the memory management communication interface, on the one hand, receives a request in the form of an AXI bus from SRIO, packages it into a request packet in the form of an on-chip network, sends it to storage particles through the on-chip network, controls the storage particles to perform memory management and read and write operations, and after completion, receives a response packet whether the operation is successful through the on-chip network, unpacks it into a response in the form of an AXI bus, and sends it to SRIO; on the other hand, it accepts a read and write request packet sent by the host through the on-chip network, unpacks it into a request in the form of an AXI bus, and sends it to SRIO. After completion, it receives a response in the form of an AXI bus from SRIO, converts it into a response packet oriented to the on-chip network type, and sends it to the host that initiated the request through the on-chip network.

[0009] In one embodiment of the present invention, the data input and output port in the form of AXI bus in the slave interface module is connected to SRIO, and the data output port in the form of on-chip network is connected to the output control module; the data input and output port in the form of AXI bus of the master interface module is connected to SRIO, the data output port in the form of on-chip network is connected to the output control module, and the data input port in the form of on-chip network is connected to the on-chip network.

[0010] In one embodiment of the present invention, the data input and output port in the form of AXI bus in the slave interface module is connected to SRIO, and the data output port in the form of on-chip network is connected to the output control module; the data input and output port in the form of AXI bus of the master interface module is connected to SRIO, the data output port in the form of on-chip network is connected to the output control module, and the data input port in the form of on-chip network is connected to the on-chip network.

[0011] In one embodiment of the present invention, the slave logic judgment unit is composed of address mapping logic, data encapsulation logic, retransmission logic, and a read control state machine;

[0012] The slave logic judgment unit receives the on-chip network coding configuration information from the data conversion unit to complete the configuration of the on-chip network. This information will be used as the coding of the on-chip network at the sending end and is necessary information for address mapping and data packet encapsulation; receives the necessary information for application, sharing, release, read, and write request events from the slave data conversion unit, completes address mapping based on the parsed information, encapsulates the data packet into a request packet in the form of an on-chip network and outputs it; caches the output request packet in the retransmission buffer, and counts after the output is completed. If the occupancy release notification is not received within the set time, retransmission is triggered, and the data packet in the retransmission buffer is output again. After the retransmission, timing will be performed again. If the occupancy release notification is still not received within the set time after the retransmission, a retransmission failure notification signal is sent. Only when the occupancy of the retransmission buffer ends, the slave logic judgment unit will continue to receive request information from the slave data conversion unit to encapsulate and output the next data packet.

[0013] In one embodiment of the present invention, the master port of the AXI bus in the master data conversion unit is interconnected with the slave port of SRIO, the input and output ports of the master data conversion unit and the slave data conversion unit are interconnected, the master data conversion unit and the input and output ports of the master logic judgment unit are interconnected, the main logic judgment unit and the input and output ports of the slave logic judgment unit are interconnected, the output port of the main logic judgment unit is connected to the output control module, and the input port of the main logic judgment unit is connected to the output port of the on-chip network.

[0014] In one embodiment of the present invention, the main logic judgment unit is composed of verification logic, memory management logic, unpacking and data encapsulation logic, confirmation packet generation logic, read response generation logic, occupation / retransmission handshake logic, and main interface logic judgment control state machine. The main logic judgment unit receives confirmation packets through the input port of the on-chip network, including application response packets, memory access response packets, write response packets, and read confirmation packets. After unpacking and verification, it will send occupation release notification information to the slave logic judgment unit, thereby releasing the occupation of the retransmission buffer in the slave logic judgment unit, and write the occupation release notification information into the main data conversion unit; through the on-chip network The input port receives the read response packet and the shared interrupt packet, unpacks and verifies them, and then writes the necessary information into the main data conversion unit; receives the read and write request packets through the input port of the on-chip network, unpacks and verifies them, and then writes the necessary information into the main data conversion unit, and sends the write response packet and the read confirmation packet through the output port of the on-chip network; receives the read data from the main data conversion unit, which is the read response data returned after receiving the read request, and encapsulates these data into a read response packet according to the on-chip network-oriented data format; receives the retransmission failure notification information from the logic judgment unit, and writes the necessary information of the retransmission failure packet into the main data conversion unit.

[0015] In one embodiment of the present invention, the main data conversion unit is composed of an AXImAW channel control state machine, an AXImW channel control state machine, an AXIm B channel control state machine, an AXImAR channel control state machine, an AXIm R channel control state machine, data encapsulation logic, IO interrupt logic, data parsing logic, and a main interface data conversion control state machine. The main data conversion unit receives necessary information of a read request from the main logic judgment unit, initiates transmission to the read request address through the AXImAR channel, and then reads the read data back through the AXIm R channel, encapsulates it into a specific format and writes it into the main logic judgment unit; receives necessary information of a read response from the main logic judgment unit, initiates transmission to the read response AXI address given in the initial configuration through the AXImAW channel, and sends the read response information and the read response data to the SRIO through the AXIm W channel; receives notification information from the main logic judgment unit, including retransmission failure notification information, shared write notification information, and occupation release notification information, initiates transmission to the notification information AXI address of the corresponding notification type given in the initial configuration through the AXImAW channel, and sends the notification information to the SRIO through the AXIm W channel. The W channel sends the notification information of the corresponding notification type to SRIO; receives the request received notification from the data conversion unit, initiates transmission to the AXI address of the request received notification given in the initial configuration through the AXImAW channel, and sends the content of the request received information notification to SRIO through the AXIm W channel.

[0016] In one embodiment of the present invention, the output control module performs arbitration and multi-channel selection in units of data packets; when two or more data packet header micro-chips are received at the same time, arbitration is performed according to the pre-priority, and the higher priority channel will occupy the output port before the entire data packet is output, and the data packet with a lower priority will wait for the next arbitration; the arbitration strategy is that the request that has obtained the output permission least recently will have the highest priority.

[0017] The present invention also provides a memory management communication method for on-chip network and SRIO protocol, which is implemented according to the memory management communication interface and includes the following steps:

[0018] Step S1: After each reset, the memory management communication interface receives initial configuration information from SRIO through the AXIs AW channel and the AXIs W channel, and completes on-chip network coding configuration, read response receiving address, interrupt information receiving address, retransmission failure receiving address, occupation release receiving address, shared write notification receiving address, write request notification receiving address, and request received notification receiving address;

[0019] Step S2: Receive memory management and read / write requests through the AXIs AW channel and the AXIs W channel, and package these requests into request packets for the on-chip network, including request packets for applying, sharing, releasing, reading, and writing;

[0020] Step S3: Complete the sending of write response, read data and various notification information through the AXImAW channel and the AXIm W channel. These notification information include retransmission failure notification, occupation release notification, shared write notification, write request information notification, and request received notification;

[0021] Step S4: receiving the read and write request packets through the on-chip network input port, unpacking and verifying them, and then performing corresponding operations according to the request type;

[0022] Step S5: receiving response packets, including application response packets, memory access response packets, write response packets, read confirmation packets, read response packets, and shared interrupt packets, through the on-chip network input port, unpacking and verifying, and performing corresponding operations according to the response type;

[0023] Step S6: The memory management communication interface sets a timeout retransmission function. The retransmission buffer will cache the last request packet sent through the on-chip network output port. If the corresponding response packet is not received within the set time after the request packet is sent, retransmission will be triggered and the request packet in the retransmission buffer will be sent again.

[0024] The above technical solution of the present invention has the following advantages over the prior art: the memory management communication interface described in the present invention adopts a parallel processing structure, and in the communication of a multi-chip interconnection network system, it can send memory management and read and write requests, and receive read and write requests from the host. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0026] Figure 1 It is an application scenario diagram of the memory management communication interface for on-chip network and SRIO protocol provided by the present invention.

[0027] Figure 2 It is a structural schematic diagram of a memory management communication interface for on-chip network and SRIO protocol provided by the present invention.

[0028] Figure 3 It is a structural schematic diagram of the slave logic conversion unit provided by the present invention.

[0029] Figure 4 It is a structural schematic diagram of the slave data conversion unit provided by the present invention.

[0030] Figure 5 It is a structural schematic diagram of the main logic conversion unit provided by the present invention.

[0031] Figure 6 It is a structural schematic diagram of the master data conversion unit provided by the present invention. DETAILED DESCRIPTION

[0032] Embodiment 1

[0033] like Figure 1 and Figure 2 As shown, this embodiment provides a memory management communication method for on-chip network and SRIO protocol, which is implemented according to the memory management communication interface and includes the following steps:

[0034] Step S1: After each reset, the memory management communication interface receives initial configuration information from SRIO through the AXIsAW channel and the AXIsW channel, and completes on-chip network coding configuration, read response receiving address, interrupt information receiving address, retransmission failure receiving address, occupation release receiving address, shared write notification receiving address, write request notification receiving address, and request received notification receiving address;

[0035] Step S2: Receive memory management and read / write requests through the AXIsAW channel and the AXIsW channel, and package these requests into request packets for the on-chip network, including request packets for applying, sharing, releasing, reading, and writing;

[0036] Step S3: Complete the sending of write response, read data and various notification information through the AXImAW channel and the AXImW channel. These notification information include retransmission failure notification, occupation release notification, shared write notification, write request information notification, and request received notification;

[0037] Step S4: receiving the read and write request packets through the on-chip network input port, unpacking and verifying them, and then performing corresponding operations according to the request type;

[0038] Step S5: receiving response packets, including application response packets, memory access response packets, write response packets, read confirmation packets, read response packets, and shared interrupt packets, through the on-chip network input port, unpacking and verifying, and performing corresponding operations according to the response type;

[0039] Step S6: The memory management communication interface sets a timeout retransmission function. The retransmission buffer will cache the last request packet sent through the on-chip network output port. If the corresponding response packet is not received within the set time after the request packet is sent, retransmission will be triggered and the request packet in the retransmission buffer will be sent again.

[0040] Embodiment 2

[0041] The present invention also provides a memory management communication interface for the on-chip network and the SRIO protocol to realize the transfer transmission between the on-chip network and the SRIO. Figure 1 As shown in the application scenario diagram, the memory management communication interface is connected to SRIO, and the storage particles and the host are connected respectively through the on-chip network.

[0042] On the one hand, the memory management communication interface can receive requests in the form of AXI bus from SRIO, package them into request packets in the form of on-chip network, send them to storage particles through the on-chip network, control the storage particles to perform memory management and read and write operations, and after completion, receive a response packet whether the operation is successful through the on-chip network, unpack it into a response in the form of AXI bus, and send it to SRIO; on the other hand, it can accept read and write request packets sent by the host through the on-chip network, unpack them into requests in the form of AXI bus, and send them to SRIO. After completion, receive a response in the form of AXI bus from SRIO, convert it into a response packet oriented to the on-chip network type, and send it to the host that initiated the request through the on-chip network.

[0043] Please refer to Figure 2 The internal structure diagram of the memory management communication interface shown in FIG. 1 is mainly composed of a slave interface module, a master interface module and an output control module.

[0044] Next, the three modules in the memory management communication interface are introduced in detail as follows:

[0045] 1. From the interface module

[0046] Specifically, the slave interface module is mainly composed of a slave logic judgment unit and a slave data conversion unit.

[0047] Specifically, the slave data conversion unit is mainly composed of an AXIsAW channel control state machine, an AXIsW channel control state machine, an AXIsB channel control state machine, and data encapsulation logic. Figure 3 The structure diagram of the slave data conversion unit is shown. Through the AW and W channels in the form of AXI bus, the request for application, sharing, release, reading and writing is received, and the necessary information for a request event such as event type, event code, event address and write data is parsed, and the information is encapsulated into a specified format and written to the slave logic judgment unit. The AXIs AW channel control state machine, AXIs W channel control state machine, AXIs B channel control state machine and data encapsulation logic are introduced as follows:

[0048] (I) AXIsAW channel control state machine

[0049] The AXIsAW channel control state machine is responsible for controlling the AXIsAW channel's processing of data, outputting control signals to the AXIs W channel, and receiving control signals from the AXIs B channel. After reset, the initialization of related signals is completed, and the sawready and AXIsAW channel completion signals are pulled low. If the AXIsB channel transmission completion signal is detected to be pulled high in this state, the AXIsAW channel transmission is enabled, and the sawready signal is pulled high. If the AXIsAW channel handshake is detected to be successful, the AXIsAW channel transmission is completed, the sawready signal is pulled low, the AXIsAW channel completion signal is pulled high, and the next AXIsAW channel transmission is enabled.

[0050] (II) AXIs W channel control state machine

[0051] The AXIs W channel control state machine is responsible for controlling the data processing of the AXIs W channel, outputting control signals to the AXIs B channel, and receiving control signals from the AXIs AW channel. It completes the reception and parsing of AXI write data, outputs initial configuration information and notification of the receipt of the initiation request to the main data conversion unit, and controls the data encapsulation logic to complete data encapsulation and data writing from the logic judgment unit.

[0052] After reset, complete the initialization of related signals and pull up the swready signal. If the AXIs W channel handshake is detected to be successful, write the initial configuration data to the main data conversion unit, and register the read response AXI address, IO interrupt enable bit, IPCGR interrupt enable bit, and the number of IO interrupt high-level pulse duration cycles. If the write is detected to be successful and the AXIs W channel handshake is successful in this state, register the retransmission failure notification AXI address and the occupation release notification AXI address. If the AXIs W channel handshake is detected to be successful, register the DMA end notification AXI address and the sharing notification AXI address. If the AXIs W channel handshake is detected to be successful and the burst transmission is completed, register the write request information notification AXI address and the request received notification AXI address. If the AXIsW channel handshake is detected to be successful and the burst transmission is completed, pull down the swready signal, register the AXI send address of the IPCGR interrupt information, and complete the initialization configuration.

[0053] Initialize AXIs W channel related signals and write control signals. If the AXIs W channel transmission completion signal is detected to be pulled high, the AXIs W channel transmission is enabled and the swready signal is pulled high. If the AXIs W channel handshake is detected to be successful, the AXIs W channel transmission is completed, the swready signal is pulled low, the AXIs W channel transmission completion signal is pulled high, and the next AXIs W channel transmission is enabled.

[0054] (III) AXIs B channel control state machine

[0055] The AXIs B channel control state machine is responsible for controlling the data processing of the AXIs B channel, outputting control signals to the AXIs AW channel, and receiving control signals from the AXIs W channel. After reset, the initialization of related signals is completed. If the AXIs W channel transmission completion signal is detected to be pulled high, the AXIs B channel transmission is started and the sbvalid signal is pulled high. If the AXIs B channel handshake is detected to be successful, the AXIs B channel transmission is completed, the sbvalid signal is pulled low, the AXIs B channel transmission completion signal is pulled high, and the next AXIs B channel transmission is started.

[0056] (IV) Data Encapsulation Logic

[0057] The data encapsulation logic encapsulates the data from the AXIs W channel according to a specific format and outputs the write data to the slave logic judgment unit.

[0058] Specifically, the slave logic judgment unit is mainly composed of address mapping logic, data encapsulation logic, retransmission logic, and read control state machine. Figure 3 The structural diagram of the slave data conversion unit is shown. The slave logic judgment unit receives the on-chip network coding configuration information from the data conversion unit to complete the configuration of the on-chip network. This information will be used as the coding of the on-chip network at the sending end and is necessary information for address mapping and data packet encapsulation; receives the necessary information for the application, sharing, release, read, and write request events from the slave data conversion unit, completes the address mapping based on the parsed information, encapsulates the data packet into a request packet in the form of an on-chip network and outputs it; caches the output request packet in the retransmission buffer, and counts after the output is completed. If the occupancy release notification is not received within the set time, retransmission is triggered, and the data packet in the retransmission buffer is output again. After retransmission, timing will be performed again. If the occupancy release notification is still not received within the set time after retransmission, a retransmission failure notification signal is sent. Only when the occupancy of the retransmission buffer ends, the slave logic judgment unit will continue to receive the request information from the slave data conversion unit to encapsulate and output the next data packet. The address mapping logic, data encapsulation logic, retransmission logic, and read-out control state machine are introduced as follows:

[0059] (I) Address Mapping Logic

[0060] The address mapping logic receives the read data from the data conversion unit, parses it into routing information required for encapsulating the on-chip network data packet according to a specific format, and outputs the parsed routing information to the data encapsulation logic.

[0061] (II) Memory Management Logic

[0062] The data encapsulation logic encapsulates the routing information from the address mapping logic and the read data from the data conversion unit in a specific format. The read control state machine controls the encapsulation of the data encapsulation logic and the output direction of the encapsulation packet. On the one hand, it outputs the encapsulation packet to the retransmission logic, and on the other hand, it outputs the encapsulation packet to the output control module.

[0063] (III) Retransmission Logic

[0064] The retransmission logic receives the encapsulation packet output by the data encapsulation logic and writes it into the retransmission buffer, receives the occupancy release notification signal and the retransmission failure signal for timing, and controls the data writing and data reading of the retransmission buffer after a certain time. The data read out of the retransmission buffer is output to the output control module. If it still fails after retransmission, a retransmission failure signal is generated and output to the main logic judgment unit.

[0065] (IV) Readout Control State Machine

[0066] The read control state machine receives an occupation release signal and a retransmission failure signal from the main logic judgment unit, controls the slave data conversion unit to read data, and controls the data encapsulation of the data encapsulation logic and the output direction of the encapsulation packet.

[0067] 2. Main interface module

[0068] Specifically, the main interface module is mainly composed of a main logic judgment unit and a main data conversion unit.

[0069] Specifically, the main logic judgment unit is mainly composed of verification logic, unpacking logic, occupation release / retransmission failure handshake logic, and main interface logic judgment control state machine. The main logic judgment unit receives response packets through the input port of the on-chip network, including application response packets, memory access response packets, write response packets, read confirmation packets, read response packets, and shared interrupt packets. After verifying and unpacking the application response packets, memory access response packets, write response packets, and read confirmation packets, the occupation release / retransmission failure handshake logic and the slave logic judgment unit will complete the handshake, thereby releasing the occupation of the retransmission buffer in the slave logic judgment unit, and writing the information required for the retransmission failure notification into the main data conversion unit; after verifying and unpacking the read response packet and the shared interrupt packet, the necessary information will be written into the main data conversion unit. The verification logic, unpacking logic, occupation release / retransmission failure handshake logic, and main interface logic judgment control state machine are introduced as follows:

[0070] (I) Verification Logic

[0071] The verification logic receives response packets from the on-chip network, including application response packets, memory access response packets, write response packets, read confirmation packets, read response packets, and shared interrupt packets. All response packets are checked for data packet format integrity, and incomplete response packets are directly discarded, and the main interface logic judgment control state machine is notified to interrupt the unpacking of the response packet.

[0072] (II) Unpacking Logic

[0073] The unpacking logic receives response packets from the on-chip network, including application response packets, memory access response packets, write response packets, read confirmation packets, read response packets, and shared interrupt packets. After unpacking the application response packets, memory access response packets, write response packets, and read confirmation packets, the response packet type is output to the main interface logic judgment control state machine. After checking and unpacking the read response packets and shared interrupt packets, the necessary information is written into the main data conversion unit. Receive the interrupt unpacking information from the main interface logic judgment control state machine and perform the next unpacking.

[0074] (III) Occupancy release / retransmission failure handshake logic

[0075] The occupancy release / retransmission failure handshake logic receives the control information from the master interface logic judgment control state machine, completes the handshake with the occupancy release signal from the slave logic judgment unit, thereby releasing the occupancy of the retransmission buffer in the slave logic judgment unit. Completes the handshake with the retransmission failure signal from the slave logic judgment unit, thereby writing the information required for the retransmission failure notification into the master data conversion unit.

[0076] (IV) Main interface logic judgment control state machine

[0077] The main interface logic judgment control state machine receives the interrupt unpacking information from the verification logic, controls the progress and interruption of the unpacking logic; receives the necessary information from the unpacking logic, controls the handshake between the occupation release / retransmission failure handshake logic and the slave logic judgment unit; receives the successful handshake information from the occupation release / retransmission failure handshake logic, and controls the information required for the retransmission failure notification to be written into the main data conversion unit.

[0078] Specifically, the main data conversion unit is mainly composed of an AXIm AW channel control state machine, an AXIm W channel control state machine, data encapsulation logic, and a main interface data conversion control state machine. The main data conversion unit receives the necessary information of the read response from the main logic judgment unit, and then initiates transmission to the read response AXI address through the AXIm AW channel, and sends the read response information and read response data to SRIO in a specified format through the AXIm W channel; it receives notification information from the main logic judgment unit, including retransmission failure notification information and shared write notification information, and then initiates transmission to the notification information AXI address of the corresponding notification type through the AXIm AW channel, and sends the notification information of the corresponding notification type to SRIO in a specified format through the AXIm W channel. The AXIm AW channel control state machine, the AXIm W channel control state machine, the data encapsulation logic, and the main interface data conversion control state machine are introduced as follows:

[0079] (I) AXIm AW channel control state machine

[0080] The AXIm AW channel control state machine controls the transmission of the necessary information and notification information of the read response to the corresponding AXI address. After reset, each signal of the AXIm AW channel is initialized, and the mawvalid signal is pulled high to start the AXIm AW channel transmission. If the AXIm AW channel handshake is detected to be successful, the AXIm AW channel transmission is completed, the mawvalid signal is pulled low, and the next transmission of the AXIm AW channel is started.

[0081] (II) AXIm W channel control state machine

[0082] The AXIm W channel control state machine controls the sending of read response information, read response data, and notification information of the corresponding notification type to SRIO in the specified format. After reset, each signal of the AXIm W channel is initialized, and the mwvalid signal is pulled high to start the AXIm W channel transmission. If the AXIm W channel handshake is detected to be successful, the AXIm W channel transmission is completed, the mwvalid signal is pulled low, and the next AXIm W channel transmission is started.

[0083] (III) Data encapsulation logic

[0084] The data encapsulation logic receives the notification information and necessary information of the read response from the main interface logic judgment unit, encapsulates the information in a specific format, and outputs it to the AXIm W channel control state machine.

[0085] (IV) Main interface data conversion control state machine

[0086] The master interface data conversion control state machine receives the notification information and necessary information of the read response packet from the master interface logic judgment unit, and controls the AXImAW channel control state machine to initiate transmission to the notification information AXI address and the read response AXI address of the corresponding notification type.

[0087] 3. Output control module

[0088] The output control unit is used to feed back the received memory management response packet or the response packet from the DDR storage particle to the on-chip network. When the memory management response packet and the response packet from the DDR storage particle are received at the same time, the response packets are prioritized according to the pre-priority, and the response packet with higher priority is fed back to the on-chip network first, and the response packet with lower priority waits for the next priority arbitration, where the pre-priority is a fixed priority, that is, the response packet from the DDR storage particle has a higher priority.

[0089] The memory management communication interface and method provided in this embodiment solve the relocation problem caused by the uncertainty of the free position and the need to allocate free space for multi-event memory access in a multi-chip interconnected network system, thereby improving the memory access efficiency; solve the conflict problem of large-scale memory access for multiple events in a multi-chip interconnected network system, thereby improving the resource utilization of the system; solve the data loss and even system crash caused by the mutual influence of different access events due to the non-isolation of address space in the multi-chip interconnected network system, thereby improving the security and stability of the system.

[0090] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A memory management communication interface for on-chip network and SRIO protocol, characterized in that: The memory management communication interface is connected to SRIO, and is connected to storage particles and a host through an on-chip network. The memory management communication interface includes: Slave interface module; the slave interface module includes a slave logic judgment unit and a slave data conversion unit. The slave data conversion unit receives application, sharing, release, read and write requests through AW and W channels in the form of AXI bus, parses out the necessary information of a request event such as event type, event code, event address and write data, and encapsulates it into a specified format and writes it to the slave logic judgment unit; the slave data conversion unit will initiate a request acceptance notification after completely receiving a write-related request; The main interface module includes a main logic judgment unit and a main data conversion unit. The main data conversion unit receives the necessary information of the write request from the main logic judgment unit, initiates transmission to the write request address through the AXImAW channel, and writes the write data to SRIO through the AXIm W channel; when the write request is completed, initiates transmission to the AXI address of the write request information notification given during the initial configuration through the AXImAW channel, and sends the content of the write request information notification to SRIO through the AXIm W channel; Output control module; for request packets from the slave interface module, including application, sharing, release, write, and read request packets, for confirmation packets from the master interface module, including application response packets, memory access response packets, write response packets, and read confirmation packets, and for read response packets from the master interface module, multiplexing is performed to resolve output conflicts.

2. The memory management communication interface according to claim 1, characterized in that: On the one hand, the memory management communication interface receives requests in the form of AXI bus from SRIO, packages them into request packets in the form of on-chip network, sends them to storage particles through the on-chip network, controls the storage particles to perform memory management and read and write operations, and after completion, receives a response packet whether the operation is successful through the on-chip network, unpacks it into a response in the form of AXI bus, and sends it to SRIO; on the other hand, it accepts read and write request packets sent by the host through the on-chip network, unpacks them into requests in the form of AXI bus, and sends them to SRIO. After completion, it receives a response in the form of AXI bus from SRIO, converts it into a response packet oriented to the on-chip network type, and sends it to the host that initiated the request through the on-chip network.

3. The memory management communication interface according to claim 1, characterized in that: The data input and output port in the form of AXI bus in the slave interface module is connected to SRIO, and the data output port in the form of on-chip network is connected to the output control module; the data input and output port in the form of AXI bus of the master interface module is connected to SRIO, the data output port in the form of on-chip network is connected to the output control module, and the data input port in the form of on-chip network is connected to the on-chip network.

4. The memory management communication interface according to claim 1, characterized in that: The slave data conversion unit is composed of an AXIsAW channel control state machine, an AXIsW channel control state machine, an AXIsB channel control state machine, and data encapsulation logic; the slave port of the AXI bus in the slave data conversion unit is interconnected with the master port of the SRIO, the slave data conversion unit is interconnected with the input and output ports of the master data conversion unit, the output port of the slave data conversion unit is connected to the input port of the slave logic judgment unit, the slave logic judgment unit is interconnected with the input and output ports of the master logic judgment unit, and the output port of the slave logic judgment unit is connected to the output control module.

5. The memory management communication interface according to claim 1, characterized in that: The slave logic judgment unit is composed of address mapping logic, data encapsulation logic, retransmission logic, and a read control state machine; The slave logic judgment unit receives the on-chip network coding configuration information from the data conversion unit to complete the configuration of the on-chip network. This information will be used as the coding of the on-chip network at the sending end and is necessary information for address mapping and data packet encapsulation. Receive the necessary information of the request events of application, sharing, release, read and write from the data conversion unit, complete the address mapping according to the parsed information, encapsulate the data packet into a request packet in the form of on-chip network and output it; The output request packet is cached in the retransmission buffer and timing is performed after the output is completed. If the occupancy release notification is not received within the set time, retransmission is triggered and the data packet in the retransmission buffer is output again. The timing will be performed again after retransmission. If the occupancy release notification is still not received within the set time after retransmission, a retransmission failure notification signal is sent. Only when the occupancy of the retransmission buffer ends, the slave logic judgment unit will continue to receive the request information from the slave data conversion unit to encapsulate and output the next data packet.

6. The memory management communication interface according to claim 1, characterized in that: The master port of the AXI bus in the master data conversion unit is interconnected with the slave port of the SRIO, the input and output ports of the master data conversion unit and the slave data conversion unit are interconnected, the master data conversion unit and the input and output ports of the master logic judgment unit are interconnected, the main logic judgment unit and the input and output ports of the slave logic judgment unit are interconnected, the output port of the master logic judgment unit is connected to the output control module, and the input port of the master logic judgment unit is connected to the output port of the on-chip network.

7. The memory management communication interface according to claim 6, characterized in that: The main logic judgment unit is composed of verification logic, memory management logic, unpacking and data encapsulation logic, confirmation packet generation logic, read response generation logic, occupation / retransmission handshake logic, and main interface logic judgment control state machine. The main logic judgment unit receives confirmation packets, including application response packets, memory access response packets, write response packets, and read confirmation packets, through the input port of the on-chip network. After unpacking and verification, the main logic judgment unit sends occupation release notification information to the slave logic judgment unit, thereby releasing the occupation of the retransmission buffer in the slave logic judgment unit, and writes the occupation release notification information into the main data conversion unit; receives read response packets and shared interrupt packets through the input port of the on-chip network, unpacks and verifies, and then writes necessary information into the main data conversion unit; receives read and write request packets through the input port of the on-chip network, unpacks and verifies, and then writes necessary information into the main data conversion unit, and sends write response packets and read confirmation packets through the output port of the on-chip network; Receive read data from the master data conversion unit, which is read response data returned after receiving a read request, and encapsulate the data into a read response packet according to the on-chip network data format; By receiving the retransmission failure notification information from the logic judgment unit, necessary information of the retransmission failure packet is written into the main data conversion unit.

8. The memory management communication interface according to claim 1, characterized in that: The master data conversion unit is composed of an AXImAW channel control state machine, an AXImW channel control state machine, an AXImB channel control state machine, an AXImAR channel control state machine, an AXImR channel control state machine, data encapsulation logic, IO interrupt logic, data parsing logic, and a master interface data conversion control state machine. The master data conversion unit receives necessary information of a read request from a master logic judgment unit, initiates transmission to a read request address through an AXImAR channel, and then reads the read data back through an AXImR channel, encapsulates it into a specific format and writes it to the master logic judgment unit; receives necessary information of a read response from the master logic judgment unit, initiates transmission to a read response AXI address given by the initial configuration through an AXImAW channel, and sends the read response information and read response data to SRIO through an AXImW channel; Receive notification information from the main logic judgment unit, including retransmission failure notification information, shared write notification information, and occupation release notification information, then initiate transmission to the notification information AXI address of the corresponding notification type given in the initial configuration through the AXImAW channel, and send the notification information of the corresponding notification type to SRIO through the AXIm W channel; receive the request received notification from the slave data conversion unit, initiate transmission to the AXI address of the request received notification given in the initial configuration through the AXIm W channel, and send the content of the request received information notification to SRIO through the AXIm W channel.

9. The memory management communication interface according to claim 1, characterized in that: The output control module performs arbitration and multiplexing in units of data packets; when two or more data packet header flit slices are received at the same time, arbitration is performed according to the pre-priority, and the one with higher priority will occupy the output port before the entire data packet is output, and the data packet with lower priority will wait for the next arbitration; The arbitration policy is that the request that least recently obtained output permission will have the highest priority.

10. A memory management communication method for on-chip network and SRIO protocol, implemented according to the memory management communication interface according to any one of claims 1 to 9, characterized in that: The steps include: Step S1: After each reset, the memory management communication interface receives initial configuration information from SRIO through the AXIs AW channel and the AXIs W channel, and completes on-chip network coding configuration, read response receiving address, interrupt information receiving address, retransmission failure receiving address, occupation release receiving address, shared write notification receiving address, write request notification receiving address, and request received notification receiving address; Step S2: Receive memory management and read / write requests through the AXIs AW channel and the AXIs W channel, and package these requests into request packets for the on-chip network, including request packets for applying, sharing, releasing, reading, and writing; Step S3: Complete the sending of write response, read data and various notification information through the AXImAW channel and the AXIm W channel. These notification information include retransmission failure notification, occupation release notification, shared write notification, write request information notification, and request received notification; Step S4: receiving the read and write request packets through the on-chip network input port, unpacking and verifying them, and then performing corresponding operations according to the request type; Step S5: receiving response packets, including application response packets, memory access response packets, write response packets, read confirmation packets, read response packets, and shared interrupt packets, through the on-chip network input port, unpacking and verifying, and performing corresponding operations according to the response type; Step S6: The memory management communication interface sets a timeout retransmission function. The retransmission buffer will cache the last request packet sent through the on-chip network output port. If the corresponding response packet is not received within the set time after the request packet is sent, retransmission will be triggered and the request packet in the retransmission buffer will be sent again.

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