A chiplet interconnect interface protocol layer circuit and chip compatible with CHI protocol

Abstract

The present invention discloses a chip interconnection interface protocol layer circuit and chip compatible with CHI protocol. The chip interconnection interface protocol layer circuit of the present invention includes a sending unit and a receiving unit in a protocol layer connected to an adapter layer and a physical layer. The sending unit includes a sending end virtual channel management module, a sending buffer unit and a packaging module connected in sequence. The sending buffer unit is used to cache micro packets of each channel and includes parallel request-monitoring sending buffer, response sending buffer, debugging and testing sending buffer and data sending buffer respectively. The receiving unit includes a parsing module, a receiving buffer unit and a receiving end virtual channel management module connected in sequence. The receiving buffer unit includes parallel request-monitoring receiving buffer, response receiving buffer, debugging and testing receiving buffer and data receiving buffer. The present invention aims to make the chip interconnection interface compatible with CHI protocol, so that the chip implemented by ARM architecture can realize consistent interconnection through CHI protocol.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interconnection interfaces between chiplets, and in particular to a chiplet interconnection interface protocol layer circuit and chip compatible with the CHI protocol. Background Art

[0002] To meet the increasing demand for computing power, chip performance continues to improve. However, as Moore's Law gradually fails, in order to further increase the number of transistors in the chip, the area of ​​a single chip continues to expand. At present, the area of ​​a single chip has approached the mask limit, and the use of core particle technology to package multiple bare cores (dies) together to build a chip has gradually become the main way to expand the chip area. Core particle technology divides the chip into multiple small core particles, and then connects and integrates them through packaging to form an integrated chip. Compared with a single large chip, the core particle has a smaller area and a higher yield. The combination of multiple core particles can make the area of ​​the integrated chip larger, the way to build the chip is more flexible, and the cost is lower. In the field of core particle interconnection research and engineering implementation, how to realize the cross-core particle (die to die, D2D) transmission of the interconnection protocol originally located between the network on chip (Network On Chip, NOC) or between chips (Chip to Chip, C2C) has become the key to achieving efficient transmission between core particles.

[0003] The current chip interconnection interface circuit or chip interconnection standard adopts the method of inheriting support for the traditional NOC communication protocol or C2C protocol to simplify the chip communication protocol design, achieve compatibility support for the original protocol, and facilitate the use of a unified implementation mechanism between chiplets and at different levels between chiplets. Taking the PCIe (Peripheral Component Interconnect Express) protocol proposed by Intel as an example, the PCIe protocol is mainly used to achieve high-bandwidth interconnection between CPU and external IO devices, such as the interconnection between Intel CPU and NVIDIA GPU, and the GPU communicates data with the CPU as the IO device of the CPU. If the PCIe protocol is also supported between chiplets, then the CPU and GPU can each be a chiplet and encapsulated in the same chip. The interconnection between the two chiplets is realized through the D2D interface, and the protocol layer adopts the same PCIe protocol as the interconnection between chips. At present, the main chiplet interconnection interface standards released at home and abroad include: Advanced Cost-driven Chiplet Interface (ACC) standard led by China Chiplet Industry Alliance, "Technical Requirements for Chiplet Interface Bus" released by China Computer Interconnect Technology Alliance, Chiplets Interconnect Protocol (CIP) protocol led by the 58th Institute of China Electronics Technology Group Corporation, Universal Chiplet Interconnect Express (UCIe) standard led by Intel, Bunch of Wires (BoW) UCIe standard specification released by OCP ODSA group, etc. The protocols supported by these standards and corresponding interface circuits include PCIe protocol, CXL protocol (including CXL.MC and CXL.IO), AXI protocol, NVLINK protocol, etc.

[0004] The CHI (Coherent Hub Interface) protocol is a commonly used consistent interconnection protocol between ARM cores. Computing cores based on the ARM architecture can be interconnected through the CHI protocol to form an integrated chip, and can also form a processor composed of multiple integrated chips through the CHI protocol. The CHI protocol can also be used to achieve consistent interconnection between integrated chips and chips that do not use core technology. The CHI protocol is mainly used in the on-chip network of ARM architecture processors. When an ARM processor is divided into multiple cores, multiple components that originally communicated in a chip through a NOC that supports the CHI interconnection protocol will be interconnected through the core interconnection interface, and the core interconnection interface is required to support the CHI protocol. At present, there is little research on the specific method of how the core interconnection interface supports ARM's CHI protocol, both in the core interface standard and in the core interface circuit, which has become a bottleneck for ARM architecture processors to expand the scale and improve performance using core technology.

[0005] like Figure 1 As shown in the figure, the core-grain interconnect interface standard is divided into three levels from top to bottom: protocol layer, adapter layer and physical layer. The physical layer contains the core-grain interconnect interface physical link. The protocol layer implements the packing and unpacking of different communication protocol messages. The sender packs various protocol messages into a unified micro-packet (Flit) format, and the receiver parses various types of protocol messages from the micro-packet. As the middle layer between the protocol layer and the physical layer, the adapter layer is mainly responsible for the reliable transmission of micro-packet data. When the core-grain interconnect interface supports the CHI protocol, it is necessary to pack the messages of different channels in the CHI protocol into the standard micro-packet format defined by the existing core-grain interconnect interface protocol, and be compatible with the existing core-grain interconnect interface flow control mechanism, so as to achieve the purpose of being able to utilize the adapter layer and physical layer of the existing interconnect interface.

[0006] The CHI protocol has 4 channels, including a request (Req) channel, a listen (Snp) channel, a response (Rsp) channel, and a data (Data) channel. The publicly published version 3 of the CHI protocol stipulates that the request channel bit width range is 117-169 bits, the listen channel bit width range is 51-59 bits, and the response channel bit width range is 81-100 bits. When the data bit width is 128 bits, the data channel bit width range is 202-214 bits. In addition, for the convenience of debugging, a debugging test Csc (CoreSight) channel (37 bits) is usually added. Taking the core grain interconnect interface implemented using the UCIe standard as an example, one of the most intuitive ways to support the CHI protocol is to multi-select different channels of CHI and package them into 512-bit micro packets of the UCIe protocol in a fair round-robin manner to achieve multiplexing of the adapter layer and physical layer of the UCIe protocol. Figure 2As shown, each channel message less than 512 bits must occupy a 512-bit micro-packet for transmission, which cannot fully utilize the effective load width of the micro-packet, resulting in bandwidth waste.

[0007] In summary, there are two difficulties in supporting the CHI protocol in the chip interconnect interface: first, how to reuse the existing chip interconnect interface standards and the adapter layer and physical layer of the circuit to maximize resource reuse and achieve compatibility with the existing chip interconnect ecosystem; second, how to efficiently package the CHI message to the adapter layer micro-packet format to maximize the bandwidth utilization of the CHI message transmitted in the chip interconnect interface. How to solve the above two problems of the chip interconnect interface supporting the CHI protocol has become a key technical issue that needs to be solved urgently. Summary of the invention

[0008] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a chip interconnection interface protocol layer circuit and chip compatible with the CHI protocol are provided. The present invention aims to make the chip interconnection interface compatible with the CHI protocol, so that the chiplets implemented by the ARM architecture can achieve consistent interconnection through the CHI protocol.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0010] A CHI-compatible chip interconnect interface protocol layer circuit comprises a sending unit and a receiving unit in a protocol layer connected to an adapter layer and a physical layer, wherein the sending unit comprises a sending end virtual channel management module, a sending buffer unit and a packaging module connected in sequence, wherein the sending end virtual channel management module is used to inject a micro-packet into the sending buffer unit, wherein the sending buffer unit is used to cache micro-packets of each channel and comprises a parallel request-listening sending buffer, a response sending buffer, a debugging and testing sending buffer and a data sending buffer, wherein the packaging module is used to package the micro-packet output by the sending buffer unit into a message with a width of 512 bits; wherein the receiving unit comprises a parsing module, a receiving buffer unit and a receiving buffer unit connected in sequence The receiving end virtual channel management module, the parsing module is used to parse the micro-packet from the received 512-bit width message and send it to the receiving buffer unit, the receiving buffer unit includes a parallel request-listening receiving buffer, a response receiving buffer, a debugging and testing receiving buffer and a data receiving buffer, and the micro-packet output by the receiving buffer unit is sent to the receiving end through the receiving end virtual channel management module; the request-listening sending buffer and the request-listening receiving buffer both correspond to the request channel and the listening channel at the same time, the response sending buffer and the response receiving buffer both correspond to the response channel, the debugging and testing sending buffer and the debugging and testing receiving buffer both correspond to the debugging and testing channel, and the data sending buffer and the data receiving buffer both correspond to the data channel.

[0011] Optionally, the output ends of the response sending buffer and the debugging test sending buffer are also connected to a multiplexing module MUX, and the output ends of the response sending buffer and the debugging test sending buffer are connected to the input end of the packaging module through the multiplexing module MUX; the input ends of the response receiving buffer and the debugging test receiving buffer are connected to a demultiplexing module DeMUX, and the input ends of the response receiving buffer and the debugging test receiving buffer are respectively connected to the output end of the analysis module through the demultiplexing module DeMUX, and the input ends of the request-listening receiving buffer and the data receiving buffer are directly connected to the output end of the analysis module.

[0012] Optionally, when the sending end virtual channel management module injects the micropacket into the sending buffer unit, the target identifier TgtID and the source identifier SrcID field widths in the micropacket formats of the request channel, the response channel and the data channel are set to 0 to achieve compression of the micropacket formats of the request channel, the response channel and the data channel.

[0013] Optionally, when the sending end virtual channel management module injects a micropacket into the sending buffer unit, if the micropacket is a micropacket of a request channel, the micropacket of the request channel is directly injected into the request-listening sending buffer with a bit width of 107 bits; if the micropacket is a micropacket of a listening channel, before injecting the request-listening sending buffer, the micropacket of the listening channel is first supplemented with 15 bits of all 0s in the low order, and then injected into the request-listening sending buffer with a bit width of 107 bits so that the request channel can share a set of request-listening sending buffers with the listening channel; if the micropacket is a micropacket of a response channel, the micropacket of the response channel is injected into the response sending buffer with a bit width of 37 bits; if the micropacket is a micropacket of a data channel, the micropacket of the data channel is injected into the data sending buffer with a bit width of 340 bits; if the micropacket is a micropacket of a tuning and testing channel, the micropacket of the tuning and testing channel is injected into the tuning and testing sending buffer with a bit width of 37 bits.

[0014] Optionally, the bit width of the request-listen receive buffer is one channel flag bit more than the bit width of the request-listen send buffer. When the parsing module parses a micropacket from the received 512-bit width message and sends it to the receive buffer unit, if the micropacket is a micropacket of the request channel or the listen channel, the channel flag bit is set to distinguish whether the micropacket injected into the request-listen receive buffer is a micropacket of the request channel or a micropacket of the listen channel.

[0015] Optionally, the 512-bit wide message consists of 4 parts, which include, from high to low, a 4-bit template TEMP, a 115-bit slot 0, a 45-bit slot 1 and a 348-bit slot 2, and the request channel and the monitoring channel share slot 0, the response channel and the test channel share slot 1, and the data channel has exclusive slot 2. The template TEMP consists of 4 1-bit valid bits, which are used to indicate the validity of slot 0, slot 1 and slot 2.

[0016] Optionally, each of slot 0, slot 1 and slot 2 consists of a 1-bit micropacket flag field FTG, a micropacket field Flit, a 6-bit credit grant field CRD and a 1-bit channel flag field CTG from high to low, and the micropacket field Flit bit widths of slot 0, slot 1 and slot 2 are different, wherein the micropacket flag field FTG is used to indicate whether the slot is a micropacket slot or a credit slot, if it is a micropacket slot, the micropacket field Flit is filled with channel micropackets, and the bit width is determined by the size of the channel micropacket; if it is a credit slot, the micropacket field Flit is filled with all 0s; the credit grant field CRD is filled with the credit value granted to the other end during the end-to-end flow control process, and the channel flag field CTG indicates the channel type filled in the slot.

[0017] Optionally, among the 4 valid bits of template TEMP, bit 0 indicates that the channel micropacket packaged from send buffer 0 to slot 0 is valid, bit 1 indicates that the channel micropacket packaged from send buffer of the test channel to slot 0 is valid, bit 2 indicates that the channel micropacket packaged from send buffer of the response channel to slot 1 is valid, and bit 3 indicates that the channel micropacket packaged from send buffer of the data channel to slot 2 is valid.

[0018] Optionally, the parsing module parses the micro-packet from the received message with a width of 512 bits and sends it to the receiving buffer unit, including: first, parsing the template TEMP from the 508th to the 511th bits of the received message with a width of 512 bits; if the 3rd bit of the template TEMP is 1 and the micro-packet flag field FTG at the 347th bit indicates a micro-packet slot, then parsing the data channel micro-packet from the 7th to the 346th bits in the micro-packet field Flit and writing it into the data channel receiving buffer; if the 2nd bit of the template TEMP is 1 and the micro-packet flag field FTG at the 392nd bit indicates a micro-packet slot, then parsing the response channel micro-packet from the 354th to the 390th bits in the micro-packet field Flit and writing it into the response channel receiving buffer; if the template TEMP is 1 and the micro-packet flag field FTG at the 392nd bit indicates a micro-packet slot, then parsing the response channel micro-packet from the 354th to the 390th bits in the micro-packet field Flit and writing it into the response channel receiving buffer; If the first bit of the board TEMP is 1 and the 392nd micropacket flag field FTG indicates a micropacket slot, the test channel micropackets at bits 354 to 390 in the micropacket field Flit are parsed and written into the test channel receiving buffer; if the 0th bit of the template TEMP is 1 and the 507th micropacket flag field FTG indicates a micropacket slot, the channel micropackets at bits 399 to 505 in the micropacket field Flit are parsed and concatenated with the 392nd channel flag field CTG and written into receiving buffer 0; the credit grant field CRD of the received 512-bit width message is parsed and sent to the credit calculation module of the corresponding channel according to the slot and channel flag field CTG for credit calculation.

[0019] In addition, the present invention also provides a chip, including a core particle and an interface circuit between core particles, wherein the interface circuit is a core particle interconnection interface protocol layer circuit compatible with the CHI protocol.

[0020] Compared with the prior art, the present invention mainly has the following advantages:

[0021] 1) The present invention provides a compatible solution for the CHI protocol and has good resource utilization. The present invention can achieve direct compatibility with the CHI protocol through the channel interface defined by the CHI protocol at the protocol layer of the core-grain interconnect interface. Currently, none of the existing core-grain interconnect interface standards provide a compatible solution for the CHI protocol. The present invention allows the request and monitoring channels to reuse the sending buffer and receiving buffer, and allows the test channel and the response channel to also reuse the sending buffer and receiving buffer, which saves hardware resources compared to each channel corresponding to a set of buffers.

[0022] 2) The present invention has good bandwidth utilization. First, while maintaining compatibility with the CHI protocol, the present invention compresses the request, response and data channel micro-packet formats of the CHI protocol for the core-grain interconnection interface, reduces the bandwidth waste caused by the three SrcID fields and TgtID fields in the 512-bit bandwidth, and improves bandwidth utilization. Secondly, the present invention allows the request channel and the listening channel to reuse a slot, so that when only one type of request channel micro-packet and listening channel micro-packet in the sending buffer is valid, the corresponding slot will not be idle to cause bandwidth waste.

[0023] The above advantages enable the chiplet interconnection interface protocol layer circuit compatible with the CHI protocol of the present invention to be compatible with the CHI protocol, so that the chiplets implemented by the ARM architecture can achieve consistent interconnection through the CHI protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The standard hierarchical architecture diagram of the chiplet interconnection interface in the prior art.

[0025] Figure 2 It is an intuitive way to pack 5 channel messages of CHI protocol into a 512-bit interface in the prior art.

[0026] Figure 3 Schematic diagram of the structure of the chiplet interconnection interface protocol layer circuit in an embodiment of the present invention.

[0027] Figure 4 It is a schematic diagram of using CHI protocol for communication between core particles in an embodiment of the present invention.

[0028] Figure 5 It is a schematic diagram of packaging CHI channel micropackets into 512-bit messages in a slot manner in an embodiment of the present invention.

[0029] Figure 6 This is a fixed packaging method for each slot in the embodiment of the present invention.

[0030] Figure 7The reference templates for parsing CHI channel micropackets from a 512-bit message in an embodiment of the present invention are shown in FIG. 1 , wherein (a) is the reference template for bits 356 to 512, and (b) is the reference template for bits 1 to 355. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The present invention will propose a chip interconnect interface protocol layer circuit and chip compatible with the CHI protocol, which has two main features. First, a protocol layer architecture compatible with the CHI protocol and existing interconnect interface standards and circuits is proposed at the protocol layer of the chip interface, including a packing and unpacking mechanism and a flow control mechanism for the CHI protocol. Second, an efficient CHI protocol channel message packing and unpacking rule is proposed, which simplifies and optimizes the format of the original channel message for the chip interconnection scenario, fully utilizes the micro-packet bit width, and achieves higher bandwidth utilization. Figure 3 As shown, this embodiment provides a CHI-compatible core-grain interconnect interface protocol layer circuit, including a sending unit and a receiving unit in a protocol layer connected to an adapter layer and a physical layer, wherein the sending unit includes a sending end virtual channel management module, a sending buffer unit and a packaging module connected in sequence, wherein the sending end virtual channel management module is used to inject a micro-packet into the sending buffer unit, wherein the sending buffer unit is used to cache micro-packets of each channel and includes a parallel request-listening sending buffer, a response sending buffer, a debugging test sending buffer and a data sending buffer, wherein the packaging module is used to package the micro-packet output by the sending buffer unit into a 512-bit width message; the receiving unit includes a parsing module, a receiving buffer unit and a receiving buffer unit connected in sequence. The buffer unit and the receiving end virtual channel management module are used for parsing the micro-packet from the received 512-bit width message and sending it to the receiving buffer unit. The receiving buffer unit includes a parallel request-listening receiving buffer, a response receiving buffer, a debugging and testing receiving buffer and a data receiving buffer. The micro-packet output by the receiving buffer unit is sent to the receiving end through the receiving end virtual channel management module; the request-listening sending buffer and the request-listening receiving buffer both correspond to the request channel and the listening channel at the same time, the response sending buffer and the response receiving buffer both correspond to the response channel, the debugging and testing sending buffer and the debugging and testing receiving buffer both correspond to the debugging and testing channel, and the data sending buffer and the data receiving buffer both correspond to the data channel.

[0033] like Figure 3As shown, the output ends of the response sending buffer and the debugging test sending buffer in this embodiment are also connected to the multiplexing module MUX, and the output ends of the response sending buffer and the debugging test sending buffer are connected to the input end of the packaging module through the multiplexing module MUX; the input ends of the response receiving buffer and the debugging test receiving buffer in this embodiment are connected to the demultiplexing module DeMUX, and the input ends of the response receiving buffer and the debugging test receiving buffer are respectively connected to the output end of the parsing module through the demultiplexing module DeMUX, and the input ends of the request-listening receiving buffer and the data receiving buffer are directly connected to the output end of the parsing module. The packaging logic implemented at the sending end of this embodiment packages the valid channel micro-packets output from the request-listening sending buffer, the multiplexer and the data channel sending buffer into a message with a width of 512 bits. A two-choice MUX (multiplexer) is implemented at the sending end, and a DeMUX (demultiplexer) is implemented at the receiving end. When the debugging test channel is working, the sending and receiving of the other four channels will be interrupted.

[0034] In this embodiment, when the virtual channel management module at the transmitting end injects the micro-packet into the sending buffer unit, the target identifier TgtID and the source identifier SrcID field width in the micro-packet format of the request channel, the response channel and the data channel are set to 0 to achieve the compression of the micro-packet format of the request channel, the response channel and the data channel. When a message is sent from one core particle to another, it will not be routed through the network layer. Figure 4 This is a schematic diagram of the communication between core grain 0 and core grain 1 using the CHI protocol in this embodiment. After the core grain 0 communication message passes through the CHI protocol proxy node 0, the proxy node 0 will calculate the destination ID and send it to the core grain 1. After the proxy node 1 receives the message, it will calculate the source ID and save it before passing the message to the core grain 1. Therefore, when the protocol layer of the core grain interconnection interface does not implement the source ID field and the destination ID field of the request, response and data channel, it can still be compatible with the CHI protocol. The sending end is used to receive the request, response, monitoring and data channel micro-packets of the CHI protocol message to the sending buffer through the channel interface specified by the CHI protocol. The sending agent module, the packing module that packs the valid channel micro-packets in the sending buffer into 512-bit messages, the receiving end is used to parse each channel micro-packet from the 512-bit message and put it into the corresponding receiving buffer. The parsing module, as well as the receiving agent module that extracts the valid channel micro-packet from the receiving buffer and submits the micro-packet upward according to the channel interface credit signal. The micro-packet format compression method defined in this embodiment is shown in Table 1.

[0035] Table 1: Schematic diagram of micropacket format compression method

[0036]

[0037] As shown in Table 1, when the present embodiment compresses the request, response and data channel micro-packet formats for the core-grain interconnection interface, the target identifier TgtID and source identifier SrcID field widths of the request, response and data channel micro-packet formats are set to 0, and the ReturnNID field of the request channel takes 11 bits, the address field Addr takes 44 bits, and the RSVDC field takes 0 bits, the SrcID field of the monitoring channel takes 11 bits, the FwdNID field takes 11 bits, and the Addr field takes 41 bits, the HomeNID field of the data channel takes 11 bits, the RSVDC field takes 0 bits, the Data field takes 256 bits, the Datacheck field takes 0 bits, and the posion field takes 4 bits. After taking the values, the total length of the request channel micro-packet is 107 bits, the total length of the response channel micro-packet is 37 bits, the total length of the monitoring channel is 92 bits, and the total length of the data channel micro-packet is 340 bits. The description of each domain involved in Table 1 is as follows: TgtID is the target identifier, SrcID is the source identifier, ReturnNID is the return network identifier, Addr is the address, RSVDC is the backup domain, FwdNID is the forwarding network identifier, Addr is the address, TgtID is the target identifier, SrcID is the source identifier, HomeNID is the home network identifier, Data is the data domain, and DataCheck is the data check domain. In addition, other compression methods for request, response and data channel micro-packet formats can be used as needed.

[0038] See also Figure 3 In this embodiment, the bandwidths of the request-listen sending buffer, the response sending buffer, the test sending buffer and the data sending buffer are 107 bits, 37 bits, 37 bits and 340 bits respectively. The sending end virtual channel management module of this embodiment puts the micropackets injected by the four channel interfaces of CHI and the test channel into the corresponding buffers. When the sending end virtual channel management module injects a micro-packet into the sending buffer unit, if the micro-packet is a micro-packet of the request channel, the micro-packet of the request channel is directly injected into the request-listening sending buffer with a bit width of 107 bits; if the micro-packet is a micro-packet of the listening channel, before injecting the request-listening sending buffer, the micro-packet of the listening channel is first supplemented with 15 bits of all 0s in the low position, and then injected into the request-listening sending buffer with a bit width of 107 bits so that the request channel can share a set of request-listening sending buffers with the listening channel; if the micro-packet is a micro-packet of the response channel, the micro-packet of the response channel is injected into the response sending buffer with a bit width of 37 bits; if the micro-packet is a micro-packet of the data channel, the micro-packet of the data channel is injected into the data sending buffer with a bit width of 340 bits; if the micro-packet is a micro-packet of the tuning test channel, the micro-packet of the tuning test channel is injected into the tuning test sending buffer with a bit width of 37 bits. In order to support the end-to-end flow control of the CHI protocol channel interface, the sending end virtual channel management module will also perform flow control on the four channels. When the channel does not have enough credit to send a message, the corresponding send buffer will not read data.

[0039] This embodiment provides a CHI protocol packaging rule based on 512 bits. Figure 3 In this embodiment, the bandwidths of the request-listen receive buffer, the response receive buffer, the test receive buffer and the data receive buffer are 108 bits respectively, that is, the bit width of the request-listen receive buffer is one channel flag bit more than the bit width (107 bits) of the request-listen send buffer. When the parsing module parses the micropacket from the received message with a width of 512 bits and sends it to the receive buffer unit, if the micropacket is a micropacket of the request channel or the listen channel, the channel flag bit is set to distinguish whether the micropacket injected into the request-listen receive buffer is a micropacket of the request channel or a micropacket of the listen channel; the bandwidths of the response receive buffer, the test receive buffer and the data receive buffer are the same, which are 37 bits, 37 bits and 340 bits respectively.

[0040] The parsing module implemented at the receiving end parses the channel micro-packet from the received 512-bit message and writes it into the receiving buffer corresponding to the channel. The receiving end channel management module is implemented at the receiving end, which reads the valid channel micro-packet from the receiving buffer and passes it up through the corresponding channel interface. Figure 5 As shown, in this embodiment, the 512-bit wide message consists of 4 parts, and the 4 parts include, from high to low, a 4-bit template TEMP, a 115-bit slot 0 (Slot 0), a 45-bit slot 1 (Slot 1) and a 348-bit slot 2 (Slot 2), and the request channel and the monitoring channel share slot 0, the response channel and the test channel share slot 1, and the data channel exclusively uses slot 2. The template TEMP consists of 4 1-bit valid bits, which are used to indicate the validity of slot 0, slot 1 and slot 2. Based on the mapping rules and the division of each slot into 4 parts: a flag bit, a channel micropacket, a credit bit and a padding bit, efficient communication of chiplet interconnection compatible with the CHI protocol can be achieved.

[0041] It is worth noting that slot 2 only carries data packets, so the slot flag field can only take one value. The cleverness of this design is that it is easy for the adapter layer to insert other 512-bit messages encoded in other ways, so that the 0th bit of the message can be used to distinguish whether it is a message from the protocol layer or a message from the adapter layer. Figure 6As shown, in this embodiment, each of slot 0, slot 1 and slot 2 comprises, from high to low, a 1-bit micropacket flag field FTG, a micropacket field Flit, a 6-bit credit grant field CRD and a 1-bit channel flag field CTG, and the micropacket field Flit of slot 0, slot 1 and slot 2 have different bit widths, wherein the micropacket flag field FTG is used to indicate whether the slot is a micropacket slot or a credit slot, and if it is a micropacket slot, the micropacket field Flit is filled with channel micropackets, and the bit width is determined by the size of the channel micropacket; if it is a credit slot, the micropacket field Flit is filled with all 0s; the credit grant field CRD is filled with the credit value granted to the other end in the end-to-end flow control process, and the channel flag field CTG indicates the channel type filled in the slot.

[0042] In this embodiment, among the 4 valid bits of the template TEMP, the 0th bit indicates that the channel micro-packet sent from the send buffer 0 to slot 0 is valid, the 1st bit indicates that the channel micro-packet sent from the test channel to slot 0 is valid, the 2nd bit indicates that the channel micro-packet sent from the response channel to slot 1 is valid, and the 3rd bit indicates that the channel micro-packet sent from the data channel to slot 2 is valid. Figure 7 Given the parsing template shown, the parsing module parses the micropacket from the received 512-bit width message and sends it to the receiving buffer unit, including:

[0043] First, parse out the template TEMP from bit 508 to bit 511 of the received 512-bit message;

[0044] If the third bit of the template TEMP is 1 and the 347th bit of the micropacket flag field FTG indicates a micropacket slot, the data channel micropacket from the 7th bit to the 346th bit in the micropacket field Flit is parsed and written into the data channel receiving buffer;

[0045] If the second bit of the template TEMP is 1 and the micropacket flag field FTG at bit 392 indicates a micropacket slot, the response channel micropackets at bits 354 to 390 in the micropacket field Flit are parsed and written into the response channel receiving buffer;

[0046] If the first bit of the template TEMP is 1 and the micro-packet flag field FTG at the 392th bit indicates a micro-packet slot, the micro-packets of the debugging and testing channel at the 354th to 390th bits in the micro-packet field Flit are parsed and written into the debugging and testing channel receiving buffer;

[0047] If the 0th bit of the template TEMP is 1 and the 507th bit of the micropacket flag field FTG indicates a micropacket slot, the channel micropacket from the 399th bit to the 505th bit in the micropacket field Flit needs to be parsed out and concatenated with the 392th bit of the channel flag field CTG and then written into the receiving buffer 0;

[0048] The credit grant field CRD of the received 512-bit wide message is parsed out and sent to the credit calculation module of the corresponding channel for credit calculation according to the slot and channel flag field CTG.

[0049] In addition, this embodiment also provides a chip, including a core particle and an interface circuit between core particles, wherein the interface circuit is a core particle interconnection interface protocol layer circuit compatible with the CHI protocol.

[0050] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A chiplet interconnect interface protocol layer circuit compatible with the CHI protocol, characterized in that: The invention comprises a sending unit and a receiving unit in a protocol layer connected to an adapter layer and a physical layer, wherein the sending unit comprises a sending end virtual channel management module, a sending buffer unit and a packaging module which are connected in sequence, wherein the sending end virtual channel management module is used to inject micro packets into the sending buffer unit, wherein the sending buffer unit is used to cache micro packets of each channel and respectively comprises a parallel request-listening sending buffer, a response sending buffer, a debugging and testing sending buffer and a data sending buffer, wherein the packaging module is used to package the micro packets output by the sending buffer unit into a message with a width of 512 bits; wherein the receiving unit comprises a parsing module, a receiving buffer unit and a receiving end virtual channel management module which are connected in sequence, The parsing module is used to parse micro packets from received messages with a width of 512 bits and send them to a receiving buffer unit. The receiving buffer unit includes a parallel request-listening receiving buffer, a response receiving buffer, a debugging and testing receiving buffer, and a data receiving buffer. The micro packets output by the receiving buffer unit are sent to the receiving end through a receiving end virtual channel management module; the request-listening sending buffer and the request-listening receiving buffer both correspond to a request channel and a listening channel at the same time, the response sending buffer and the response receiving buffer both correspond to a response channel, the debugging and testing sending buffer and the debugging and testing receiving buffer both correspond to a debugging and testing channel, and the data sending buffer and the data receiving buffer both correspond to a data channel.

2. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 1, characterized in that: The output ends of the response sending buffer and the debugging and testing sending buffer are also connected to the multiplexing module MUX, and the output ends of the response sending buffer and the debugging and testing sending buffer are connected to the input end of the packaging module through the multiplexing module MUX; the input ends of the response receiving buffer and the debugging and testing receiving buffer are connected to the demultiplexing module DeMUX, and the input ends of the response receiving buffer and the debugging and testing receiving buffer are respectively connected to the output end of the analysis module through the demultiplexing module DeMUX, and the input ends of the request-listening receiving buffer and the data receiving buffer are directly connected to the output end of the analysis module.

3. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 2, characterized in that: When the sending end virtual channel management module injects the micropacket into the sending buffer unit, the target identifier TgtID and the source identifier SrcID field widths in the micropacket formats of the request channel, the response channel and the data channel are set to 0 to achieve compression of the micropacket formats of the request channel, the response channel and the data channel.

4. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 3, characterized in that: When the sending end virtual channel management module injects the micro-packet into the sending buffer unit, if the micro-packet is a micro-packet of the request channel, the micro-packet of the request channel is directly injected into the request-listening sending buffer with a bit width of 107 bits; If the micro-packet is a micro-packet of a listening channel, before injecting the micro-packet into the request-listening sending buffer, the micro-packet of the listening channel is first supplemented with 15 bits of all 0s in the low order, and then injected into the request-listening sending buffer with a bit width of 107 bits so that the request channel can share a set of request-listening sending buffers with the listening channel; If the micro-packet is a micro-packet of the response channel, the micro-packet of the response channel is injected into the response sending buffer with a bit width of 37 bits; If the micropacket is a micropacket of a data channel, the micropacket of the data channel is injected into a data sending buffer with a bit width of 340 bits; if the micropacket is a micropacket of a tuning test channel, the micropacket of the tuning test channel is injected into a tuning test sending buffer with a bit width of 37 bits.

5. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 4, characterized in that: The bit width of the request-listen receive buffer is one channel flag bit more than the bit width of the request-listen send buffer. When the parsing module parses the micropacket from the received 512-bit width message and sends it to the receive buffer unit, if the micropacket is a micropacket of the request channel or the listen channel, the channel flag bit is set to distinguish whether the micropacket injected into the request-listen receive buffer is a micropacket of the request channel or a micropacket of the listen channel.

6. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 5, characterized in that: The 512-bit wide message consists of 4 parts, which include, from high to low, a 4-bit template TEMP, a 115-bit slot 0, a 45-bit slot 1 and a 348-bit slot 2. The request channel and the monitoring channel share slot 0, the response channel and the test channel share slot 1, and the data channel exclusively uses slot 2. The template TEMP consists of 4 1-bit valid bits, which are used to indicate the validity of slot 0, slot 1 and slot 2.

7. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 6, characterized in that: Each of slot 0, slot 1 and slot 2 consists of a 1-bit micropacket flag field FTG, a micropacket field Flit, a 6-bit credit grant field CRD and a 1-bit channel flag field CTG from high to low, and the micropacket field Flit of slot 0, slot 1 and slot 2 has different bit widths, wherein the micropacket flag field FTG is used to indicate whether the slot is a micropacket slot or a credit slot. If it is a micropacket slot, the micropacket field Flit is filled with channel micropackets, and the bit width is determined by the size of the channel micropacket. If it is a credit slot, the micropacket field Flit is filled with all 0s; the credit grant field CRD is filled with the credit value granted to the other end during the end-to-end flow control process, and the channel flag field CTG indicates the channel type filled in the slot.

8. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 7, characterized in that: Among the 4 valid bits of template TEMP, bit 0 indicates that the channel micropacket packaged from send buffer 0 to slot 0 is valid, bit 1 indicates that the channel micropacket packaged from the test channel send buffer to slot 0 is valid, bit 2 indicates that the channel micropacket packaged from the response channel send buffer to slot 1 is valid, and bit 3 indicates that the channel micropacket packaged from the data channel send buffer to slot 2 is valid.

9. The chiplet interconnect interface protocol layer circuit compatible with the CHI protocol according to claim 8, characterized in that: The parsing module parses the micro-packet from the received 512-bit width message and sends it to the receiving buffer unit, including: firstly, parsing the template TEMP from the 508th to the 511th bit of the received 512-bit width message; if the 3rd bit of the template TEMP is 1 and the 347th bit of the micro-packet flag field FTG indicates a micro-packet slot, then parsing the data channel micro-packet from the 7th to the 346th bit in the micro-packet field Flit and writing it into the data channel receiving buffer; if the 2nd bit of the template TEMP is 1 and the 392nd bit of the micro-packet flag field FTG indicates a micro-packet slot, then parsing the response channel micro-packet from the 354th to the 390th bit in the micro-packet field Flit and writing it into the response channel receiving buffer; if the template T If the first bit of EMP is 1 and the 392nd micropacket flag field FTG indicates a micropacket slot, the test channel micropackets at bits 354 to 390 in the micropacket field Flit are parsed and written into the test channel receiving buffer; if the 0th bit of template TEMP is 1 and the 507th micropacket flag field FTG indicates a micropacket slot, the channel micropackets at bits 399 to 505 in the micropacket field Flit are parsed and concatenated with the 392nd channel flag field CTG and written into receiving buffer 0; the credit grant field CRD of the received 512-bit width message is parsed and sent to the credit calculation module of the corresponding channel according to the slot and channel flag field CTG for credit calculation.

10. A chip, comprising a core particle and an interface circuit between the core particles, characterized in that: The interface circuit is a chiplet interconnect interface protocol layer circuit compatible with the CHI protocol as described in any one of claims 1 to 9.

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