A method to solve the problem of multiple layout libraries with the same name being linked to each other

Abstract

The present invention discloses a method for solving the problem of multiple layout libraries with the same name being linked to each other, and relates to the technical field of data processing. The method includes analyzing the design hierarchy structure of the top layer in the design library, identifying and capturing all cells from the top layer to the bottom layer, and generating a list; establishing a new cell library according to the generated list, and copying all cells to the new cell library with new names; entering the new cell library, processing the current level for each cell, and replacing all cell names with new names in the new cell library according to the list; the present invention recursively captures the hierarchical structure of the design library, establishes a complete hierarchical tree, and comprehensively records the information of each cell. By classifying and renaming, the naming conflict and cross-library reference problems of cells with the same name in different libraries or levels are solved, and by systematic analysis and reallocation, the consistency of the same cell in different libraries is ensured to avoid the problem of inconsistent views.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a method for solving the problem of multiple layout libraries with the same name being linked to each other. Background Art

[0002] In the process of handling layout, complex naming and management problems often occur in the design library due to various reasons. For example, different designers perform various layout designs based on the same schematic, which may produce cells with the same name but located in different libraries or with different viewnames. At the same time, in order to solve the problem of the number of dummies in the circuit or other design requirements, designers may need to change libraries or cells, resulting in the same cell appearing in different libraries, causing problems such as inconsistent libraries and views. During the version update process, some cells need to be re-layouted, while other cells may remain in the original library, resulting in cells with the same name but different designs.

[0003] These problems will lead to multiple cells that call each other in the design library, which brings major challenges to subsequent version upgrades and maintenance. In order to solve these problems, some companies have to invest a lot of manpower and time, but this process is prone to errors, such as overwriting cells with the same name in different designs or causing cell positions to change and lose. Other companies choose not to deal with it, resulting in multiple design libraries in the project, which brings difficulties to version control and subsequent maintenance. Some companies rely on CAD personnel to write scripts for processing, but this also has the risk of overwriting the original cells and difficulty in rollback. Summary of the invention

[0004] The purpose of the present invention is to provide a method for solving the problem of multiple layout libraries with the same name being linked to each other, so as to solve the problem of multiple libraries being linked to each other.

[0005] The present application provides a method for solving the problem of multiple layout libraries with the same name being linked to each other, including the following steps:

[0006] Get the top level in the electronic design library, starting from the top cell, recursively and capture all cells at the bottom level;

[0007] By analyzing the top-level design hierarchy in the design library, identify and capture all cells from the top to the bottom, generate a row of cell information according to the cellName viewName libName information, process all cells and generate a list;

[0008] According to the generated list, a new cell library is created, the correctness of the hierarchical relationship and references is verified, and all cells included in the new replacement relationship are copied to the new cell library with new names to avoid the risk of overwriting the original library;

[0009] Among them, according to the generated list, all cell information is sorted, including:

[0010] Catch all cells with the same name, perform lvl on them, merge cells with the same lvl, and record the corresponding replacement relationship to the new library; rename cells with different lvls, and record the corresponding replacement relationship to the new library;

[0011] For cells with different names, directly record the corresponding replacement relationship to the new library;

[0012] By entering the new cell library, for each cell, only the current level is processed, and all cell names are replaced with new names in the new cell library according to the replacement relationship according to the list, so as to organize the new cell library;

[0013] The top level in the electronic design library includes a first subunit and a second subunit, and the first subunit and the second subunit have the same unit name.

[0014] Furthermore, obtaining the top level in the electronic design library also includes determining the hierarchical relationship between the first sub-unit and the second sub-unit; when the first sub-unit is the parent unit of the second sub-unit and there is no cross-library reference relationship between the first sub-unit and the second sub-unit, a first instruction is generated to enable the first sub-unit to use the second sub-unit as its sub-unit.

[0015] Further, when the first subunit is the parent unit of the second subunit and there is a cross-library reference relationship between the first subunit and the second subunit, a second instruction is generated to enable the first subunit to use the second subunit as its subunit and replace it with a new unit library reference relationship.

[0016] Further, determining the hierarchical relationship between the first subunit and the second subunit includes: obtaining the hierarchical relationship between the first subunit and the second subunit by traversing the hierarchical relationship tree of each subunit at the top level in the electronic design library.

[0017] Furthermore, identifying and capturing all cells from the top layer to the bottom layer includes:

[0018] Starting from the top-level cell in the electronic design library, using the recursive function of the EDA tool, we deeply explore and record the detailed information of each child cell, including the name, type, attributes and position in the hierarchical structure. Specifically, we build a hierarchical tree to visualize the relationship between all cells. Each cell from the top to the bottom is identified and recorded. The captured cells are analyzed to identify units with the same name but belonging to different levels or libraries, clarify the parent-child relationship and whether there are cross-level references.

[0019] Furthermore, the top-level design hierarchy structure in the analysis design library includes:

[0020] Traversing the top-level design hierarchy structure in the electronic design library to obtain all units in the design library;

[0021] For any two cells in the design library, if the two cells have the same cell name and belong to different cell libraries or different viewnames, determining whether the two cells are of the same design;

[0022] If any two cells are of the same design, the two cells are classified into the same cell library and use the same cell name;

[0023] If any two cells are not of the same design, the different cell is renamed, and the replacement relationship before and after the renaming is recorded, and then they are included in the same cell library.

[0024] Furthermore, before traversing the top-level design hierarchy structure in the electronic design library to obtain all the units in the design library, it also includes: only copying all the units related to the top-level in the electronic design library.

[0025] Further, determining whether the arbitrary two units are of the same design includes: calculating the similarity between the arbitrary two units; if the similarity between the arbitrary two units is greater than a preset threshold, determining that the arbitrary two units are of the same design.

[0026] Furthermore, the specific steps of establishing a new cell library include:

[0027] Based on the generated list, determine all cells that need to be processed;

[0028] Rebuild the hierarchy in the new unit library according to the new naming rules;

[0029] Copy all cells to the new cell library according to the replacement relationship of replacing them to the new library, and store them according to the new structure classification;

[0030] Verify the correctness of the hierarchical relationships and references, and thoroughly check the cells in the new cell library to ensure that all hierarchical relationships and cell references are correct.

[0031] Furthermore, the newly established unit library is loaded into the simulation environment, and the simulation tool refers to the key units in the new unit library. For each key unit, a test stimulus signal is designed for verification. The test stimulus should cover the functional path of the key unit, including normal operation, boundary conditions and abnormal conditions. Run the simulation tool to perform simulation tests on the key units; use the waveform viewing tool to view the simulation output signal to check whether it meets expectations; for key units with abnormalities, adjust the simulation parameters or input the stimulus and re-simulate.

[0032] The beneficial effects of the present invention are:

[0033] By recursively capturing the hierarchical structure of the design library, comprehensively recording the information and hierarchical relationship of each cell, and establishing a complete hierarchical tree, this process can identify cells with the same name but located in different libraries or hierarchies, and eliminate naming conflicts and cross-library reference problems by categorizing and renaming. At the same time, for those library or cell changes caused by design requirements, this solution ensures the consistency of the same cell in different libraries through systematic hierarchical analysis and reallocation, avoiding view inconsistency problems;

[0034] When processing version updates, by re-establishing the hierarchical structure in the new cell library and copying all cells to the new cell library according to the new naming convention, the risk of overwriting the original library is avoided and the consistency and integrity of the library is maintained. By strictly verifying the hierarchical relationship and references of the new cell library, the structure of the design library is ensured to be clear and the references are reasonable, thereby greatly reducing errors and maintenance difficulties in version control. Ultimately, this solution not only solves the problem of multiple design libraries calling each other, but also greatly simplifies the subsequent version upgrade and management process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0036] Figure 1 A flowchart of a method for solving the problem of multiple layout libraries with the same name being linked to each other provided in Example 1 of the present application;

[0037] Figure 2 A schematic diagram of a flow chart of analyzing the top-level design hierarchy structure in a design library in a method for solving the problem of multiple layout libraries with the same name being linked to each other provided in Example 1 of the present application;

[0038] Figure 3A schematic diagram of a flow chart of establishing a new unit library in a method for solving the problem of multiple layout libraries with the same name being linked to each other provided in Example 1 of the present application. DETAILED DESCRIPTION

[0039] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0040] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0041] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0042] See also Figure 1-Figure 3 This embodiment provides a method for solving the problem of multiple layout libraries with the same name being linked to each other, which is used to solve the problem of multiple libraries being linked to each other.

[0043] The present invention provides a method for solving the problem of multiple layout libraries with the same name being linked to each other, comprising the following steps:

[0044] S1. Get the top layer in the electronic design library, starting from the top cell, recursively and capture all cells at the bottom layer;

[0045] It should be explained that layout is the physical layout design of the integrated circuit (IC), that is, the layout design or geometric layout; cell is the basic unit or module that constitutes a complex integrated circuit. Each cell can represent a logic gate, trigger, storage unit or other circuit component. From the topcell level, all the cells at the bottom layer can be captured. At this time, you can write a script to capture it yourself, or use the tree cell function that comes with Cadence. Determine the outermost cell in the design, which will be the starting point for analysis.

[0046] Specifically, starting from the top-level cell, each child cell is recursively visited. This process will traverse all levels until the bottom-level cells with no child units are reached. During the recursive process, detailed information of each cell is captured, including but not limited to the cell name, type, attributes, location, and the hierarchical relationship between them. Based on the captured information, a hierarchical tree is constructed. This tree structure clearly shows all cells from the top to the bottom and their relationships.

[0047] Further, obtaining the top level in the electronic design library includes a first sub-unit and a second sub-unit, wherein the first sub-unit and the second sub-unit contain the same unit name; determining the hierarchical relationship between the first sub-unit and the second sub-unit; and when the first sub-unit is the parent unit of the second sub-unit and there is no cross-library reference relationship between the first sub-unit and the second sub-unit, generating a first instruction so that the first sub-unit uses the second sub-unit as its sub-unit.

[0048] Further, when the first subunit is the parent unit of the second subunit and there is a cross-library reference relationship between the first subunit and the second subunit, a second instruction is generated to enable the first subunit to use the second subunit as its subunit and replace it with a new unit library reference relationship.

[0049] Further, determining the hierarchical relationship between the first subunit and the second subunit includes: obtaining the hierarchical relationship between the first subunit and the second subunit by traversing the hierarchical relationship tree of each subunit at the top level in the electronic design library.

[0050] An intelligent solution is described for handling the hierarchical relationship between the first subunit and the second subunit with the same name in the design library, which clears the non-compliant references and avoids potential design errors and maintenance problems, ensures a clear hierarchy and reasonable unit references in the electronic design library, avoids naming conflicts and cross-library reference errors, and thus improves the maintainability and scalability of the design.

[0051] S2. By analyzing the top-level design hierarchy in the design library, identify and capture all cells from the top to the bottom, generate a row of cell information according to the information of cellName viewName libName, process all cells and generate a list;

[0052] Specifically, identifying and capturing all cells from the top layer to the bottom layer includes:

[0053] Starting from the top-level cell of the design library, using the recursive function of the EDA tool, we dig deep and record the detailed information of each sub-cell, including the name, type, attributes and their position in the hierarchical structure. Specifically, we build a hierarchical tree to visualize the relationship between all cells, ensure that each cell from the top to the bottom is identified and recorded, analyze the captured cells, identify units with the same name but belonging to different levels or libraries, clarify the parent-child relationship between them and whether there are cross-library references. Based on this information, we generate corresponding instructions to adjust the hierarchical relationship of the cells, resolve any reference conflicts, and finally generate a detailed cell list, which will serve as the basis for subsequent design organization and library management.

[0054] Furthermore, the top-level design hierarchy structure in the analysis design library includes:

[0055] S21, traversing the top-level design hierarchy structure in the electronic design library to obtain all units in the design library;

[0056] S22, for any two units in the design library, if the two units have the same unit name and belong to different unit libraries or different viewnames, determine whether the two units are the same design;

[0057] Among them, viewname is the name of a specific view in the layout. In layout design, a unit can have multiple views, each view showing a different aspect or level of the unit.

[0058] S23, if the two arbitrary units are of the same design, the two arbitrary units are classified into the same unit library and use the same unit name;

[0059] S24. If any two cells are not of the same design, the different cell is renamed, and the replacement relationship before and after the renaming is recorded, and then the cells are included in the same cell library.

[0060] Furthermore, before traversing the top-level design hierarchy structure in the electronic design library to obtain all the units in the design library, it also includes: only copying all the units related to the top-level in the electronic design library.

[0061] Further, determining whether the arbitrary two units are of the same design includes: calculating the similarity between the arbitrary two units; if the similarity between the arbitrary two units is greater than a preset threshold, determining that the arbitrary two units are of the same design.

[0062] Specifically, it is as follows: classification of cells with the same name but in the same library but in different cellviews, identifying and capturing all cells with the same name but in different cellviews, performing a hierarchical check on the cells, classifying the same cells into one cellview, renaming the different ones, and recording the old and new cell names; classification of cells with the same name but in different libraries, identifying and capturing cells with the same name but in different libraries, performing a hierarchical check, classifying the same cells into one library, renaming the different ones, and recording the new cell names; generation of a list after conflict resolution, generating a clear cell list, recording the old and new names of all cells from the topcell to the bottom layer, to ensure that there are no duplicate names and view inconsistencies.

[0063] Specifically, by checking whether there are cross-library references and determining how to handle these references to avoid conflicts in subsequent steps, after completing classification and renaming, a list containing all cell information is generated. This list will serve as the basis for subsequent operations to ensure that each cell has a clear and unique identifier; map the copied cells and update all references to the corresponding cells in the new cell library;

[0064] By recursively analyzing the design hierarchy, cells at all levels are fully captured. Based on the capture, cells with the same name but that may belong to different views or libraries are carefully classified and renamed to resolve potential naming and view conflicts. The effect is to generate an accurate and unambiguous cell list that clearly records the old and new names of all cells and their hierarchical relationships in the design, thereby ensuring the consistency, accuracy and maintainability of the design data. This process is critical for maintaining large and complex integrated circuit design libraries because it helps simplify design management, reduce errors, and lay a solid foundation for future design iterations and upgrades.

[0065] S3. Create a new cell library based on the generated list, and copy all cells included in the new replacement relationship to the new cell library with new names to avoid the risk of overwriting the original library.

[0066] Among them, according to the generated list, all cell information is sorted, including:

[0067] Catch all cells with the same name, and perform lvl (layout vs layout) on them. Merge cells with the same lvl and record the corresponding replacement relationship to the new library. Rename cells with different lvls and record the corresponding replacement relationship to the new library.

[0068] For cells with different names, directly record the corresponding replacement relationship to the new library.

[0069] Specifically, lvl (layout vs layout) is an EDA (Electronic Design Automation) software function used for integrated circuit (IC) back-end physical verification; its main function is to quickly compare two layouts and report the differences between them.

[0070] Specifically, the specific steps of establishing a new cell library include:

[0071] S31. According to the generated list, determine all cells that need to be processed; specifically, use the generated list as a reference to determine that the cells are included in the new cell library, and understand the new names and hierarchical relationships.

[0072] S32. Rebuild the hierarchical structure in the new cell library according to the new naming rules; create an organizational structure in the new cell library to ensure that the placement of each cell follows the new naming rules and hierarchical logic for easy management and identification.

[0073] S33, copying all cells to the new cell library according to the replacement relationship of replacing them to the new library, and storing them according to the new structure classification; using an automated tool or script to copy each cell to the appropriate position in the new cell library while maintaining their hierarchical relationship and classification.

[0074] S34. Verify the correctness of hierarchical relationships and references. Thoroughly check the cells in the new cell library to ensure that all hierarchical relationships and cell references are correct without omissions or errors.

[0075] Furthermore, the newly established unit library is loaded into the simulation environment, and the simulation tool refers to the key units in the new unit library. For each key unit, a test stimulus signal (input signal sequence) is designed to verify its function. The test stimulus should cover the main functional paths of the key unit, including normal operation, boundary conditions and abnormal conditions. Run the simulation tool to perform simulation tests on the key units; use the waveform viewing tool to view the simulation output signal to check whether it meets expectations; for key units with abnormalities, adjust the simulation parameters or input stimulus and re-simulate.

[0076] The specific test stimulus signal is generated according to the characteristics of the test target circuit unit and the test target, including:

[0077] Check that the circuit behavior at maximum and minimum operating limits is expressed as:

[0078] ,in, and They are respectively the maximum and minimum input voltages that the circuit can withstand.

[0079] The maximum and minimum input voltages that the circuit can withstand are expressed as:

[0080] , where f varies from low frequency to high frequency to test the frequency response range of the circuit.

[0081] The ability of the evaluation circuit to respond to fast changing signals is expressed as:

[0082] ,in, is the magnitude of the step change, is the time when the step occurs.

[0083] The anti-interference ability of the circuit to noise signals is expressed as:

[0084] ,in It is a signal of expectation. is the noise signal, which can be Gaussian white noise or other types of noise.

[0085] The behavior of the verification circuit under power supply fluctuations is expressed as:

[0086] ,in is the DC component of the power supply, is the AC fluctuation amplitude, is the fluctuation frequency.

[0087] The sensitivity of the evaluation circuit to interference from other signal sources is expressed as:

[0088] ,in:

[0089] is the main signal, and the summation term represents the interference signals of different frequencies.

[0090] S4. Enter the new cell library, process the current level for each cell, replace all cell names with new names in the new cell library according to the replacement relationship according to the list, and organize the new cell library.

[0091] This embodiment is used to solve the complex problem caused by multiple layout libraries referencing each other in integrated circuit design. The working principle and process of this method are as follows:

[0092] Starting from the top level of the electronic design library in the design library, recursively access and capture units of all levels until the bottom level unit, build a hierarchical tree, and clearly show the relationship between units; identify units with the same name but different levels or libraries, and determine whether they are of the same design by calculating similarity; classify units of the same design and rename units of different designs to solve naming conflicts and cross-library reference problems; according to the generated list, establish a new unit library, and copy all units to the new unit library according to the new naming rules, maintain the original hierarchical structure and the reference relationship between units, and design and apply test stimulus signals for key units in the new unit library. These signals cover normal operation, boundary conditions and abnormal conditions to verify whether the functions of the units meet expectations; use waveform viewing tools to analyze simulation outputs, and adjust simulation parameters or input stimulus for abnormal units, and re-simulate until the design requirements are met; finally, for each unit in the new unit library, replace all unit names with new names in the new unit library according to the hierarchical list to organize the new unit library.

[0093] Through this process, clear and standardized management of the design library is achieved, naming conflicts and reference errors caused by string libraries are avoided, and the maintainability and scalability of the design are improved. At the same time, through precise simulation tests, the functional correctness and reliability of the design are ensured, laying a solid foundation for future design iterations and upgrades.

[0094] Example 2

[0095] This embodiment is different from Embodiment 1 in that it describes the top-level layout adjustment in the electronic design library. It is not only the organization of the design library, but also includes the optimization of the layout of the top-level circuit. By using the hierarchical information to adjust the layout position, this embodiment aims to ensure the structural rationality of the circuit design while improving the circuit performance and the convenience of maintenance. While solving the library management problem, this embodiment also focuses on the optimization of the circuit layout to achieve higher design quality and efficiency.

[0096] This embodiment will identify all circuit units that constitute the top layer in the electronic design library, including the first-level information and the second-level information, and perform precise layout adjustments on these units based on the layout data in the second-level information. In addition, before performing these operations, target layout rules based on performance indicators will be established to ensure that the layout adjustments meet the performance requirements of the circuit. Finally, necessary process adjustments will be made based on the process parameters of the circuit units to ensure that the design meets manufacturing standards. This embodiment is a comprehensive automated method from design file parsing to circuit unit layout and process adjustment, which aims to optimize the performance and manufacturing adaptability of integrated circuit designs.

[0097] Specific content includes:

[0098] Obtain first-level information of a top-level circuit in an electronic design library, and second-level information corresponding to the first-level information; determine all circuit units involved in the top-level circuit according to the first-level information; and adjust all circuit units involved in the top-level circuit according to the second-level information.

[0099] Before obtaining the first-level information of the top-level circuit in the electronic design library and the second-level information corresponding to the first-level information, it also includes: obtaining the design file of the top-level circuit in the electronic design library; parsing the design file of the top-level circuit in the electronic design library to generate a circuit topology structure of the top-level circuit in the electronic design library.

[0100] According to the first level information, all circuit units involved in the top-level circuit in the electronic design library are determined, specifically including: obtaining all circuit units involved in the top-level circuit in the electronic design library by traversing the circuit topology structure.

[0101] According to the second-level information, all circuit units involved in the top-level circuit in the electronic design library are adjusted, specifically including: according to the second-level information, obtaining layout data of all circuit units involved in the top-level circuit in the electronic design library; according to the layout data, adjusting the layout of all circuit units involved in the top-level circuit in the electronic design library.

[0102] Before obtaining the first level information of the top-level circuit in the electronic design library and the second level information corresponding to the first level information, it also includes: establishing a target layout rule; wherein the target layout rule is determined according to the performance index of the top-level circuit in the electronic design library.

[0103] According to the second-level information, all circuit units involved in the top-level circuit in the electronic design library are adjusted, specifically including: according to the second-level information, obtaining target layout data of all circuit units involved in the top-level circuit in the electronic design library; according to the target layout data, adjusting the layout of all circuit units involved in the top-level circuit in the electronic design library;

[0104] The method also includes obtaining process parameters of all circuit units involved in the top-level circuit in the electronic design library; and performing process adjustments on all circuit units involved in the top-level circuit in the electronic design library according to the process parameters.

[0105] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for solving the problem of multiple layout libraries with the same name being linked to each other, characterized in that: The steps include: Get the top level in the electronic design library, starting from the top cell, recursively and capture all cells at the bottom level; By analyzing the top-level design hierarchy in the design library, identify and capture all cells from the top to the bottom, generate a row of cell information according to the cellName viewName libName information, process all cells and generate a list; According to the generated list, a new cell library is created, the correctness of the hierarchical relationship and references are verified, and all cells included in the new replacement relationship are copied to the new cell library with the new name; Among them, according to the generated list, all cell information is sorted, including: Catch all cells with the same name, perform lvl on them, merge cells with the same lvl, and record the corresponding replacement relationship to the new library; rename cells with different lvls, and record the corresponding replacement relationship to the new library; For cells with different names, directly record the corresponding replacement relationship to the new library; By entering the new cell library, processing the current level for each cell, and replacing all cell names with new names in the new cell library according to the replacement relationship according to the list, the new cell library is organized; The top level in the electronic design library includes a first subunit and a second subunit, and the first subunit and the second subunit have the same unit name.

2. A method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 1, characterized in that: Obtaining the top level within the electronic design library also includes determining the hierarchical relationship between the first sub-unit and the second sub-unit; when the first sub-unit is the parent unit of the second sub-unit and there is no cross-library reference relationship between the first sub-unit and the second sub-unit, generating a first instruction to enable the first sub-unit to use the second sub-unit as its sub-unit.

3. A method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 2, characterized in that: When the first subunit is the parent unit of the second subunit and there is a cross-library reference relationship between the first subunit and the second subunit, a second instruction is generated to make the first subunit use the second subunit as its subunit and replace it with a new unit library reference relationship.

4. A method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 2, characterized in that: Determining the hierarchical relationship between the first subunit and the second subunit includes: obtaining the hierarchical relationship between the first subunit and the second subunit by traversing the hierarchical relationship tree of each subunit at the top level in the electronic design library.

5. The method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 2, characterized in that: Identify and capture all cells from the top to the bottom layer including: Starting from the top-level cell in the electronic design library, using the recursive function of the EDA tool, we deeply explore and record the detailed information of each child cell, including the name, type, attributes and position in the hierarchical structure. Specifically, we build a hierarchical tree to visualize the relationship between all cells. Each cell from the top to the bottom is identified and recorded. The captured cells are analyzed to identify units with the same name but belonging to different levels or libraries, clarify the parent-child relationship and whether there are cross-level references.

6. A method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 1, characterized in that: The top-level design hierarchy within the analysis design library includes: Traversing the top-level design hierarchy structure in the electronic design library to obtain all units in the design library; For any two cells in the design library, if the two cells have the same cell name and belong to different cell libraries or different viewnames, determining whether the two cells are of the same design; If any two cells are of the same design, the two cells are classified into the same cell library and use the same cell name; If any two cells are not of the same design, the different cell is renamed, and the replacement relationship before and after the renaming is recorded, and then they are included in the same cell library.

7. A method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 6, characterized in that: Before traversing the top-level design hierarchy structure in the electronic design library to obtain all the units in the design library, the method further includes: only copying all the units related to the top-level in the electronic design library.

8. A method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 6, characterized in that: Determining whether the arbitrary two units are of the same design includes: calculating the similarity between the arbitrary two units; if the similarity between the arbitrary two units is greater than a preset threshold, determining that the arbitrary two units are of the same design.

9. The method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 1, characterized in that: The specific steps to create a new cell library include: Based on the generated list, determine all cells that need to be processed; Rebuild the hierarchy in the new unit library according to the new naming rules; Copy all cells to the new cell library according to the replacement relationship of replacing them to the new library; Verify the correctness of the hierarchical relationships and references, and thoroughly check the cells in the new cell library to ensure that all hierarchical relationships and cell references are correct.

10. A method for solving the problem of multiple layout libraries with the same name being linked to each other according to claim 9, characterized in that: Load the newly created cell library into the simulation environment, and let the simulation tool reference the key cells in the new cell library. Design test stimulus signals for each key cell to verify it. The test stimulus should cover the functional path of the key cell, including normal operation, boundary conditions, and abnormal conditions. Run the simulation tool to perform simulation tests on the key cells. Use the waveform viewing tool to view the simulation output signal to check whether it meets expectations; for key units with abnormalities, adjust the simulation parameters or input stimulus and re-simulate.

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