Network-on-chip simulation method, device, equipment and storage medium

Abstract

The application provides a network-on-chip simulation method and device, electronic equipment and computer readable storage medium, and relates to the technical field of computers, which comprises determining each hardware unit used to constitute a network-on-chip, and determining the execution actions included in the hardware unit in each execution cycle; constructing the execution code segment of each hardware unit in the execution cycle through a preset compilation language according to the execution actions included in the hardware unit; constructing a network-on-chip design file according to the execution code segment of each hardware unit; and performing simulation running on the network-on-chip design file to obtain a simulation running result. The application simulates all execution actions of the hardware unit in each execution cycle, and the migration of the execution actions occurs over time, so that the flow of the execution actions of the hardware unit in the execution cycle is simulated through the scheduling of the simulation process, which can more meticulously construct the design file of the entire network-on-chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a network-on-chip simulation method and device, electronic equipment and computer readable storage medium. BACKGROUND

[0002] The circuit design file is a file written by a high-level language, which is used to describe the internal structure and characteristics of the circuit.

[0003] At present, for the field of network-on-chip, a set of state machines can be constructed for each network layer data packet by taking the transmitted network layer data packet as an index, so as to realize logical modeling and obtain a network-on-chip design file.

[0004] However, the network-on-chip design file constructed by taking the transmitted network layer data packet as an index has poor precision. SUMMARY

[0005] Embodiments of the present application provide a network-on-chip simulation method and device, electronic equipment and computer readable storage medium, to solve the problems in the related art.

[0006] In a first aspect, the embodiments of the present application provide a network-on-chip simulation method, and the method comprises the following steps:

[0007] determining each hardware unit used to constitute a network-on-chip, and determining the execution actions included in each hardware unit in each execution cycle;

[0008] constructing, by a preset compilation language, an execution code segment of each hardware unit in the execution cycle according to the execution actions included in the hardware unit;

[0009] constructing a network-on-chip design file according to the execution code segments of all the hardware units;

[0010] performing simulation running on the network-on-chip design file to obtain a simulation running result.

[0011] In a second aspect, the embodiments of the present application provide a network-on-chip simulation device, and the device comprises:

[0012] a determination module, configured to determine each hardware unit used to constitute a network-on-chip, and determine the execution actions included in each hardware unit in each execution cycle;

[0013] a first construction module, configured to construct, by a preset compilation language, an execution code segment of each hardware unit in the execution cycle according to the execution actions included in the hardware unit;

[0014] a second construction module, configured to construct a network-on-chip design file according to the execution code segments of all the hardware units.

[0015] running a module for simulating running of the network-on-chip design file to obtain a simulation running result.

[0016] In a third aspect, an electronic device is provided, including a processor;

[0017] a memory for storing the processor-executable instructions;

[0018] The processor is configured to execute the instructions to implement the method of the first aspect.

[0019] In a fourth aspect, a computer-readable storage medium is provided, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method of the first aspect.

[0020] In the embodiments of the present application, according to the execution actions included in the hardware units in the network-on-chip, the execution code segments of each hardware unit in an execution cycle are constructed by a preset compiling language, and the network-on-chip design file is constructed according to the execution code segments of all hardware units, to simulate running of the network-on-chip design file to obtain a simulation running result. The embodiments of the present application can simulate all execution actions of the hardware units in each execution cycle with the execution cycle as an index, and the migration of the execution actions occurs with the passage of time, so that the flow of the execution actions of the hardware units in the execution cycle is simulated through the scheduling of the simulation process, which can more meticulously construct the design file of the entire network-on-chip.

[0021] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 is a step flowchart of a network-on-chip simulation method provided by the embodiments of the present application;

[0024] Figure 2 is a specific step flowchart of a network-on-chip simulation method provided by the embodiments of the present application;

[0025] Figure 3 is a timing logic diagram of a routing module in a network on chip provided by an embodiment of the present application;

[0026] Figure 4 is a code structure diagram of a routing module in a network on chip provided by an embodiment of the present application;

[0027] Figure 5 is a structure diagram of a node of a network on chip provided by an embodiment of the present application;

[0028] Figure 6 is a connection mode schematic diagram between nodes of a network on chip provided by an embodiment of the present application;

[0029] Figure 7 is a structure of a network on chip provided by an embodiment of the present application;

[0030] Figure 8 is a block diagram of a network on chip simulation device provided by an embodiment of the present application;

[0031] Figure 9 is a block diagram of an electronic device provided by an embodiment of the present application;

[0032] Figure 10 is a block diagram of another electronic device of another embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0034] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the relationship between the associated objects, which means that there are three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0035] Figure 1 is a step flow chart of a network-on-chip simulation method provided by the embodiments of the present application, as shown in Figure 1 The method can include the following steps.

[0036] Step 101, determining each hardware unit used to constitute a network-on-chip, and determining the execution actions included in each hardware unit in each execution cycle.

[0037] In actual applications, although each processor core in a multi-core processor performs its own code, data sharing and synchronization are required between the processor cores, and therefore the multi-core processor hardware structure must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.

[0038] Therefore, the network-on-chip (NOC) is a key technology of the multi-processor architecture, is an interconnection path and a communication network in the processor, is responsible for message transmission, and is the basis for the cooperative work of the processor. The network-on-chip aims to solve the communication problem in the multi-core processor. The network-on-chip is an integrated circuit on a network-based communication subsystem, and is a router-based packet switching network between system-on-chips. The network-on-chip technology draws on the interconnection network structure of parallel computers, integrates a large number of computing resources and on-chip communication networks connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through the on-chip communication network. The processor cores use a message communication mechanism, and use router and packet switching technology to replace the on-chip bus of related technologies to complete the communication task, thereby solving various bottleneck problems caused by the bus interconnection of related technologies.

[0039] The network-on-chip can include a plurality of hardware units, which can include a routing module, an access device, a consistency module, a processor core, a buffer, etc., wherein the routing module is an important constituent unit of the network-on-chip, and the routing module is used to implement important functions in the network-on-chip, such as routing calculation and data arbitration. In addition, the number of routing modules can be multiple, and the multiple routing modules can be connected with each other, and the routing module can also be connected with other access devices, such as an access device connected with an injection port of the routing module, which can include a memory, a graphics card, a network card and other external devices, that is, the function implementation of the multi-core processor architecture is improved by selecting a rich additional access device.

[0040] In this step, when the network-on-chip is working, the hardware units implement related functions by performing the same execution action in each execution cycle, and different hardware units in the network-on-chip include different execution actions. For example, each execution cycle of the routing module can include execution actions such as routing path calculation, data packet arbitration and routing strategy selection. Each execution cycle of the buffer can include execution actions such as push, pop, empty check and full check.

[0041] Step 102, according to the execution action included in the hardware unit, an execution code segment of each hardware unit in the execution cycle is constructed by a preset compilation language.

[0042] In a related technology, a set of state machines can be constructed for each network layer data packet by taking the transmitted network layer data packet as an index, and the time delay and other parameters of the network layer data packet in the routing module are calculated according to the time overlap of the current network layer data packet and other network layer data packets in the same routing module or buffer. However, the design file of the network-on-chip constructed based on this way cannot meet the requirement of further design in the precision of the description of hardware details.

[0043] Therefore, the embodiment of the present application aims to construct all states of the hardware unit in each execution cycle by taking the time cycle as an index, and the state migration occurs with the passage of time. Compared with the related technology, this way can realize very free topology and real-time simulation of the hardware unit by hardware unit modeling and highly hardware-like topology construction, and the execution action of the hardware unit in the execution cycle can be simulated by the scheduling of the simulation process, so that the design file of the entire network-on-chip can be constructed in detail.

[0044] Specifically, the embodiment of the present application can use a high-level language (such as python) to write the design file of the network on chip, and the embodiment of the present application can use a single-step simulator model (Network on Chip) to construct the design file of the network on chip. The single-step simulator model supports the configuration of a large number of parameters such as the size of the network on chip, the number and location of processing elements (PE, Processing Element), the structure and function of the routing module, the injection rate (the probability of a PE injecting a packet per cycle), and the like.

[0045] In addition, the single-step simulator model also has high scalability, and can add any new routing algorithm, arbitration algorithm, topology network structure, modify any bus protocol, modify any hardware unit, modify the execution action of the hardware unit, modify to any discrete clock domain, and the like. The PE can be mounted with any form of load, such as the master node, the request node, and the like in the bus coherence protocol (CHI, Coherent Hub Interface), or directly mounted with an analog processor core. In addition, based on python 3.10, the single-step simulator model can introduce a large number of new dynamic routing methods containing machine learning.

[0046] In this step, the execution code segment of each hardware unit in the execution cycle can be first constructed according to the execution actions included in the hardware unit by using a preset compilation language, and the execution code segment is used to control the corresponding hardware unit to execute a fixed plurality of execution actions in each execution cycle. In the process of constructing the execution code segment, the writing order of the execution actions in the execution code segment can be determined according to the dependency relationship between the execution actions. Thus, the embodiment of the present application constructs the network on chip with the execution actions of the hardware unit in the execution cycle as the dimension. Such design can index each execution cycle with the time period to determine all states of the hardware unit in each execution cycle, and the state migration occurs with the passage of time. The execution actions of the hardware unit in the execution cycle are simulated through the scheduling of the simulation process, and the design file of the entire network on chip can be constructed in detail.

[0047] For example, assuming that a hardware unit A of the network on chip includes execution actions a, b, and c. Then for the hardware unit A, the execution statements of the execution actions a, b, and c can be written by using the compilation language, and the writing order of the execution actions a, b, and c in the execution code segment can be determined according to the dependency relationship between the execution actions a, b, and c. Thus, the execution code segment of the hardware unit A is constructed, and the execution code segment of the hardware unit A can control the hardware unit A to sequentially execute the execution actions a, b, and c in each execution cycle according to the execution order.

[0048] Step 103, constructing a network-on-chip design file according to the execution code segments of all the hardware units respectively.

[0049] In the embodiment of the present application, after the execution code segments of each hardware unit are constructed independently, the execution code segments of all the hardware units can be summarized into a set of network-on-chip design files. In the process of summarizing the execution code segments of all the hardware units into a set of network-on-chip design files, the result assignment code segments between the hardware units can be written according to the input-output relationship between the hardware units, so as to meet the data interaction requirements between the hardware units in the network-on-chip.

[0050] For example, the embodiment of the present application can provide a channel for managing the running state of each hardware unit and a connection port for all access devices at the top layer (network layer) of the summarized network-on-chip design file. Subsequently, the network-on-chip design file can be imported into a simulated running environment for simulation running and verification, or the verified network-on-chip design file can be written to a board card for work.

[0051] Step 104, simulating running the network-on-chip design file to obtain a simulation running result.

[0052] In the embodiment of the present application, in the process of verifying the network-on-chip design file, the network-on-chip design file can be imported into the verification platform built for compilation and running to obtain a measured running result. Then, the measured running result can be compared with a preset reference running result. If they are consistent, the verification result is passed. If they are inconsistent, the verification result is failed.

[0053] In addition, in the case of passing the verification, the network-on-chip design file can be burned to a board card for running, thereby completing the landing of the network-on-chip design.

[0054] In summary, in the embodiment of the present application, according to the execution actions included in the hardware units in the network-on-chip, the execution code segments of each hardware unit in the execution period can be constructed by a preset compilation language, and a network-on-chip design file can be constructed according to the execution code segments of all the hardware units respectively, so as to simulate running the network-on-chip design file to obtain a simulation running result. The embodiment of the present application can simulate all the execution actions of the hardware units in each execution period with the execution period as an index, and the migration of the execution actions occurs with the passage of time, so as to simulate the flow of the execution actions of the hardware units in the execution period through the scheduling of the simulation process. In this way, the design file of the entire network-on-chip can be constructed more meticulously.

[0055] Figure 2 is a specific step flowchart of a network-on-chip simulation method provided by the embodiment of the present application, as shown inFigure 2 The method can include:

[0056] Step 201, determining each hardware unit for constituting a network-on-chip, and determining an execution action included in each hardware unit in each execution cycle.

[0057] This step can refer to the above step 101, and will not be described here.

[0058] Step 202, determining a dependency relationship between the execution actions.

[0059] Step 203, constructing an execution code segment of each hardware unit in the execution cycle by a preset compiling language according to the dependency relationship.

[0060] In the embodiment of the present application, for steps 202-203, the dependency relationship reflects the constraint relationship and flow sequence between the execution actions, for example, if one execution action needs to wait for another execution action to be executed before being executed, then there is a dependency relationship between the two execution actions. Or one execution action needs to obtain the output result of another execution action before being executed, then there is also a dependency relationship between the two execution actions.

[0061] Specifically, according to the dependency relationship, the writing order of the execution statements corresponding to the execution actions in the execution code segment can be determined, so the embodiment of the present application can specifically construct the execution code segment of each hardware unit in the execution cycle by the preset compiling language according to the dependency relationship.

[0062] Optionally, the execution actions include a first execution action and a second execution action with a dependency relationship; step 203 can specifically include:

[0063] Sub-step 2031, writing a first execution statement corresponding to the first execution action and a second execution statement corresponding to the second execution action in the execution code segment by the preset compiling language.

[0064] Sub-step 2032, determining the writing order of the first execution statement and the second execution statement in the execution code segment according to the dependency relationship, thereby constructing the execution code segment of the hardware unit in the execution cycle.

[0065] In the embodiment of the present application, for sub-steps 2031-2032, if the execution action includes a first execution action and a second execution action with a dependency relationship, the embodiment of the present application can determine the writing order of the first execution statement and the second execution statement in the execution code segment according to the dependency relationship, thereby constructing the execution code segment of the hardware unit in the execution period. When the on-chip network is subsequently run, the execution code segment can control the first execution statement of the first execution action and the second execution statement of the second execution action to perform according to the correct execution order, thereby meeting the requirements of the dependency relationship of the first execution action and the second execution action. Thus, the embodiment of the present application can index the time period to construct all states (execution actions) of the hardware unit in each execution period, and the state (execution action) migration occurs over time. Compared with the related art, this way can realize very free topology and real-time simulation of the hardware unit through hardware unit-oriented modeling and highly hardware-like topology construction, and simulate the execution action of the hardware unit in the execution period through the scheduling of the simulation process, thereby being able to construct the design file of the entire on-chip network in detail.

[0066] Optionally, the dependency relationship is that the first execution action is used to complete execution after obtaining the execution result of the second execution action. Sub-step 2031 can specifically include:

[0067] Sub-step 20311, in the execution code segment, the first execution statement is written before the second execution statement.

[0068] In the embodiment of the present application, the dependency relationship can be specifically refined as the relationship between the producer and the consumer, that is, the consumer can consume only after the producer produces the product. In the embodiment of the present application, if the first execution action is used to complete execution after obtaining the execution result of the second execution action, the first execution action can be the consumer role and the second execution action can be the producer role.

[0069] In the specific determination of the writing order of the first execution statement of the first execution action and the second execution statement of the second execution action in the execution code segment, the first execution statement can be written before the second execution statement. The purpose is that in an execution cycle 1, the first execution statement written first is not executed because the execution result of the second execution statement is not obtained, the second execution statement written later can be executed and the execution result is generated, and then in the next execution cycle 2, the first execution statement can obtain the execution result of the second execution statement in the execution cycle 1 and perform execution. For another example, in an execution cycle 1, the first execution statement written first can obtain the execution result of the second execution statement in the last execution cycle 0 and perform execution, and the second execution statement written later can be executed and the execution result of the execution cycle 1 is generated. Then in the next execution cycle 2, the first execution statement can obtain the execution result of the second execution statement in the execution cycle 2 and perform execution, and the second execution statement can be executed and the execution result of the execution cycle 2 is generated.

[0070] If there are a large number (more than 2) of execution actions in an execution cycle, two execution actions with a dependency relationship can be found among the execution actions, and the respective roles of the execution actions are determined. The execution code is written according to the rule that the execution statement of the consumer role is written before the execution statement of the producer role.

[0071] For example, it is assumed that the hardware unit A includes execution actions a, b and c, wherein there is a dependency relationship between the execution actions a and b, there is a dependency relationship between the execution actions b and c, the execution action a needs to obtain the running result of the execution action b to be executed, and the execution action b needs to obtain the running result of the execution action c to be executed. When writing the execution code segment of the hardware unit A, the execution statement of the execution action a is written before the execution statement of the execution action b, and the execution statement of the execution action b is written before the execution statement of the execution action c, that is, the writing order of the execution statement a—execution statement b—execution statement c is obtained.

[0072] In step 204, the on-chip network design file is constructed according to the respective execution code segments of all the hardware units.

[0073] The step can specifically refer to the above-mentioned step 103, and will not be described here.

[0074] Optionally, in an implementation manner, the step 204 can specifically include:

[0075] In sub-step 2041, the input-output relationship between the hardware units is determined.

[0076] In sub-step 2042, the result assignment code segment between the hardware units is written by using the preset compiling language according to the input-output relationship.

[0077] Sub-step 2043: constructing the on-chip network design file according to the result assignment code segment and the execution code segment of each hardware unit.

[0078] In the embodiment of the present application, for sub-steps 2041-2043, the on-chip network is composed of hardware units, and in order to realize data transmission within the on-chip network, data interaction between the hardware units of the on-chip network is needed. Therefore, when constructing the on-chip network design file, in addition to writing the execution code segment of each hardware unit, the result assignment code segment between the hardware units can also be written by using a preset compiling language. The result assignment code segment is used to control data interaction between the hardware units in the on-chip network, and the result assignment code segment can be specifically written based on the input-output relationship between the hardware units.

[0079] The input-output relationship between the hardware units is used to control data flow between the hardware units. For example, assuming that there are hardware 1 and hardware 2, if hardware 2 needs the output result of hardware 1, the output value of hardware 2 can be assigned to hardware 1 for use, that is, there is an input-output relationship between hardware 1 and hardware 2. The result assignment code segment written for hardware 1 and hardware 2 is a code segment for realizing the process of assigning the output value of hardware 2 to hardware 1 for use.

[0080] Optionally, in another implementation manner, step 204 can specifically include:

[0081] Sub-step 2044: constructing a calculation code segment for simulating calculation of the power consumption of the on-chip network according to the static power consumption calculation rule and the dynamic power consumption calculation rule.

[0082] Sub-step 2045: constructing the on-chip network design file according to the calculation code segment and the execution code segment of each hardware unit.

[0083] In the embodiment of the present application, for sub-steps 2044-2045, the on-chip network design file of the embodiment of the present application also supports simulating calculation of the power consumption of the on-chip network, and the on-chip network can be accurately analyzed in performance / power consumption by using this model subsequently.

[0084] Specifically, the simulation calculation of the power consumption can be divided into static power consumption calculation and dynamic power consumption calculation. The embodiment of the present application can construct a calculation code segment for simulating calculation of the power consumption of the on-chip network according to the static power consumption calculation rule and the dynamic power consumption calculation rule, and add the calculation code segment to the on-chip network design file.

[0085] Optionally, the static power consumption calculation rule is used to calculate the static power consumption of the hardware unit according to a data bit width of the hardware unit and a preset corresponding relationship between data bit widths and power consumptions; the dynamic power consumption calculation rule is used to calculate the dynamic power consumption of the hardware unit according to an execution action included in the hardware unit and an action power consumption corresponding to each execution action; and the total power consumption of the hardware unit is a sum of the static power consumption and the dynamic power consumption of the hardware unit.

[0086] In the embodiments of the present application, static power consumption calculation is implemented by judging which components in the network-on-chip to calculate power consumption. In hardware, these components are all built by circuits, and the circuits have leakage current loss, so all the components have self power consumption. In software simulation of the network-on-chip, the power consumption can be simplified into several parts: power consumption of a buffer, power consumption of a routing module, power consumption of a direction selection module (selection), and power consumption of an output module (Crossbar). These power consumptions have corresponding relationships with data such as configured data bit widths, and the corresponding relationships can be built into a mapping table obtained through mathematical calculation. For example, when XY routing (a kind of selection of the routing module) is performed in simulation, the static power consumption is 1.20e-4 Joule, and if WEST_FIRST routing (another kind of routing module) is selected, the static power consumption is 1.28e-4 Joule. For example, if a fifo (a kind of buffer following first-in-first-out) with a depth of 2 and an entry bit width of 128 bits is selected, the static power consumption is 5.0e-3 Joule, and if a fifo with a depth of 4 and an entry bit width of 256 bits is selected, the static power consumption is 1.64e-2 Joule. These power consumption values are known and can be directly called according to the selection.

[0087] The dynamic power consumption is calculated by analyzing the operations performed by each component, including the power consumption of the push and pop operations of the buffer, the push and pop power consumption of the buffer to the tile, the push and pop power consumption of the tile to the buffer, the power consumption of the routing module (power consumption required for each execution), the power consumption of the selection module, the power consumption of the crossbar output module, and the transmission power consumption of the line (power consumption of transmitting a flit from a to b). These power consumptions are counted once for each execution of a specific operation in the program, simulating the power consumed by the hardware for the specific operation. The dynamic power consumption is also calculated from the pre-calculated simulation power consumption, for example, if a fifo (first-in, first-out buffer) with a selection depth of 2 and an entry bit width of 128 bits is used, the energy consumed when performing a push operation is 2.25e-12 joules, and the energy consumed when performing a pop operation is 1.25e-12 joules. In the simulation of the network-on-chip, the operation is performed multiple times, and each time the operation needs to be counted.

[0088] Step 205, simulating the running of the network-on-chip design file to obtain simulation running results.

[0089] This step can refer to the above-mentioned step 104, and will not be repeated here.

[0090] In an example, the execution code segment is written for the hardware unit buffer, which can be written as a class containing various execution actions, such as push, pop, empty check, full check, etc.

[0091] Suppose that according to the dependency relationship between the execution actions, the writing order of the hardware unit buffer is determined as follows: the clock period updating action is written before the setting buffer capacity action, the setting buffer capacity action is before the checking maximum buffer capacity action, the checking maximum buffer capacity action is before the checking how much capacity is left in the buffer action, the checking how much capacity is left in the buffer action is before the checking whether the buffer is full action, the checking whether the buffer is full action is before the checking whether the buffer capacity is empty action, the checking whether the buffer capacity is empty action is before the error reporting action when the buffer is full and the push operation continues, and the error reporting action when the buffer is full and the push operation continues is before the error reporting action when the buffer is empty and the pop operation continues. The execution code segment of the hardware unit buffer includes:

[0092] def Update_cycle(self, clock):

[0093] self.clock = clock # Clock cycle update function

[0094] def SetMaxBufferSize(self, bms): # Set Buffer max size (in flits)

[0095] assert bms > 0

[0096] self.max_buffer_size = bms # Set the capacity of this buffer function

[0097] def GetMaxBufferSize(self): # Get max buffer size

[0098] return self.max_buffer_size # Function to view the maximum capacity of this buffer

[0099] def getCurrentFreeSlots(self): # free buffer slots

[0100] return self.max_buffer_size - len(self.buffer) # Function to view how much capacity is left in this buffer

[0101] def IsFull(self): # Returns true if buffer is full

[0102] return len(self.buffer) == self.max_buffer_size # Check if this buffer is full

[0103] def IsEmpty(self): # Returns true if buffer is empty

[0104] return len(self.buffer) == 0 # Check if this buffer is empty

[0105] def Drop(self, flit): # Called by Push() when buffer is full

[0106] assert False # When buffer is full, error if continue push;

[0107] def Empty(self): #Called by Pop() when buffer is empty

[0108] assert False # When buffer is empty, error if continue pop.

[0109] Referring to Figure 3 , it shows the timing logic of the routing module in the network on chip, wherein the execution actions of the routing module include: input buffer action, arbitration action, distribution action, when writing the execution code segment of the routing module, the distribution action can be written before the arbitration action, and the arbitration action can be written before the previous input buffer action based on the dependency relationship between the actions. Specifically, after a data packet passes through the selection of the routing strategy, the data packet is transmitted from the virtual channel indicated by the routing transmission path based on the routing transmission path calculation of the routing strategy, and then the data packet is output to the distribution channel for data distribution based on the arbitration of the selected arbitration strategy, thereby realizing the processing of the routing module on one data packet.

[0110] Further referring to Figure 4 , it shows the code structure of the routing module in the network on chip, including: arbitration submodule, input / output queue, local routing table, routing submodule, data verification submodule, switch allocation submodule, distribution submodule.

[0111] Further referring to Figure 5 , it shows the structure of one node of the network on chip, including: routing module, processing unit, and the routing module and the processing unit are connected through the transmission protocol.

[0112] Further referring to Figure 6 , it shows the connection mode between the nodes of the network on chip, wherein the nodes are connected with each other through the transmission protocol and the judgment module, and the judgment module is used to judge whether the current destination routing module has a free position to process data.

[0113] Finally referring to Figure 7 , it shows the structure of the network on chip, it can be seen that the network on chip is composed of an array structure (4x4 specification) of multiple nodes, realizing the horizontal and vertical (X / Y direction) transmission of data in the network on chip. Figure 7

[0114] ​To sum up, in the embodiment of the application, the execution code segment of each hardware unit in an execution period can be constructed by a preset compiling language according to the execution actions included by the hardware unit in the network on a chip, and the network on a chip design file can be constructed according to the execution code segments of all the hardware units, so as to simulate and run the network on a chip design file to obtain a simulation running result. The embodiment of the application can simulate all the execution actions of the hardware unit in each execution period by taking the execution period as an index, and the migration of the execution actions occurs with the passage of time, so that the flow of the execution actions of the hardware unit in the execution period is simulated by the scheduling of the simulation process, which can more finely construct the design file of the entire network on a chip.

[0115] Figure 8 is a block diagram of a network on a chip simulation device provided by the embodiment of the application, which comprises:

[0116] The determining module 301 is configured to determine the hardware units for constituting the network on a chip, and determine the execution actions included by the hardware units in each execution period.

[0117] The first constructing module 302 is configured to construct the execution code segment of each hardware unit in the execution period by a preset compiling language according to the execution actions included by the hardware units.

[0118] The second constructing module 303 is configured to construct the network on a chip design file according to the execution code segments of all the hardware units.

[0119] The running module 304 is configured to simulate and run the network on a chip design file to obtain a simulation running result.

[0120] Optionally, the first constructing module 302 comprises:

[0121] The dependency determining sub-module is configured to determine the dependency relationship between the execution actions.

[0122] The first compiling sub-module is configured to construct the execution code segment of each hardware unit in the execution period by a preset compiling language according to the dependency relationship.

[0123] Optionally, the execution actions comprise a first execution action and a second execution action with a dependency relationship.

[0124] The first compiling sub-module comprises:

[0125] The first compiling unit is configured to compile the first execution statement corresponding to the first execution action and the second execution statement corresponding to the second execution action in the execution code segment by the preset compiling language.

[0126] The second compiling unit is configured to determine the compiling order of the first execution statement and the second execution statement in the execution code segment according to the dependency relationship, thereby constructing the execution code segment of the hardware unit in the execution cycle.

[0127] Optionally, the dependency relationship is that the first execution action is used to complete execution after obtaining the execution result of the second execution action.

[0128] The second compiling unit comprises:

[0129] The compiling sub-unit compiles the first execution statement before the second execution statement in the execution code segment.

[0130] Optionally, the second constructing module 303 comprises:

[0131] The determining sub-module is configured to determine the input-output relationship between the hardware units.

[0132] The third compiling sub-module is configured to compile the result assignment code segment between the hardware units by using the preset compiling language according to the input-output relationship.

[0133] The first constructing sub-module is configured to construct the network-on-chip design file according to the result assignment code segment and the respective execution code segments of the hardware units.

[0134] Optionally, the second constructing module 303 comprises:

[0135] The second constructing sub-module is configured to construct a calculation code segment for simulating the calculation of the power consumption of the network-on-chip according to the static power consumption calculation rule and the dynamic power consumption calculation rule.

[0136] The third constructing sub-module is configured to construct the network-on-chip design file according to the calculation code segment and the respective execution code segments of all the hardware units.

[0137] Optionally, the static power consumption calculation rule is used to calculate the static power consumption of the hardware unit according to the data bit width of the hardware unit and a preset corresponding relationship between data bit width and power consumption.

[0138] The dynamic power consumption calculation rule is used to calculate the dynamic power consumption of the hardware unit according to the execution actions included in the hardware unit and the action power consumption corresponding to each execution action.

[0139] The total power consumption of the hardware unit is the sum of the static power consumption and the dynamic power consumption of the hardware unit.

[0140] To sum up, in the embodiment of the present application, the execution code segments of each hardware unit in an execution cycle can be constructed by a preset compiling language according to the execution actions included in the hardware unit in the network-on-chip, and the network-on-chip design file can be constructed according to the execution code segments of all hardware units, so as to simulate and run the network-on-chip design file to obtain a simulation running result. The embodiment of the present application can simulate all execution actions of the hardware unit in each execution cycle by taking the execution cycle as an index, and the migration of the execution actions occurs with the passage of time, so that the flow of the execution actions of the hardware unit in the execution cycle is simulated through the scheduling of the simulation process, which can more meticulously construct the design file of the entire network-on-chip.

[0141] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiment.

[0142] Each embodiment in the present specification is described in a progressive manner, and each embodiment mainly describes the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0143] For the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0144] The embodiment of the present application provides a network-on-chip simulation device, which includes a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors to perform the method described in one or more embodiments.

[0145] Figure 9 is a block diagram of an electronic device 600 according to an exemplary embodiment. The electronic device 600 can be, for example, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

[0146] Referring to Figure 9 , the electronic device 600 can include one or more of the following components: a processing component 602, a memory component 604, a power component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0147] The processing component 602 generally controls the overall operations of the electronic device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 can include one or more processors 620 to execute instructions and to complete all or part of steps of the above-described methods. In addition, the processing component 602 can include one or more modules to facilitate interaction between the processing component 602 and other components. For example, the processing component 602 can include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0148] The memory 604 is used to store various types of data to support operations of the electronic device 600. Examples of these data include instructions for any application or method operating on the electronic device 600, contact data, phonebook data, messages, pictures, multimedia, and so on. The memory 604 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic storage devices, flash memory, magnetic disks, or optical disks.

[0149] The power component 606 provides power to the various components of the electronic device 600. The power component 606 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.

[0150] The multimedia component 608 includes a screen providing an output interface between the electronic device 600 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensors can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. The front camera and / or the rear camera can receive external multimedia data when the electronic device 600 is in an operation mode, such as a shooting mode or a multimedia mode. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0151] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC) for receiving an external audio signal when the electronic device 600 is in a particular mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0152] The I / O interface 612 provides an interface between the processing component 602 and peripheral interface modules, which can include a keypad, a click wheel, buttons, and so on. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0153] The sensor component 614 includes one or more sensors for providing status assessments of various aspects of the electronic device 600. For example, the sensor component 614 can detect an open / closed position of the electronic device 600, relative positioning of components, such as a display and a keypad of the electronic device 600, a change of position of the electronic device 600 or a component of the electronic device 600, presence or absence of user contact with the electronic device 600, orientation or acceleration / deceleration / g-force and temperature of the electronic device 600. The sensor component 614 can include an orientation sensor, a proximity sensor, a motion sensor, a temperature sensor, a light sensor, a pressure sensor, a gas sensor, a color sensor, an acceleration sensor, a gyroscope sensor, a magnetism sensor, a biometric sensor, a chemical sensor, a smell sensor, and / or the like.

[0154] The communication component 616 is configured to facilitate wired or wireless communication between the electronic device 600 and other devices. The electronic device 600 can access a wireless network based on a corresponding communication standard, such as WiFi, a cellular network (e.g., 2G, 3G, 4G, or 5G), or a combination thereof. In an example embodiment, the communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 616 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technology.

[0155] In an example embodiment, the electronic device 600 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic elements, for implementing the methods provided by the embodiments of the present application.

[0156] In an example embodiment, a non-transitory computer readable storage medium including instructions, such as the memory 604 including instructions, is also provided, which when executed by the processor 620 of the electronic device 600, can complete the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0157] Figure 10 is a block diagram of an electronic device 700 according to an example embodiment. For example, the electronic device 700 can be provided as a server. Referring to Figure 10 , the electronic device 700 includes a processing component 722, which further includes one or more processors, and a memory resource represented by a memory 732, for storing instructions executable by the processing component 722, such as an application program. The application program stored in the memory 732 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute the instructions to perform the methods provided by the embodiments of the present application.

[0158] The electronic device 700 can also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input / output (I / O) interface 758. The electronic device 700 can operate based on an operating system stored in the memory 732, such as Windows ServerTM, Mac OSXTM, UnixTM, LinuxTM, FreeBSDTM or the like.

[0159] The embodiments of the present application also provide a computer program product, including a computer program, which when executed by a processor, implements the method described in the above embodiments.

[0160] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0161] It is to be understood that the application is not limited to the precise construction herein described and as shown in the attached drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is to be indicated by the appended claims, rather than the description.

Claims

1. A method of network-on-chip simulation, the method comprising: The method comprises: determining various hardware units for constituting a network-on-chip, and determining execution actions included in each hardware unit in each execution cycle; constructing an execution code segment of each hardware unit in the execution cycle by a preset compiling language according to the execution actions included in the hardware unit; the execution code segment is used for controlling the corresponding hardware unit to execute a fixed plurality of execution actions in each execution cycle; constructing a network-on-chip design file according to the execution code segments of all the hardware units; performing simulation running on the network-on-chip design file to obtain a simulation running result; the constructing a network-on-chip design file according to the execution code segments of all the hardware units comprises: determining input-output relationships between the hardware units; writing a result assignment code segment between the hardware units by the preset compiling language according to the input-output relationships; and constructing the network-on-chip design file according to the result assignment code segment and the execution code segments of the hardware units.

2. The network-on-chip emulation method of claim 1, wherein, the constructing an execution code segment of each hardware unit in the execution cycle by a preset compiling language according to the execution actions included in the hardware unit comprises: determining dependency relationships between the execution actions; constructing an execution code segment of each hardware unit in the execution cycle by a preset compiling language according to the dependency relationships.

3. The network-on-chip emulation method of claim 2, wherein, the execution actions comprise a first execution action and a second execution action having dependency relationships; the constructing an execution code segment of each hardware unit in the execution cycle by a preset compiling language according to the dependency relationships comprises: writing a first execution statement corresponding to the first execution action and a second execution statement corresponding to the second execution action in the execution code segment by the preset compiling language; determining a writing order of the first execution statement and the second execution statement in the execution code segment according to the dependency relationships, thereby constructing the execution code segment of the hardware unit in the execution cycle.

4. The network-on-chip emulation method of claim 3, wherein, the dependency relationships are that the first execution action is used for completing execution after obtaining an execution result of the second execution action; the determining a writing order of the first execution statement and the second execution statement in the execution code segment according to the dependency relationships comprises: writing the first execution statement before the second execution statement in the execution code segment.

5. The network-on-chip emulation method of claim 1, wherein, the constructing a network-on-chip design file according to the execution code segments of all the hardware units comprises: constructing a calculation code segment for simulating calculation of power consumption of the network-on-chip according to a static power consumption calculation rule and a dynamic power consumption calculation rule; constructing a network-on-chip design file according to the calculation code segment and the execution code segments of all the hardware units.

6. The network-on-chip emulation method of claim 5, wherein, the static power consumption calculation rule is used for calculating static power consumption of the hardware unit according to a data bit width of the hardware unit and a preset corresponding relationship between data bit widths and power consumption; The dynamic power consumption calculation rule is used to calculate the dynamic power consumption of the hardware unit according to the execution actions included by the hardware unit and the action power consumption corresponding to each execution action. The total power consumption of the hardware unit is the sum of the static power consumption and the dynamic power consumption of the hardware unit.

7. A network-on-chip simulation apparatus, characterized by comprising: The apparatus comprises: A determination module is configured to determine various hardware units constituting a network-on-chip and determine execution actions included by the hardware units in each execution cycle; A first construction module is configured to construct an execution code segment of each hardware unit in the execution cycle through a preset compiling language according to the execution actions included by the hardware units; the execution code segment is used to control the corresponding hardware unit to execute a fixed number of execution actions in each execution cycle A second construction module is configured to construct a network-on-chip design file according to the execution code segments of all the hardware units respectively; A running module is configured to perform simulation running on the network-on-chip design file to obtain a simulation running result; The second construction module comprises: A determination submodule is configured to determine an input-output relationship between the hardware units; A third compiling submodule is configured to compile a result assignment code segment between the hardware units through the preset compiling language according to the input-output relationship; A first construction submodule is configured to construct the network-on-chip design file according to the result assignment code segment and the execution code segments of the hardware units respectively.

8. An electronic device, comprising: comprises: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, When the instructions in the computer readable storage medium are executed by the processor of the electronic device, the electronic device can perform the method of any one of claims 1 to 6.

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