Display substrate, display device and working method

Abstract

The present disclosure provides a display substrate, a display device and a working method. Specifically, the display substrate is characterized in that it comprises a plurality of pixel driving circuits and a plurality of light-emitting elements connected with the plurality of pixel driving circuits respectively, the plurality of pixel driving circuits are arranged to drive the plurality of light-emitting elements to emit light, and at least one pixel driving circuit comprises a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, a write sub-circuit, a driving sub-circuit and a light-emitting sub-circuit. Such a technical solution helps to improve the defect of gray scale display unevenness of the display substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display substrate, a display device and a working method. BACKGROUND

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which is widely used in various electronic devices and has the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, high response speed, lightness and thinness, and low cost.

[0003] In the related art, each pixel of an OLED product is independently controlled, and the control circuit thereof includes a thin film transistor (TFT). However, the characteristics of different TFTs usually differ, which inevitably causes a problem of insufficient display uniformity. SUMMARY

[0004] Therefore, the present disclosure aims to provide a display substrate, a display device and a working method.

[0005] To achieve the above purpose, the present disclosure provides a display substrate, which comprises a plurality of pixel driving circuits and a plurality of light emitting elements connected with the plurality of pixel driving circuits respectively, the plurality of pixel driving circuits are configured to drive the plurality of light emitting elements to emit light, at least one pixel driving circuit comprises a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, a write sub-circuit, a driving sub-circuit and a light emitting sub-circuit; wherein,

[0006] The first reset sub-circuit is connected with a first initial signal line, a fourth node and a reset signal line respectively, and is configured to write a first initial signal of the first initial signal line into the fourth node under the control of the reset signal line;

[0007] The second reset sub-circuit is connected with a second initial signal line, a reset signal line and a first node respectively, and is configured to write a second initial signal of the second initial signal line into the first node under the control of the reset signal line; wherein the second initial signal is determined based on the gray scale of the light emitting element;

[0008] The compensation sub-circuit is connected with a first power line, a scan signal line, the first node, a third node N3 and the fourth node respectively, and is configured to provide a signal of the third node to the fourth node under the control of the scan signal line;

[0009] The write sub-circuit is connected with the scan signal line, the data signal line and the second node respectively, and is configured to write the data signal of the data signal line into the second node under the control of the scan signal line, and couple the signal of the second node to the first node in a data write stage;

[0010] The drive sub-circuit is connected with the first node, the second node and the third node respectively, and is configured to write the data signal of the second node into the third node in the data write stage, and provide a drive current to the third node according to the signals of the first node and the second node in a light emitting stage;

[0011] The light emitting sub-circuit is connected with the first power supply line, the second node, the third node, the first light emitting signal line, the second light emitting signal line and the first pole of the light emitting element respectively, and is configured to write the signal of the first power supply line into the second node under the control of the first light emitting signal line, and write the signal of the third node into the first pole of the light emitting element under the control of the second light emitting signal line.

[0012] Based on the same inventive concept, the embodiment of the present disclosure further provides a working method of a display substrate, the display substrate comprising a plurality of pixel driving circuits and a plurality of light emitting elements connected with the plurality of pixel driving circuits respectively, the plurality of pixel driving circuits being configured to drive the plurality of light emitting elements to emit light, at least one pixel driving circuit comprising a first reset sub-circuit, a compensation sub-circuit, a write sub-circuit, a second reset sub-circuit, a drive sub-circuit and a light emitting sub-circuit, the working method of the display substrate comprising:

[0013] The first reset sub-circuit writes the first initial signal of the first initial signal line into the fourth node under the control of the reset signal line;

[0014] The second reset sub-circuit provides the second initial signal of the second initial signal line to the first node under the control of the reset signal line, wherein the second initial signal is determined based on the gray scale of the light emitting element;

[0015] The write sub-circuit writes the data signal of the data signal line into the second node under the control of the scan signal line, and couples the signal of the second node to the first node in a data write stage;

[0016] The drive sub-circuit provides a drive current to the third node according to the signals of the first node and the second node;

[0017] The light emitting sub-circuit writes the signal of the first power supply line into the second node under the control of the first light emitting signal line, and writes the signal of the third node into the first pole of the light emitting element under the control of the second light emitting signal line.

[0018] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device comprising the display substrate according to any one of the above.

[0019] As can be seen from the above, the display substrate, the display device and the working method provided by the present disclosure, the display substrate comprises a plurality of pixel driving circuits, at least one pixel driving circuit writes a second initial signal of a second initial signal line into the first node through a second reset sub-circuit in a reset stage; wherein the second initial signal is determined based on the gray scale of the light emitting element, so that the signal after the first node is coupled with the data signal is controlled by the gray scale of the light emitting element, which helps to improve the defect of uneven gray scale display of the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 A structural schematic diagram of a display substrate is shown;

[0022] Figure 2 A planar structural schematic diagram of a display substrate is shown;

[0023] Figure 3 A cross-sectional structural schematic diagram of a display substrate is shown;

[0024] Figure 4A An equivalent circuit schematic diagram of a pixel driving circuit is shown;

[0025] Figure 4B The working diagram of the equivalent circuit of Figure 4A in the reset stage is shown;

[0026] Figure 4C The working diagram of the equivalent circuit of Figure 4A in the data writing stage is shown;

[0027] Figure 4D The working diagram of the equivalent circuit of Figure 4A in the light emitting stage is shown;

[0028] Figure 5A The Id-Vg curve of a low-temperature polysilicon type TFT is shown;

[0029] Figure 5B The deviation diagram of Vgs of different TFTs under different currents is shown;

[0030] Figure 6AA structure schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure is shown.

[0031] Figure 6B An equivalent circuit schematic diagram of the pixel driving circuit provided by an embodiment of the present disclosure is shown.

[0032] Figure 6C A top view structure schematic diagram of the pixel driving circuit provided by an embodiment of the present disclosure is shown.

[0033] Figure 7 A working timing diagram of a display substrate provided by an embodiment of the present disclosure is shown.

[0034] Figure 8A A working diagram of the equivalent circuit in a reset stage provided by an embodiment of the present disclosure is shown.

[0035] Figure 8B A working diagram of the equivalent circuit in a data writing stage provided by an embodiment of the present disclosure is shown.

[0036] Figure 8C A working diagram of the equivalent circuit in a light emitting stage provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure is further described in detail below with reference to specific embodiments and drawings.

[0038] Note that, unless otherwise defined, technical or scientific terms used in the present disclosure shall have the same meaning as those which are commonly understood by a person skilled in the art to which the present disclosure pertains. The terms "first", "second", and similar terms in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish one element from another. The terms "include", "comprise", and the like are intended to mean that the elements listed after the terms encompass the elements recited in the terms and equivalents thereof, and do not exclude other elements. The terms "connected" and "linked" and the like do not mean that the connection or linkage is direct or mechanical, but can include the case where another element exists in between. The terms "upper", "lower", "left", "right", and the like are used to indicate relative relationships between elements, and the relative relationships change when the absolute positions of the elements are changed. The term "parallel" means that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus, the case where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, the term "perpendicular" means that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. The term "film" and the term "layer" can be interchanged. For example, the "conductive layer" can be replaced with the "conductive film". Similarly, the "insulating film" can be replaced with the "insulating layer".

[0039] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in the present disclosure, the channel region refers to a region where current flows mainly.

[0040] In the present disclosure, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case where transistors having opposite polarities are used or the case where the direction of current flow is changed in the operation of a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged, and the "source terminal" and the "drain terminal" can be interchanged. In the present disclosure, a gate electrode can be referred to as a control electrode.

[0041] Figure 1 A structure of a display substrate is shown. As Figure 1As shown, the display substrate 100 can include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array, the timing controller being connected to the data signal driver, the scan signal driver, and the light emission signal driver, respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), and the light emission signal driver is connected to a plurality of light emission signal lines (E1 to Eo). The pixel array can include a plurality of sub-pixels P xij , i and j can be natural numbers, and at least one sub-pixel P xij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit can include at least one scan signal line, at least one data signal line, at least one light emission signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver can sample the gray scale value using the clock signal and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of pixels, n can be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate the scan signals in such a manner that the scan start signal provided in the form of an on-pulse is sequentially transferred to the next stage circuit under the control of the clock signal, m can be a natural number. The light emission signal driver can generate emission signals to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driver can sequentially provide emission signals having off-pulse to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured in the form of a shift register, and can generate the emission signals in such a manner that the emission stop signal provided in the form of an off-pulse is sequentially transferred to the next stage circuit under the control of the clock signal, o can be a natural number.

[0042] Figure 2 A schematic diagram of a planar structure of a display substrate is shown. As shown, the display substrate 100 can include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array, the timing controller being connected to the data signal driver, the scan signal driver, and the light emission signal driver, respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), and the light emission signal driver is connected to a plurality of light emission signal lines (E1 to Eo). The pixel array can include a plurality of sub-pixels PFigure 2 As shown, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light emitting device. The pixel driving circuit in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is connected with a scan signal line, a data signal line, and a light emitting signal line respectively, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting device in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is connected with the pixel driving circuit of the sub-pixel where the light emitting device is located respectively, and the light emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light emitting device is located.

[0043] In an exemplary embodiment, the pixel unit P can include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. The shape and arrangement of the sub-pixels in the pixel unit are not limited by the present disclosure.

[0044] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate is shown. Figure 3 The structure of three sub-pixels of an OLED display substrate is shown. As shown, Figure 3 As shown, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 302 disposed on a substrate 301, and a light emitting structure layer 303 and an encapsulation layer 304 disposed in turn on the side of the driving circuit layer 302 away from the substrate 301. In some possible embodiments, the display substrate can include other film layers, such as a spacer, and the present disclosure does not limit the same.

[0045] In some embodiments, the substrate 301 can be a flexible substrate, or can be a rigid substrate, which is not limited in the present disclosure. The driving circuit layer 302 of each sub-pixel can include a plurality of transistors (for example 3021) and a storage capacitor constituting a pixel driving circuit. The light emitting structure layer 303 can include an anode 3031 connected with the drain electrode of the driving transistor 3021 through a via, an organic light emitting layer 3032 connected with the anode 3031, a cathode 3033 connected with the organic light emitting layer 3032, and the organic light emitting layer 3032 emits light of a corresponding color under the driving of the anode 3031 and the cathode 3033. The encapsulation layer 304 can include a plurality of encapsulation layers stacked, for example, a first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The encapsulation layer 304 can prevent external moisture from entering the light emitting structure layer 303, thereby ensuring the performance and service life of the display substrate.

[0046] In some embodiments, the organic light emitting layer 3032 can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL) stacked.

[0047] In some embodiments, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4A An equivalent circuit schematic diagram of a pixel driving circuit is shown. As Figure 4AAs shown, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C1, and can be connected with 7 signal lines (data signal line Vdata, reset signal line Reset, scanning signal line Gate, light-emitting signal line EM, initial signal line Initial, first power supply line Vdd and second power supply line Vss). Here, the data signal line Vdata can be selected from one or more of D1, D2, …, Dn described above; the reset signal line Reset and the scanning signal line Gate are independently selected from one or more of S1, S2, …, Sm described above; the light-emitting signal line EM is selected from one or more of E1, E2, …, Eo described above. It should be understood that the specific signal lines corresponding to the 7 signal lines of different sub-pixels can be different, for example, the data signal line Vdata corresponding to part of the sub-pixels is D1, and the data signal line Vdata corresponding to part of the sub-pixels is D2; the reset signal line Reset corresponding to part of the sub-pixels is S2, and the reset signal line Reset corresponding to part of the sub-pixels is S3, and the like will not be listed.

[0048] Exemplarily, the pixel driving circuit can include a first node N1, a second node N2 and a third node N3. Wherein, the second node N2 is connected with the first electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 respectively, the first node N1 is connected with the second electrode of the first transistor T1, the second electrode of the second transistor T2, the control electrode of the third transistor T3 and the second end of the storage capacitor C1 respectively, and the third node N3 is connected with the first electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 respectively.

[0049] Further, the first end of the storage capacitor C1 is connected with the first power supply line Vdd, and the second end of the storage capacitor C1 is connected with the first node N1, i.e. the second end of the storage capacitor C1 is connected with the control electrode of the third transistor T3.

[0050] Further, the control electrode of the first transistor T1 is connected with the reset signal line Reset, the first electrode of the first transistor T1 is connected with the initial signal line Initial, and the second electrode of the first transistor is connected with the first node N1. When the turn-on level scanning signal is applied to the reset signal line Reset, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so as to initialize the charge amount of the control electrode of the third transistor T3.

[0051] Further, a control electrode of the second transistor T2 is connected to the scan signal line Gate, a second electrode of the second transistor T2 is connected to the first node N1, and a first electrode of the second transistor T2 is connected to the third node N3. When an on-level scan signal is applied to the scan signal line Gate, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0052] Further, a control electrode of the third transistor T3 is connected to the first node N1, i.e., the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driver transistor, and the third transistor T3 determines an amount of a drive current flowing between the first power supply line Vdd and the second power supply line Vss in accordance with a potential difference between the control electrode and the first electrode thereof.

[0053] Further, a control electrode of the fourth transistor T4 is connected to the scan signal line Gate, a first electrode of the fourth transistor T4 is connected to the data signal line Vdata, and a second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, or the like, and when an on-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 inputs a data voltage of the data signal line Vdata to the pixel driving circuit.

[0054] Further, a control electrode of the fifth transistor T5 is connected to the emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power supply line Vdd, and a second electrode of the fifth transistor T5 is connected to the second node N2. A control electrode of the sixth transistor T6 is connected to the emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When an on-level emission signal is applied to the emission signal line EM, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a drive current path between the first power supply line Vdd and the second power supply line Vss.

[0055] Further, a control electrode of the seventh transistor T7 is connected to the reset signal line Reset, a first electrode of the seventh transistor T7 is connected to the initial signal line Initial, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When an on-level scan signal is applied to the reset signal line Reset, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize an amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0056] In some embodiments, the second electrode of the light-emitting device is connected to the second power line Vss, the signal of the second power line Vss is a low-level signal, and the signal of the first power line Vdd is a continuously high-level signal.

[0057] Optionally, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some alternative embodiments, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0058] In some embodiments, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (corresponding to the anode), an organic light-emitting layer, and a second electrode (corresponding to the cathode) stacked together.

[0059] The following is through Figure 4A The operation of the example pixel driving circuit illustrates an exemplary embodiment. Figure 4A The pixel driving circuit includes 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C1, and 7 signal lines (data signal line Vdata, reset signal line Reset, scan signal line Gate, light emission signal line EM, initial signal line Initial, first power supply line Vdd, and second power supply line Vss). All 7 transistors are N-type transistors.

[0060] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0061] like Figure 4B As shown, in the first stage, called the reset stage, the first transistor T1 is turned on, and the Initial signal line is provided to the first node N1 to initialize the storage capacitor C1 and clear the original data voltage in the storage capacitor. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.

[0062] like Figure 4CAs shown, in the second stage, referred to as the data writing stage or threshold compensation stage, the fourth transistor T4, the third transistor T3 and the second transistor T2 are turned on, the data signal line Vdata outputs a data voltage, and the data voltage output by the data signal line Vdata is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage (Vd) output by the data signal line Vdata and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1, and the voltage at the second end (the first node N1) of the storage capacitor C1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Vdata, and Vth is the threshold voltage of the third transistor T3.

[0063] As shown in FIG. 5, in the third stage, referred to as the light emitting stage, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage Vdd output by the first power supply line Vdd provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so as to drive the OLED to emit light. Figure 4D

[0064] The Vth compensation operation is performed on the third transistor T3, so that the pixel gate voltage is set to Vd-|Vth|, and according to the current formula, the driving current I of the third transistor T3 is proportional to [(Vdd-Vd) / Vth]2. 2 Therefore, the current size between pixels is not affected by Vth, and the technical effect of improving display uniformity is achieved.

[0065] However, generally, Vd is relatively small in the writing stage, and the writing current decreases when Vgs>Vth, so generally, the Vth compensated in the pixel circuit with a writing time of 60 Hz (5-6 μs) is approximately the Vgs corresponding to the TFT when I is approximately 1 nA. Here, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0066] Figure 5A An Id-Vg curve of a low temperature poly-silicon (LTPS) TFT is shown in FIG. 6; Figure 5B A deviation diagram of Vgs of different TFTs under different currents is shown in FIG. 7. As shown in FIG. 7, the driving current 501 of the third transistor T3 corresponding to the gray scale 255 is approximately 1 nA, and the driving current 501' of the third transistor T3 corresponding to the gray scale 0-5 is approximately 1 pA. In other words, the driving current of the third transistor T3 is obviously different for different gray scales, so the corresponding Vgs is also different. As shown in FIG. 7, the Vgs of the third transistor T3 corresponding to the gray scale 255 is Vdd-Vd-|Vth|, and the Vgs of the third transistor T3 corresponding to the gray scale 0-5 is Vdd-Vd-2|Vth|. Figure 5A Figure 5B ​​As shown, the Id-Vg curves of two third transistors T3 are shown, which are 502 and 502' respectively. Considering that the initial signal of the initial signal line Initial is a constant value, the corresponding compensation current is I (in related technologies, the compensation current can be 1nA), the driving current under a high gray scale is close to I, the difference between the driving current and the compensation current of each of the two third transistors T3 is small, the Vgs corresponding to the compensation current is close to the Vgs corresponding to the driving current, and good uniformity can be achieved; however, the driving current under a low gray scale is II (for example, 1pA), the difference between the driving current (1pA) of the third transistor T3 and the compensation current (1nA) is large, the difference between the compensation Vgs and the driving Vgs under the control of the initial signal of the initial signal line Initial is large, and due to the different slopes of the two Id-Vg curves (502 and 502'), the deviation between the two third transistors T3 is different, so it is difficult to ensure the gray scale uniformity.

[0067] In view of this, the display substrate provided by the embodiments of the present disclosure includes a plurality of pixel driving circuits, and at least one pixel driving circuit writes a second initial signal of a second initial signal line into the first node in a reset stage through a second reset sub-circuit; wherein the second initial signal is determined based on the gray scale of the light emitting element, so that the signal after the first node is coupled with the data signal is adjusted according to the gray scale of the light emitting element, which helps to improve the defect of uneven display of the display substrate gray scale.

[0068] Figure 6A The structure schematic diagram of the pixel driving circuit in the display substrate provided by the embodiments of the present disclosure is shown. The display substrate can include a plurality of pixel driving circuits and a plurality of light emitting elements (such as OLED) connected with the plurality of pixel driving circuits respectively, and the plurality of pixel driving circuits are arranged to drive the plurality of light emitting elements to emit light. As shown in the figure, Figure 6A As shown, at least one pixel driving circuit includes a first reset sub-circuit 601, a second reset sub-circuit 602, a compensation sub-circuit 603, a writing sub-circuit 604, a driving sub-circuit 605 and a light emitting sub-circuit 606.

[0069] The first reset sub-circuit 601 is connected with the first initial signal line Initial 1, the fourth node N4 and the reset signal line Reset respectively, and is arranged to write the first initial signal of the first initial signal line Initial 1 into the fourth node N4 under the control of the reset signal line Reset;

[0070] The second reset sub-circuit 602 is connected with the second initial signal line Initial 2, the reset signal line Reset and the first node N1 respectively, and is configured to write the second initial signal of the second initial signal line Initial 2 into the first node N1 under the control of the reset signal line Reset, wherein the second initial signal is determined based on the gray scale of the light emitting element.

[0071] The compensation sub-circuit 603 is connected with the first power supply line Vdd, the scanning signal line Gate, the first node N1, the third node N3 and the fourth node N4 respectively, and is configured to provide the signal of the third node N3 to the fourth node N4 under the control of the scanning signal line Gate.

[0072] The write sub-circuit 604 is connected with the scanning signal line Gate, the data signal line Vdata and the second node N2 respectively, and is configured to write the data signal of the data signal line Vdata into the second node N2 under the control of the scanning signal line Gate, and couple the signal of the second node N2 to the first node N1 in the data writing stage.

[0073] The drive sub-circuit 605 is connected with the first node N1, the second node N2 and the third node N3 respectively, and is configured to write the data signal of the second node N2 into the third node N3 in the data writing stage, and provide a drive current to the third node N3 according to the signals of the first node N1 and the second node N2 in the light emitting stage.

[0074] The light emitting sub-circuit 606 is connected with the first power supply line Vdd, the second node N2, the third node N3, the first light emitting signal line, the second light emitting signal line and the first pole of the light emitting element respectively, and is configured to write the signal of the first power supply line Vdd into the second node N2 under the control of the first light emitting signal line, and write the signal of the third node N3 into the first pole of the light emitting element under the control of the second light emitting signal line.

[0075] It can be seen that the display substrate provided by the embodiment of the present disclosure pre-charges the first node N1 by introducing the second initial signal line Initial 2, and pre-makes the working interval of T3 to a lower current state to start data writing. The bootstrap function of the compensation sub-circuit 603 will change the potential of the first node N1, and finally the voltage of the first node N1 is closer to Vd+Vgs (I=1pA), so that the light emitting element has better uniformity at low gray scale. In addition, different second initial signals can be written based on different gray scale requirements, so that the voltage of the first node N1 is more matched with the Vgs voltage value compensation of the gray scale. It should be noted that the second initial signal can be determined in the gray scale definition stage of the module, and the present disclosure does not make detailed description.

[0076] Optionally, the scan signal line Gate can be a scan signal line in the pixel driving circuit of the current display row, and the reset signal line Reset can be a scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the scan signal line Gate is S(n), the reset signal line Reset is S(n-1), the reset signal line Reset of the current display row and the scan signal line Gate in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow frame of the display panel.

[0077] It should be noted that the first light-emitting signal line and the second light-emitting signal line can be two different branches of the same light-emitting signal line, which is not limited in the present disclosure.

[0078] Figure 6B An equivalent circuit schematic diagram of the pixel driving circuit provided by the embodiments of the present disclosure is shown. In some embodiments, as shown in Figure 6B The second reset sub-circuit 602 includes an eighth transistor T8; the control electrode of the eighth transistor T8 is connected with the reset signal line Reset, the first electrode of the eighth transistor T8 is connected with the second initial signal line Initial 2, and the second electrode of the eighth transistor T8 is connected with the first node N1.

[0079] In some embodiments, as shown in Figure 6B The compensation sub-circuit 603 includes a second transistor T2, a first capacitor C1 and a second capacitor C2;

[0080] The control electrode of the second transistor T2 is connected with the scan signal line Gate, the first electrode of the second transistor T2 is connected with the third node N3, and the second electrode of the second transistor T2 is connected with the fourth node N4;

[0081] The first plate of the first capacitor C1 is connected with the first power supply line Vdd, and the second plate of the first capacitor C1 is connected with the first node N1;

[0082] The first plate of the second capacitor C2 is connected with the first node N1, and the second plate of the second capacitor C2 is connected with the fourth node N4.

[0083] In some embodiments, as shown in Figure 6B The write sub-circuit 604 includes a fourth transistor T4;

[0084] The control electrode of the fourth transistor T4 is connected with the scan signal line Gate, the first electrode of the fourth transistor T4 is connected with the data signal line Vdata, and the second electrode of the fourth transistor T4 is connected with the second node N2.

[0085] In some embodiments, as shown in Figure 6B The light-emitting sub-circuit 606 includes a fifth transistor T5 and a sixth transistor T6;

[0086] The control electrode of the fifth transistor T5 is connected to the first light-emitting signal line, the first electrode of the fifth transistor T5 is connected to the first power supply line Vdd, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0087] The control electrode of the sixth transistor T6 is connected to the second light-emitting signal line, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element.

[0088] It should be noted that the first and second light-emitting signal lines can be two separate signal lines or the same light-emitting signal line EM; this disclosure does not limit this. In other words, the light-emitting signal line EM can simultaneously control the fifth transistor T5 and the sixth transistor T6.

[0089] In some embodiments, such as Figure 6B As shown, the first reset circuit 601 includes a first transistor T1;

[0090] The control electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the first initial signal line Initial 1, and the second electrode of the first transistor T1 is connected to the fourth node N4.

[0091] In some embodiments, such as Figure 6B As shown, the driving sub-circuit 605 includes a third transistor T3;

[0092] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0093] In some embodiments, such as Figure 6A As shown, it also includes a third reset sub-circuit 607, which is connected to the first initial signal line Initial 1, the reset signal line Reset and the first pole of the light-emitting element, respectively, and is configured to write the initial signal of the first initial signal line Initial 1 into the first pole of the light-emitting element under the control of the reset signal line Reset.

[0094] In some embodiments, such as Figure 6B As shown, the third reset circuit includes the seventh transistor T7;

[0095] The control electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the first initial signal line Initial 1, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element.

[0096] In some embodiments, such asFigure 6B As shown, the first reset sub-circuit 601 includes a first transistor T1; the compensation sub-circuit 603 includes a second transistor T2, a first capacitor C1 and a second capacitor C2; the driving sub-circuit 605 includes a third transistor T3; the writing sub-circuit 604 includes a fourth transistor T4; the light-emitting sub-circuit 606 includes a fifth transistor T5 and a sixth transistor T6; the third reset sub-circuit includes a seventh transistor T7; the second reset sub-circuit 602 includes an eighth transistor T8;

[0097] The control electrode of the first transistor T1 is connected with the reset signal line Reset, the first electrode of the first transistor T1 is connected with the first initial signal line Initial 1, and the second electrode of the first transistor T1 is connected with the fourth node N4;

[0098] The control electrode of the second transistor T2 is connected with the scan signal line Gate, the first electrode of the second transistor T2 is connected with the third node N3, and the second electrode of the second transistor T2 is connected with the fourth node N4;

[0099] The control electrode of the third transistor T3 is connected with the first node N1, the first electrode of the third transistor T3 is connected with the second node N2, and the second electrode of the third transistor T3 is connected with the third node N3;

[0100] The control electrode of the fourth transistor T4 is connected with the scan signal line Gate, the first electrode of the fourth transistor T4 is connected with the data signal line Vdata, and the second electrode of the fourth transistor T4 is connected with the second node N2;

[0101] The first electrode of the fifth transistor T5 is connected with the first power supply line Vdd, and the second electrode of the fifth transistor T5 is connected with the second node N2;

[0102] The control electrode of the sixth transistor T6 is connected with the second light-emitting signal line, the first electrode of the sixth transistor T6 is connected with the third node N3, and the second electrode of the sixth transistor T6 is connected with the first electrode of the light-emitting element;

[0103] The control electrode of the seventh transistor T7 is connected with the reset signal line Reset, the first electrode of the seventh transistor T7 is connected with the first initial signal line Initial 1, and the second electrode of the seventh transistor T7 is connected with the first electrode of the light-emitting element;

[0104] The control electrode of the eighth transistor T8 is connected with the reset signal line Reset, the first electrode of the eighth transistor T8 is connected with the second initial signal line Initial 2, and the second electrode of the eighth transistor T8 is connected with the first node N1;

[0105] The first plate of the first capacitor C1 is connected with the first power supply line Vdd, and the second plate of the first capacitor C1 is connected with the first node N1;

[0106] The first plate of the second capacitor C2 is connected to the first node N1, and the second plate of the second capacitor C2 is connected to the fourth node N4.

[0107] In some embodiments, the first transistor T1 to the eighth transistor T8 are low-temperature polycrystalline silicon transistors.

[0108] Figure 6C This diagram shows a top view of a pixel driving circuit according to an embodiment of the present disclosure. Figure 6C It can be seen that the scan signal line Gate, the reset signal line Reset, the light emission signal line EM, and the first initial signal line Initial 1 and the second initial signal line Initial 2 extend horizontally. The first power supply line Vdd and the second power supply line Vss ( Figure 6C (Not shown in the image) and data signal line Vdata can extend vertically. The first initial signal line Initial 1 and the second initial signal line Initial 2 can be disposed on the same layer as the first gate layer 701; the scan signal line Gate, the reset signal line Reset, and the light emission signal line EM can be disposed on the same layer as the second gate layer 702; the first power supply line Vdd can be disposed on the same layer as the first source-drain layer 703; the data signal line Vdata is disposed on the same layer as the second source-drain layer 704; the active layer 705 can be disposed separately; and the conductive connection between different layers can be realized by using the via pillar 706.

[0109] Figure 7 This diagram illustrates the timing diagram of a display substrate according to an embodiment of the present disclosure, wherein the structure of the display substrate is as follows: Figure 6B As shown, all eight transistors are P-type transistors. Figure 8A This diagram illustrates the operation of the equivalent circuit provided in the embodiments of this disclosure during the reset phase. Figure 8B This diagram illustrates the operation of the equivalent circuit provided in the embodiments of this disclosure during the data writing stage; Figure 8C This diagram illustrates the operation of the equivalent circuit provided in the embodiments of this disclosure during the light-emitting stage. For example... Figure 7 and Figure 8A - Figure 8C As shown, the working process of the display substrate may include a first stage A1, a second stage A2, and a third stage A3.

[0110] Phase 1 A1: This can be called the reset phase or initialization phase. The EM and Gate signal lines are at a high level, while the Reset signal line is at a low level. For example... Figure 8AAs shown, since the reset signal line Reset is low, the first transistor T1, the seventh transistor T7 and the eighth transistor T8 are turned on, the initial voltage V1 output by the first initial signal line Initial 1 is provided to the fourth node N4 through the first transistor T1, and the fourth node N4 is low (the initial voltage V1 output by the first initial signal line Initial 1, for example, V1 = Vss = -3V); the initial voltage V1 output by the first initial signal line Initial 1 is also provided to the first electrode of the light emitting element through the seventh transistor T1. The initial voltage V2 output by the second initial signal line Initial 2 is provided to the first node N1 through the eighth transistor T8. Referring to Figure 5A and Figure 5B Since the working Vgs of the driving circuit at different gray scales is different, and the slope of the Id-Vg curve of different pixels is different, in order to make the pixel obtain more accurate compensation at different gray scales, different Initial 2 needs to be used at different gray scales. The initial voltage V2 output by the second initial signal line Initial 2 depends on the gray scale corresponding to the light emitting element, and the corresponding relationship between the initial voltage V2 and the gray scale can be determined in the gray scale definition stage. As shown, Figure 7 The initial voltage V2 output by the second initial signal line Initial 2 is higher at low gray scale than at high gray scale, so as to supplement the higher Vgs at low gray scale afterwards, which is suitable for lower working current, for example, 1pA. Since the signals of the emission signal line EM and the scan signal line Gate are high, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off, and the data voltage output by the data signal line Vdata cannot be written to the second node N2 through the fourth transistor T4; the signal of the first power supply line Vdd cannot provide a driving voltage to the first electrode of the OLED through the fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the OLED does not emit light at this stage.

[0111] The second stage A2 can be called a data writing stage and a compensation stage, and the signals of the emission signal line EM and the reset signal line Reset are high, and the signal of the scan signal line Gate is low. As shown, Figure 8BAs shown, since the signal of the scanning signal line Gate is low, the fourth transistor T4 and the second transistor T2 are turned on. Considering that the first node N1 inputs the initial voltage V2, in order to ensure that the third transistor T3 is turned on, the data voltage Vdata output by the data signal line data can be appropriately increased. Exemplarily, Vdd=4.6V, Vss=-3V, and the picture of the gray scale of 3 is taken as an example, the normal data voltage Vdata can be 3V, and the increased data voltage Vdata can be ~6-7V, so that the third transistor T3 can be turned on, and since the Vds of the third transistor T3 is 9-10V, the larger Vds can ensure that the current between the N2-N4 nodes flows normally. The data voltage Vdata output by the data signal line data is written to the second node N2 through the fourth transistor T4, and the potential of the second node N2 becomes the data voltage Vdata, which further affects the fourth node N4 through the third transistor T3 and the fourth transistor T4, and the voltage of the fourth node N4 rises. Based on the bootstrap function of the second capacitor C2, the voltage of the first node N1 rises with the voltage of the fourth node N4, until N1-N2Vgs, and finally the voltage of the first node N1=Vdata+Vgs. Here, the initial voltage V2 output by the second initial signal line Initial 2 determines Vgs, if the initial voltage V2 is set based on a low gray scale, Vgs corresponds to the Vgs when the working current of the low gray scale is 1pA, and if the initial voltage V2 is set based on a high gray scale, Vgs corresponds to the Vgs when the working current of the high gray scale is 1nA. In combination with Figure 5A , the Vgs corresponding to the working current of the low gray scale is greater than the Vgs corresponding to the working current of the high gray scale, so that the voltage of the first node N1 at the low gray scale is greater than the voltage at the high gray scale, which helps to realize that the Vgs of each pixel is more accurate and meets the demand of the working voltage when the low gray scale picture is compensated, so that each pixel has better uniformity in the light emitting stage.

[0112] Since the signals of the emitting signal line EM and the reset signal line Reset are high, the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Since the fifth transistor T5 and the sixth transistor T6 are turned off, the signal of the first power supply line Vdd cannot provide a driving voltage to the first electrode of the OLED through the fifth transistor T5, the third transistor T3, and the sixth transistor T6, and the OLED does not emit light in this stage.

[0113] The third stage A3 can be called the light emitting stage, the signals of the scanning signal line Gate and the reset signal line Reset are high, and the signal of the emitting signal line EM is low. As shown in FIG. 4, the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Figure 8CAs shown, the signal of the reset signal line Reset is high level, and the eighth transistor T8 is off. Since the signal of the emitting signal line EM is low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first power supply voltage Vdd output by the first power supply line Vdd is provided to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to drive the OLED to emit light.

[0114] Corresponding to any of the above embodiments based on the same inventive concept, the present disclosure also provides a working method of a display substrate. As Figure 6A The implemented display substrate includes a plurality of pixel driving circuits and a plurality of light emitting elements connected with the plurality of pixel driving circuits respectively, the plurality of pixel driving circuits are configured to drive the plurality of light emitting elements to emit light, at least one pixel driving circuit includes a first reset sub-circuit 601, a compensation sub-circuit 603, a writing sub-circuit 604, a second reset sub-circuit 602, a driving sub-circuit 605 and a light emitting sub-circuit 606, and the working method of the display substrate includes:

[0115] Under the control of the reset signal line Reset, the first reset sub-circuit 601 writes the first initial signal (for example, an initial voltage V1) of the first initial signal line Initial1 to the fourth node;

[0116] Under the control of the reset signal line Reset, the second reset sub-circuit 602 provides the second initial signal of the second initial signal line Initial2 to the first node N1; wherein the second initial signal is determined based on the gray scale of the light emitting element;

[0117] Under the control of the scanning signal line Gate, the writing sub-circuit 604 writes the data signal of the data signal line Vdata to the second node N2; the signal of the second node N2 is coupled to the first node N1 in the data writing stage;

[0118] According to the signals of the first node N1 and the second node N2, the driving sub-circuit 605 provides a driving current to the third node N3;

[0119] Under the control of the first emitting signal line, the light emitting sub-circuit 606 writes the signal of the first power supply line Vdd to the second node N2, and under the control of the second emitting signal line, the light emitting sub-circuit writes the signal of the third node N3 to the first electrode of the light emitting element. It should be noted that the first emitting signal line and the second emitting signal line can be the same emitting signal line EM.

[0120] In some embodiments, the pixel driving circuit further includes a third reset sub-circuit 607; and the working method further includes:

[0121] The third reset sub-circuit 607 writes the first initial signal (for example, V1) of the first initial signal line Initial1 to the first electrode of the light emitting element under the control of the reset signal line Reset.

[0122] The working method of the above-mentioned embodiments is applied to the corresponding display substrate in any of the above-mentioned embodiments, and has the beneficial effects of the corresponding display substrate embodiments, which will not be repeated here.

[0123] Based on the same inventive concept, the display device corresponding to the display substrate of any of the above-mentioned embodiments is also provided by the embodiments of the present disclosure, which comprises the display substrate of any of the above-mentioned embodiments.

[0124] The device of the above-mentioned embodiments comprises the corresponding display substrate in any of the above-mentioned embodiments, and has the beneficial effects of the corresponding display substrate embodiments, which will not be repeated here.

[0125] Those skilled in the art should understand that the discussion of any of the above-mentioned embodiments is only exemplary and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples; under the idea of the present disclosure, the above-mentioned embodiments or technical features in different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the embodiments of the present disclosure as described above, which are not provided in details for the sake of brevity.

[0126] The embodiments of the present disclosure are intended to cover all such alternatives, modifications and variations as fall within the broad scope of the appended claims. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A display substrate, characterized by, The pixel driving circuit comprises a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit, a write sub-circuit, a driving sub-circuit and a light-emitting sub-circuit. The first reset sub-circuit is connected with a first initial signal line, a fourth node and a reset signal line, and is configured to write a first initial signal of the first initial signal line into the fourth node under the control of the reset signal line. The second reset sub-circuit is connected with a second initial signal line, a reset signal line and a first node, and is configured to write a second initial signal of the second initial signal line into the first node under the control of the reset signal line. The compensation sub-circuit is connected with a first power line, a scanning signal line, the first node, a third node and the fourth node, and is configured to provide a signal of the third node to the fourth node under the control of the scanning signal line. The write sub-circuit is connected with the scanning signal line, a data signal line and a second node, and is configured to write a data signal of the data signal line into the second node under the control of the scanning signal line, and to couple a signal of the second node to the first node in a data writing stage. The driving sub-circuit is connected with the first node, the second node and the third node, and is configured to write the data signal of the second node into the third node in the data writing stage, and to provide a driving current to the third node according to signals of the first node and the second node in a light-emitting stage. The light-emitting sub-circuit is connected with the first power line, the second node, the third node, a first light-emitting signal line, a second light-emitting signal line and a first electrode of the light-emitting element, and is configured to write a signal of the first power line into the second node under the control of the first light-emitting signal line, and to write a signal of the third node into the first electrode of the light-emitting element under the control of the second light-emitting signal line. The compensation sub-circuit comprises a second capacitor, a first electrode plate of the second capacitor is connected with the first node, and a second electrode plate of the second capacitor is connected with the fourth node.

2. The display substrate of claim 1, wherein, The second reset sub-circuit comprises an eighth transistor. A control electrode of the eighth transistor is connected with the reset signal line, a first electrode of the eighth transistor is connected with the second initial signal line, and a second electrode of the eighth transistor is connected with the first node.

3. The display substrate of claim 1, wherein, The compensation sub-circuit further comprises a second transistor and a first capacitor. A control electrode of the second transistor is connected with the scanning signal line, a first electrode of the second transistor is connected with the third node, and a second electrode of the second transistor is connected with the fourth node. A first electrode plate of the first capacitor is connected with the first power line, and a second electrode plate of the first capacitor is connected with the first node.

4. The display substrate of claim 1, wherein, The write sub-circuit comprises a fourth transistor. The control electrode of the fourth transistor is connected with the scan signal line, the first electrode of the fourth transistor is connected with the data signal line, and the second electrode of the fourth transistor is connected with the second node.

5. The display substrate of claim 1, wherein, The light-emitting sub-circuit comprises a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected with the first light-emitting signal line, the first electrode of the fifth transistor is connected with the first power supply line, and the second electrode of the fifth transistor is connected with the second node; The control electrode of the sixth transistor is connected with the second light-emitting signal line, the first electrode of the sixth transistor is connected with the third node, and the second electrode of the sixth transistor is connected with the first electrode of the light-emitting element. 6.The display substrate of claim 1, wherein, The first reset sub-circuit comprises a first transistor; The control electrode of the first transistor is connected with the reset signal line, the first electrode of the first transistor is connected with the first initial signal line, and the second electrode of the first transistor is connected with the fourth node.

7. The display substrate of claim 1, wherein, The driving sub-circuit comprises a third transistor; The control electrode of the third transistor is connected with the first node, the first electrode of the third transistor is connected with the second node, and the second electrode of the third transistor is connected with the third node. 8.The display substrate of claim 1, wherein, Further comprising a third reset sub-circuit connected with the first initial signal line, the reset signal line and the first electrode of the light-emitting element respectively, and arranged to write the initial signal of the first initial signal line into the first electrode of the light-emitting element under the control of the reset signal line. 9.The display substrate of claim 8, wherein, The third reset sub-circuit comprises a seventh transistor; The control electrode of the seventh transistor is connected with the reset signal line, the first electrode of the seventh transistor is connected with the first initial signal line, and the second electrode of the seventh transistor is connected with the first electrode of the light-emitting element. 10.The display substrate of claim 8, wherein, The first reset sub-circuit comprises a first transistor; the compensation sub-circuit comprises a second transistor, a first capacitor and a second capacitor; the driving sub-circuit comprises a third transistor; the writing sub-circuit comprises a fourth transistor; the light-emitting sub-circuit comprises a fifth transistor and a sixth transistor; the third reset sub-circuit comprises a seventh transistor; and the second reset sub-circuit comprises an eighth transistor; The control electrode of the first transistor is connected with the reset signal line, the first electrode of the first transistor is connected with the first initial signal line, and the second electrode of the first transistor is connected with the fourth node. The control electrode of the second transistor is connected with the reset signal line, the first electrode of the second transistor is connected with the third node, and the second electrode of the second transistor is connected with the fourth node. The control electrode of the third transistor is connected with the first node, the first electrode of the third transistor is connected with the second node, and the second electrode of the third transistor is connected with the third node. The control electrode of the fourth transistor is connected with the scan signal line, the first electrode of the fourth transistor is connected with the data signal line, and the second electrode of the fourth transistor is connected with the second node. The first electrode of the fifth transistor is connected with the first power supply line, and the second electrode of the fifth transistor is connected with the second node. A control electrode of the sixth transistor is connected with the second light-emitting signal line, a first electrode of the sixth transistor is connected with the third node, and a second electrode of the sixth transistor is connected with the first electrode of the light-emitting element; A control electrode of the seventh transistor is connected with the reset signal line, a first electrode of the seventh transistor is connected with the first initial signal line, and a second electrode of the seventh transistor is connected with the first electrode of the light-emitting element; A control electrode of the eighth transistor is connected with the reset signal line, a first electrode of the eighth transistor is connected with the second initial signal line, and a second electrode of the eighth transistor is connected with the first node; A first plate of the first capacitor is connected with the first power supply line, and a second plate of the first capacitor is connected with the first node; A first plate of the second capacitor is connected with the first node, and a second plate of the second capacitor is connected with the fourth node. 11.The display substrate of claim 10, wherein, The first transistor to the eighth transistor are low-temperature polysilicon transistors. 12.The method of Claim 1, wherein The display substrate includes a plurality of pixel driving circuits and a plurality of light-emitting elements connected with the plurality of pixel driving circuits respectively, the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, at least one pixel driving circuit includes a first reset sub-circuit, a compensation sub-circuit, a write sub-circuit, a second reset sub-circuit, a driving sub-circuit and a light-emitting sub-circuit, and a working method of the display substrate includes: Under the control of the reset signal line, the first reset sub-circuit writes the first initial signal of the first initial signal line to the fourth node; Under the control of the reset signal line, the second reset sub-circuit provides the second initial signal of the second initial signal line to the first node; wherein the second initial signal is determined based on the gray scale of the light-emitting element; Under the control of the scan signal line, the write sub-circuit writes the data signal of the data signal line to the second node; and the signal of the second node is coupled to the first node in the data writing stage; According to the signals of the first node and the second node, the driving sub-circuit provides a driving current to the third node; Under the control of the first light-emitting signal line, the light-emitting sub-circuit writes the signal of the first power supply line to the second node, and under the control of the second light-emitting signal line, the light-emitting sub-circuit writes the signal of the third node to the first electrode of the light-emitting element.

13. The method of claim 12, wherein, The pixel driving circuit further includes a third reset sub-circuit, and the working method further includes: Under the control of the reset signal line, the third reset sub-circuit writes the first initial signal of the first initial signal line to the first electrode of the light-emitting element.

14. A display device comprising: The display substrate as claimed in any one of claims 1 to 11. The display substrate as claimed in any one of claims 1 to 11.

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