Display substrate, test method thereof, and display device

Abstract

The present disclosure provides a display substrate and a testing method thereof, and a display device. The display substrate has a display area and a peripheral area surrounding the display area, and includes: a plurality of gate lines extending in a first direction; a plurality of data lines extending in a second direction; at least two driving circuits located in the peripheral area and configured to provide gate driving signals and source driving signals to pixel driving circuits located in the display area through the plurality of gate lines and the plurality of data lines, respectively; one or more test signal lines located in the peripheral area and extending to a side opposite to a corresponding driving circuit of the at least two driving circuits, each test signal line including a plurality of branches at a point of the side, each branch extending from the point to connect to the corresponding pixel driving circuit, so as to provide a test signal to the corresponding pixel driving circuit during an inspection test; and at least one test signal terminal configured to provide the test signal to the one or more test signal lines.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a testing method thereof, and a display device. Background Technology

[0002] As display screen sizes increase and the cost of back-end module materials rises, proactively intercepting defective products to avoid wasting back-end module materials and thus save costs becomes increasingly important. However, with the increase in screen size, the space required for the switching transistors (SW TFTs) and their signal lines used for cell testing also gradually increases. This means that conventional designs placing them below the integrated circuit (IC) can no longer meet design requirements. Forcing them to be placed on the side where the IC is located would increase the space on that side, resulting in a larger screen bezel. This clearly contradicts the current design philosophy of pursuing narrow bezels and does not meet the needs of the general public. Summary of the Invention

[0003] In a first aspect, this disclosure provides a display substrate having a display area and a peripheral area arranged around the display area, and comprising: a plurality of gate lines extending along a first direction; a plurality of data lines extending along a second direction; at least two driving circuits located in the peripheral area and configured to provide gate driving signals and source driving signals, respectively, to a plurality of pixel driving circuits arranged in an array including multiple rows and columns located in the display area via the plurality of gate lines and the plurality of data lines; one or more test signal lines located in the peripheral area and extending to a side opposite to a corresponding driving circuit of one of the at least two driving circuits, each test signal line including a plurality of branches at a point on that side, each branch extending from that point to connect to the corresponding pixel driving circuit, thereby providing a test signal to the corresponding pixel driving circuit during inspection testing; and at least one test signal terminal configured to provide the test signal to the one or more test signal lines.

[0004] In some embodiments of this disclosure, the peripheral region includes a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, wherein the first side connects the third side and the fourth side, and the second side connects the third side and the fourth side; and the peripheral region includes a first corner located between the first side and the fourth side, a second corner located between the second side and the fourth side, a third corner located between the second side and the third side, and a fourth corner located between the first side and the third side.

[0005] In some embodiments of this disclosure, the at least two driving circuits include source driving circuits located on the first side of the peripheral region and configured to provide the source driving signal to the same column of pixel driving circuits located in the display area via corresponding data lines; the at least one test signal terminal includes a first test signal terminal disposed on the first side of the peripheral region near the first corner of the source driving circuit; and a second test signal terminal disposed on the first side of the peripheral region near the first corner of the source driving circuit; the one or more test signal lines include a first test signal line and a second test signal line; one end of the first test signal line is connected to the first test signal terminal and extends from the first test signal terminal along the... A fourth side extends from the first corner to the second corner, and extends along the second side from the second corner to a first point on the second side located in the peripheral region; one end of the second test signal line is connected to the second test signal terminal, and extends from the second test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a second point on the second side located in the peripheral region; the first test signal line is configured to provide a first test signal from the first test signal terminal to the odd-numbered column pixel driving circuit during inspection testing; and the second test signal line is configured to provide a second test signal from the second test signal terminal to the even-numbered column pixel driving circuit during inspection testing.

[0006] In some embodiments of this disclosure, the first test signal line is divided into multiple branches at the first point on the second side of the peripheral region, each branch being connected to a corresponding data line to provide the first test signal for the same odd-numbered column pixel driving circuit during inspection testing; and the second test signal line is divided into multiple branches at the second point on the second side of the peripheral region, each branch being connected to a corresponding data line to provide the second test signal for the same even-numbered column pixel driving circuit during inspection testing.

[0007] In some embodiments of this disclosure, the data lines connected to each branch of the first test signal line provide the first test signal from the first test signal terminal and the source drive signal from the source drive circuit to the same odd-numbered column pixel drive circuit; and the data lines connected to each branch of the second test signal line provide the second test signal from the second test signal terminal and the source drive signal from the source drive circuit to the same even-numbered column pixel drive circuit.

[0008] In some embodiments of this disclosure, all odd-numbered column pixel driving circuits are arranged in a mirror-symmetric manner with respect to a straight line passing through the first point and perpendicular to the first side and the second side; and all even-numbered column pixel driving circuits are arranged in a mirror-symmetric manner with respect to a straight line passing through the second point and perpendicular to the first side and the second side.

[0009] In some embodiments of this disclosure, the display substrate includes a plurality of sub-pixels arranged in an array in multiple rows and columns located in the display area, wherein each of the plurality of sub-pixels corresponds to a plurality of pixel driving circuits; the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the at least two driving circuits include source driving circuits located on the first side of the peripheral area and configured to provide source driving signals to the same column of pixel driving circuits located in the display area via corresponding data lines; the at least one test signal terminal includes a first sub-pixel test signal terminal disposed near the source driving circuit on the first side of the peripheral area. The location of the first corner; the location of the second sub-pixel test signal terminal, which is disposed on the first side of the peripheral region near the first corner of the source driving circuit; and the location of the third sub-pixel test signal terminal, which is disposed on the first side of the peripheral region near the first corner of the source driving circuit; the one or more test signal lines include a first sub-pixel test signal line, a second sub-pixel test signal line, and a third sub-pixel test signal line; one end of the first sub-pixel test signal line is connected to the first sub-pixel test signal terminal, and extends from the first sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and along... The second side extends from the second corner to a first point on the second side located in the peripheral region; one end of the second sub-pixel test signal line is connected to the second sub-pixel test signal terminal, and extends from the second sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a second point on the second side located in the peripheral region; one end of the third sub-pixel test signal line is connected to the third sub-pixel test signal terminal, and extends from the third sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a third point on the second side located in the peripheral region; the first sub-pixel test signal line is configured to provide a first test signal from the first sub-pixel test signal terminal to all column pixel driving circuits corresponding to the first sub-pixel during the inspection test; the second sub-pixel test signal line is configured to provide a second test signal from the second sub-pixel test signal terminal to all column pixel driving circuits corresponding to the second sub-pixel during the inspection test; and the third sub-pixel test signal line is configured to provide a third test signal from the third sub-pixel test signal terminal to all column pixel driving circuits corresponding to the third sub-pixel during the inspection test.

[0010] In some embodiments of this disclosure, the first sub-pixel test signal line is divided into multiple branches at the first point on the second side of the peripheral region, each branch being connected to a corresponding data line, so as to provide the first test signal from the first sub-pixel test signal terminal to the corresponding column of pixel driving circuits corresponding to the first sub-pixel during the inspection test; the second sub-pixel test signal line is divided into multiple branches at the second point on the second side of the peripheral region, each branch being connected to a corresponding data line, so as to provide the second test signal from the second sub-pixel test signal terminal to the corresponding column of pixel driving circuits corresponding to the second sub-pixel during the inspection test; and the third sub-pixel test signal line is divided into multiple branches at the third point on the second side of the peripheral region, each branch being connected to a corresponding data line, so as to provide the third test signal from the third sub-pixel test signal terminal to the corresponding column of pixel driving circuits corresponding to the third sub-pixel during the inspection test.

[0011] In some embodiments of this disclosure, the data lines connected to each branch of the first sub-pixel test signal line provide the first test signal from the first sub-pixel test signal terminal and the source drive signal from the source drive circuit to the corresponding pixel drive circuit corresponding to the first sub-pixel; the data lines connected to each branch of the second sub-pixel test signal line provide the second test signal from the second sub-pixel test signal terminal and the source drive signal from the source drive circuit to the corresponding pixel drive circuit corresponding to the second sub-pixel; and the data lines connected to each branch of the third sub-pixel test signal line provide the third test signal from the third sub-pixel test signal terminal and the source drive signal from the source drive circuit to the corresponding pixel drive circuit corresponding to the third sub-pixel.

[0012] In some embodiments of this disclosure, all column pixel driving circuits corresponding to the first sub-pixel are arranged in a mirror-symmetric manner about a straight line passing through the first point and perpendicular to the first side and the second side; all column pixel driving circuits corresponding to the second sub-pixel are arranged in a mirror-symmetric manner about a straight line passing through the second point and perpendicular to the first side and the second side; and all column pixel driving circuits corresponding to the third sub-pixel are arranged in a mirror-symmetric manner about a straight line passing through the third point and perpendicular to the first side and the second side.

[0013] In some embodiments of this disclosure, the at least two driving circuits include gate driving circuits located on the third side of the peripheral region and configured to provide the gate driving signal to pixel driving circuits in the same row of the display area via corresponding gate lines; the at least one test signal terminal includes a first test signal terminal disposed on the first side of the peripheral region near the third corner of the gate driving circuit; and a second test signal terminal disposed on the first side of the peripheral region near the third corner of the gate driving circuit; the one or more test signal lines include a first test signal line and a second test signal line; one end of the first test signal line is connected to the first test signal terminal and extends from the first test signal terminal along the third... The second test signal line extends from the third corner to the second corner on both sides, and extends along the fourth side from the second corner to a first point on the fourth side located in the peripheral region; one end of the second test signal line is connected to the second test signal terminal, and extends from the second test signal terminal along the second side from the third corner to the second corner, and extends along the fourth side from the second corner to a second point on the fourth side located in the peripheral region; the first test signal line is configured to provide a first test signal from the first test signal terminal to the odd-numbered row pixel driving circuit during the inspection test; and the second test signal line is configured to provide a second test signal from the second test signal terminal to the even-numbered row pixel driving circuit during the inspection test.

[0014] In some embodiments of this disclosure, the first test signal line is divided into multiple branches at the first point on the fourth side of the peripheral region, each branch being connected to a corresponding gate line to provide the first test signal for the same odd-numbered row pixel driving circuit during inspection testing; and the second test signal line is divided into multiple branches at the second point on the fourth side of the peripheral region, each branch being connected to a corresponding gate line to provide the second test signal for the same even-numbered row pixel driving circuit during inspection testing.

[0015] In some embodiments of this disclosure, the gate line connected to each branch of the first test signal line provides the first test signal from the first test signal terminal and the gate drive signal from the gate drive circuit to the same odd-numbered row pixel drive circuit; and the gate line connected to each branch of the second test signal line provides the second test signal from the second test signal terminal and the gate drive signal from the gate drive circuit to the same even-numbered row pixel drive circuit.

[0016] In some embodiments of this disclosure, all odd-numbered row pixel driving circuits are arranged in a mirror-symmetric manner with respect to a straight line passing through the first point and perpendicular to the third and fourth sides; and all even-numbered row pixel driving circuits are arranged in a mirror-symmetric manner with respect to a straight line passing through the second point and perpendicular to the third and fourth sides.

[0017] In some embodiments of this disclosure, the display substrate further includes a switch signal terminal disposed on the same side as the at least one test signal terminal; a switch signal line extending in the peripheral region and connected to the switch signal terminal; and a plurality of switch transistors connected to the switch signal line, the one or more test signal lines, and a corresponding pixel driving circuit; wherein the plurality of switch transistors are configured to control the one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during the inspection test by means of a switch signal provided by the switch signal line.

[0018] In some embodiments of this disclosure, the display substrate further includes a substrate; a first conductive layer located on the substrate and having a first opening therein; a gate insulating layer located on the side of the first conductive layer away from the substrate and located in the first opening; a passivation layer located on the side of the gate insulating layer away from the substrate; a second opening and a third opening extending through the gate insulating layer and the passivation layer; and a second conductive layer located on the side of the passivation layer away from the substrate and covering the second opening and the third opening to contact the first conductive layer; wherein the orthographic projection of the first opening on the substrate and the orthographic projection of the second opening on the substrate do not at least partially overlap; the first opening on the substrate... The orthographic projection on the substrate and the orthographic projection of the third opening on the substrate do not overlap at least partially; and the spacing between the two portions of the first conductive layer that are interrupted by the first opening is greater than or equal to 20 μm; wherein each of the one or more test signal lines includes a first portion and a second portion; the switch signal line includes a first portion and a second portion; the first portion of each test signal line and the first portion of the switch signal line are located in the first conductive layer; and the second portion of each test signal line and the second portion of the switch signal line are located in the second conductive layer; and the first opening, the second opening and the third opening are located at the first corner and the second corner, or at the second corner and the third corner.

[0019] In a second aspect, this disclosure provides a display device including the display substrate described in the first aspect, and one or more integrated circuits connected to the display substrate.

[0020] In a third aspect, this disclosure provides a method for testing a display substrate as described in the first aspect, the method comprising an inspection test phase: in the inspection test phase, providing a test signal to one or more test signal lines via the at least one test signal terminal, the test signal being transmitted to a corresponding pixel driving circuit via the one or more test signal lines to test the display substrate; and after the inspection test phase, binding the at least one test signal terminal to a corresponding terminal of a driving circuit to provide a ground signal to the one or more test signal lines via the at least one test signal terminal during a display phase of the display substrate.

[0021] In some embodiments of this disclosure, the display substrate further includes: a switch signal terminal disposed on the same side as the at least one test signal terminal; a switch signal line extending in the peripheral region and connected to the switch signal terminal; and a plurality of switch transistors connected to the switch signal line, the one or more test signal lines, and a corresponding pixel driving circuit; wherein the method further includes: during the inspection and testing phase, providing a switch signal from the switch signal terminal to the plurality of switch transistors via the switch signal line, thereby controlling the one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during the inspection and testing phase; and after the inspection and testing phase, binding the switch signal terminal to a corresponding terminal of the driving circuit so that during the display phase of the display substrate, the driving circuit provides a low-level signal to the switch signal line via the switch signal terminal. Attached Figure Description

[0022] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0023] Figure 1 This is a plan view of a display substrate according to some embodiments of the present disclosure.

[0024] Figure 2 The display area and peripheral area of ​​a display substrate according to some embodiments of the present disclosure are shown.

[0025] Figure 3 A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown.

[0026] Figure 4a A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown.

[0027] Figure 4b A schematic diagram of an alternative structure of a display substrate according to some embodiments of the present disclosure is shown.

[0028] Figure 5 This diagram illustrates how excessive resistance in the signal line can cause signal attenuation.

[0029] Figure 6a It shows along Figure 4a The cross-sectional view of line AA' in the diagram.

[0030] Figure 6b The diagram shows the bonding connections between the switch signal line, the first test signal line, and the second test signal line and the drive circuit after the inspection and testing process.

[0031] Figure 7 A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown.

[0032] Figure 8 A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown.

[0033] Figure 9 A flowchart is shown of a method for testing a display substrate according to some embodiments of the present disclosure. Detailed Implementation

[0034] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0035] This disclosure relates to medium-to-large-sized products with Gate & Source ICs, and more specifically, to a display substrate and display device including a gate driving circuit and a source driving circuit, wherein the gate driving circuit and the source driving circuit are respectively configured to drive an array of pixel driving circuits in rows and columns.

[0036] In some embodiments of this disclosure, medium and large-size products refer to display devices with a screen size of 7 inches or more. The display substrate and display device of this disclosure are particularly suitable for LCDs (Liquid Crystal Displays) with ADS (Advanced Super Dimension Switching) display mode.

[0037] Typically, the manufacturing process of an LCD includes: Array process, Cell process, and MDL process (i.e., module assembly process). The Cell process includes an inspection and testing process, which is the last step in the Cell process. This process uses electrical means to test the individual display substrates formed by the previous processes, promptly detects defective products, and prevents defective products from flowing into subsequent processes and causing waste.

[0038] Therefore, this disclosure particularly provides a display substrate and a testing method thereof, and a display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display substrate. In some embodiments, the display substrate has a display area and a peripheral area arranged around the display area, and includes: a plurality of gate lines extending along a first direction; a plurality of data lines extending along a second direction; at least two driving circuits located in the peripheral area and configured to provide gate driving signals and source driving signals, respectively, to a plurality of pixel driving circuits arranged in an array including multiple rows and columns located in the display area through the plurality of gate lines and the plurality of data lines; one or more test signal lines located in the peripheral area and extending to a side opposite to a corresponding driving circuit of one of the at least two driving circuits, each test signal line including a plurality of branches at a point on that side, each branch extending from that point to connect to the corresponding pixel driving circuit, thereby providing a test signal to the corresponding pixel driving circuit during inspection testing; and at least one test signal terminal configured to provide a test signal to the one or more test signal lines.

[0039] Various suitable pixel driving circuits can be used in the display substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. Various suitable light-emitting elements can be used in the display substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0040] Figure 1 This is a plan view of a display substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1The display substrate includes an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The display substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of first voltage supply lines Vdd, and various second voltage supply lines (e.g., low voltage supply lines). Each subpixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0041] Figure 2 The display area and peripheral area of ​​a display substrate according to some embodiments of the present disclosure are shown. (Refer to...) Figure 2In some embodiments, the display substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area DA" refers to the area of ​​the display substrate that actually displays an image. Optionally, the display area DA may include a subpixel area and an inter-subpixel area. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting display. Optionally, the subpixel area is the light-emitting area of ​​a red subpixel. Optionally, the subpixel area is the light-emitting area of ​​a green subpixel. Optionally, the subpixel area is the light-emitting area of ​​a blue subpixel. Optionally, the subpixel area is the light-emitting area of ​​a white subpixel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting display. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas of two adjacent pixels. Optionally, the inter-subpixel area is the area between the subpixel area of ​​a red subpixel and the subpixel area of ​​an adjacent green subpixel. Optionally, the inter-pixel region is the area between the sub-pixel region of a red sub-pixel and the sub-pixel region of an adjacent blue sub-pixel. Optionally, the inter-pixel region is the area between the sub-pixel region of a green sub-pixel and the sub-pixel region of an adjacent blue sub-pixel. As used herein, the term "peripheral area PA" refers to the area of ​​a display substrate (e.g., an opposing substrate or an array substrate) in a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display device, opaque or light-blocking components of the display device (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area PA instead of the display area DA.

[0042] In some embodiments of this disclosure, such as Figure 2 As shown, the surrounding area PA includes a first side SP and a second side SO opposite to each other, and a third side GP and a fourth side GO opposite to each other, wherein the first side SP connects the third side GP and the fourth side GO, and the second side SO connects the third side GP and the fourth side GO. In some embodiments of this disclosure, such as Figure 2 As shown, the surrounding area PA includes a first corner CR1 located between the first side SP and the fourth side GO, a second corner CR2 located between the second side SO and the fourth side GO, a third corner CR3 located between the second side SO and the third side GP, and a fourth corner CR4 located between the first side SP and the third side GP.

[0043] In some embodiments of this disclosure, the display substrate includes at least two driving circuits located in the peripheral region PA. These at least two driving circuits are configured to provide gate driving signals and source driving signals, respectively, to multiple pixel driving circuits PDC located in the display region DA, arranged in a multi-row, multi-column array, via multiple gate lines GL and multiple data lines DL. Figure 2 As shown, at least two driving circuits include a source driving circuit (SIC) and a gate driving circuit (GIC). The source driving circuit (SIC) is located on the first side (SP) of the peripheral region (PA), and the gate driving circuit (GIC) is located on the third side (GP) of the peripheral region (PA). In some embodiments of this disclosure, the source driving circuit (SIC) is configured to provide a source driving signal to the pixel driving circuit (PDC) located in the display region (DA) to drive the corresponding light-emitting element to emit light, and the gate driving circuit (GIC) is configured to provide a gate driving signal to the pixel driving circuit (PDC) located in the display region (DA). In this disclosure, the example of at least two driving circuits including a source driving circuit (SIC) and a gate driving circuit (GIC) is used for illustration.

[0044] Figure 3 A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 3 In some embodiments, the display substrate includes a plurality of pixel units PX arranged in an array, that is, the display substrate includes M columns of pixel units PX, where M is a positive integer greater than or equal to 1. Figure 3 Two adjacent columns of pixel units PX are shown, namely, the (2k-1)th column pixel unit PX and the (2k)th column pixel unit PX, where 1≤k≤M / 2. In some embodiments of this disclosure, each pixel unit PX includes a corresponding first sub-pixel Sp1, a corresponding second sub-pixel Sp2, and a corresponding third sub-pixel Sp3. Optionally, each pixel unit PX of the display substrate includes a corresponding first sub-pixel Sp1, a corresponding second sub-pixel Sp2, and a corresponding third sub-pixel Sp3. The plurality of sub-pixels in the display substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, where S1 represents the corresponding first sub-pixel Sp1, S2 represents the corresponding second sub-pixel Sp2, and S3 represents the corresponding third sub-pixel Sp3. In another example, the S1-S2-S3 format is a C1-C2-C3 format, where C1 represents the corresponding first sub-pixel Sp1 of the first color, C2 represents the corresponding second sub-pixel Sp2 of the second color, and C3 represents the corresponding third sub-pixel Sp3 of the third color. In another example, the C1-C2-C3 format is RGB format, where the corresponding first sub-pixel Sp1 is the red sub-pixel, the corresponding second sub-pixel Sp2 is the green sub-pixel, and the corresponding third sub-pixel Sp3 is the blue sub-pixel.

[0045] In some embodiments of this disclosure, such as Figure 3 As shown, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 of each pixel unit PX are arranged sequentially along a first direction DR1. In an alternative embodiment, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 of each pixel unit PX may be arranged sequentially along a second direction DR2. In an alternative embodiment, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 of each pixel unit PX may be arranged sequentially along a direction different from the first direction DR1 and the second direction DR2. In an alternative embodiment, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 of each pixel unit PX may be arranged sequentially in other ways. This disclosure does not impose specific limitations on the arrangement of the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 of each pixel unit PX.

[0046] In an alternative embodiment, each pixel unit PX includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each pixel unit PX of the display substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the display substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, S3 represents a corresponding third sub-pixel, and S4 represents a corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, C3 represents a corresponding third sub-pixel of a third color, and C4 represents a corresponding fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, the corresponding third sub-pixel is a blue sub-pixel, and the corresponding fourth sub-pixel is a green sub-pixel.

[0047] As used herein, the terms "column (2k-1)" and "column (2k)" are used in the context of column K. The display substrate may or may not include additional columns preceding the first column of column K and / or additional columns following the last column of column K. In the context of the display substrate, the term "column (2k-1)" does not necessarily refer to an odd-numbered column, and the term "column (2k)" does not necessarily refer to an even-numbered column. In one example, column (2k-1) is an odd-numbered column in the context of column K, but may be an even-numbered column in the context of the display substrate. In another example, column (2k-1) is an odd-numbered column in both the context of column K and the context of the display substrate. In one example, column (2k) is an even-numbered column in the context of column K, but may be an odd-numbered column in the context of the display substrate. In another example, column (2k) is an even-numbered column in both the context of column K and the context of the display substrate.

[0048] In some embodiments of this disclosure, such as Figure 3 As shown, the display substrate includes a plurality of gate lines extending along a first direction DR1 and a plurality of data lines DL extending along a second direction DR2. The gate lines and data lines DL intersect each other, and a sub-pixel (a first sub-pixel Sp1, a second sub-pixel Sp2, or a third sub-pixel Sp3) is disposed at each intersection of the gate lines and data lines DL. In some embodiments of this disclosure, such as... Figure 3 As shown, each gate line includes a first gate line GL1 and a second gate line GL2.

[0049] In some embodiments of this disclosure, such as Figure 3 As shown, the source drive circuit SIC is configured to provide source drive signals to the pixel drive circuit PDC corresponding to the same column of sub-pixels located in the display area DA (i.e., the pixel drive circuit PDC corresponding to the first sub-pixel Sp1, the second sub-pixel Sp2, or the third sub-pixel Sp3 in the same column) via the corresponding data line DL, so as to drive the corresponding sub-pixels to emit light.

[0050] In some embodiments of this disclosure, such as Figure 3 As shown, sub-pixels in the same column are sub-pixels of the same color. For example, sub-pixels in the same column may be the first sub-pixel Sp1, the second sub-pixel Sp2, or the third sub-pixel Sp3. Alternatively, in other embodiments of this disclosure, sub-pixels in the same column may include sub-pixels of any color. For example, sub-pixels in the same column may include the first sub-pixel Sp1, the second sub-pixel Sp2, and / or the third sub-pixel Sp3. This disclosure does not impose any specific limitations on this.

[0051] In some embodiments of this disclosure, such as Figure 3As shown, the gate drive circuit GIC is configured to provide gate drive signals to the pixel drive circuits PDC corresponding to the same row of sub-pixels in the display area DA through the corresponding first gate line GL1 and the corresponding second gate line GL2, so as to control these pixel drive circuits PDC.

[0052] Figure 4a A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown. For example... Figure 4a As shown, along the first direction DR1, Figure 4a The M-column pixel units PX are shown sequentially, including the first column pixel unit PX, the second column pixel unit PX, ..., the (2k-1)th column pixel unit PX, the (2k)th column pixel unit PX, ..., the (M-1)th column pixel unit PX, and the Mth column pixel unit PX.

[0053] In some embodiments of this disclosure, the display substrate further includes one or more test signal lines located in the peripheral region PA and extending to a side opposite to a corresponding driving circuit of one of the at least two driving circuits. Each test signal line includes multiple branches at a point on that side, each branch extending from that point to connect to the corresponding pixel driving circuit, thereby providing a first test signal or a second test signal to the corresponding pixel driving circuit during inspection testing; and at least one test signal terminal configured to provide a test signal to the one or more test signal lines.

[0054] Reference Figure 4a In some embodiments, besides Figure 3 The structure shown includes a display substrate that also includes multiple switching transistors (STFTs). Each switching transistor (STFT) is disposed at one end of a data line DL connected to a column of pixel units (PX), while the other end of the data line DL is connected to the source drive circuit (SIC).

[0055] In some embodiments of this disclosure, the display substrate further includes a switch signal terminal SW, which is disposed on the same side as at least one test signal terminal. For example... Figure 4a As shown, the switch signal terminal SW is located on the first side SP of the peripheral region PA and near the fourth side GO (i.e., located at the first corner CR1 of the peripheral region PA) and is configured to provide a switch signal to each switch transistor STFT via the switch signal line SWL. In some embodiments of this disclosure, such as Figure 4aAs shown, one end of the switch signal line SWL is connected to the switch signal terminal SW, and extends from the switch signal terminal SW along the first direction DR1 toward the fourth side GO to the first corner CR1, and then along the fourth side GO from the first corner CR1 to the second corner CR2. Further, it extends along the second side SO from the second corner CR2 to connect with each switch transistor STFT, and controls the switching of the switch transistor STFT by providing a switch signal to each switch transistor STFT.

[0056] The higher the resolution, the greater the screen load, and the larger the channel width-to-length ratio (W / L) of the required switching transistor STFT.

[0057] In some embodiments of this disclosure, one or more test signal lines include a first test signal line DOL and a second test signal line DEL. In some embodiments of this disclosure, at least one test signal terminal includes a first test signal terminal DO, which is disposed on the first side of the peripheral region PA near the first corner CR1 of the source drive circuit; and a second test signal terminal DE, which is disposed on the first side of the peripheral region PA near the first corner CR1 of the source drive circuit.

[0058] like Figure 4a As shown, the first test signal terminal DO is located on the first side SP of the peripheral region PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral region PA), and is configured to provide the first test signal DOS to the odd-column pixel unit PX through the first test signal line DOL.

[0059] like Figure 4a As shown, the second test signal terminal DE is located on the first side SP of the peripheral region PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral region PA), and is configured to provide the second test signal DES to the even-numbered column pixel unit PX through the second test signal line DEL.

[0060] like Figure 4a As shown, the display substrate also includes a common electrical terminal Vcom, which is configured to provide a test signal during inspection and testing, thereby testing the display substrate.

[0061] In the prior art, the first test signal line DOL or the second test signal line DEL provides test signals to all column pixel units PX sequentially from one side of the display substrate to the other side of the display substrate (e.g., from the fourth side GO to the third side GP). Figure 5 This diagram illustrates how excessive resistance in the signal line can cause signal attenuation. Figure 5As shown, as the distance between signal lines increases, the resistance of the signal lines becomes larger and larger. As a result, in the prior art, the input test signal from one side will cause signal attenuation, which in turn will cause display abnormalities (i.e., display inconsistency) on the left and right sides of the display substrate (the third side GP and the fourth side GO).

[0062] In some embodiments of this disclosure, such as Figure 4a As shown, one end of the first test signal line DOL is connected to the first test signal terminal DO, and extends from the first test signal terminal DO along the first direction DR1 towards the fourth side GO to the first corner CR1, then along the fourth side GO from the first corner CR1 to the second corner CR2, and further along the second side SO from the second corner CR2 to a first point O near the center of the display substrate. In some embodiments of this disclosure, such as Figure 4a As shown, the first test signal line DOL splits into multiple branches at point O on the second side SO of the peripheral region PA. Each branch is connected to a switching transistor STFT located in an odd-numbered column. In this way, all the switching transistors STFT in the odd-numbered columns are arranged in a mirror-symmetric manner about a straight line passing through point O and perpendicular to the first side SP and the second side SO. This ensures that the first test signal DOS is simultaneously transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate, avoiding display abnormalities (i.e., inconsistent displays) on the left and right sides (the third side GP and the fourth side GO) caused by the gradual attenuation of the first test signal DOS.

[0063] like Figure 4a As shown, the first test signal line DOL splits into two branches at point O on the second side SO of the peripheral region PA, namely, the first branch OL1 and the second branch OL2. The first branch OL1 extends along the first direction DR1 towards the third side GP, and the second branch OL2 extends along the first direction DR1 towards the fourth side GO. The display substrate also includes a plurality of first leads OLL, each of which extends along the second direction DR2, and one end of each first lead OLL is connected to a switching transistor STFT located in an odd-numbered column, and the other end of each first lead OLL is connected to the corresponding position of the corresponding branch, such as... Figure 4a As shown. In this way, the corresponding positions of each first lead OLL connected to the first branch OL1 and the second branch OL2 are arranged in a mirror-symmetric manner about the first point O.

[0064] In some embodiments of this disclosure, such as Figure 4aAs shown, in each odd-numbered column, the source drive circuit SIC is connected to one end of each data line DL. Each data line DL is connected to a column of pixel units PX, and then to a switching transistor STFT. The switching transistor STFT is then connected to a corresponding branch via a corresponding first lead OLL, and then to a first point O near the center of the display substrate. All the first leads OLL converge at the first point O via the first branch OL1 and the second branch OL2 to form a first test signal line DOL. The first test signal line DOL extends from the first point O along the second side SO, the fourth side GO, and the first side SP to the first test signal terminal DO. In some embodiments of this disclosure, such as Figure 4a As shown, each column of pixel units PX is provided with a first test signal DOS from the first test signal terminal DO and a source drive signal from the source drive circuit SIC via the same data line DL. In some embodiments of this disclosure, there are a total of L odd-numbered columns of switching transistors STFT and N even-numbered columns of switching transistors STFT, where L + N = M. Here, L is a positive integer greater than or equal to 1; and N is a positive integer greater than or equal to 1.

[0065] In some embodiments of this disclosure, all odd-numbered columns of switching transistors STFTs (i.e., L odd-numbered columns of switching transistors STFTs) are arranged in a mirror-symmetric manner about a line passing through a first point O and perpendicular to the first side SP and the second side SO. For example, the first odd-numbered column of switching transistors STFTs (i.e., the 1st column of M columns of switching transistors STFTs) and the last odd-numbered column of switching transistors STFTs (i.e., the Mth column of M columns of switching transistors STFTs or the (M-1)th column of switching transistors STFTs) are arranged in a mirror-symmetric manner about a line passing through a first point O and perpendicular to the first side SP and the second side SO; the second odd-numbered column of switching transistors STFTs (i.e., the 3rd column of M columns of switching transistors STFTs) and the penultimate odd-numbered column of switching transistors STFTs (i.e., the Mth column of M columns of switching transistors STFTs) are arranged in a mirror-symmetric manner about a line passing through a first point O and perpendicular to the first side SP and the second side SO; and the second odd-numbered column of switching transistors STFTs (i.e., the 3rd column of M columns of switching transistors STFTs) are arranged in a mirror-symmetric manner about a line passing through a first point O and perpendicular to the first side SP and the second side SO. The (M-2)th or (M-3)th column of switching transistors STFTs in the body transistor STFT are arranged in a mirror image symmetrical about a straight line passing through the first point O and perpendicular to the first side SP and the second side SO, ... When L is odd, the (L+1) / 2th odd-numbered column of switching transistors STFTs is located on a straight line passing through the first point O and perpendicular to the first side SP and the second side SO; when L is even, the L / 2th odd-numbered column of switching transistors STFTs and the (L+2) / 2th odd-numbered column of switching transistors STFTs are arranged in a mirror image symmetrical about a straight line passing through the first point O and perpendicular to the first side SP and the second side SO. In this way, all odd-numbered columns of switching transistors STFTs (i.e., L odd-numbered columns of switching transistors STFTs) are arranged in a mirror-symmetric manner about a straight line passing through the first point O and perpendicular to the first side SP and the second side SO. This allows the first test signal DOS to be transmitted simultaneously to the left and right sides of the display substrate (the third side GP and the fourth side GO), avoiding display abnormalities (i.e., inconsistent displays) on the left and right sides of the display substrate (the third side GP and the fourth side GO) caused by the gradual attenuation of the first test signal DOS.

[0066] Similarly, in some embodiments of this disclosure, such as Figure 4a As shown, one end of the second test signal line DEL is connected to the second test signal terminal DE, and extends from the second test signal terminal DE along the first direction DR1 toward the fourth side GO toward the first corner CR1, then along the fourth side GO from the first corner CR1 to the second corner CR2, and further along the second side SO from the second corner CR2 to a second point E near the center of the display substrate. In some embodiments of this disclosure, such as Figure 4aAs shown, the second test signal line DEL splits into multiple branches at point E on the second side SO of the peripheral region PA. Each branch is connected to a switching transistor STFT located in an even-numbered column. In this way, all the switching transistors STFT in the even-numbered columns are arranged in a mirror-symmetric manner about a straight line passing through point E and perpendicular to the first side SP and the second side SO. This ensures that the second test signal DES is simultaneously transmitted to the left and right sides (third side GP and fourth side GO) of the display substrate, avoiding display abnormalities (i.e., inconsistent displays) on the left and right sides (third side GP and fourth side GO) caused by the gradual attenuation of the second test signal DES.

[0067] like Figure 4a As shown, the second test signal line DEL splits into two branches at point E on the second side SO of the peripheral region PA, namely, the first branch EL1 and the second branch EL2. The first branch EL1 extends along the first direction DR1 towards the third side GP, and the second branch EL2 extends along the first direction DR1 towards the fourth side GO. The display substrate also includes multiple second leads ELL, each second lead ELL extending along the second direction DR2, and one end of each second lead ELL is connected to a switching transistor STFT located in an even-numbered column, and the other end of each second lead ELL is connected to the corresponding position of the corresponding branch, such as... Figure 4a As shown. In this way, the corresponding positions of each second lead ELL connected to the first branch EL1 and the second branch EL2 are arranged in a mirror-symmetric manner about the second point E.

[0068] In some embodiments of this disclosure, such as Figure 4a As shown, in each even-numbered column, the source drive circuit SIC is connected to one end of each data line DL. Each data line DL is connected to a column of pixel units PX, and then to a switching transistor STFT. The switching transistor STFT is then connected to the corresponding branch via a corresponding second lead ELL, and then to a second point E near the center of the display substrate. All the second leads ELL converge at the second point E via the first branch EL1 and the second branch EL2 to form a second test signal line DEL. The second test signal line DEL extends from the second point E along the second side SO, the fourth side GO, and the first side SP to the second test signal terminal DE. In some embodiments of this disclosure, such as Figure 4a As shown, each column of pixel units PX is provided with a second test signal DES from the second test signal terminal DE and a source drive signal from the source drive circuit SIC through the same data line DL.

[0069] In some embodiments of this disclosure, all even-numbered columns of switching transistors STFTs (i.e., N even-numbered columns of switching transistors STFTs) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the first side SP and the second side SO. For example, the first even-numbered column of switching transistors STFTs (i.e., the 2nd column of switching transistors STFTs in M ​​columns) and the last even-numbered column of switching transistors STFTs (i.e., the Mth column of switching transistors STFTs or the (M-1)th column of switching transistors STFTs in M ​​columns) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the first side SP and the second side SO; the second even-numbered column of switching transistors STFTs (i.e., the 4th column of switching transistors STFTs in M ​​columns) and the second-to-last even-numbered column of switching transistors STFTs (i.e., the Mth column of switching transistors STFTs) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the first side SP and the second side SO; and the second even-numbered column of switching transistors STFTs (i.e., the 4th column of switching transistors STFTs in M ​​columns) and the penultimate even-numbered column of switching transistors STFTs (i.e., the Mth column of switching transistors STFTs) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the first side SP and the second side SO. The (M-2)th or (M-3)th column of switching transistors STFTs in the body transistor STFT are arranged in a mirror image symmetrical about a line passing through the second point E and perpendicular to the first side SP and the second side SO, ... When N is odd, the (N+1) / 2th even-numbered column of switching transistors STFTs is located on a line passing through the second point E and perpendicular to the first side SP and the second side SO; when N is even, the N / 2th even-numbered column of switching transistors STFTs and the (N+2) / 2th even-numbered column of switching transistors STFTs are arranged in a mirror image symmetrical about a line passing through the second point E and perpendicular to the first side SP and the second side SO. In this way, all even-numbered columns of switching transistors STFT (i.e., N even-numbered columns of switching transistors STFT) are arranged in a mirror-symmetric manner about a straight line passing through the second point E and perpendicular to the first side SP and the second side SO. This allows the second test signal DES to be transmitted to the left and right sides of the display substrate simultaneously (the third side GP and the fourth side GO), avoiding display abnormalities (i.e., inconsistent displays) on the left and right sides of the display substrate (the third side GP and the fourth side GO) caused by the gradual attenuation of the second test signal DES.

[0070] exist Figure 4a The illustrated embodiment is described using the example of one switching transistor STFT per column of pixel units PX. That is, a column of first sub-pixels Sp1, a column of second sub-pixels Sp2, and a column of third sub-pixels Sp3 within each column of pixel units PX share one switching transistor STFT. In an alternative embodiment, one switching transistor STFT is provided per column of sub-pixels. That is, one switching transistor STFT is provided per column of first sub-pixels Sp1, one switching transistor STFT is provided per column of second sub-pixels Sp2, and one switching transistor STFT is provided per column of third sub-pixels Sp3. This disclosure does not impose specific limitations in this regard.

[0071] exist Figure 4aIn the illustrated embodiment, the M-column pixel units PX are divided into alternating odd-numbered and even-numbered column pixel units PX. Two test signal lines (i.e., a first test signal line DOL and a second test signal line DEL) are provided to offer a first test signal DOS to the odd-numbered column pixel units PX and a second test signal DES to the even-numbered column pixel units PX for inspection testing. In an alternative embodiment, the same test signal can be provided to the M-column pixel units PX simultaneously using the same test signal line for inspection testing. In an alternative embodiment, three test signal lines can also be provided for each color sub-pixel unit to control each column of sub-pixels in each column pixel unit PX separately. This disclosure does not impose specific limitations in this regard.

[0072] The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL need to extend from the first side SP of the peripheral area PA along the fourth side GO to the second side SO opposite to the first side SP. Therefore, the lengths of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are too long, and at the points where the extension direction of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL changes (i.e., at the first corner CR1 and / or the second corner CR2, such as...) Figure 4a The area within the dashed box is prone to electrostatic discharge (ESD), which can cause abnormal signal line function, burn out internal functional connection holes and traces of the display substrate, resulting in display defects and affecting product yield.

[0073] Figure 6a It shows along Figure 4a A cross-sectional view of line AA' in the diagram. In some embodiments of this disclosure, the portion of the second test signal line DEL at the second corner CR2 is used for illustration. The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL change direction at points (i.e., at the first corner CR1 and / or the second corner CR2, such as...) Figure 4a The parts within the dashed box have similar structures.

[0074] In some embodiments of this disclosure, such as Figure 6aAs shown, the display substrate includes a substrate BS; a first conductive layer CT1 located on the substrate BS and having a first opening AP1 therein; a gate insulating layer GI located on the side of the first conductive layer CT1 away from the substrate BS and within the first opening AP1; a passivation layer PVX located on the side of the gate insulating layer GI away from the substrate BS; and a second opening AP2 and a third opening AP3 extending through the gate insulating layer GI and the passivation layer PVX. The orthographic projection of the first opening AP1 onto the substrate BS does not overlap at least partially with the orthographic projection of the second opening AP2 onto the substrate BS. The orthographic projection of the first opening AP1 onto the substrate BS does not overlap at least partially with the orthographic projection of the third opening AP3 onto the substrate BS. The display substrate also includes a second conductive layer CT2 located on the side of the passivation layer PVX away from the substrate BS and covering the second opening AP2 and the third opening AP3 to contact the first conductive layer CT1.

[0075] In some embodiments of this disclosure, each test signal line (first test signal line DOL or second test signal line DEL) includes a first portion located in the first conductive layer CT1 and a second portion located in the second conductive layer CT2; the switch signal line SWL includes a first portion located in the first conductive layer CT1 and a second portion located in the second conductive layer CT2; the first opening AP1, the second opening AP2 and the third opening AP3 are located at the first corner CR1 and the second corner CR2.

[0076] In some embodiments of this disclosure, the first opening AP1 divides the first conductive layer CT1 into two disconnected parts. These two parts are electrically insulated by a portion of the gate insulating layer GI located within the first opening AP1, and are connected together by the second conductive layer CT2 at portions of the second opening AP2 and the third opening AP3, thereby achieving the connection of the second test signal line DEL at the second corner CR2. In this way, electrostatic discharge (ESD) can be avoided at the points where the extension direction of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL changes (i.e., at the first corner CR1 and / or the second corner CR2), which could lead to abnormal signal line function. This also avoids burning out the functional connection holes and traces inside the display substrate, preventing display defects and thus improving product yield.

[0077] In some embodiments of this disclosure, such as Figure 6a As shown, the distance D between the two parts of the first conductive layer CT1 that are disconnected by the first opening AP1 is greater than or equal to 20 μm.

[0078] Each test signal line or switch signal line SWL extends and turns at the corner, such as Figure 4aAs shown, each test signal line and switch signal line SWL extends along the first side SP, turns 90 degrees at the first corner CR1, then extends along the fourth side GO, then turns 90 degrees at the second corner CR2, and then extends along the second side SO. Therefore, each test signal line or switch signal line SWL may include three parts: a first part extending along the first side SP, a second part extending along the fourth side GO, and a third part extending along the second side SO.

[0079] like Figure 6a The overall idea behind the wire breakage jumper hole setting method shown is as follows: in the two parts located on both sides of the corresponding corner, the first opening AP1, the second opening AP2 and the third opening AP3 are set at the part with a larger length to achieve a better anti-static effect.

[0080] like Figure 4a and Figure 6a As shown, on both sides of the first corner CR1, there is a first part and a second part of each test signal line or switch signal line SWL. The length of the second part is greater than the length of the first part. Therefore, the first opening AP1, the second opening AP2, and the third opening AP3 are located at the end of the second part near the first corner CR1. Similarly, on both sides of the second corner CR2, there is a second part and a third part of each test signal line or switch signal line SWL. The length of the third part is greater than the length of the second part. Therefore, the first opening AP1, the second opening AP2, and the third opening AP3 are located at the end of the third part near the second corner CR2. Figure 4a The location of the break-through hole is indicated by a bold line within the dashed box.

[0081] Figure 4b A schematic diagram of an alternative structure of a display substrate according to some embodiments of the present disclosure is shown. In the alternative embodiments, such as Figure 4b and Figure 6a As shown, the first opening AP1, the second opening AP2, and the third opening AP3 are located at one end of the first part near the first corner CR1, and at one end of the second part near the second corner CR2. That is, the first opening AP1, the second opening AP2, and the third opening AP3 are located on the part with the shorter length. Figure 4a and Figure 4b The antistatic effects achieved by the various embodiments are not significantly different, but Figure 4a The antistatic effect achieved by the embodiments is better than Figure 4a Figure 4b The antistatic effect achieved by the embodiments.

[0082] In an alternative embodiment, the first opening AP1, the second opening AP2, and the third opening AP3 can be located at the longer portion of each test signal line or switch signal line SWL, employing... Figure 6a The break-through hole settings shown can all achieve good anti-static effects.

[0083] In some embodiments of this disclosure, various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer CT1. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer CT1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0084] In some embodiments of this disclosure, examples of suitable second conductive layer CT2 materials include, but are not limited to, metallic conductive electrode materials and non-metallic conductive electrode materials. Examples of suitable metallic conductive electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates comprising them. Examples of suitable non-metallic conductive electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO).

[0085] In some embodiments of this disclosure, examples of materials for the gate insulating layer GI and the passivation layer PVX include various suitable resin materials, polyimide, silicon oxide (SiOy), silicon nitride (SiNy, such as Si3N4), and silicon oxynitride (SiOxNy).

[0086] In some embodiments of this disclosure, the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL become inactive after the inspection and testing process, essentially floating signal lines. Following the inspection and testing process, during the MDL process, the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are bound to a driving circuit. During use, this driving circuit provides a ground (GND) signal to the first test signal line DOL and the second test signal line DEL, and a low-level signal (VGL) to the switch signal line SWL to completely turn off the switching transistor STFT. This prevents crosstalk between signals during use and avoids abnormal screen display caused by potential signal coupling.

[0087] Figure 6bThis illustrates the bonding connections between the switch signal line, the first test signal line, and the second test signal line and the drive circuit after the inspection and testing process. (See diagram.) Figure 4a and Figure 6b As shown, during the MDL process, the switch signal terminal SW, the first test signal terminal DO, and the second test signal terminal DE are bonded to the corresponding terminals of the driver circuit IC (e.g., the ground terminal and low voltage signal terminal of the driver circuit IC). In use, the driver circuit IC provides a low-level signal (VGL) to the switch signal line SWL through the switch signal terminal SW to completely turn off the switch transistor STFT, and provides ground (GND) signals to the first test signal line DOL and the second test signal line DEL through the first test signal terminal DO and the second test signal terminal DE, respectively.

[0088] Figure 7 A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown. For example... Figure 7 As shown, along the first direction DR1, Figure 7 The M-column pixel units PX are shown sequentially. Specifically, along the first direction DR1, Figure 7 The first sub-pixel Sp1 of column 1, the second sub-pixel Sp2 of column 1, the third sub-pixel Sp3 of column 1, ..., the first sub-pixel Sp1 of column M, the second sub-pixel Sp2 of column M, and the third sub-pixel Sp3 of column M are shown sequentially. (Refer to...) Figure 7 In some embodiments, besides Figure 3 The structure shown includes a display substrate that also includes multiple switching transistors STFTs. Each switching transistor STFT is disposed at one end of the data line DL connected to a column of sub-pixels (i.e., a column of first sub-pixels Sp1, a column of second sub-pixels Sp2, or a column of third sub-pixels Sp3), and the other end of the data line DL is connected to the source drive circuit SIC.

[0089] In some embodiments of this disclosure, such as Figure 7 As shown, the display substrate also includes a switch signal terminal SW, which is disposed on the first side SP of the peripheral region PA and near the fourth side GO (i.e., located at the first corner CR1 of the peripheral region PA) and configured to provide a switch signal to each switch transistor STFT via the switch signal line SWL. In some embodiments of this disclosure, such as Figure 7As shown, one end of the switch signal line SWL is connected to the switch signal terminal SW, and extends from the switch signal terminal SW along the first direction DR1 toward the fourth side GO to the first corner CR1, and then along the fourth side GO from the first corner CR1 to the second corner CR2. Further, it extends along the second side SO from the second corner CR2 to connect with each switch transistor STFT, and controls the switching of the switch transistor STFT by providing a switch signal to each switch transistor STFT.

[0090] In some embodiments of this disclosure, at least one test signal terminal includes a first sub-pixel test signal terminal DSp1, which is disposed on the first side of the peripheral region PA near the first corner CR1 of the source driving circuit; a second sub-pixel test signal terminal DSp2, which is disposed on the first side of the peripheral region PA near the first corner CR1 of the source driving circuit; and a third sub-pixel test signal terminal DSp3, which is disposed on the first side of the peripheral region PA near the first corner CR1 of the source driving circuit; one or more test signal lines include a first sub-pixel test signal line DSpL1, a second sub-pixel test signal line DSpL2, and a third sub-pixel test signal line DSpL3.

[0091] In some embodiments of this disclosure, such as Figure 7 As shown, the first sub-pixel test signal terminal DSp1 is located on the first side SP of the peripheral region PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral region PA), and is configured to provide a first test signal DR to each column of first sub-pixels Sp1 through the first sub-pixel test signal line DSpL1.

[0092] In some embodiments of this disclosure, such as Figure 7 As shown, the second sub-pixel test signal terminal DSp2 is located on the first side SP of the peripheral region PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral region PA), and is configured to provide a second test signal DG to each column of second sub-pixels Sp2 through the second sub-pixel test signal line DSpL2.

[0093] In some embodiments of this disclosure, such as Figure 7 As shown, the third sub-pixel test signal terminal DSp3 is located on the first side SP of the peripheral region PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral region PA), and is configured to provide a third test signal DB for each column of third sub-pixels Sp3 through the third sub-pixel test signal line DSpL3.

[0094] In some embodiments of this disclosure, such as Figure 7As shown, one end of the first sub-pixel test signal line DSpL1 is connected to the first sub-pixel test signal terminal DSp1, and extends from the first sub-pixel test signal terminal DSp1 along the first direction DR1 toward the fourth side GO to the first corner CR1, then extends along the fourth side GO from the first corner CR1 to the second corner CR2, and further extends along the second side SO from the second corner CR2 to a first point O1 near the center of the display substrate. In some embodiments of this disclosure, such as Figure 7 As shown, the first sub-pixel test signal line DSpL1 is divided into multiple branches at point O1 on the second side SO of the peripheral region PA. Each branch is connected to a column of first sub-pixels Sp1. In this way, all M columns of first sub-pixels Sp1 are arranged in a mirror symmetrical manner with respect to the straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO. This allows the first test signal DR to be transmitted to both the left and right sides of the display substrate (the third side GP and the fourth side GO) simultaneously, avoiding display abnormalities (i.e., inconsistent displays) on the left and right sides of the display substrate (the third side GP and the fourth side GO) caused by the gradual attenuation of the first test signal DR.

[0095] like Figure 7 As shown, the first sub-pixel test signal line DSpL1 splits into two branches at point O1 on the second side SO of the peripheral region PA, namely, the first branch O11 and the second branch O12. The first branch O11 extends along the first direction DR1 towards the third side GP, and the second branch O12 extends along the first direction DR1 towards the fourth side GO. The display substrate also includes a plurality of first leads OLL1, each of which extends along the second direction DR2, and one end of each first lead OLL1 is connected to a switching transistor STFT corresponding to a column of first sub-pixels Sp1, and the other end of each first lead OLL1 is connected to the corresponding position of the corresponding branch, such as... Figure 7 As shown. In this way, the corresponding positions of each first lead OLL1 connected to the first branch O11 and the second branch O12 are arranged in a mirror-symmetric manner about the first point O1.

[0096] In some embodiments of this disclosure, such as Figure 7As shown, in each column of first sub-pixels Sp1, the source driving circuit SIC is connected to one end of each data line DL. Each data line DL is connected to a column of first sub-pixels Sp1, and then to a switching transistor STFT. The switching transistor STFT is then connected to the corresponding branch through the corresponding first lead OLL1, and then to a first point O1 near the center of the display substrate. All the first leads OLL1 converge at the first point O1 through the first branch O11 and the second branch O12 to form a first sub-pixel test signal line DSpL1. The first sub-pixel test signal line DSpL1 extends from the first point O1 along the second side SO, the fourth side GO, and the first side SP to the first sub-pixel test signal terminal DSp1. In some embodiments of this disclosure, such as Figure 7 As shown, the first test signal DR from the first sub-pixel test signal terminal DSp1 and the source drive signal from the source drive circuit SIC are provided to the first sub-pixel Sp1 of each column through the same data line DL.

[0097] In some embodiments of this disclosure, all the switching transistors STFTs (i.e., the first M switching transistors STFTs) corresponding to the first sub-pixels Sp1 in the M columns are arranged in a mirror-symmetric manner about a straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO. For example, the switching transistor STFT corresponding to the first sub-pixel Sp1 in the first column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the first sub-pixel Sp1 in the last column about a line passing through the first point O1 and perpendicular to the first side SP and the second side SO. The switching transistor STFT corresponding to the first sub-pixel Sp1 in the second column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the first sub-pixel Sp1 in the penultimate column about a line passing through the first point O1 and perpendicular to the first side SP and the second side SO. ... When M is odd, the switching transistor STFT corresponding to the first sub-pixel Sp1 in the (M+1) / 2th column is located on the line passing through the first point O1 and perpendicular to the first side SP and the second side SO. When M is even, the switching transistor STFT corresponding to the first sub-pixel Sp1 in the M / 2th column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the first sub-pixel Sp1 in the (M+2) / 2th column about a line passing through the first point O1 and perpendicular to the first side SP and the second side SO. In this way, all the switching transistors STFTs corresponding to the first sub-pixels Sp1 in the M columns (i.e., the first M switching transistors STFTs) are arranged in a mirror symmetry about the straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO. This allows the first test signal DR to be transmitted to the left and right sides of the display substrate (the third side GP and the fourth side GO) at the same time, avoiding display abnormalities (i.e., display inconsistencies) on the left and right sides of the display substrate (the third side GP and the fourth side GO) caused by the gradual attenuation of the first test signal DR.

[0098] In some embodiments of this disclosure, such as Figure 7 As shown, one end of the second sub-pixel test signal line DSpL2 is connected to the second sub-pixel test signal terminal DSp2, and extends from the second sub-pixel test signal terminal DSp2 along the first direction DR1 toward the fourth side GO to the first corner CR1, then extends along the fourth side GO from the first corner CR1 to the second corner CR2, and further extends along the second side SO from the second corner CR2 to a second point O2 near the center of the display substrate. In some embodiments of this disclosure, such as Figure 7 As shown, the second sub-pixel test signal line DSpL2 splits into multiple branches at point O2 on the second side SO of the peripheral region PA. Each branch connects to a column of second sub-pixels Sp2. In this way, all M columns of second sub-pixels Sp2 are arranged in a mirror-symmetric manner about a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO. This ensures that the second test signal DG is simultaneously transmitted to the left and right sides (third side GP and fourth side GO) of the display substrate, avoiding display abnormalities (i.e., inconsistent displays) on the left and right sides (third side GP and fourth side GO) caused by the gradual attenuation of the second test signal DG.

[0099] like Figure 7 As shown, the second sub-pixel test signal line DSpL2 splits into two branches at point O2 on the second side SO of the peripheral region PA, namely, the first branch O21 and the second branch O22. The first branch O21 extends along the first direction DR1 towards the third side GP, and the second branch O22 extends along the first direction DR1 towards the fourth side GO. The display substrate also includes a plurality of second leads OLL2, each second lead OLL2 extending along the second direction DR2, and one end of each second lead OLL2 is connected to the switching transistor STFT corresponding to a column of second sub-pixels Sp2, and the other end of each second lead OLL2 is connected to the corresponding position of the corresponding branch, such as... Figure 7 As shown. In this way, the corresponding positions of each second lead OLL2 connected to the first branch O21 and the second branch O22 are arranged in a mirror-symmetric manner with respect to the second point O2.

[0100] In some embodiments of this disclosure, such as Figure 7As shown, in each column of second sub-pixels Sp2, the source driving circuit SIC is connected to one end of each data line DL. Each data line DL is connected to a column of second sub-pixels Sp2, and then to a switching transistor STFT. The switching transistor STFT is then connected to the corresponding branch through the corresponding second lead OLL2, and then to the second point O2 near the center of the display substrate. All the second leads OLL2 converge at the second point O2 through the first branch O21 and the second branch O22 to form the second sub-pixel test signal line DSpL2. The second sub-pixel test signal line DSpL2 extends from the second point O2 along the second side SO, the fourth side GO, and the first side SP to the second sub-pixel test signal terminal DSp2. In some embodiments of this disclosure, such as Figure 7 As shown, the second test signal DG from the second sub-pixel test signal terminal DSp2 and the source drive signal from the source drive circuit SIC are provided to each column of second sub-pixels Sp2 through the same data line DL.

[0101] In some embodiments of this disclosure, all the switching transistors STFTs (i.e., the second M switching transistors STFTs) corresponding to the second sub-pixels Sp2 in the M columns are arranged in a mirror-symmetric manner about a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO. For example, the switching transistor STFT corresponding to the second sub-pixel Sp2 in the first column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the second sub-pixel Sp2 in the last column about a line passing through the second point O2 and perpendicular to the first side SP and the second side SO. The switching transistor STFT corresponding to the second sub-pixel Sp2 in the second column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the second sub-pixel Sp2 in the penultimate column about a line passing through the second point O2 and perpendicular to the first side SP and the second side SO. ... When M is odd, the switching transistor STFT corresponding to the second sub-pixel Sp2 in the (M+1) / 2th column is located on a line passing through the second point O2 and perpendicular to the first side SP and the second side SO. When M is even, the switching transistor STFT corresponding to the second sub-pixel Sp2 in the M / 2th column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the second sub-pixel Sp2 in the (M+2) / 2th column about a line passing through the second point O2 and perpendicular to the first side SP and the second side SO. In this way, all the switching transistors STFTs corresponding to the second sub-pixels Sp2 in the M columns (i.e., the second M switching transistors STFTs) are arranged in a mirror symmetry about the straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO. This allows the second test signal DG to be transmitted to the left and right sides of the display substrate (the third side GP and the fourth side GO) at the same time, avoiding display abnormalities (i.e., display inconsistencies) on the left and right sides of the display substrate (the third side GP and the fourth side GO) caused by the gradual attenuation of the second test signal DG.

[0102] In some embodiments of this disclosure, such as Figure 7 As shown, one end of the third sub-pixel test signal line DSpL3 is connected to the third sub-pixel test signal terminal DSp3, and extends from the third sub-pixel test signal terminal DSp3 along the first direction DR1 toward the fourth side GO to the first corner CR1, then along the fourth side GO from the first corner CR1 to the second corner CR2, and further along the second side SO from the second corner CR2 to a third point O3 near the center of the display substrate. In some embodiments of this disclosure, such as Figure 7 As shown, the third sub-pixel test signal line DSpL3 is divided into multiple branches at the third point O3 on the second side SO of the peripheral region PA. Each branch is connected to a column of third sub-pixels Sp3. In this way, all M columns of third sub-pixels Sp3 are arranged in a mirror-symmetric manner about the straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO. This allows the third test signal DB to be transmitted to both the left and right sides of the display substrate (the third side GP and the fourth side GO) simultaneously, avoiding display abnormalities (i.e., inconsistent displays) on the left and right sides of the display substrate (the third side GP and the fourth side GO) caused by the gradual attenuation of the third test signal DB.

[0103] like Figure 7 As shown, the third sub-pixel test signal line DSpL3 splits into two branches at point O3 on the second side SO of the peripheral region PA: a first branch O31 and a second branch O32. The first branch O31 extends along the first direction DR1 towards the third side GP, and the second branch O32 extends along the first direction DR1 towards the fourth side GO. The display substrate also includes multiple third leads OLL3, each extending along the second direction DR2. One end of each third lead OLL3 is connected to a switching transistor STFT corresponding to a column of third sub-pixels Sp3, and the other end of each third lead OLL3 is connected to the corresponding position of the corresponding branch, such as... Figure 7 As shown. In this way, the corresponding positions of each third lead OLL3 connected to the first branch O31 and the second branch O32 are arranged in a mirror-symmetric manner with respect to the third point O3.

[0104] In some embodiments of this disclosure, such as Figure 7As shown, in each column of third sub-pixels Sp3, the source drive circuit SIC is connected to one end of each data line DL. Each data line DL is connected to a column of third sub-pixels Sp3, and then to a switching transistor STFT. The switching transistor STFT is then connected to the corresponding branch through the corresponding third lead OLL3, and then to the third point O3 near the center of the display substrate. All the third leads OLL3 converge at the third point O3 through the first branch O31 and the second branch O32 to form the third sub-pixel test signal line DSpL3. The third sub-pixel test signal line DSpL3 extends from the third point O3 along the second side SO, the fourth side GO, and the first side SP to the third sub-pixel test signal terminal DSp3. In some embodiments of this disclosure, such as Figure 7 As shown, the third test signal DB from the third sub-pixel test signal terminal DSp3 and the source drive signal from the source drive circuit SIC are provided to each column's third sub-pixel Sp3 through the same data line DL.

[0105] In some embodiments of this disclosure, all the switching transistors STFTs corresponding to the third sub-pixels Sp3 in the M columns (i.e., the third M switching transistors STFTs) are arranged in a mirror-symmetric manner about a straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO. For example, the switching transistor STFT corresponding to the third sub-pixel Sp3 in the first column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the third sub-pixel Sp3 in the last column about a line passing through the third point O3 and perpendicular to the first side SP and the second side SO. The switching transistor STFT corresponding to the third sub-pixel Sp3 in the second column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the third sub-pixel Sp3 in the penultimate column about a line passing through the third point O3 and perpendicular to the first side SP and the second side SO. ... When M is odd, the switching transistor STFT corresponding to the third sub-pixel Sp3 in the (M+1) / 2th column is located on a line passing through the third point O3 and perpendicular to the first side SP and the second side SO. When M is even, the switching transistor STFT corresponding to the third sub-pixel Sp3 in the M / 2th column is mirror-symmetrically arranged with respect to the switching transistor STFT corresponding to the third sub-pixel Sp3 in the (M+2) / 2th column about a line passing through the third point O3 and perpendicular to the first side SP and the second side SO. In this way, all the switching transistors STFTs corresponding to the third sub-pixel Sp3 in the M columns (i.e., the third M switching transistors STFTs) are arranged in a mirror symmetry about the straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO. This allows the third test signal DB to be transmitted to the left and right sides of the display substrate (the third side GP and the fourth side GO) simultaneously, avoiding display abnormalities (i.e., display inconsistencies) on the left and right sides of the display substrate (the third side GP and the fourth side GO) caused by the gradual attenuation of the third test signal DB.

[0106] exist Figure 7 In the illustrated embodiment, the M-column pixel unit PX is divided into M-column first sub-pixels Sp1, M-column second sub-pixels Sp2, and M-column third sub-pixels Sp3 arranged alternately. Three test signal lines (i.e., the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3) are set to provide test signals (i.e., the first test signal DR, the second test signal DG, and the third test signal DB) for the M-column first sub-pixel Sp1, M-column second sub-pixel Sp2, and M-column third sub-pixel Sp3, respectively, to perform the inspection test process.

[0107] In an alternative embodiment, in an LCD product using Dual-gate (DRD) driving technology, DY / DC / DM test signals are typically provided for the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 in column M, where DY / DC / DM represent the yellow test signal, the cyan test signal, and the magenta test signal, respectively.

[0108] In an alternative embodiment, six test signal lines are provided: the first test signal line DSpL1 is divided into two test signal lines DSpL1+ and DSpL1- that provide test signals DR+ and DR- with opposite polarities; the second test signal line DSpL2 is divided into two test signal lines DSpL2+ and DSpL2- that provide test signals DG+ and DG- with opposite polarities; and the third test signal line DSpL3 is divided into two test signal lines DSpL3+ and DSpL3- that provide test signals DB+ and DB- with opposite polarities. Test signals DR+ and DR- with opposite polarities are provided for two adjacent first sub-pixels Sp1 in each pair of adjacent pixel units PX via two test signal lines DSpL1+ and DSpL1-. Test signals DG+ and DG- with opposite polarities are provided for two adjacent second sub-pixels Sp2 in each pair of adjacent pixel units PX via two test signal lines DSpL2+ and DSpL2-. Test signals DB+ and DB- with opposite polarities are provided for two adjacent third sub-pixels Sp3 in each pair of adjacent pixel units PX via two test signal lines DSpL3+ and DSpL3-. This disclosure does not impose any specific limitations on this.

[0109] The switch signal line SWL, the first test signal line DSPL1, the second test signal line DSPL2, and the third test signal line DSPL3 need to extend from the first side SP of the peripheral area PA along the fourth side GO to the second side SO opposite to the first side SP. Therefore, the lengths of the switch signal line SWL, the first test signal line DSPL1, the second test signal line DSPL2, and the third test signal line DSPL3 are too long, and at the points where the extension direction of the switch signal line SWL, the first test signal line DSPL1, the second test signal line DSPL2, and the third test signal line DSPL3 changes (i.e., at the first corner CR1 and / or the second corner CR2, such as...) Figure 7 The area within the dashed box is prone to electrostatic discharge (ESD), which can cause abnormal signal line function, burn out internal functional connection holes and traces of the display substrate, resulting in display defects and affecting product yield.

[0110] like Figure 6a The cross-sectional view shown, in some embodiments of this disclosure, taking the second test signal line DSpL2 as an example, shows that at the points where the extension direction of the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 changes (i.e., at the first corner CR1 and / or the second corner CR2, such as...) Figure 7 The parts within the dashed box have similar structures.

[0111] In some embodiments of this disclosure, such as Figure 6a As shown, the display substrate includes a substrate BS; a first conductive layer CT1 located on the substrate BS and having a first opening AP1 therein; a gate insulating layer GI located on the side of the first conductive layer CT1 away from the substrate BS and within the first opening AP1; a passivation layer PVX located on the side of the gate insulating layer GI away from the substrate BS; and a second opening AP2 and a third opening AP3 extending through the gate insulating layer GI and the passivation layer PVX. The orthographic projection of the first opening AP1 onto the substrate BS does not overlap at least partially with the orthographic projection of the second opening AP2 onto the substrate BS. The orthographic projection of the first opening AP1 onto the substrate BS does not overlap at least partially with the orthographic projection of the third opening AP3 onto the substrate BS. The display substrate also includes a second conductive layer CT2 located on the side of the passivation layer PVX away from the substrate BS and covering the second opening AP2 and the third opening AP3 to contact the first conductive layer CT1.

[0112] In some embodiments of this disclosure, each test signal line (first test signal line DSpL1, second test signal line DSpL2, or third test signal line DSpL3) includes a first portion located in the first conductive layer CT1 and a second portion located in the second conductive layer CT2; the switch signal line SWL includes a first portion located in the first conductive layer CT1 and a second portion located in the second conductive layer CT2; the first opening AP1, the second opening AP2, and the third opening AP3 are located at the first corner CR1 and the second corner CR2.

[0113] In some embodiments of this disclosure, the first opening AP1 divides the first conductive layer CT1 into two disconnected parts. These two parts are electrically insulated by a portion of the gate insulating layer GI located in the first opening AP1, and are connected together by the second conductive layer CT2 at portions of the second opening AP2 and the third opening AP3, thereby achieving the connection of the second test signal line DSpL2 at the second corner CR2. In this way, electrostatic discharge (ESD) can be avoided at the points where the extension direction of the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 changes (i.e., at the first corner CR1 and / or the second corner CR2), which could lead to abnormal signal line function. This avoids damage to the functional connection holes and traces inside the display substrate, prevents display defects, and thus improves product yield.

[0114] In some embodiments of this disclosure, such as Figure 6a As shown, the distance D between the two parts of the first conductive layer CT1 that are disconnected by the first opening AP1 is greater than or equal to 20 μm.

[0115] In some embodiments of this disclosure, various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer CT1. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer CT1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0116] In some embodiments of this disclosure, examples of suitable second conductive layer CT2 materials include, but are not limited to, metallic conductive electrode materials and non-metallic conductive electrode materials. Examples of suitable metallic conductive electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates comprising them. Examples of suitable non-metallic conductive electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO).

[0117] In some embodiments of this disclosure, examples of materials for the gate insulating layer GI and the passivation layer PVX include various suitable resin materials, polyimide, silicon oxide (SiOy), silicon nitride (SiNy, such as Si3N4), and silicon oxynitride (SiOxNy).

[0118] In some embodiments of this disclosure, the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 are rendered inactive after the inspection and testing process, effectively becoming floating signal lines. After the MDL process, during use, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 are all connected to ground (GND), and the switch signal line SWL is connected to a low-level signal (VGL) to completely turn off the switching transistor STFT, preventing crosstalk between signals and avoiding abnormal screen display caused by potential signal coupling.

[0119] exist Figures 4a to 7 In the illustrated embodiment, the switching transistor STFT is located on the second side SO, opposite to the first side SP where the source drive circuit SIC is located. Both the test signal line and the switching signal line SWL are led to this second side SO, thereby avoiding wiring difficulties caused by the small space on the first side SP and effectively utilizing the space on the second side SO. Furthermore, this also achieves a uniform film thickness across the entire display substrate.

[0120] Figure 8 A schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure is shown. For example... Figure 8 As shown, along the first direction DR1, Figure 8 The first column pixel unit PX and the Mth column pixel unit PX are shown sequentially. Along the second direction DR2, Figure 8 The Q-row pixel units PX are shown sequentially, including the first row PX, the second row PX, ..., the (2q-1)th row PX, the (2q)th row PX, ..., the (Q-1)th row PX, and the Qth row PX. Here, Q is a positive integer greater than or equal to 1, and 1 ≤ q ≤ Q / 2. (See reference...) Figure 8 In some embodiments, besides Figure 3 The structure shown includes a display substrate further comprising multiple switching transistors (STFTs). Each STFT is disposed at one end of a gate line GL (either a first gate line GL1 or a second gate line GL2) to which a row of pixel units PX is connected, while the other end of the gate line is connected to a gate driving circuit GIC. Figure 8In one embodiment, each switching transistor STFT is disposed at one end of a first gate line GL1 connected to a row of pixel units PX, and the other end of the first gate line GL1 is connected to a gate driving circuit GIC. In an alternative embodiment, each switching transistor STFT is disposed at one end of a second gate line GL2 connected to a row of pixel units PX, and the other end of the second gate line GL2 is connected to a gate driving circuit GIC.

[0121] In some embodiments of this disclosure, such as Figure 8 As shown, the display substrate also includes a switch signal terminal SW, which is disposed on the third side GP of the peripheral region PA and close to the second side SO (i.e., located in the third triangular portion CR3 of the peripheral region PA) and configured to provide a switch signal to each switch transistor STFT via the switch signal line SWL. In some embodiments of this disclosure, such as Figure 8 As shown, one end of the switch signal line SWL is connected to the switch signal terminal SW, and extends from the switch signal terminal SW along the second direction DR2 toward the second side SO to the third corner CR3, then along the second side SO from the third corner CR3 to the second corner CR2, and further extends along the fourth side GO from the second corner CR2 to connect with each switch transistor STFT, and controls the switching of the switch transistor STFT by providing a switch signal to each switch transistor STFT.

[0122] In some embodiments of this disclosure, at least one test signal terminal includes a first test signal terminal DO, which is disposed on the first side of the peripheral region PA near the third corner CR3 of the gate drive circuit GIC; and a second test signal terminal DE, which is disposed on the first side of the peripheral region PA near the third corner CR3 of the gate drive circuit GIC; one or more test signal lines include a first test signal line DOL and a second test signal line DEL.

[0123] In some embodiments of this disclosure, such as Figure 8 As shown, the first test signal terminal DO is located on the third side GP of the peripheral region PA and close to the second side SO (i.e., located in the third triangular part CR3 of the peripheral region PA), and is configured to provide the first test signal DOS to the odd-numbered row pixel unit PX through the first test signal line DOL.

[0124] In some embodiments of this disclosure, such as Figure 8 As shown, the second test signal terminal DE is located on the third side GP of the peripheral region PA and close to the second side SO (i.e., located in the third triangular part CR3 of the peripheral region PA), and is configured to provide the second test signal DES to the even-numbered row pixel unit PX through the second test signal line DEL.

[0125] In the prior art, the first test signal line DOL or the second test signal line DEL provides test signals to all column pixel units PX sequentially from one side of the display substrate to the other side of the display substrate (e.g., from the second side SO to the first side SP). Figure 5 This diagram illustrates how excessive resistance in the signal line can cause signal attenuation. Figure 5 As shown, as the distance between signal lines increases, the resistance of the signal lines becomes larger and larger. As a result, in the prior art, the input test signal from one side will cause signal attenuation, which in turn will cause display abnormalities (i.e., display inconsistency) on the upper and lower sides (the first side SP and the second side SO) of the display substrate.

[0126] In some embodiments of this disclosure, such as Figure 8 As shown, one end of the first test signal line DOL is connected to the first test signal terminal DO, and extends from the first test signal terminal DO along the second direction DR2 toward the second side SO toward the third corner CR3, then along the second side SO from the third corner CR3 to the second corner CR2, and further, along the fourth side GO from the second corner CR2 to a first point O near the center of the display substrate. In some embodiments of this disclosure, such as Figure 8 As shown, the first test signal line DOL splits into multiple branches at point O on the fourth side GO of the peripheral region PA. Each branch is connected to a switching transistor STFT located in an odd-numbered row. In this way, all the switching transistors STFT in the odd-numbered rows are arranged in a mirror-symmetric manner about a straight line passing through point O and perpendicular to the third side GP and the fourth side GO. This ensures that the first test signal DOS is simultaneously transmitted to the top and bottom sides (first side SP and second side SO) of the display substrate, avoiding display abnormalities (i.e., inconsistent displays) on the top and bottom sides (first side SP and second side SO) of the display substrate caused by the gradual attenuation of the first test signal DOS.

[0127] like Figure 8 As shown, the first test signal line DOL splits into two branches at point O on the fourth side GO of the peripheral region PA, namely, the first branch OL1 and the second branch OL2. The first branch OL1 extends along the second direction DR2 towards the second side SO, and the second branch OL2 extends along the second direction DR2 towards the first side SP. The display substrate also includes a plurality of first leads OLL, each first lead OLL extending along the first direction DR1, and one end of each first lead OLL is connected to a switching transistor STFT located in an odd-numbered row, and the other end of each first lead OLL is connected to the corresponding position of the corresponding branch, such as... Figure 8 As shown. In this way, the corresponding positions of each first lead OLL connected to the first branch OL1 and the second branch OL2 are arranged in a mirror-symmetric manner about the first point O.

[0128] In some embodiments of this disclosure, such as Figure 8 As shown, in each odd-numbered row, the gate drive circuit GIC is connected to one end of each first gate line GL1. Each first gate line GL1 is connected to a row pixel unit PX, and then to a switching transistor STFT. The switching transistor STFT is then connected to a corresponding branch via a corresponding first lead OLL, and then to a first point O near the center of the display substrate. All the first leads OLL converge at the first point O via the first branch OL1 and the second branch OL2 to form a first test signal line DOL. The first test signal line DOL extends from the first point O along the fourth side GO, the second side SO, and the third side GP to the first test signal terminal DO. In some embodiments of this disclosure, such as Figure 8 As shown, each row of pixel units PX is provided with a first test signal DOS from the first test signal terminal DO and a gate drive signal from the gate drive circuit GIC through the same first gate line GL1.

[0129] In some embodiments of this disclosure, there are a total of O odd-numbered rows of switching transistors STFTs and P even-numbered rows of switching transistors STFTs, where O + P = Q. Here, O is a positive integer greater than or equal to 1, and P is a positive integer greater than or equal to 1.

[0130] In some embodiments of this disclosure, all odd-numbered rows of switching transistor STFTs (i.e., O odd-numbered rows of switching transistor STFTs) are arranged in a mirror-symmetric manner about a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO. For example, the first odd-numbered row of switching transistor STFTs (i.e., the first row of switching transistor STFTs in the Q rows) and the last odd-numbered row of switching transistor STFTs (i.e., the Qth row or (Q-1)th row of switching transistor STFTs in the Q rows) are arranged in a mirror-symmetric manner about a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO; the second odd-numbered row of switching transistor STFTs (i.e., the third row of switching transistor STFTs in the Q rows) and the penultimate odd-numbered row of switching transistor STFTs (i.e., the second row of switching transistor STFTs in the Q rows) are arranged in a mirror-symmetric manner about a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO; and the second odd-numbered row of switching transistor STFTs (i.e., the third row of switching transistor STFTs in the Q rows) are arranged in a mirror-symmetric manner about a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO. The (Q-2)th row or (Q-3)th row of switching transistors in the body transistor STFT are arranged in a mirror image symmetrical about a line passing through the first point O and perpendicular to the third side GP and the fourth side GO, ... When O is odd, the (O+1) / 2th odd-numbered row of switching transistors STFT is located on a line passing through the first point O and perpendicular to the third side GP and the fourth side GO; when O is even, the (O+2) / 2th odd-numbered row of switching transistors STFT and the (O+2) / 2th odd-numbered row of switching transistors STFT are arranged in a mirror image symmetrical about a line passing through the first point O and perpendicular to the third side GP and the fourth side GO. In this way, all odd-numbered rows of switching transistors STFTs (i.e., O odd-numbered rows of switching transistors STFTs) are arranged in a mirror-symmetric manner about a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO. This allows the first test signal DOS to be transmitted to the top and bottom sides (first side SP and second side SO) of the display substrate simultaneously, avoiding display abnormalities (i.e., inconsistent displays) on the top and bottom sides (first side SP and second side SO) of the display substrate caused by the gradual attenuation of the first test signal DOS.

[0131] Similarly, in some embodiments of this disclosure, such as Figure 8 As shown, one end of the second test signal line DEL is connected to the second test signal terminal DE, and extends from the second test signal terminal DE along the second direction DR2 toward the second side SO toward the third corner CR3, then along the second side SO from the third corner CR3 to the second corner CR2, and further, along the fourth side GO from the second corner CR2 to a second point E near the center of the display substrate. In some embodiments of this disclosure, such as Figure 8As shown, the second test signal line DEL splits into multiple branches at point E on the fourth side GO of the peripheral region PA. Each branch connects to a switching transistor STFT located in an even-numbered row. In this way, all the switching transistors STFT in the even-numbered rows are arranged in a mirror-symmetric manner about a straight line passing through point E and perpendicular to the third side GP and the fourth side GO. This ensures that the second test signal DES is simultaneously transmitted to the top and bottom sides (first side SP and second side SO) of the display substrate, avoiding display abnormalities (i.e., inconsistent displays) on the top and bottom sides (first side SP and second side SO) of the display substrate caused by the gradual attenuation of the second test signal DES.

[0132] like Figure 8 As shown, the second test signal line DEL splits into two branches at point E on the fourth side GO of the peripheral region PA, namely, the first branch EL1 and the second branch EL2. The first branch EL1 extends along the second direction DR2 towards the second side SO, and the second branch EL2 extends along the second direction DR2 towards the first side SP. The display substrate also includes multiple second leads ELL, each second lead ELL extending along the first direction DR1, and one end of each second lead ELL is connected to a switching transistor STFT located in an even-numbered row, and the other end of each second lead ELL is connected to the corresponding position of the corresponding branch, such as... Figure 8 As shown. In this way, the corresponding positions of each second lead ELL connected to the first branch EL1 and the second branch EL2 are arranged in a mirror-symmetric manner about the second point E.

[0133] In some embodiments of this disclosure, such as Figure 8 As shown, in each even-numbered row, the gate drive circuit GIC is connected to one end of each first gate line GL1. Each first gate line GL1 is connected to a row pixel unit PX, and then to a switching transistor STFT. The switching transistor STFT is then connected to the corresponding branch via the corresponding second lead ELL, and then to a second point E near the center of the display substrate. All the second leads ELL converge at the second point E via the first branch EL1 and the second branch EL2 to form a second test signal line DEL. The second test signal line DEL extends from the second point E along the fourth side GO, the second side SO, and the third side GP to the second test signal terminal DE. In some embodiments of this disclosure, such as Figure 8 As shown, each row of pixel units PX is provided with a second test signal DES from the second test signal terminal DE and a gate drive signal from the gate drive circuit GIC through the same first gate line GL1.

[0134] In some embodiments of this disclosure, all even-numbered rows of switching transistor STFTs (i.e., P even-numbered rows of switching transistor STFTs) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the third side GP and the fourth side GO. For example, the first even-numbered row of switching transistor STFTs (i.e., the second row of switching transistor STFTs in the Q rows) and the last even-numbered row of switching transistor STFTs (i.e., the Qth row or (Q-1)th row of switching transistor STFTs in the Q rows) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the third side GP and the fourth side GO; the second even-numbered row of switching transistor STFTs (i.e., the fourth row of switching transistor STFTs in the Q rows) and the penultimate even-numbered row of switching transistor STFTs (i.e., the second row of switching transistor STFTs in the Q rows) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the third side GP and the fourth side GO; and the second even-numbered row of switching transistor STFTs (i.e., the fourth row of switching transistor STFTs in the Q rows) are arranged in a mirror-symmetric manner about a line passing through the second point E and perpendicular to the third side GP and the fourth side GO. The (Q-2)th row or (Q-3)th row of switching transistors in the body transistor STFT are arranged in a mirror image symmetrical about a line passing through the second point E and perpendicular to the third side GP and the fourth side GO, ... When P is odd, the (P+1) / 2th even-numbered row of switching transistors STFT is located on a line passing through the second point E and perpendicular to the third side GP and the fourth side GO; when P is even, the P / 2th even-numbered row of switching transistors STFT and the (P+2) / 2th even-numbered row of switching transistors STFT are arranged in a mirror image symmetrical about a line passing through the second point E and perpendicular to the third side GP and the fourth side GO. In this way, all even-numbered rows of switching transistors STFT (i.e., P even-numbered rows of switching transistors STFT) are arranged in a mirror-symmetric manner about the straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO. This allows the second test signal DES to be transmitted to the top and bottom sides (first side SP and second side SO) of the display substrate simultaneously, avoiding display abnormalities (i.e., inconsistent displays) on the top and bottom sides (first side SP and second side SO) of the display substrate caused by the gradual attenuation of the second test signal DES.

[0135] exist Figure 8In the illustrated embodiment, the Q-row pixel unit PX is divided into alternating odd-numbered and even-numbered rows of pixel units PX. Two test signal lines (i.e., the first test signal line DOL and the second test signal line DEL) are provided to offer a first test signal DOS to the odd-numbered rows of pixel units PX and a second test signal DES to the even-numbered rows of pixel units PX for inspection testing. In an alternative embodiment, the same test signal line can be used to simultaneously provide the same test signal to the Q-row pixel unit PX for inspection testing. In another alternative embodiment, three test signal lines can be provided for each color sub-pixel unit to control the sub-pixels of the same color in each row of pixel units PX. That is, the first test signal line is connected to all first sub-pixels Sp1 in each row of pixel units PX for control, the second test signal line is connected to all second sub-pixels Sp2 in each row of pixel units PX for control, and the third test signal line is connected to all third sub-pixels Sp3 in each row of pixel units PX for control. Specifically, a first switching transistor STFT and a first connecting line are provided for all first sub-pixels Sp1 in each row of pixel units PX; a second switching transistor STFT and a second connecting line are provided for all second sub-pixels Sp2 in each row of pixel units PX; and a third switching transistor STFT and a third connecting line are provided for all third sub-pixels Sp3 in each row of pixel units PX. The first, second, and third switching transistors STFT are respectively connected to three test signal lines, and test signals are provided to the first sub-pixels Sp1, second sub-pixels Sp2, and third sub-pixels Sp3 through the first, second, and third connecting lines for inspection testing. In an alternative embodiment, in an LCD product using Dual-gate (DRD) driving technology, DY / DC / DM test signals can also be provided to the first sub-pixels Sp1, second sub-pixels Sp2, and third sub-pixels Sp3. In an alternative embodiment, six test signal lines may also be provided, namely, test signals DR+ and DR- with opposite polarities are provided for adjacent first sub-pixels Sp1, test signals DG+ and DG- with opposite polarities are provided for adjacent second sub-pixels Sp2, and test signals DB+ and DB- with opposite polarities are provided for adjacent third sub-pixels Sp3. This disclosure does not impose specific limitations in this regard.

[0136] The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL need to extend from the third side GP of the peripheral area PA along the second side SO to the fourth side GO opposite to the third side GP. Therefore, the lengths of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are too long, and at the points where the extension direction of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL changes (i.e., at the first triangular portion CR3 and / or the second corner portion CR2, such as...) Figure 8 The area within the dashed box is prone to electrostatic discharge (ESD), which can cause abnormal signal line function, burn out internal functional connection holes and traces of the display substrate, resulting in display defects and affecting product yield.

[0137] The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL change direction at the points where their extension directions change (i.e., at the first triangular portion CR3 and / or the second triangular portion CR2, such as...). Figure 8 The part within the dashed box has the following characteristics: Figure 6a A similar structure is shown. The first opening AP1, the second opening AP2, and the third opening AP3 are located at the second corner CR2 and the third corner CR3. This design avoids electrostatic discharge (ESD) affecting the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL at points where their extension direction changes (i.e., at the first corner CR3 and / or the second corner CR2), thus preventing signal line malfunctions, burning out internal functional connection holes and traces on the display substrate, and avoiding display defects, thereby improving product yield.

[0138] In some embodiments of this disclosure, the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL become inactive after the inspection and testing process, essentially floating signal lines. After the MDL process, during use, both the first test signal line DOL and the second test signal line DEL are connected to ground (GND), and the switch signal line SWL is connected to a low-level signal (VGL) to completely turn off the switching transistor STFT, preventing crosstalk between signals and avoiding abnormal screen display caused by potential signal coupling.

[0139] exist Figure 8 In the illustrated embodiment, the switching transistor STFT is located on the fourth side GO, opposite to the third side GP where the gate drive circuit GIC is located. Both the test signal line and the switching signal line SWL are led to this fourth side GO, thus avoiding wiring difficulties caused by the small space on the third side GP and effectively utilizing the space on the fourth side GO. Furthermore, this also achieves a uniform film thickness across the entire display substrate.

[0140] In another aspect, this disclosure provides a display device including a display substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the display substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0141] In another aspect, this disclosure provides a method for testing the display substrate described herein. Figure 9 A flowchart illustrating a method for testing a display substrate according to some embodiments of the present disclosure is shown. For example... Figure 9 As shown, the method includes an inspection and testing phase: during the inspection and testing phase, a test signal is provided to the one or more test signal lines through the at least one test signal terminal, the test signal being transmitted to a corresponding pixel driving circuit through the one or more test signal lines to test the display substrate; and after the inspection and testing phase, the at least one test signal terminal is bonded to a corresponding terminal of a driving circuit to provide a ground signal to the one or more test signal lines through the at least one test signal terminal during the display phase of the display substrate.

[0142] In some embodiments of this disclosure, the display substrate further includes: a switch signal terminal disposed on the same side as the at least one test signal terminal; a switch signal line extending in the peripheral region and connected to the switch signal terminal; and a plurality of switch transistors connected to the switch signal line, the one or more test signal lines, and a corresponding pixel driving circuit; wherein the method further includes: during the inspection and testing phase, providing a switch signal from the switch signal terminal to the plurality of switch transistors via the switch signal line, thereby controlling the one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during the inspection and testing phase; and after the inspection and testing phase, binding the switch signal terminal to a corresponding terminal of the driving circuit so that during the display phase of the display substrate, the driving circuit provides a low-level signal to the switch signal line via the switch signal terminal. The above description of embodiments of the invention has been given for purposes of illustration and description. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation considered. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein all terms, unless otherwise stated, are to have the broadest reasonable meaning. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the particular embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that those skilled in the art can make changes to the described embodiments without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended to be made public, whether or not they are expressly recited in the appended claims.

Claims

1. A display substrate having a display area and a peripheral area arranged around the display area, and comprising: Multiple grid lines extend along a first direction; Multiple data lines extend along the second direction; At least two driving circuits are located in the peripheral area and are configured to provide gate driving signals and source driving signals to multiple pixel driving circuits arranged in an array, including multiple rows and columns, located in the display area through the plurality of gate lines and the plurality of data lines, respectively. One or more test signal lines are located in the peripheral area and extend to a side opposite to a corresponding drive circuit of one of the at least two drive circuits. Each test signal line includes multiple branches at a point on that side, and each branch extends from that point to connect to the corresponding pixel drive circuit, thereby providing a test signal to the corresponding pixel drive circuit during the inspection test. as well as At least one test signal terminal is configured to provide the test signal to the one or more test signal lines, wherein the peripheral region includes a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, wherein the first side connects the third side and the fourth side, and the second side connects the third side and the fourth side; and The peripheral region includes a first corner located between the first side and the fourth side, a second corner located between the second side and the fourth side, a third corner located between the second side and the third side, and a fourth corner located between the first side and the third side. The at least two driving circuits include source driving circuits located on the first side of the peripheral region and configured to provide the source driving signal to the same column of pixel driving circuits located in the display area via corresponding data lines. The at least one test signal terminal includes a first test signal terminal disposed on the first side of the peripheral region near the first corner of the source drive circuit; and a second test signal terminal disposed on the first side of the peripheral region near the first corner of the source drive circuit. The one or more test signal lines include a first test signal line and a second test signal line; One end of the first test signal line is connected to the first test signal terminal, and extends from the first test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a first point on the second side located in the peripheral area; One end of the second test signal line is connected to the second test signal terminal, and extends from the second test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a second point located on the second side of the peripheral region; The first test signal line is configured to provide a first test signal from the first test signal terminal to the odd-column pixel driving circuit during inspection testing; and The second test signal line is configured to provide a second test signal from the second test signal terminal to the even-numbered column pixel driving circuit during inspection testing, wherein the first test signal line is divided into multiple branches at the first point on the second side of the peripheral region, each branch being connected to a corresponding data line to provide the first test signal to the same odd-numbered column pixel driving circuit during inspection testing; and The second test signal line branches into multiple branches at the second point on the second side of the peripheral region. Each branch is connected to a corresponding data line to provide the second test signal to the same even-numbered column pixel driving circuit during the inspection test. The data line connected to each branch of the first test signal line provides the same odd-numbered column pixel driving circuit with the first test signal from the first test signal terminal and the source driving signal from the source driving circuit. Each branch of the second test signal line is connected to a data line that provides the second test signal from the second test signal terminal and the source drive signal from the source drive circuit to the same even-numbered column pixel drive circuit, wherein all odd-numbered column pixel drive circuits are arranged in a mirror-symmetric manner about a straight line passing through the first point and perpendicular to the first side and the second side; and All even-numbered column pixel driving circuits are arranged in a mirror-symmetric manner with respect to a straight line passing through the second point and perpendicular to the first and second sides.

2. A display substrate having a display area and a peripheral area arranged around the display area, and comprising: Multiple grid lines extend along a first direction; Multiple data lines extend along the second direction; At least two driving circuits are located in the peripheral area and are configured to provide gate driving signals and source driving signals to multiple pixel driving circuits arranged in an array, including multiple rows and columns, located in the display area through the plurality of gate lines and the plurality of data lines, respectively. One or more test signal lines are located in the peripheral area and extend to a side opposite to a corresponding drive circuit of one of the at least two drive circuits. Each test signal line includes multiple branches at a point on that side, and each branch extends from that point to connect to the corresponding pixel drive circuit, thereby providing a test signal to the corresponding pixel drive circuit during the inspection test. as well as At least one test signal terminal is configured to provide the test signal to the one or more test signal lines. The surrounding area includes a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, wherein the first side connects the third side and the fourth side, and the second side connects the third side and the fourth side; and The surrounding area includes a first corner located between the first side and the fourth side, a second corner located between the second side and the fourth side, a third corner located between the second side and the third side, and a fourth corner located between the first side and the third side. The display substrate includes multiple sub-pixels arranged in an array in multiple rows and columns located in the display area. Each sub-pixel is configured in a one-to-one correspondence with a pixel driving circuit. The multiple sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The at least two driving circuits include a source driving circuit located on the first side of the peripheral region and configured to provide the source driving signal to the same column of pixel driving circuits located in the display area via corresponding data lines; The at least one test signal terminal includes a first sub-pixel test signal terminal disposed on the first side of the peripheral region near the first corner of the source driving circuit; a second sub-pixel test signal terminal disposed on the first side of the peripheral region near the first corner of the source driving circuit; and a third sub-pixel test signal terminal disposed on the first side of the peripheral region near the first corner of the source driving circuit. The one or more test signal lines include a first sub-pixel test signal line, a second sub-pixel test signal line, and a third sub-pixel test signal line; One end of the first sub-pixel test signal line is connected to the first sub-pixel test signal terminal, and extends from the first sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a first point located on the second side of the peripheral region; One end of the second sub-pixel test signal line is connected to the second sub-pixel test signal terminal, and extends from the second sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a second point located on the second side of the peripheral region; One end of the third sub-pixel test signal line is connected to the third sub-pixel test signal terminal, and extends from the third sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a third point located on the second side of the peripheral region; The first sub-pixel test signal line is configured to provide a first test signal from the first sub-pixel test signal terminal to all column pixel driving circuits corresponding to the first sub-pixel during the inspection test process. The second sub-pixel test signal line is configured to provide a second test signal from the second sub-pixel test signal terminal to all column pixel driving circuits corresponding to the second sub-pixel during the inspection test; and The third sub-pixel test signal line is configured to provide a third test signal from the third sub-pixel test signal terminal to all column pixel driving circuits corresponding to the third sub-pixel during the inspection test. The first sub-pixel test signal line is divided into multiple branches at the first point on the second side of the peripheral area, and each branch is connected to a corresponding data line to provide the first test signal from the first sub-pixel test signal terminal to the corresponding column pixel driving circuit of the first sub-pixel during the inspection test. The second sub-pixel test signal line is divided into multiple branches at the second point on the second side of the peripheral region. Each branch is connected to a corresponding data line to provide the second test signal from the second sub-pixel test signal terminal to the corresponding column of pixel driving circuits during the inspection test. The third sub-pixel test signal line is divided into multiple branches at the third point on the second side of the peripheral region. Each branch is connected to a corresponding data line to provide the third test signal from the third sub-pixel test signal terminal to the corresponding column of pixel driving circuits corresponding to the third sub-pixel during the inspection and testing process. The data line connected to each branch of the first sub-pixel test signal line provides the first test signal from the first sub-pixel test signal terminal and the source driving signal from the source driving circuit to the corresponding column of pixel driving circuits corresponding to the first sub-pixel. The data lines connected to each branch of the second sub-pixel test signal line provide the second test signal from the second sub-pixel test signal terminal and the source drive signal from the source drive circuit to the corresponding column of pixels driving circuits corresponding to the second sub-pixel; and The data line connected to each branch of the third sub-pixel test signal line provides the third test signal from the third sub-pixel test signal terminal and the source drive signal from the source drive circuit to the corresponding column pixel drive circuit of the third sub-pixel. The column pixel drive circuits corresponding to the first sub-pixel are arranged in a mirror symmetric arrangement about the straight line passing through the first point and perpendicular to the first side and the second side. The driving circuits for all column pixels corresponding to the second sub-pixel are arranged in a mirror-symmetric manner about a straight line passing through the second point and perpendicular to the first and second sides; and The driving circuits for all column pixels corresponding to the third sub-pixel are arranged in a mirror-symmetric manner about a straight line passing through the third point and perpendicular to the first side and the second side.

3. A display substrate having a display area and a peripheral area arranged around the display area, and comprising: Multiple grid lines extend along a first direction; Multiple data lines extend along the second direction; At least two driving circuits are located in the peripheral area and are configured to provide gate driving signals and source driving signals to multiple pixel driving circuits arranged in an array, including multiple rows and columns, located in the display area through the plurality of gate lines and the plurality of data lines, respectively. One or more test signal lines are located in the peripheral area and extend to a side opposite to a corresponding drive circuit of one of the at least two drive circuits. Each test signal line includes multiple branches at a point on that side, and each branch extends from that point to connect to the corresponding pixel drive circuit, thereby providing a test signal to the corresponding pixel drive circuit during the inspection test. as well as At least one test signal terminal is configured to provide the test signal to the one or more test signal lines. The surrounding area includes a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, wherein the first side connects the third side and the fourth side, and the second side connects the third side and the fourth side; and The surrounding area includes a first corner located between the first side and the fourth side, a second corner located between the second side and the fourth side, a third corner located between the second side and the third side, and a fourth corner located between the first side and the third side. The at least two driving circuits include a gate driving circuit located on the third side of the peripheral region and configured to provide the gate driving signal to the same row of pixel driving circuits located in the display area through corresponding gate lines; The at least one test signal terminal includes a first test signal terminal disposed on the first side of the peripheral region near the third corner of the gate driving circuit; and a second test signal terminal disposed on the first side of the peripheral region near the third corner of the gate driving circuit. The one or more test signal lines include a first test signal line and a second test signal line; One end of the first test signal line is connected to the first test signal terminal, and extends from the first test signal terminal along the second side from the third corner to the second corner, and extends along the fourth side from the second corner to a first point on the fourth side located in the peripheral area; One end of the second test signal line is connected to the second test signal terminal, and extends from the second test signal terminal along the second side from the third corner to the second corner, and extends along the fourth side from the second corner to a second point located on the fourth side of the peripheral region; The first test signal line is configured to provide a first test signal from the first test signal terminal to the odd-row pixel driving circuit during the inspection test; and The second test signal line is configured to provide a second test signal from the second test signal terminal to the even-numbered row pixel driving circuit during inspection testing, wherein the first test signal line is divided into multiple branches at the first point on the fourth side of the peripheral region, each branch being connected to a corresponding gate line to provide the first test signal to the same odd-numbered row pixel driving circuit during inspection testing; and The second test signal line is divided into multiple branches at the second point on the fourth side of the peripheral region. Each branch is connected to a corresponding gate line to provide the second test signal to the same even-numbered row pixel driving circuit during the inspection test. The gate line connected to each branch of the first test signal line provides the same odd-numbered row pixel driving circuit with the first test signal from the first test signal terminal and the gate driving signal from the gate driving circuit. Each branch of the second test signal line is connected to a gate line that provides the second test signal from the second test signal terminal and the gate drive signal from the gate drive circuit to the same even-numbered row pixel drive circuit, wherein all odd-numbered row pixel drive circuits are arranged in a mirror-symmetric manner about a straight line passing through the first point and perpendicular to the third and fourth sides; and All even-numbered row pixel driving circuits are arranged in a mirror-symmetric manner with respect to the straight line passing through the second point and perpendicular to the third and fourth sides.

4. The display substrate according to any one of claims 1 to 3 further includes a switch signal terminal, which is disposed on the same side as the at least one test signal terminal; A switch signal line that extends in the peripheral area and is connected to the switch signal terminal; as well as Multiple switching transistors are connected to the switching signal lines, the one or more test signal lines, and the corresponding pixel driving circuits; The plurality of switching transistors are configured to control one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during the inspection and testing process via a switching signal provided by the switching signal line.

5. The display substrate according to claim 4, further comprising: Substrate; A first conductive layer is located on the substrate and has a first opening therein; A gate insulating layer is located on the side of the first conductive layer away from the substrate and in the first opening; A passivation layer is located on the side of the gate insulating layer away from the substrate. The second and third openings extend through the gate insulating layer and the passivation layer; as well as A second conductive layer is located on the side of the passivation layer away from the substrate and covers the second opening and the third opening to contact the first conductive layer; Wherein, the orthographic projection of the first opening on the substrate and the orthographic projection of the second opening on the substrate do not overlap at least partially; The orthographic projection of the first opening on the substrate and the orthographic projection of the third opening on the substrate do not overlap at least partially; and The spacing between the two portions of the first conductive layer that are disconnected by the first opening is greater than or equal to 20 μm; Each of the one or more test signal lines includes a first part and a second part; The switch signal line consists of a first part and a second part; The first portion of each test signal line and the first portion of the switch signal line are located in the first conductive layer; and The second portion of each test signal line and the second portion of the switch signal line are located in the second conductive layer; and The first opening, the second opening, and the third opening are located at the first corner and the second corner, or at the second corner and the third corner.

6. A display device comprising a display substrate according to any one of claims 1 to 5, and one or more integrated circuits connected to the display substrate.

7. A method for testing a display substrate according to any one of claims 1 to 5, the method comprising an inspection and testing phase: During the inspection and testing phase, test signals are provided to the one or more test signal lines through the at least one test signal terminal. These test signals are then transmitted to the corresponding pixel driving circuits via the one or more test signal lines to test the display substrate. After the inspection and testing phase, the at least one test signal terminal is bonded to a corresponding terminal of a driving circuit so that during the display phase of the display substrate, the driving circuit provides a ground signal to the one or more test signal lines through the at least one test signal terminal.

8. The method according to claim 7, wherein, The display substrate further includes a switch signal terminal, which is disposed on the same side as the at least one test signal terminal; A switch signal line that extends in the peripheral region and connects to the switch signal terminal; and Multiple switching transistors are connected to the switching signal lines, the one or more test signal lines, and the corresponding pixel driving circuits; The method further includes: during the inspection and testing phase, providing a switching signal from the switching signal terminal to the plurality of switching transistors via the switching signal line, thereby controlling the one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during the inspection and testing phase; and After the inspection and testing phase, the switch signal terminal is bonded to the corresponding terminal of the driving circuit so that during the display phase of the display substrate, the driving circuit provides a low-level signal to the switch signal line through the switch signal terminal.

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