Liquid crystal panel timing drive circuit and display device

Abstract

Embodiments of the present application relate to a liquid crystal panel timing driving circuit and a display device. The circuit comprises a master control module, a power management module, a first level conversion module, and a second level conversion module. The first level conversion module is configured to receive a first group of input clock control signals and a first start scanning control signal from the master control module, and output a first group of clock signals and a first start scanning signal to the liquid crystal panel. The second level conversion module is configured to receive a second group of input clock control signals and a second start scanning control signal from the master control module, and output a second group of clock signals and a second start scanning signal to the liquid crystal panel. The power management module is configured to output clock levels to the first level conversion module and the second level conversion module. Embodiments of the present application realize the joint application of the first level conversion module and the second level conversion module, provide more clock signals and start scanning signals, and thus expand the application scenarios of the panel driving circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and in particular to a liquid crystal panel timing driving circuit and a display device. BACKGROUND

[0002] With the development of display panel technology, the timing of the row driving module (GOA, Gate on Array) of the panel varies greatly, and higher requirements are put forward for the level conversion chip (LSIC, Level shifter IC). For example, in order to display the H1 Line picture in the HSR mode, all odd rows (or even rows) need to be turned on and charged to L0 gray scale (or L255 gray scale) when the odd frame (or even frame) is needed, and all even rows (or odd rows) need to be turned on and charged to L255 gray scale (or L0 gray scale) when the even frame (or odd frame) is needed. In this way, the H1 Line picture in the HSR mode can be displayed in a special driving mode.

[0003] In order to adapt to diversified scanning driving modes, the traditional GOA module with only one frame start scanning signal STV is not enough, and at least two STVs are required. For example, STV1A and STV1B are used to control the start scanning of odd frames and even frames, respectively. Moreover, in order to improve the charging time, the GOA unit is often increased, and the number of corresponding clocks is also large, for example, generally 12 CK (clock) and above.

[0004] In summary, in order to drive various special panels, the LSIC (connected with the panel, providing the signals and timing required for the scanning of the GOA unit of the panel) needs to provide multiple STV channels and multiple CK channels, as well as LC, VSS, etc. The current single LSIC cannot provide more STV channels and CK channels, which limits the application scenarios of the panel driving circuit. SUMMARY

[0005] In view of this, in order to solve part or all of the above technical problems, the embodiments of the present application provide a liquid crystal panel timing driving circuit and a display device.

[0006] In a first aspect, the embodiments of the present application provide a liquid crystal panel timing driving circuit, which comprises a master control module, a power management module, a first level conversion module and a second level conversion module. The first level conversion module is connected with the master control module and the liquid crystal panel, and is configured to receive a first group of input clock control signals and a first start scanning control signal from the master control module, and output a first group of clock signals and a first start scanning signal to the liquid crystal panel. The second level conversion module is connected with the master control module and the liquid crystal panel, and is configured to receive a second group of input clock control signals and a second start scanning control signal from the master control module, and output a second group of clock signals and a second start scanning signal to the liquid crystal panel. The power management module is connected with the level conversion module, and is configured to output clock levels to the first level conversion module and the second level conversion module.

[0007] In a possible implementation, output ends of the first group of clock signals and the second group of clock signals are connected with clock input ends of the liquid crystal panel in turn and staggered.

[0008] In a possible implementation, the first level conversion module is configured to output each clock signal in the first group of clock signals in turn according to a preset clock output interval time at a first start time of the first group of clock control signals. The second level conversion module is configured to output each clock signal in the second group of clock signals in turn according to the clock output interval time at a second start time of the second group of clock control signals. The first start time is earlier than the second start time, and an interval time between the first start time and the second start time is half of the clock output interval time.

[0009] In a possible implementation, the clock output interval time is a period of the first group of clock control signals and the second group of clock control signals.

[0010] In a possible implementation, the first group of clock control signals comprises a first clock control signal and a second clock control signal, and the second group of clock control signals comprises a third clock control signal and a fourth clock control signal. The first level conversion module is configured to output a first level of each clock signal in the first group of clock signals in turn when a level of the first clock control signal reaches a first preset state, and output a second level of each clock signal in the first group of clock signals in turn when a level of the second clock control signal reaches a second preset state. The second level conversion module is configured to output a first level of each clock signal in the second group of clock signals in turn when a level of the third clock control signal reaches the first preset state, and output a second level of each clock signal in the second group of clock signals in turn when a level of the fourth clock control signal reaches the second preset state.

[0011] In a possible implementation, the first level conversion module or the second level conversion module is further configured to receive an input reset control signal from the master module, and output a reset signal to the liquid crystal panel.

[0012] In a possible implementation, the first level conversion module and the second level conversion module each comprise a row drive enable signal output end and a low potential voltage output end; any row drive enable signal output end and any low potential voltage output end comprised by the first level conversion module and the second level conversion module are connected to the liquid crystal panel to output a row drive enable signal and a low potential voltage to the liquid crystal panel.

[0013] In a possible implementation, the first level conversion module and the second level conversion module are integrated in the same level conversion chip; the level conversion chip is connected to the master module and the power management module.

[0014] In a possible implementation, the first level conversion module, the second level conversion module, and the power management module are integrated in the same power management chip, and the power management chip is connected to the master module.

[0015] In a second aspect, the embodiments of the present application provide a display device, comprising: a mainboard, a control board, and a liquid crystal panel, the mainboard being connected to the control board, and the control board being connected to the liquid crystal panel; the mainboard is provided with a master module comprised by the liquid crystal panel timing driving circuit described in the first aspect, and the control board is provided with a power management module, a first level conversion module, and a second level conversion module comprised by the liquid crystal panel timing driving circuit.

[0016] The liquid crystal panel timing driving circuit and the display device provided by the embodiments of the present application achieve the joint application of the first level conversion module and the second level conversion module by setting the master module, the power management module, the level conversion module, the first level conversion module, and the second level conversion module, controlling the timing of the first level conversion module and the second level conversion module by the master module, and providing the power required by the first level conversion module and the second level conversion module by the power management module, thereby providing more clock signals and start scanning signals, expanding the application scenarios of the panel driving circuit, and improving the flexibility of providing timing signals to the panel. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0019] One or more embodiments are illustrated by the pictures in the drawings corresponding thereto, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, unless otherwise specified. The drawings in the drawings do not constitute a proportional limitation.

[0020] Figure 1 A structural schematic diagram of a liquid crystal panel timing driving circuit is provided for the embodiments of the present application.

[0021] Figure 2 A signal flow conversion schematic diagram of two level conversion modules is provided for the embodiments of the present application.

[0022] Figure 3 A timing diagram of clock signals output by the two level conversion modules is provided for the embodiments of the present application.

[0023] Figure 4 A signal flow conversion schematic diagram of integrating the two level conversion modules into a level conversion chip is provided for the embodiments of the present application.

[0024] Figure 5A A delay schematic diagram of a start scan signal in the case of separating the two level conversion modules is provided for the embodiments of the present application.

[0025] Figure 5B A delay schematic diagram of a start scan signal in the case of integrating the two level conversion modules into the same chip is provided for the embodiments of the present application.

[0026] Figure 6 A signal flow conversion schematic diagram of integrating the two level conversion modules and a power management module into a power management chip is provided for the embodiments of the present application.

[0027] Figure 7 A structural schematic diagram of a display device is provided for the embodiments of the present application.

[0028] Reference signs:

[0029] 100 - liquid crystal panel timing driving circuit; 101 - master control module; 102 - power management module; 103 - first level conversion module; 104 - second level conversion module; 105 - level conversion chip; 106 - power management chip; 700 - display device; 701 - main board; 702 - control board; 703 - liquid crystal panel. DETAILED DESCRIPTION

[0030] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. The described embodiments are merely exemplary of the application, and it should be understood that the application can be carried out in various ways other than those specifically set forth herein. It should also be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to limit the scope of the application.

[0031] It should be understood that the terms "first", "second" and "third" and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are not to be construed as limited to the order in which they are discussed herein.

[0032] It is also to be understood that the terminology used herein is for the purpose of describing the embodiments only and is not intended to limit the scope of the application.

[0033] It should be understood that any of the components, data and structures described in the embodiments of the present application can be one or more unless specifically limited otherwise or clearly indicated to the contrary by the context in which they are described.

[0034] In addition, the term "and / or" in the present application is merely used to describe associated objects, and can exist in three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present application generally represents an "or" relationship between the front and rear associated objects.

[0035] It should be understood that the description of the various embodiments of the present application focuses on the differences between the various embodiments, and the same or similar parts can be referred to each other, and for brevity, will not be repeated.

[0036] The following description of at least one example embodiment is merely illustrative in nature and is in no way limiting of the application or its use nor the application and use thereof.

[0037] Techniques, circuitry, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered as part of the description, where appropriate.

[0038] It should be noted that like reference numerals and letters refer to like items in the following drawings, and thus, once an item is defined in one drawing, it need not be discussed further in subsequent drawings.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. To facilitate understanding of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0040] To meet the driving requirements of existing special panels such as HSR and to solve the problem of insufficient STV and CK channels in existing panel driving circuits, this application provides a liquid crystal panel timing driving circuit that can jointly control two level conversion modules and improve the scene adaptability of the driving circuit.

[0041] Figure 1 This is a schematic diagram of a timing driving circuit for a liquid crystal panel provided in an embodiment of this application. The circuit specifically includes: a main control module 101, a power management module 102, a first level conversion module 103, and a second level conversion module 104.

[0042] The main control module 101 can be any type of electronic device with logic operation capabilities. For example, the main control module 101 can be a SOC chip or a chip such as an MCU. Optionally, the main control module 101 can integrate timing control function (TCON), that is, this circuit can be applied to a TCON-less architecture (i.e., without using a separate TCONIC, the function of the TCON IC is integrated into the SOC).

[0043] The power management module 102, the first level conversion module 103, and the second level conversion module 104 can be separate chips, or they can be circuit boards composed of multiple discrete components, or any two or all of the three modules can be integrated into the same chip.

[0044] In this embodiment, as Figure 1 As shown, the first level conversion module 103 is connected to the main control module 101 and the LCD panel, and is used to receive a first set of clock control signals and a first start scan control signal from the main control module 101, and output the first set of clock signals and the first start scan signal to the LCD panel. The second level conversion module 104 is connected to the main control module 101 and the LCD panel, and is used to receive a second set of clock control signals and a second start scan control signal from the main control module 101, and output the second set of clock signals and the second start scan signal to the LCD panel.

[0045] The master control module 101 can generate clock control signals according to a certain logic, and output the clock control signals to the first level conversion module 103 and the second level conversion module 104. The signal input end of the first level conversion module 103 and the second level conversion module 104 receives the clock control signals and converts the level thereof. For example, the high level DVDD 3V3 is pulled up from 3.3V level to VGH (different panel voltages are different, such as 36V, etc.), and for example, the low level 0V input therein is lowered to VGL (different panel voltages are different, such as -10V, etc.). The master control module 101 usually inputs a square wave with a high level of 3.3V and a low level of 0V to the first level conversion module 103 and the second level conversion module 104, and the first level conversion module 103 and the second level conversion module 104 pull up the square wave to a high level of VGH and a low level of VGL.

[0046] The first group of clock control signals and the second group of clock control signals are output by the master control module 101 to the first level conversion module 103 and the second level conversion module 104, and the two groups of signals are used to control the timing of the clock signal. For example, for a level conversion module with 2-in-6-out, it can receive a group of clock control signals composed of CPV1 and CPV2.

[0047] The first group of clock signals and the second group of clock signals are used to provide clock to the row scan driving module (for example, GOA) on the liquid crystal panel, so that the liquid crystal panel can drive each row of pixels to display the corresponding color according to the clock.

[0048] The first group of clock signals and the second group of clock signals can be input to the row scan driving module included in the liquid crystal panel in a set order. For example, the first group of clock signals is output through the six ports CK1-CK6 included in the first level conversion module 103, and the second group of clock signals is output through the six ports CK1-CK6 included in the second level conversion module 104, and the two groups of ports can be connected to the CLK1-CLK6 ports and the CLK7-CLK12 ports on the liquid crystal panel, respectively.

[0049] The first start scan control signal and the first start scan signal, and the second start scan control signal and the second start scan signal can be in a one-to-one relationship, such as Figure 2As shown, the master control module 101 inputs the first start scanning control signal STV1A_IN and the second start scanning control signal STV1B_IN to the first level conversion module 103 and the second level conversion module 104 respectively, and outputs the first start scanning signal STV1A and the second start scanning signal STV1B. The start scanning signal is used to control the start scanning time of a frame of image, and in the case of needing to control the odd frame and the even frame respectively, two start scanning signals STV1A and STV1B can be outputted.

[0050] In the embodiment, the power management module 102 is connected with the level conversion module, and is used to output the clock level to the first level conversion module 103 and the second level conversion module 104.

[0051] The clock level is the size of the high and low level of the clock signal outputted by the level conversion module, for example, the above-mentioned VGH and VGL. The power management module 102 can input the power supply voltage externally, and normally work in the case of writing the necessary register, and output various voltages for the work of other modules. That is, the level conversion module provides the DVDD3V3 signal and the VGL, VGH signal and the like.

[0052] Generally, the level conversion module can provide the AVDD (Analog Voltage Driver), HAVDD (High-Voltage Analog Voltage Driver), DVDD1V8 (1.8V digital power voltage), DVDD1V9 (1.9V digital power voltage) and the like voltage to the liquid crystal panel, and provide the GM1 / GM2 / GM3......GM13 / GM14 and the like (assuming that 14 GM nodes are needed) Gamma voltage and the reference voltage VCOM (VCOM1 / VCOM2) and the like voltage for the data driving module (source driver) on the liquid crystal panel. That is, the level conversion module integrates the functions of the PMIC (Power Management IC) and the GMIC (Gamma Management IC) two chips.

[0053] The liquid crystal panel timing driving circuit provided by the embodiment of the application realizes the joint application of the first level conversion module and the second level conversion module, provides more clock signals and start scanning signals, thereby expanding the application scene of the panel driving circuit and improving the flexibility of providing the timing signal to the panel.

[0054] In some optional implementations of the embodiment, the output ends of the first group of clock signals and the output ends of the second group of clock signals are staggered and connected to the clock input ends of the liquid crystal panel in turn.

[0055] The staggered connection refers to being connected to the first clock signal output end of the first level conversion module 103, the first clock signal output end of the second level conversion module 104, the second clock signal output end of the first level conversion module 103, the second clock signal output end of the second level conversion module 104, and so on in turn according to the arrangement order of the clock input ends of the liquid crystal panel. Figure 2 As shown in the figure, the first level conversion module 103 and the second level conversion module 104 both include CK1-CK6 ports, which are staggered and connected to the 12 clock input end ports of the liquid crystal panel and output 12 clock signals CLK1-CLK12 in turn according to a preset timing sequence.

[0056] As shown in the figure, the first level conversion module 103 and the second level conversion module 104 both include CK1-CK6 ports, which are staggered and connected to the 12 clock input end ports of the liquid crystal panel and output 12 clock signals CLK1-CLK12 in turn according to a preset timing sequence. Figure 3 As shown in the figure, the first level conversion module 103 and the second level conversion module 104 both include CK1-CK6 ports, which are staggered and connected to the 12 clock input end ports of the liquid crystal panel and output 12 clock signals CLK1-CLK12 in turn according to a preset timing sequence.

[0057] The embodiment can make the first level conversion module and the second level conversion module continuously output clock signals according to the same signal period by staggering and connecting the output ends of the two groups of clock signals to the clock input ends of the liquid crystal panel in turn, and only needs to adjust the starting output time of the first group of clock signals and the second group of clock signals, thereby helping to stably output a larger number of clock signals to the liquid crystal panel.

[0058] In some optional implementations of the embodiment, the first level conversion module 103 is configured to:

[0059] At the first starting time of the first group of clock control signals, output each clock signal in the first group of clock signals in turn according to a preset clock output interval time.

[0060] The second level conversion module 104 is configured to:

[0061] At the second starting time of the second group of clock control signals, output each clock signal in the second group of clock signals in turn according to a clock output interval time.

[0062] The first starting time is earlier than the second starting time, and the interval time between the first starting time and the second starting time is half of the clock output interval time.

[0063] As shown in the figure, CPV1 and CPV2 are the first group of clock control signals, and CPV3 and CPV4 are the second group of clock control signals. t1 is the first starting time, and after the first starting time, the CK port of the first level conversion module 103 outputs CLK1, CLK3, CLK5, CLK7, CLK9 and CLK11 in turn. The interval time between every two adjacent CLK signals is the same. t2 is the second starting time, and after the second starting time, the CK port of the second level conversion module 104 outputs CLK2, CLK4, CLK6, CLK8, CLK10 and CLK12 in turn. Figure 3

[0064] The timing of the first group of clock signals and the second group of clock signals provided by the embodiment realizes the combination of the two level conversion modules, and the two level conversion modules output the clock signals to the liquid crystal panel in turn and alternately, so that the circuit can accurately control the scanning timing of various liquid crystal panels.

[0065] In some optional implementation manners of the embodiment, the clock output interval time is one period of the first group of clock control signals and the second group of clock control signals.

[0066] As shown in the figure, the clock output interval time is one period of CPV1, CPV2, CPV3 and CPV4. The interval time between t1 and t2 is half a period of CPV1 and CPV2. Figure 3 Based on the period of the clock control signal to set the output interval time of the clock signal, the scanning timing of the liquid crystal panel can be more accurately controlled.

[0067] In some optional implementation manners of the embodiment, the first group of clock control signals includes a first clock control signal and a second clock control signal, and the second group of clock control signals includes a third clock control signal and a fourth clock control signal. As shown in the figure, CPV1 and CPV2 are the first clock control signal and the second clock control signal, and CPV3 and CPV4 are the third clock control signal and the fourth clock control signal.

[0068] Figure 2 Figure 3

[0069] The first level conversion module 103 is configured to:

[0070] When the level of the first clock control signal reaches a first preset state, the first level conversion module 103 outputs the first level of each clock signal in the first group of clock signals in turn; and when the level of the second clock control signal reaches a second preset state, the first level conversion module 103 outputs the second level of each clock signal in the first group of clock signals in turn.

[0071] ​​​​Specifically, the first preset state, the second preset state, the first level and the second level can be set according to requirements. For example, as shown in FIG. 8, the first preset state can be a state of changing from a low level to a high level, that is, a rising edge, and the second preset state is also a rising edge. The first level is a high level, and the second level is a low level. That is, the rising edge of CPV1, the high level of each CLK signal is output, and then, when the rising edge of CPV2 is reached, the low level of each CLK signal is output. Thus, the output of the CLK signal is controlled according to the CPV1 and CPV2 signals. Figure 3

[0072] The second level conversion module 104 is configured to:

[0073] When the level of the third clock control signal reaches the first preset state, the first level of each clock signal in the second group of clock signals is sequentially output; and when the level of the fourth clock control signal reaches the second preset state, the second level of each clock signal in the second group of clock signals is sequentially output.

[0074] The timing of the clock signal output by the second level conversion module 104 is as shown in FIG. 9. The rising edge of CPV3, the high level of each CLK signal is output, and then, when the rising edge of CPV4 is reached, the low level of each CLK signal is output. Thus, the output of the CLK signal is controlled according to the CPV3 and CPV4 signals. Figure 3

[0075] It should be noted that, Figure 3 The timing diagram shown in FIG. 9 is only an example. The first preset state and the second preset state described above can also be set as falling edges, and the first level and the second level can be opposite to the levels shown in FIG. 9. Figure 3

[0076] The embodiment sets the trigger timing of the output clock signal and sets the duration of the high and low levels of the clock signal, so as to accurately control the timing of the clock signal output of the two level conversion units.

[0077] ​​​Optionally, the number of clock signal output terminals included in the first level conversion module 103 and the second level conversion module 104 can be greater than the number of clock signal input terminals of the liquid crystal panel, i.e. some clock signal output terminals can not be connected to the liquid crystal panel. For example, the first level conversion module 103 and the second level conversion module 104 can each include 10 clock signal output terminals, i.e. CK1-CK10. In use, CK1-CK6 included in each level conversion module can be connected to the liquid crystal panel to output 12 channels of clock signals. In addition, the required clock signal timing can be output in cooperation with the register setting of the level conversion module (e.g. set to 6 phase output). When the level conversion module is set to 6 phase clock output, the other 4 CK channels output VGL low level. Since these CK channels are not connected to the panel, they do not affect the waveform to the panel. The unused CK ports can be used as reserved ports to improve the scalability of the circuit.

[0078] In some optional implementations of the present embodiment, the first level conversion module 103 or the second level conversion module 104 is further configured to receive an input reset control signal from the master module 101 and output a reset signal to the liquid crystal panel.

[0079] The reset signal is used to reset various signals input to the panel at the end of the display stage of a frame of image, so as to wait for the input of the next frame of data. In the present embodiment, the STV0 input port in the first level conversion module 103 or the second level conversion module 104 can be used to receive the reset control signal STV0_IN input by the master module 101 and output the reset signal STV0. As shown in Figure 2 The STV0_IN signal can be input to the first level conversion module 103, and the first level conversion module 103 outputs the STV0 signal.

[0080] In some types of panels, at least three STV signals are usually required to control the scanning timing of a frame of image. For example, in order to light up the special picture of H1Line in HSR mode, STV1A and STV1B are required to control the start scanning of odd frames and even frames, respectively. In addition, a reset signal STV0 at the end of a frame is also required. Therefore, the present embodiment combines the first start scanning signal and the second start scanning signal to provide three STV signals to the liquid crystal panel, so as to support the driving timing of special types of panels and expand the application range of the liquid crystal driving circuit.

[0081] In some optional implementations of the embodiment, the first level conversion module 103 and the second level conversion module 104 each include a row drive enable signal output end and a low potential voltage output end. The row drive enable signal output end can output a row drive enable signal LC, and the low potential voltage output end is configured to output a low potential voltage VSS required by the liquid crystal panel.

[0082] The row drive enable signal output end and the low potential voltage output end included in the first level conversion module 103 and the second level conversion module 104 are connected to the liquid crystal panel, and are configured to output the row drive enable signal and the low potential voltage to the liquid crystal panel.

[0083] As shown in Figure 2 The row drive enable control signal LC_IN output by the host module 101 can be input to the first level conversion module 103, and the first level conversion module 103 outputs the row drive enable signal LC1 / LC2 and the low potential voltage VSS1 / VSS2.

[0084] The row drive enable signal output end and the low potential voltage output end included in the first level conversion module 103 and the second level conversion module 104 are connected to the liquid crystal panel, and are configured to output the row drive enable signal and the low potential voltage to the liquid crystal panel.

[0085] In some optional implementations of the embodiment, the first level conversion module 103 and the second level conversion module 104 are integrated in the same level conversion chip 105, and the level conversion chip is connected to the host module 101 and the power management module 102.

[0086] As shown in Figure 4 The first level conversion module 103 and the second level conversion module 104 are integrated in the level conversion chip 105, the level conversion chip 105 receives CPV1, CPV2, CPV3, CPV4, STV1A_IN, STV1B_IN, LC_IN, and STV0_IN input by the host module 101, and outputs clock signals CK1-CK12, start scanning control signals STV1A and STV1B, a reset control signal STV0, row drive enable signals LC1 / LC2, and low potential voltages VSS1 / VSS2. In addition, the host module 101 and the level conversion chip 105, and the power management module 102 can be connected in communication through a bus, so as to realize communication between the host module 101 and the level conversion chip 105 and the power management module 102. Figure 4As shown, the bus can be an IIC (Inter-Integrated Circuit) bus, including two communication lines of SDA (data line) and SCL (clock line).

[0087] The power management module 102 can receive an externally input power supply voltage (12V) and output DVDD1V8, DVDD1V9, AVDD, GM1-GM14, VCOM1 / VCOM2, and the like.

[0088] The first level conversion module and the second level conversion module are integrated in the same level conversion chip, which can make the circuit structure more simple, thereby helping to simplify the design and manufacturing process of the circuit and reduce the cost. Longer wires may cause problems such as equivalent capacitance when transmitting signals, causing signal transmission delay. The embodiment can simplify the wiring of discrete component layout. Since the level conversion chip has a small size, the signal delay between the two starting scan control signals caused by wire connection can be reduced. As shown in Figure 5A and Figure 5B As shown, in the case of discrete components, there is a delay (T_gap) of about 1 microsecond between STV1A and STV1B. After integrating the first level conversion module and the second level conversion module in the level conversion chip, the delay between STV1A and STV1B is reduced to 0.

[0089] In some optional implementations of the embodiment, the first level conversion module 103, the second level conversion module 104, and the power management module 102 are integrated in the same power management chip 106, and the power management chip 106 is connected with the master control module 101.

[0090] As shown in Figure 6 The power management chip 106 includes the first level conversion module 103, the second level conversion module 104, and the power management module 102. The external part of the power management chip 106 is connected with the master control module 101 and the liquid crystal panel, and the internal connection mode can refer to the Figure 1 、 Figure 2 corresponding embodiment. The power management chip 106 receives CPV1, CPV2, CPV3, CPV4, STV1A_IN, STV1B_IN, LC_IN, and STV0_IN input by the master control module 101, and outputs clock signals CK1-CK12, starting scan control signals STV1A and STV1B, reset control signal STV0, row drive enable signals LC1 / LC2, low potential voltage VSS1 / VSS2, and DVDD1V8, DVDD1V9, AVDD, GM1-GM14, VCOM1 / VCOM2, and the like.

[0091] This embodiment integrates the first level conversion module, the second level conversion module, and the power management module into a single power management chip, which further simplifies the wiring of discrete components and reduces signal transmission delay caused by wiring. It also makes the circuit structure simpler, thereby simplifying the circuit design and manufacturing process and reducing costs.

[0092] Figure 7 This is a schematic diagram of the structure of a display device 700 provided in an embodiment of this application, as shown below. Figure 7 As shown, the display device 700 includes: a main board 701, a control board 702, and a liquid crystal panel 703. The main board is connected to the control board, and the control board is connected to the liquid crystal panel. The main board and the control board can be connected via a flat cable containing multiple pins. The control board and the liquid crystal panel can be connected via an FFC cable. Typically, the control board is connected to the X-PCB board (e.g., PCB) on the liquid crystal panel via the FFC cable. Figure 7 The XLL, XLR, XRL, and XRR connections in the code.

[0093] The motherboard is equipped with the main control module 101, which is included in the above-mentioned LCD panel timing drive circuit. The control board is equipped with the power management module 102, the first level conversion module 103, and the second level conversion module 104, which are included in the above-mentioned LCD panel timing drive circuit.

[0094] In this embodiment, the main control module 101 can be a System-on-a-Chip (SoC) or a microcontroller (MCU) or other chip with logic operation functions. The main control module 101 provides timing signals and control signals to the power management module 102, the first level conversion module 103, and the second level conversion module 104. The LCD panel displays the signals output by the control board.

[0095] The signals output by the power management module 102, the first level conversion module 103, and the second level conversion module 104 can be output to the LCD panel through the interface between the control board and the LCD panel.

[0096] Optionally, the first level conversion module 103 and the second level conversion module 104 can be integrated into the same level conversion chip 105, which, along with the power management module 102, is mounted on the control board. Alternatively, the first level conversion module 103, the second level conversion module 104, and the power management module 102 can all be integrated into the same power management chip 106, which, along with the power management module 102, is mounted on the control board.

[0097] The display device provided by the embodiment of the present application realizes the joint application of the first level conversion module and the second level conversion module by applying the liquid crystal panel timing driving circuit, more clock signals and start scanning signals are provided, thereby expanding the application scene of the display device and improving the flexibility of the application of the display device.

[0098] Those skilled in the art will further appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, various aspects of examples have been described herein in terms of their functionality. Whether such functionality is implemented in hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation should not be interpreted as a departure from the scope of the present application.

[0099] The steps of the circuit or algorithm described in connection with the embodiments disclosed herein can be embodied in hardware, software executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), a memory, a read only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0100] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The steps, processes, and operations described herein are not to be construed as necessarily requiring their occurrence in the particular order in which they are described unless expressly specified as being ordered. It is also to be understood that additional or alternative steps can be employed.

[0101] The above description is merely that of specific embodiments of the present application, and thus is not intended to limit the present application. Various modifications to these embodiments can be apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Accordingly, the present application is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A timing driving circuit for a liquid crystal panel, characterized in that, The circuit comprises a master module, a power management module, a first level conversion module and a second level conversion module; The first level conversion module is connected with the master module and a liquid crystal panel, and is configured to receive a first group of input clock control signals and a first start scanning control signal from the master module, and output a first group of clock signals and a first start scanning signal to the liquid crystal panel; The second level conversion module is connected with the master module and the liquid crystal panel, and is configured to receive a second group of input clock control signals and a second start scanning control signal from the master module, and output a second group of clock signals and a second start scanning signal to the liquid crystal panel; The power management module is connected with the level conversion module, and is configured to output a clock level to the first level conversion module and the second level conversion module; The first group of clock control signals comprises a first clock control signal and a second clock control signal, and the second group of clock control signals comprises a third clock control signal and a fourth clock control signal; The first level conversion module is configured to: output a first level of each clock signal in the first group of clock signals in sequence when a level of the first clock control signal reaches a first preset state, and output a second level of each clock signal in the first group of clock signals in sequence when a level of the second clock control signal reaches a second preset state; The second level conversion module is configured to: output a first level of each clock signal in the second group of clock signals in sequence when a level of the third clock control signal reaches the first preset state, and output a second level of each clock signal in the second group of clock signals in sequence when a level of the fourth clock control signal reaches the second preset state.

2. The circuit of claim 1, wherein, Output ends of the first group of clock signals and output ends of the second group of clock signals are connected with clock input ends of the liquid crystal panel in sequence and alternately.

3. The circuit of claim 2, wherein, The first level conversion module is configured to: output each clock signal in the first group of clock signals in sequence at a first start moment of the first group of clock control signals according to a preset clock output interval time; The second level conversion module is configured to: output each clock signal in the second group of clock signals in sequence at a second start moment of the second group of clock control signals according to the clock output interval time, wherein the first start moment is earlier than the second start moment, and an interval time between the first start moment and the second start moment is half of the clock output interval time.

4. The circuit of claim 3, wherein, The clock output interval time is one period of the first group of clock control signals and the second group of clock control signals.

5. The circuit of claim 1, wherein, The first level conversion module or the second level conversion module is further configured to receive a reset control signal input from the master module, and output a reset signal to the liquid crystal panel.

6. The circuit of claim 5, wherein, The first level conversion module and the second level conversion module each comprise a row drive enable signal output end and a low potential voltage output end. Any row drive enable signal output end and any low potential voltage output end included in the first level conversion module and the second level conversion module are connected with the liquid crystal panel to output row drive enable signal and low potential voltage to the liquid crystal panel.

7. The circuit of claim 1, wherein, The first level conversion module and the second level conversion module are integrated in the same level conversion chip; the level conversion chip is connected with the main control module and the power management module.

8. The circuit of claim 1, wherein, The first level conversion module, the second level conversion module and the power management module are integrated in the same power management chip; the power management chip is connected with the main control module.

9. A display device, characterized by comprising: Comprise: A main board, a control board and a liquid crystal panel, the main board is connected with the control board, and the control board is connected with the liquid crystal panel; The main control module included in the liquid crystal panel timing driving circuit of any one of claims 1-8 is arranged on the main board, and the power management module, the first level conversion module and the second level conversion module included in the liquid crystal panel timing driving circuit are arranged on the control board.

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