Storage unit, data read-write circuit, memory and preparation method thereof

Abstract

The present disclosure relates to a storage unit, a data read-write circuit, a memory and a preparation method thereof, and relates to the field of integrated circuit design and manufacturing technology. The storage unit includes a horizontal semiconductor layer extending along a first direction, and a write bit line, a write transistor, a read transistor, and a read word line arranged in sequence along the first direction on the horizontal semiconductor layer; the write bit line and the read word line extend along a second direction intersecting the first direction; the read transistor extends along a third direction perpendicular to the first direction and the second direction and penetrates the horizontal semiconductor layer, and the source line, the read transistor, and the read bit line are arranged along the third direction. At least it can support the simultaneous photolithography of multi-layer stacked storage units while reducing the area overhead of single-layer storage units.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a storage unit, a data read-write circuit, a memory and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the market has higher and higher requirements on the capacity, preparation cost, and data transmission rate of storage products, and the three-dimensional stacked storage structure has become an important development direction.

[0003] Two-dimensional memory arrays pose great challenges to processes and manufacturing equipment in terms of miniaturization. Stacking multiple layers of two-dimensional memory cell arrays in the vertical direction has become a technical development direction to achieve high-density storage. Summary of the invention

[0004] Based on this, the present disclosure provides a storage unit, a data read and write circuit, a memory and a preparation method thereof, which can at least reduce the area overhead of a single-layer storage unit while supporting simultaneous photolithography of multi-layer stacked storage units, thereby reducing the volume of the prepared product while ensuring that the storage capacity is not reduced, and reducing the process complexity and cost of the prepared product.

[0005] According to various embodiments of the present disclosure, a first aspect provides a storage unit, comprising: a source line, a read bit line, a write word line, a horizontal semiconductor layer extending along a first direction, and a write bit line, a write transistor, a read transistor, and a read word line arranged in sequence along the first direction on the horizontal semiconductor layer; the write bit line and the read word line extend along a second direction intersecting with the first direction; the read transistor extends along a third direction perpendicular to the first direction and the second direction and penetrates the horizontal semiconductor layer, the read transistor comprises a vertical gate dielectric layer and a vertical semiconductor layer extending along the third direction, the vertical gate dielectric layer is located between the vertical semiconductor layer and the horizontal semiconductor layer; the write transistor extends along the first direction and surrounds a portion of the horizontal semiconductor layer; the horizontal semiconductor layer and the write word line are arranged along the second direction; the source line, the read transistor, and the read bit line are arranged along the third direction.

[0006] In the memory cell in the above embodiment, a write transistor is arranged to extend along a first direction and surround a portion of the horizontal semiconductor layer, a read transistor is extended along a third direction and penetrates the horizontal semiconductor layer, and a write bit line, a write transistor, a read transistor, and a read word line are arranged in sequence along the first direction, the horizontal semiconductor layer and the write word line are arranged in the second direction, and the source line, the read transistor, and the read bit line are arranged in sequence along the third direction. Two control gates are formed by using a portion of the vertical gate dielectric layer, the vertical semiconductor layer, and a portion of the vertical gate dielectric layer arranged in sequence along the first direction, thereby effectively reducing the volume of the two control gates, facilitating the memory cell array in the same layer, the memory cells adjacent along the second direction share the write bit line and the read word line, and the memory cells adjacent along the third direction share the write word line, thereby supporting the simultaneous lithography of multi-layer stacked memory cells, and reducing the process complexity and cost of manufacturing products; since one of the two control gates is connected to one end of the write transistor and forms a storage node, and the other control gate is connected to the read word line for easy reading of data, the area occupied by the capacitor is relatively reduced, thereby reducing the area overhead of a single-layer memory cell, and reducing the volume of the manufactured product while ensuring that the storage capacity is not reduced.

[0007] According to some embodiments, the vertical gate dielectric layer extends along a third direction and circumferentially surrounds the vertical semiconductor layer, thereby forming an annular vertical gate dielectric layer extending in a direction perpendicular to the substrate. The vertical semiconductor layer surrounded by the vertical gate dielectric layer is used as a common vertical semiconductor layer for the two gates, thereby effectively reducing the volume of the two control gates and reducing the process complexity and cost of manufacturing products. Since one of the two control gates is connected to one end of the write transistor to form a storage node, and the other control gate is connected to the read word line to facilitate reading of data, the area occupied by the capacitor is relatively reduced, thereby reducing the area overhead of the single-layer storage unit, and can reduce the volume of the manufactured product while ensuring that the storage capacity is not reduced.

[0008] According to some embodiments, the write transistor includes a ring-gate dielectric layer, a first source / drain contact region and a second source / drain contact region, the ring-gate dielectric layer extends along a first direction and circumferentially surrounds a portion of the horizontal semiconductor layer; the write word line extends along a third direction and is located on a side of the ring-gate dielectric layer away from the horizontal semiconductor layer along the second direction; the first source / drain contact region is located on the horizontal semiconductor layer between the write bit line and the ring-gate dielectric layer; the second source / drain contact region is located on the horizontal semiconductor layer between the ring-gate dielectric layer and the read transistor. By setting the write transistor to include a first source / drain contact region, a horizontal semiconductor layer, and a second source / drain contact region arranged in sequence along the first direction, a ring-gate dielectric layer extending along the first direction and circumferentially surrounding a portion of the horizontal semiconductor layer is formed to prepare a ring-gate transistor with a horizontal channel, which facilitates the simultaneous preparation of write word lines of adjacent storage cells along a direction perpendicular to the substrate in the same process step, thereby reducing the complexity and cost of the preparation process.

[0009] According to some embodiments, the write transistor also includes a ring gate electrode layer, which is located between the write word line and the ring gate dielectric layer and circumferentially surrounds the ring gate dielectric layer, thereby facilitating the simultaneous preparation of the ring gate electrode layer of adjacent storage cells along a direction perpendicular to the substrate in the same process step, and the simultaneous preparation of the write word lines of adjacent storage cells along a direction perpendicular to the substrate in the same process step, thereby reducing the complexity and cost of the preparation process.

[0010] According to some embodiments, the read transistor includes a first source / drain contact region and a second source / drain contact region, wherein the first source / drain contact region is located on a horizontal semiconductor layer and a vertical semiconductor layer between a read bit line; and the second source / drain contact region is located on a vertical semiconductor layer between a horizontal semiconductor layer and a source line, so as to facilitate the preparation of a vertical channel ring-gate transistor, support simultaneous photolithography of multi-layer stacked memory cells, and facilitate the simultaneous preparation of vertical semiconductor layers and vertical gate dielectric layers of adjacent memory cells along a direction perpendicular to the substrate in the same process step, thereby reducing the complexity and cost of the preparation process.

[0011] According to various embodiments of the present disclosure, a second aspect provides a memory, comprising at least one layer of memory array; one layer of memory array comprises a plurality of memory cells as described in any of the foregoing embodiments, which are arranged in an array with a first direction as a row direction and a second direction as a column direction; at least one layer of memory array is arranged along a third direction; memory cells adjacent along the first direction share a read word line extending along the second direction and a write bit line extending along the second direction; memory cells adjacent along the third direction share a write word line extending along the third direction, and support simultaneous photolithography of multi-layer stacked memory cells, so as to facilitate simultaneous preparation of vertical semiconductor layers and vertical gate dielectric layers of adjacent memory cells along a direction perpendicular to the substrate in the same process step, thereby reducing the complexity and cost of the preparation process.

[0012] According to various embodiments of the present disclosure, a third aspect provides a data read-write circuit, including a write transistor and a read transistor, wherein the write transistor is configured as follows: a first end is connected to a write bit line, and a control end is connected to a write word line; and the read transistor is configured as follows: a first control end is connected to a second end of the write transistor, a second control end is connected to a read word line, a first end is connected to a read bit line, and a second end is connected to a source line, wherein the read transistor is a ring-gate transistor with a vertical channel, and the read transistor includes a vertical gate dielectric layer and a vertical semiconductor layer extending in a direction perpendicular to the substrate, the vertical gate dielectric layer surrounds the outer wall of the vertical semiconductor layer, and the vertical gate dielectric layer is located between the vertical semiconductor layer and the horizontal semiconductor layer. By setting the second end of the write transistor to be connected to the first control end of the read transistor and forming a storage node, setting the second control end of the read transistor to be connected to the read word line, setting the first end of the read transistor to be connected to the read bit line and the second end to the source line, when the write transistor is turned on by the write word line, data is written to the storage node via the write bit line; when the read transistor is turned on by the read word line, data is read from the storage node via the read bit line. The area occupied by the capacitor is relatively reduced, thereby reducing the area cost of the single-layer storage unit, and can reduce the volume of the manufactured product while ensuring that the storage capacity is not reduced.

[0013] According to various embodiments of the present disclosure, a fourth aspect provides a three-dimensional data read-write circuit, comprising at least one layer of circuit array; one layer of circuit array comprises a plurality of data read-write circuits as described in any of the above embodiments arranged in an array with a first direction as a row direction and a second direction as a column direction; at least one layer of circuit array is arranged along a third direction; adjacent data read-write circuits along the first direction share a read word line and a write bit line; adjacent data read-write circuits along the third direction share a write word line, wherein the read transistor is a ring-gate transistor with a vertical channel, the read transistor comprises a vertical gate dielectric layer and a vertical semiconductor layer extending along a vertical substrate direction, the vertical gate dielectric layer surrounds the outer side wall of the vertical semiconductor layer, and the vertical gate dielectric layer is located between the vertical semiconductor layer and the horizontal semiconductor layer. Thus, it can support the simultaneous lithography of multi-layer stacked storage units, reducing the process complexity and cost of manufacturing products; since one of the two control gates is connected to one end of the write transistor and forms a storage node, and the other control gate is connected to the read word line to facilitate reading data, the area occupied by the capacitor is relatively reduced, thereby reducing the area overhead of the single-layer storage unit, and can reduce the volume of the manufactured product while ensuring that the storage capacity is not reduced.

[0014] According to various embodiments of the present disclosure, a fifth aspect provides a memory preparation method, including:

[0015] A substrate is provided, wherein the substrate comprises a stack, wherein the stack comprises sacrificial layers and semiconductor material layers alternately stacked in sequence in a direction away from the substrate, and wherein the stack comprises a plurality of first grooves arranged in an array with a first direction as a row direction and a second direction as a column direction, exposing a portion of the substrate;

[0016] forming an isolation layer that fills the first groove and covers the top surface of the top semiconductor material layer of the stack;

[0017] forming a first through hole in the stack to expose a portion of the substrate and a portion of the semiconductor material layer, wherein the first through hole is used to define a write transistor;

[0018] After forming a write transistor surrounding a portion of the semiconductor material layer in each semiconductor material layer through the first through hole, a write word line filling the first through hole is formed;

[0019] forming a second groove in the stacked layer to expose a portion of the substrate, the second groove being used to define a read transistor;

[0020] After forming a vertical gate dielectric layer on the inner wall of the second groove, a vertical semiconductor layer filling the second groove is formed, a portion of the semiconductor material layer extending along the second direction is used to form a write bit line, a portion of the semiconductor material layer extending along the second direction is used to form a read word line, the vertical gate dielectric layer and the vertical semiconductor layer are used to jointly form a read transistor, so as to obtain a write bit line, a write transistor, a read transistor, and a read word line arranged in sequence along the first direction; a portion of the semiconductor material layer extending along the first direction is used to form a horizontal semiconductor layer; the first direction and the second direction intersect.

[0021] The memory preparation method in the above-mentioned embodiment forms a stack of sacrificial layers and semiconductor material layers alternately stacked in a direction away from the substrate on a substrate, firstly forms a plurality of first grooves in the stack that are arranged in an array with a first direction as a row direction and a second direction as a column direction, exposing a portion of the substrate, thereby preliminarily defining the shape, size, position and other parameters of each memory cell in the subsequent preparation of the memory cell array; forms a first through hole in the stack that exposes a portion of the substrate and a portion of the semiconductor material layer, and the first through hole is used to define a write transistor, thereby defining the shape, size and position and other parameters of the write transistor of each memory cell in the subsequent preparation of the memory cell array; after forming a write transistor surrounding a portion of the semiconductor material layer in each semiconductor material layer through the first through hole, a filler is formed. The first through hole is filled with a write word line, so that the shared write word line of the adjacent memory cells along the direction perpendicular to the substrate is prepared at the same time in the same process step; a second groove exposing a part of the substrate is formed in the stack, and the second groove is used to define the read transistor, so as to define the shape, size and position and other parameters of the read transistor of each memory cell in the subsequent preparation of the memory cell array; after forming a vertical gate dielectric layer on the inner side wall of the second groove, a vertical semiconductor layer is formed to fill the second groove, and a part of the semiconductor material layer extending along the second direction is used to form a write bit line, and a part of the semiconductor material layer extending along the second direction is used to form a read word line. The vertical gate dielectric layer and the vertical semiconductor layer are used to form a read transistor together to obtain a write bit line, a write transistor, a read transistor, and a read word line arranged in sequence along the first direction. The area occupied by the capacitor is relatively reduced, so the area overhead of the single-layer memory cell is reduced, and the volume of the prepared product can be reduced while ensuring that the storage capacity is not reduced.

[0022] According to some embodiments, an etch stop layer is included between the substrate and the stack; based on the etch stop layer, the stack is etched to form at least one of the first groove, the first through hole, and the second groove, so as to avoid unnecessary etching damage to the substrate during the process of etching any one of the first groove, the first through hole, and the second groove, thereby improving the yield, performance and reliability of the manufactured product. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic top view of a storage unit provided in some embodiments of the present disclosure;

[0025] Figure 2 for Figure 1A schematic diagram of a longitudinal section along the X-axis direction;

[0026] Figure 3 for Figure 1 A schematic diagram of a longitudinal section along the Y axis;

[0027] Figure 4 A schematic top view of a memory provided in some embodiments of the present disclosure;

[0028] Figure 5 for Figure 4 A schematic diagram of a longitudinal section along the X-axis direction;

[0029] Figure 6 for Figure 4 A schematic diagram of a longitudinal section along the Y axis;

[0030] Figure 7 A schematic diagram of a memory manufacturing method provided in some embodiments of the present disclosure;

[0031] Figure 8 It is a schematic top view of a structure obtained after forming a stack in step S10 in a memory manufacturing method provided in some embodiments of the present disclosure;

[0032] Fig. 9 for Figure 8 A schematic diagram of a longitudinal section along the X-axis direction;

[0033] Fig.10 for Figure 8 A schematic diagram of a longitudinal section along the Y axis;

[0034] Fig.11 It is a schematic top view of a structure obtained after forming a first groove in step S10 in a memory manufacturing method provided in some embodiments of the present disclosure;

[0035] Fig.12 for Fig.11 A schematic diagram of a longitudinal section along the X-axis direction;

[0036] Fig.13 for Fig.11 A schematic diagram of a longitudinal section along the Y axis;

[0037] Fig.14 It is a schematic top view of a structure obtained after forming an isolation layer in step S20 in a memory manufacturing method provided in some embodiments of the present disclosure;

[0038] Fig.15 for Fig.14 A schematic diagram of a longitudinal section along the X-axis direction;

[0039] Fig.16 for Fig.14 A schematic diagram of a longitudinal section along the Y axis;

[0040] Fig.17 It is a schematic top view of a structure obtained after forming a first through hole in step S30 in a memory manufacturing method provided in some embodiments of the present disclosure;

[0041] Fig.18 for Fig.17 A schematic diagram of a longitudinal section along the X-axis direction;

[0042] Fig.19 for Fig.18 A schematic diagram of a longitudinal section along the Y axis;

[0043] Fig. 20 A schematic top view of a structure obtained after forming a write word line in step S40 in a memory manufacturing method provided in some embodiments of the present disclosure;

[0044] Fig.21 for Fig. 20 A schematic diagram of a longitudinal section along the X-axis direction;

[0045] Fig. 22 for Fig. 20 A schematic diagram of a longitudinal section along the Y axis;

[0046] Fig.23 It is a schematic top view of a structure obtained after forming a second groove in step S50 in a memory manufacturing method provided in some embodiments of the present disclosure; wherein, Fig.23 The longitudinal section diagram along the Y axis can be referred to Fig. 22 ;

[0047] Fig.24 for Fig.23 A schematic diagram of a longitudinal section along the X-axis direction;

[0048] Fig.25 It is a schematic top view of a structure obtained after forming a read transistor in step S60 in a memory preparation method provided in some embodiments of the present disclosure; wherein, Fig.25 The longitudinal section diagram along the Y axis can be referred to Fig. 22 ;

[0049] Fig.26 for Fig.25 A schematic diagram of a longitudinal section along the X-axis direction;

[0050] Fig. 27 A circuit diagram of a data reading and writing circuit provided in some embodiments of the present disclosure;

[0051] Fig.28 A circuit diagram of a three-dimensional data reading and writing circuit provided in some embodiments of the present disclosure.

[0052] Description of reference numerals:

[0053] 100, storage unit; 10, substrate; 11, source line; 12, read bit line; 13, write word line; 14, write bit line; 15, write transistor; 16, read transistor; 161, vertical gate dielectric layer; 162, vertical semiconductor layer; 17, read word line; 20, horizontal semiconductor layer; 151, ring gate dielectric layer; 152, ring gate electrode layer; S1 / D1, first source / drain contact region; S2 / D2, second source / drain contact region; 200, memory; 300, data read / write circuit; 400, three-dimensional data read / write circuit; 30, stack; 31, sacrificial layer; 32, semiconductor material layer; 41, first groove; 32T, top semiconductor material layer; 42, isolation layer; 43, first through hole; 44, second groove; 45, etch stop layer. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0056] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0057] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0060] Please note that the mutual insulation between the two in the embodiments of the present disclosure includes but is not limited to at least one of the presence of insulating material, insulating atmosphere or gap between the two. The direction perpendicular to the substrate in the embodiments of the present disclosure may be a direction perpendicular to the substrate surface, such as the top surface, and the direction parallel to the substrate may be a direction parallel to the substrate surface, such as the top surface.

[0061] Please refer to Figure 1-Figure 3 In some embodiments, a memory cell 100 is provided, comprising: a source line 11, a read bit line 12, a write word line 13, a horizontal semiconductor layer 20 extending along a first direction, and a write bit line 14, a write transistor 15, a read transistor 16, and a read word line 17 arranged in sequence along the first direction on the horizontal semiconductor layer 20; the write bit line 14 and the read word line 17 extend along a second direction intersecting the first direction; the read transistor 16 extends along a third direction perpendicular to the first direction and the second direction and penetrates the horizontal semiconductor layer 20, the read transistor 16 comprises a vertical gate dielectric layer 161 and a vertical semiconductor layer 162 extending along the third direction, the vertical gate dielectric layer 161 is located between the vertical semiconductor layer 162 and the horizontal semiconductor layer 20; the write transistor 15 extends along the first direction and surrounds a portion of the horizontal semiconductor layer 20; the horizontal semiconductor layer 20 and the write word line 13 are arranged along the second direction; the source line 11, the read transistor 16, and the read bit line 12 are arranged along the third direction.

[0062] For example, the memory cell 100 in the above embodiment is configured to extend the write transistor 15 along the first direction and surround a portion of the horizontal semiconductor layer 20, and the read transistor 16 extends along the third direction and penetrates the horizontal semiconductor layer 20, and the write bit line 14, the write transistor 15, the read transistor 16, and the read word line 17 are arranged in sequence along the first direction, the horizontal semiconductor layer 20 and the write word line 13 are arranged in the second direction, and the source line 11, the read transistor 16, and the read bit line 12 are arranged in the third direction. Two control gates are formed by using a portion of the vertical gate dielectric layer 161, the vertical semiconductor layer 162, and a portion of the vertical gate dielectric layer 161 arranged in sequence along the first direction, thereby effectively reducing the volume of the two control gates. In an array of memory cells 100 arranged in the same layer, adjacent memory cells 100 along the second direction share a write bit line 14 and a read word line 17, and adjacent memory cells 100 along the third direction share a write word line 13, thereby supporting simultaneous photolithography of multi-layer stacked memory cells 100, thereby reducing the process complexity and cost of manufacturing products; since one of the two control gates is connected to one end of the write transistor 15 to form a storage node, and the other control gate is connected to the read word line 17 to facilitate reading data, the area occupied by the capacitor is relatively reduced, thereby reducing the area overhead of a single-layer memory cell 100, and can reduce the volume of the manufactured product while ensuring that the storage capacity is not reduced.

[0063] Please continue to refer to Figure 1-Figure 3 In some embodiments, the vertical gate dielectric layer 161 extends along the third direction and circumferentially surrounds the vertical semiconductor layer 162, thereby forming an annular vertical gate dielectric layer 161 extending in the direction perpendicular to the substrate 10. The vertical semiconductor layer 162 surrounded by the vertical gate dielectric layer 161 is used as the common vertical semiconductor layer 162 of the two gates, which effectively reduces the volume of the two control gates and reduces the process complexity and cost of manufacturing products. Since one of the two control gates is connected to one end of the write transistor 15 to form a storage node, and the other control gate is connected to the read word line 17 to facilitate reading data, the area occupied by the capacitor is relatively reduced. Therefore, the area overhead of the single-layer storage unit 100 is reduced, and the volume of the manufactured product can be reduced while ensuring that the storage capacity is not reduced.

[0064] Please continue to refer to Figure 1-Figure 3In some embodiments, the write transistor 15 includes a ring gate dielectric layer 151, a first source / drain contact region S1, and a second source / drain contact region S2. The ring gate dielectric layer 151 extends along a first direction and circumferentially surrounds a portion of the horizontal semiconductor layer 20. The write word line 13 extends along a third direction and is located on a side of the ring gate dielectric layer 151 away from the horizontal semiconductor layer 20 along the second direction. The first source / drain contact region S1 is located on the horizontal semiconductor layer 20 between the write bit line 14 and the ring gate dielectric layer 151. The second source / drain contact region S2 is located on the ring gate dielectric layer 1 51. On the horizontal semiconductor layer 20 between the read transistors 16, by setting the write transistor 15 including the first source / drain contact area S1, the horizontal semiconductor layer 20, and the second source / drain contact area S2 arranged in sequence along the first direction, a ring-gate dielectric layer 151 is formed that extends along the first direction and circumferentially surrounds a portion of the horizontal semiconductor layer 20 to prepare a ring-gate transistor with a horizontal channel, which is convenient for simultaneously preparing the write word lines 13 of the adjacent storage cells 100 along the direction vertical to the substrate 10 in the same process step, thereby reducing the complexity and cost of the preparation process.

[0065] Please continue to refer to Figure 1-Figure 3 In some embodiments, the write transistor 15 further includes a ring gate electrode layer 152, and the ring gate electrode layer 152 is located between the write word line 13 and the ring gate dielectric layer 151, and circumferentially surrounds the ring gate dielectric layer 151, so as to facilitate the simultaneous preparation of the ring gate electrode layer 152 of adjacent memory cells 100 along a direction perpendicular to the substrate 10 in the same process step, and the simultaneous preparation of the write word lines 13 of adjacent memory cells 100 along a direction perpendicular to the substrate 10 in the same process step, thereby reducing the complexity and cost of the preparation process.

[0066] Please continue to refer to Figure 1-Figure 3 In some embodiments, the read transistor 16 includes a first source / drain contact region D1 and a second source / drain contact region D2. The first source / drain contact region D1 is located on the vertical semiconductor layer 162 between the horizontal semiconductor layer 20 and the read bit line 12; the second source / drain contact region D2 is located on the vertical semiconductor layer 162 between the horizontal semiconductor layer 20 and the source line 11, which is convenient for preparing a ring-gate transistor with a vertical channel, supports simultaneous photolithography of multi-layer stacked memory cells 100, and facilitates the simultaneous preparation of the vertical semiconductor layer 162 and the vertical gate dielectric layer 161 of adjacent memory cells 100 along the direction vertical to the substrate 10 in the same process step, thereby reducing the complexity and cost of the preparation process.

[0067] Please refer to Figure 4-Figure 6In some embodiments, a memory 200 is provided, comprising at least one layer of memory array; one layer of memory array comprises a plurality of memory cells 100 as described in any of the foregoing embodiments, which are arranged in an array with a first direction as a row direction and a second direction as a column direction; at least one layer of memory array is arranged along a third direction; memory cells 100 adjacent to each other along the first direction share a read word line 17 extending along the second direction and a write bit line 14 extending along the second direction; memory cells 100 adjacent to each other along the third direction share a write word line 13 extending along the third direction, and support simultaneous photolithography of multi-layer stacked memory cells 100, so as to facilitate simultaneous preparation of a vertical semiconductor layer 162 and a vertical gate dielectric layer 161 of adjacent memory cells 100 along a direction perpendicular to the substrate 10 in the same process step, thereby reducing the complexity and cost of the preparation process.

[0068] Please refer to Figure 7 In some embodiments, a memory preparation method is provided, comprising:

[0069] Step S10: providing a substrate, the substrate comprising a stack, the stack comprising sacrificial layers and semiconductor material layers alternately stacked in sequence in a direction away from the substrate, the stack comprising a plurality of first grooves arranged in an array with a first direction as a row direction and a second direction as a column direction, exposing a portion of the substrate;

[0070] Step S20: forming an isolation layer that fills the first groove and covers the top surface of the top semiconductor material layer of the stack;

[0071] Step S30: forming a first through hole in the stack to expose a portion of the substrate and a portion of the semiconductor material layer, wherein the first through hole is used to define a write transistor;

[0072] Step S40: After forming a write transistor surrounding a portion of the semiconductor material layer in each semiconductor material layer through the first through hole, a write word line filling the first through hole is formed;

[0073] Step S50: forming a second groove in the stacked layer to expose a portion of the substrate, wherein the second groove is used to define a read transistor;

[0074] Step S60: After forming a vertical gate dielectric layer on the inner wall of the second groove, a vertical semiconductor layer filling the second groove is formed, a portion of the semiconductor material layer extending along the second direction is used to constitute a write bit line, a portion of the semiconductor material layer extending along the second direction is used to constitute a read word line, the vertical gate dielectric layer and the vertical semiconductor layer are used to jointly constitute a read transistor, so as to obtain a write bit line, a write transistor, a read transistor, and a read word line arranged in sequence along the first direction; a portion of the semiconductor material layer extending along the first direction is used to constitute a horizontal semiconductor layer; the first direction and the second direction intersect.

[0075] Please refer to Figure 8-Figure 10In some embodiments, the substrate 10 provided in step S10 may be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0076] The above-mentioned substrate may also be other structures with supporting functions, such as peripheral circuits. The multilayer array of the present application is arranged on a supporting structure formed by peripheral circuits, and the supporting structure may also be understood as a substrate.

[0077] Please continue to refer to Figure 8-Figure 13 In some embodiments, the substrate 10 includes a stack 30, which includes sacrificial layers 31 and semiconductor material layers 32 that are alternately stacked in a direction away from the substrate 10 (for example, the z-axis direction), and the stack 30 includes a plurality of first grooves 41 that are arranged in an array with a first direction (for example, the x-direction or the X-axis direction) as a row direction and a second direction (for example, the y-direction or the Y-axis direction) as a column direction, exposing a portion of the substrate 10.

[0078] Please continue to refer to Figure 8-Figure 13 In some embodiments, a deposition process and / or a spin on glass coating (SOG) process may be used to form a sacrificial layer 31 on the top surface of the substrate 10 . Then, a semiconductor material layer 32 is formed on the sacrificial layer 31 by a deposition process.

[0079] For example, the material of the sacrificial layer 31 may include silicon oxide, silicon nitride (SiN x ), aluminum oxide (AlO x ), silicon carbide (SiC), or the like. For example, the material of the sacrificial layer 31 may include silicon oxide.

[0080] By way of example, the semiconductor material layer 32 may be silicon germanium (SiGe).

[0081] Please refer to Figure 14-16 In some embodiments, a deposition process may be used to form an isolation layer 42 that fills the first groove 41 and covers the top surface of the top semiconductor material layer 32T of the stack 30. The material of the isolation layer 42 may include at least one of silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0082] Please refer to Figure 17-Figure 19 In some embodiments, an etching process may be used to form a first through hole 43 in the stack 30 that exposes a portion of the substrate 10 and a portion of the semiconductor material layer 32. The first through hole 43 is used to define a write transistor. The first through hole 43 exposes a horizontal semiconductor layer used to form a write transistor.

[0083] Please refer to Figure 20-22 In some embodiments, at least one of an in-situ steam generation process (ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (RTO) can be used to form a ring gate dielectric layer 151 on the exposed surface of the horizontal semiconductor layer in the first through hole 43. The ring gate dielectric layer 151 surrounds the horizontal semiconductor layer exposed by the first through hole 43; the material of the ring gate dielectric layer 151 can be selected from silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride, aluminum oxide (Al2O3), aluminum oxynitride (AlON) and combinations thereof. The ring gate dielectric layer 151 can also be a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an anti-ferroelectric material, silicon carbide (SiC), or any combination thereof.

[0084] Please refer to Figure 20-22 In some embodiments, an atomic layer deposition process may be used to form a ring gate electrode layer 152 or a write word line 13 in the first through hole 43. The ring gate dielectric layer 151 and the ring gate electrode layer 152 are used to form a write transistor 15. The material of the ring gate electrode layer 152 or the write word line 13 is selected from Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, Ir, Ru, ITO, heavily doped polysilicon, etc. and combinations thereof.

[0085] Please refer to Figure 23-Figure 24 In some embodiments, an etching process may be used to form a second groove 44 in the stack 30 that exposes a portion of the substrate 10 . The second groove 44 is used to define the read transistor 16 .

[0086] Please refer to Figure 25-26In some embodiments, at least one of an in-situ steam generation process (ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (RTO) can be used to form a vertical gate dielectric layer 161 on the inner sidewall of the second groove 44, and then a vertical semiconductor layer 162 filling the second groove 44 is formed. A portion of the semiconductor material layer 32 extending along the second direction is used to form a write bit line 14, and a portion of the semiconductor material layer 32 extending along the second direction is used to form a read word line 17. The vertical gate dielectric layer 161 and the vertical semiconductor layer 162 are used to form a read transistor 16 together, so as to obtain a write bit line 14, a write transistor 15, a read transistor 16, and a read word line 17 arranged in sequence along the first direction; a portion of the semiconductor material layer 32 extending along the first direction is used to form a horizontal semiconductor layer 20; the first direction and the second direction intersect. The material of the vertical semiconductor layer 162 can be selected from indium gallium zinc oxide, indium zinc oxide, transition metal, transition metal oxide, and a combination thereof. It should be noted that the vertical semiconductor layer 162 can be composed of a single layer or a multi-layer composite material film, and the composite material film can be selected from Si, ZnO, Ga2O3, In2O3, SnO2, IGO, IZO, AZO, ITO, IGZO, IAZO, ITZO and combinations thereof.

[0087] Please continue to refer to Figure 7-Figure 26, a stack 30 including sacrificial layers 31 and semiconductor material layers 32 alternately stacked in a direction away from the substrate 10 is formed on the substrate 10, firstly, a plurality of first grooves 41 are formed in the stack 30, which are arranged in an array with a first direction as a row direction and a second direction as a column direction, exposing a portion of the substrate 10, so as to preliminarily define the shape, size, position and other parameters of each memory cell 100 in the subsequent preparation of the memory cell 100 array; a first through hole 43 is formed in the stack 30, which exposes a portion of the substrate 10 and a portion of the semiconductor material layer 32, and the first through hole 43 is used to define the write transistor 15, so as to define the shape, size and position and other parameters of the write transistor 15 of each memory cell 100 in the subsequent preparation of the memory cell 100 array; after forming the write transistor 15 surrounding the portion of the semiconductor material layer 32 in each semiconductor material layer 32 through the first through hole 43, a write word line 13 filling the first through hole 43 is formed, Thus, a shared write word line 13 of adjacent memory cells 100 along a direction perpendicular to the substrate 10 is prepared at the same time in the same process step; a second groove 44 exposing a portion of the substrate 10 is formed in the stack 30, and the second groove 44 is used to define the read transistor 16, thereby defining the shape, size, position and other parameters of the read transistor 16 of each memory cell 100 in the subsequent preparation of the memory cell 100 array; after a vertical gate dielectric layer 161 is formed on the inner side wall of the second groove 44, a vertical semiconductor layer 162 filling the second groove 44 is formed, a portion of the semiconductor material layer 32 extending along the second direction is used to form the write bit line 14, and a portion of the semiconductor material layer 32 extending along the second direction is used to form the read word line 17, and the vertical gate dielectric layer 161 and the vertical semiconductor layer 162 are used to jointly form the read transistor 16, so as to obtain the write bit line 14, the write transistor 15, the read transistor 16, and the read word line 17 arranged in sequence along the first direction. The area occupied by the capacitor is relatively reduced, thereby reducing the area cost of the single-layer storage unit 100, and can reduce the volume of the manufactured product while ensuring that the storage capacity is not reduced.

[0088] In some embodiments, the material of the read bit line 12 may be selected from copper, tungsten, aluminum, copper alloys, and combinations thereof.

[0089] In some embodiments, the material of the source line 11 can be selected from conductive metal, metal silicide, doped polysilicon, and the like, and combinations thereof.

[0090] In some embodiments, the material of the write bit line 14 may be selected from copper, tungsten, aluminum, copper alloys, and combinations thereof.

[0091] Please continue to refer to Figure 8-Figure 26In some embodiments, an etch stop layer 45 is included between the substrate 10 and the stack 30; based on the etch stop layer 45, the stack 30 is etched to form at least one of the first groove 41, the first through hole 43, and the second groove 44, so as to avoid unnecessary etching damage to the substrate 10 during the process of etching any one of the first groove 41, the first through hole 43, and the second groove 44, thereby improving the yield, performance and reliability of the manufactured product.

[0092] In some embodiments, the material of the etch stop layer 45 may include SiO 2 or SiN.

[0093] Please refer to Figure 1-Figure 3 , Fig. 27 In some embodiments, a data read / write circuit 300 is provided, including a write transistor 15 and a read transistor 16. The write transistor 15 is configured as follows: a first end is connected to a write bit line 14, and a control end is connected to a write word line 13; the read transistor 16 is configured as follows: a first control end is connected to a second end of the write transistor 15, a second control end is connected to a read word line 17, a first end is connected to a read bit line 12, and a second end is connected to a source line 11, wherein the read transistor 16 is a vertical channel ring-gate transistor, the read transistor 16 includes a vertical gate dielectric layer 161 and a vertical semiconductor layer 162 extending in a direction perpendicular to the substrate 10, the vertical gate dielectric layer 161 surrounds the outer side wall of the vertical semiconductor layer 162, and the vertical gate dielectric layer 161 is located between the vertical semiconductor layer 162 and the horizontal semiconductor layer 20. By setting the second end of the write transistor 15 to be connected to the first control end of the read transistor 16 and forming a storage node, setting the second control end of the read transistor 16 to be connected to the read word line 17, setting the first end of the read transistor 16 to be connected to the read bit line 12 and the second end to the source line 11, when the write transistor 15 is turned on by the write word line 13, data is written to the storage node via the write bit line 14; when the read transistor 16 is turned on by the read word line 17, data is read from the storage node via the read bit line 12. The area occupied by the capacitor is relatively reduced, so the area cost of the single-layer storage unit 100 is reduced, and the volume of the manufactured product can be reduced while ensuring that the storage capacity is not reduced.

[0094] In the data read / write circuit 300 in the above embodiment, when the write word line 13 controls the write transistor 15 to be turned on, the write signal is provided to the write bit line 14 to write data to the storage node SN; and when the write transistor 15 is turned off, the conduction characteristic of the read transistor 16 is controlled by the read word line 17, and the data is read out through the amplitude of the electric signal obtained by the read bit line 12. For example, if the conduction characteristic of the read transistor 16 is good, the amplitude of the electric signal (such as a voltage signal or a current signal) obtained through the read bit line 12 is relatively large, and the read data "1" is determined; on the contrary, if the conduction characteristic of the read transistor 16 is poor, the amplitude of the electric signal obtained through the read bit line 12 is relatively small, and the read data "0" is determined. Since the writing and reading of the storage data are realized by using two transistors without the aid of a capacitor structure, the spatial volume generated by the capacitor structure can be avoided while ensuring that the storage capacity within the unit volume is not reduced, thereby improving the storage density of the storage unit while improving the performance and reliability of the storage unit.

[0095] In some embodiments, please refer to Fig. 27 The write transistor 15 and the read transistor 16 may be N-type transistors. The write transistor 15 and the read transistor 16 may also be P-type transistors. The write transistor 15 and the read transistor 16 may be the same type of transistors or different types of transistors.

[0096] Please refer to Fig.28 In some embodiments, a three-dimensional data read-write circuit 400 is provided, including at least one layer of circuit array; one layer of circuit array includes a plurality of data read-write circuits as described in any of the above embodiments, which are arranged in an array with a first direction as a row direction and a second direction as a column direction; at least one layer of circuit array is arranged along a third direction; adjacent data read-write circuits along the first direction share a read word line 17 and a write bit line 14; adjacent data read-write circuits along the third direction share a write word line 13, wherein the read transistor 16 is a ring-gate transistor with a vertical channel, and the read transistor 16 includes a vertical gate dielectric layer 161 and a vertical semiconductor layer 162 extending in a direction perpendicular to the substrate 10, the vertical gate dielectric layer 161 surrounds the outer side wall of the vertical semiconductor layer 162, and the vertical gate dielectric layer 161 is located between the vertical semiconductor layer 162 and the horizontal semiconductor layer 20. This can support simultaneous lithography of multi-layer stacked memory cells 100, reducing the process complexity and cost of manufacturing products; since one of the two control gates is connected to one end of the write transistor 15 to form a storage node, and the other control gate is connected to the read word line 17 to facilitate reading data, the area occupied by the capacitor is relatively reduced, thereby reducing the area overhead of the single-layer memory cell 100, and can reduce the volume of the "2T0C" memory cell while ensuring that the storage capacity is not reduced.

[0097] It should be understood that although Figure 7 The steps in the above-mentioned process steps are shown in sequence according to arrows or step sequence indications, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7 At least part of the steps in the process described above may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0098] The order of preparing the write bit line, write transistor, storage node, read bit line, read transistor and source line in the above embodiments can be arbitrarily changed or combined with each other. Therefore, those skilled in the art can combine and / or change any number of preparation processes of the write bit line, write transistor, storage node, read bit line, read transistor and reference line without creative work, which should all fall within the protection scope of the embodiments of the present disclosure.

[0099] In some embodiments, an electronic device is provided, including a memory as described in any of the embodiments of the present disclosure. The electronic device is, for example but not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

[0100] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. The database involved in the embodiments provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., but are not limited thereto. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0102] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0103] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A memory preparation method, characterized in that: include: A substrate is provided, wherein the substrate comprises a stack, wherein the stack comprises sacrificial layers and semiconductor material layers alternately stacked in sequence in a direction away from the substrate, and wherein the stack comprises a plurality of first grooves arranged in an array with a first direction as a row direction and a second direction as a column direction, exposing a portion of the substrate; forming an isolation layer that fills the first groove and covers the top surface of the top semiconductor material layer of the stack; forming a first through hole in the stack to expose a portion of the substrate and a portion of the semiconductor material layer, wherein the first through hole is used to define a write transistor; After forming a write transistor surrounding a portion of the semiconductor material layer in each semiconductor material layer through the first through hole, a write word line filling the first through hole is formed; forming a second groove in the stacked layer to expose a portion of the substrate, wherein the second groove is used to define a read transistor; After forming a vertical gate dielectric layer on the inner sidewall of the second groove, a vertical semiconductor layer filling the second groove is formed, a portion of the semiconductor material layer extending along the second direction is used to form a write bit line, and a portion of the semiconductor material layer extending along the second direction is used to form a read word line, and the vertical gate dielectric layer and the vertical semiconductor layer are used to jointly form the read transistor, so as to obtain the write bit line, the write transistor, the read transistor, and the read word line arranged in sequence along the first direction; A portion of the semiconductor material layer extending along the first direction is used to form a horizontal semiconductor layer; the first direction and the second direction intersect.

2. The memory manufacturing method according to claim 1, characterized in that: An etch stop layer is included between the substrate and the stack; Based on the etch stop layer, the stack is etched to form at least one of the first groove, the first through hole, and the second groove.

3. The memory manufacturing method according to claim 1, characterized in that: The storage unit in the memory includes: a source line, a read bit line, a write word line, a horizontal semiconductor layer extending along a first direction, and a write bit line, a write transistor, a read transistor, and a read word line arranged in sequence along the first direction on the horizontal semiconductor layer; The write bit line and the read word line extend along a second direction intersecting the first direction; The read transistor extends along a third direction perpendicular to the first direction and the second direction and penetrates the horizontal semiconductor layer, the read transistor comprises a vertical gate dielectric layer and a vertical semiconductor layer extending along the third direction, the vertical gate dielectric layer is located between the vertical semiconductor layer and the horizontal semiconductor layer; The write transistor extends along the first direction and surrounds a portion of the horizontal semiconductor layer; The horizontal semiconductor layer and the write line are arranged along the second direction; The source line, the read transistor, and the read bit line are arranged along the third direction.

4. The memory manufacturing method according to claim 3, characterized in that: The vertical gate dielectric layer extends along the third direction and circumferentially surrounds the vertical semiconductor layer.

5. The memory preparation method according to claim 3, characterized in that: The write transistor comprises: a ring-gate dielectric layer extending along the first direction and circumferentially surrounding a portion of the horizontal semiconductor layer; the write line extending along the third direction and located on a side of the ring-gate dielectric layer away from the horizontal semiconductor layer along the second direction; A first source / drain contact region is located on the horizontal semiconductor layer between the write bit line and the ring gate dielectric layer; The second source / drain contact region is located on the horizontal semiconductor layer between the ring gate dielectric layer and the read transistor.

6. The memory manufacturing method according to claim 5, characterized in that: The write transistor further comprises: The ring gate electrode layer is located between the write word line and the ring gate dielectric layer, and circumferentially surrounds the ring gate dielectric layer.

7. The memory manufacturing method according to any one of claims 3 to 6, characterized in that: The read transistor comprises: A first source / drain contact region is located on the horizontal semiconductor layer and the vertical semiconductor layer between the read bit lines; The second source / drain contact region is located on the horizontal semiconductor layer and the vertical semiconductor layer between the source lines.

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