Surface-mounted capacitor with double-chip superposition parallel design

Abstract

The invention relates to the technical field of capacitors, in particular to a surface-mounted capacitor with double chips superposed and connected in parallel, which comprises a capacitor plastic package body, a double-chip capacitor structure is arranged in the capacitor plastic package body, and the double-chip capacitor structure comprises a first capacitor chip and a second capacitor chip. The second capacitor chip is arranged above the first capacitor chip, and a first pin is arranged on the second capacitor chip. According to the invention, the first capacitor chip and the second capacitor chip are packaged in parallel in series through the capacitor conductor, and then the first pin, the second pin and the third pin are connected with the first capacitor chip and the second capacitor chip, so that the requirements of large capacitance value and high voltage resistance of the capacitor can be met; meanwhile, the first capacitor chip and the second capacitor chip which are small in diameter can be selected to be manufactured in series, so that the diameter does not need to be increased, the appearance size of the capacitor is not changed, and the use requirements of small size, large capacitance value and high voltage resistance are met.

Description

Technical Field

[0001] The invention relates to a chip capacitor, in particular to a chip capacitor with a double-chip stacking and parallel design, belonging to the technical field of capacitors. Background Art

[0002] Capacitors are important electrical components that are widely used in the production of electronic products, mechanical equipment and other fields. They play an indispensable role. With the development trend of miniaturization of electrical products, electrical components are also developing in the direction of miniaturization. A capacitor with small size, large capacitance and high withstand voltage is an urgent need for many manufacturers. The working principle of capacitors is based on the movement and accumulation of charges in an electric field. When a dielectric is added between conductors, the movement of charges is hindered, thereby accumulating on the conductor to form capacitance. Inside the capacitor, the two electrodes are connected to two metal plates separated by a dielectric. When charging, the metal plate connected to the negative pole of the battery absorbs electrons, while the metal plate connected to the positive pole of the battery releases electrons to form charge accumulation. The capacitor can store charge and release it when needed, which makes it have multiple uses in electronic circuits. As an important component in electronic equipment, capacitors have multiple functions and a wide range of applications. When using it, you need to pay attention to relevant matters to ensure its normal operation and extend its service life.

[0003] The basic design of the capacitors currently produced is a single-chip assembly, that is, the lower lead, the first layer of solder, the capacitor chip, the second layer of solder, and the upper lead are assembled one by one in the limiting groove of the welding fixture in sequence. There is only one capacitor chip in this assembly. If you need to produce a capacitor with a large capacitance and a high withstand voltage, you must increase the diameter of the capacitor chip. Due to the increase in the chip diameter, the appearance size of the produced capacitor will also increase accordingly, which cannot meet the small size requirements; if you use a capacitor chip with a smaller diameter for assembly, although the purpose of reducing the size of the capacitor can be achieved, the capacitance will also become smaller. In short, capacitors assembled with a single-chip design are difficult to simultaneously meet the three requirements of small size, large capacitance, and high withstand voltage.

[0004] Therefore, there is an urgent need to improve a chip capacitor with a dual-chip stacking and parallel design to solve the above-mentioned problems. Summary of the invention

[0005] The purpose of the present invention is to provide a chip capacitor with a dual-chip stacking parallel design, which is formed by packaging a first capacitor chip and a second capacitor chip in parallel and in series through a capacitor conductor, and then using a first pin, a second pin and a third pin to connect the first capacitor chip and the second capacitor chip, so as to meet the requirements of large capacitance and high withstand voltage of the capacitor. At the same time, the first capacitor chip and the second capacitor chip with a smaller diameter can be selected to be manufactured in series, so that there is no need to increase the diameter, and the appearance size will not be changed, so as to meet the use requirements of small size, large capacitance and high withstand voltage.

[0006] In order to achieve the above object, the main technical solutions adopted by the present invention include:

[0007] A chip capacitor with a dual-chip stacking parallel design includes a capacitor plastic package, a dual-chip capacitor structure is arranged inside the capacitor plastic package, the dual-chip capacitor structure includes a first capacitor chip and a second capacitor chip, the second capacitor chip is arranged above the first capacitor chip, a first pin is arranged on the second capacitor chip, a second pin is arranged on the first capacitor chip, a capacitor conductor is fixedly installed between the first capacitor chip and the second capacitor chip, and a third pin connected to the capacitor conductor is arranged between the first capacitor chip and the second capacitor chip.

[0008] Preferably, bosses are fixedly mounted on the bottom of the first capacitor chip and the top of the second capacitor chip, and limiting rings matched with the bosses are fixedly mounted on one end of the first pin and the second pin.

[0009] Preferably, notches are provided on the top and bottom of the capacitor conductor, and a connecting block adapted to the notches is fixedly mounted on one end of the third pin.

[0010] Preferably, the boss and the limiting ring as well as the notch and the connecting block are connected by bonding with conductive adhesive.

[0011] Preferably, the capacitor plastic package body is made of epoxy resin, and a connecting strip is provided on the surface.

[0012] Preferably, the first capacitor chip and the second capacitor chip are made of ceramic material, and the first pin, the second pin and the third pin are made of strip copper sheets.

[0013] Preferably, tail ends of the first pin, the second pin and the third pin are in the same horizontal plane.

[0014] Preferably, one end of the first pin, the second pin and the third pin passes through the capacitor plastic package body and bends toward the bottom of the capacitor plastic package body and fits against the bottom wall of the capacitor plastic package body.

[0015] Preferably, an indicator mark is provided on the top of the capacitor plastic package body, and a reflective sticker is provided on the surface of the indicator mark.

[0016] Preferably, the indicator is configured as a groove, a convex block, a number, a symbol, etc., and the height of the notch matches that of the connecting block.

[0017] The present invention has at least the following beneficial effects:

[0018] The first capacitor chip and the second capacitor chip are packaged in parallel and in series through a capacitor conductor, and then the first pin, the second pin and the third pin are used to connect the first capacitor chip and the second capacitor chip, so that the requirements of large capacitance and high withstand voltage of the capacitor can be met. At the same time, the first capacitor chip and the second capacitor chip with a smaller diameter can be selected to be made in series, so there is no need to increase the diameter, and the appearance size will not be changed, so as to meet the use requirements of small size, large capacitance and high withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 It is a front view structural schematic diagram of the first capacitor chip and the second capacitor chip of the present invention;

[0021] Figure 2 This is a schematic diagram of the bottom structure of the first capacitor chip of the present invention;

[0022] Figure 3 It is a schematic diagram of the notch and connecting block structure of the present invention;

[0023] Figure 4 It is a schematic diagram of the bottom structure of the capacitor plastic package of the present invention;

[0024] Figure 5 It is a schematic diagram of the top structure of the capacitor plastic package of the present invention;

[0025] Figure 6 It is a schematic diagram of the structure of multiple capacitor plastic packages connected to each other according to the present invention.

[0026] In the figure, 1. plastic package of capacitor; 2. dual-chip capacitor structure; 3. first capacitor chip; 4. second capacitor chip; 5. first pin; 6. second pin; 7. capacitor conductor; 8. third pin; 9. boss; 10. limit ring; 11. notch; 12. connection block; 13. connection strip; 14. indicator mark. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0028] like Figure 1-Figure 6 As shown, this embodiment provides an embodiment of a chip capacitor with a dual-chip stacked and parallel design.

[0029] A chip capacitor with a double-chip stacking parallel design includes a capacitor plastic package 1, a double-chip capacitor structure 2 is arranged inside the capacitor plastic package 1, the double-chip capacitor structure 2 includes a first capacitor chip 3 and a second capacitor chip 4, the second capacitor chip 4 is arranged above the first capacitor chip 3, a first pin 5 is arranged on the second capacitor chip 4, a second pin 6 is arranged on the first capacitor chip 3, a capacitor conductor 7 is fixedly installed between the first capacitor chip 3 and the second capacitor chip 4, and a third pin 8 connected to the capacitor conductor 7 is arranged between the first capacitor chip 3 and the second capacitor chip 4. The first capacitor chip 3 and the second capacitor chip 4 are packaged in parallel and in series through the capacitor conductor 7, and then the first pin 5, the second pin 6 and the third pin 8 are used to connect the first capacitor chip 3 and the second capacitor chip 4, so that the requirements of large capacitance and high withstand voltage of the capacitor can be met, and at the same time, the first capacitor chip 3 and the second capacitor chip 4 with a smaller diameter can be selected to be made in series, so that there is no need to increase the diameter, and the appearance size will not be changed, so as to meet the use requirements of small size, large capacitance and high withstand voltage.

[0030] In this embodiment, Figure 1-Figure 6As shown, the bottom of the first capacitor chip 3 and the top of the second capacitor chip 4 are fixedly installed with a boss 9, one end of the first pin 5 and the second pin 6 is fixedly installed with a limit ring 10 adapted to the boss 9, the top and bottom of the capacitor conductor 7 are provided with a notch 11, and one end of the third pin 8 is fixedly installed with a connection block 12 adapted to the notch 11, and the boss 9 and the limit ring 10, as well as the notch 11 and the connection block 12 are connected by conductive adhesive. Through the setting of the boss 9 and the limit ring 10, one end of the first pin 5 and the second pin 6 can be connected to the center of the first capacitor chip 3 and the second capacitor chip 4, with the positioning function, and can better use the conductive adhesive to bond and connect the first pin 5 and the second capacitor chip 4, the first capacitor chip 3 and the second pin 6, through the setting of the notch 11 and the connection block 12, it can also play a positioning role on one end of the third pin 8, so that one end of the third pin 8 can also be connected to the center of the first capacitor chip 3 and the second capacitor chip 4, and it is also convenient to use the conductive adhesive for bonding and connection.

[0031] In this embodiment, Figure 1-Figure 6 As shown, the capacitor plastic package 1 is made of epoxy resin, and a connecting strip 13 is arranged on the surface. The first capacitor chip 3 and the second capacitor chip 4 are made of ceramic material. The first pin 5, the second pin 6 and the third pin 8 are made of strip copper sheets, and the tail ends of the first pin 5, the second pin 6 and the third pin 8 are in the same horizontal plane. By using epoxy resin to make the capacitor plastic package 1, it can play the role of insulation and moisture-proof. At the same time, in the process of making the capacitor plastic package 1, the use of one-piece injection molding can greatly improve the utilization rate of epoxy resin and reduce the scrap amount of epoxy resin. In addition, when the one-piece casting is performed, a connecting strip 13 is reserved on the surface of the capacitor plastic package 1, which can facilitate the subsequent separation of the one-piece capacitor plastic package 1 by cutting to meet production requirements. By using ceramic materials to make the first capacitor chip 3 and the second capacitor chip 4, the first capacitor chip 3 and the second capacitor chip 4 are more stable and not easily affected by external factors. At the same time, they have excellent high-frequency response capabilities and meet the requirements of high response speed. By using copper sheets to make the first pin 5, the second pin 6 and the third pin 8, the first pin 5, the second pin 6 and the third pin 8 have excellent conductivity, high stability, are not easily deformed by temperature, and are easy to form and process and corrosion-resistant.

[0032] In this embodiment, Figure 1-Figure 6As shown, one end of the first pin 5, the second pin 6 and the third pin 8 penetrates the capacitor plastic package 1 and bends toward the bottom of the capacitor plastic package 1, and fits on the bottom wall of the capacitor plastic package 1. An indicator mark 14 is provided on the top of the capacitor plastic package 1, and a reflective sticker is provided on the surface of the indicator mark 14. The indicator mark 14 is provided as a groove, a protrusion, a number, a symbol, etc., and the height of the notch 11 matches that of the connecting block 12. By bending one end of the first pin 5, the second pin 6 and the third pin 8 toward the bottom of the capacitor plastic package 1, the space occupied by the capacitor plastic package 1 when mounted on the circuit board can be saved. By setting the indicating mark 14, the first pin 5, the second pin 6 and the third pin 8 are respectively set to high potential and low potential. The indicating mark 14 can be easily identified and positioned, thereby facilitating the installation of the capacitor plastic package 1 on the circuit board. At the same time, the setting of the reflective strip makes the indicating mark 14 more recognizable. By matching the height of the notch 11 and the connecting block 12, when the notch 11 and the connecting block 12 are connected, the connecting block 12 can be tightly attached to the first capacitor chip 3 and the second capacitor chip 4, thereby improving the stability of the connection.

[0033] In this embodiment, if Figure 1-Figure 6 As shown, the working process of a chip capacitor with a dual-chip stacking and parallel connection design provided in this embodiment is as follows:

[0034] The first capacitor chip 3 and the second capacitor chip 4 are packaged in parallel and in series through the capacitor conductor 7, and then the first pin 5, the second pin 6 and the third pin 8 are used to connect the first capacitor chip 3 and the second capacitor chip 4, so that the requirements of large capacitance and high withstand voltage of the capacitor can be met. At the same time, the first capacitor chip 3 and the second capacitor chip 4 with a relatively small diameter can be selected to be manufactured in series, so that there is no need to increase the diameter, and the appearance size will not be changed, so as to meet the use requirements of small size, large capacitance and high withstand voltage;

[0035] The assembly steps are as follows: the first step is to place the capacitor conductor 7 between the first capacitor chip 3 and the second capacitor chip 4; the second step is to install the limiting ring 10 at one end of the first pin 5 on the boss 9 at the top of the second capacitor chip 4, and the limiting ring 10 at one end of the second pin 6 on the boss 9 at the bottom of the first capacitor chip 3, and then the boss 9 and the limiting ring 10 are bonded and connected by conductive glue; the third step is to insert the connecting block 12 at one end of the third pin 8 into the notch 11 on the capacitor conductor 7, so that one end of the third pin 8 is attached to the bottom of the second capacitor chip 4 and the top of the first capacitor chip 3, and then the notch 11 and the connecting block 12 are still bonded and connected by conductive glue; the fourth step is to perform conjoined injection molding on the connected first capacitor chip 3, the second capacitor chip 4, the first pin 5, the second pin 6 and the third pin 8 to form a capacitor plastic package 1 to wrap the first capacitor chip 3 and the second capacitor chip 4; the fifth step is to use a cutting tool to cut along the connecting strips 13 between the plurality of capacitor plastic packages 1 to separate the conjoined capacitor plastic packages 1 into independent monomers.

[0036] In summary, in this embodiment, according to a double-chip stacked parallel design of the present embodiment, the first pin 5 and the second pin 6 can be connected to the center of the first capacitor chip 3 and the second capacitor chip 4 through the setting of the boss 9 and the limiting ring 10, and have the positioning function, and can better use the conductive glue to bond the first pin 5 and the second capacitor chip 4, the first capacitor chip 3 and the second pin 6. Through the setting of the notch 11 and the connecting block 12, one end of the third pin 8 can also be positioned, so that one end of the third pin 8 can also be connected to the first The center of the capacitor chip 3 and the second capacitor chip 4 is also conveniently connected by conductive glue. By using epoxy resin to make the capacitor plastic package 1, it can play an insulating and moisture-proof role. At the same time, in the process of making the capacitor plastic package 1, the use of the one-piece injection molding method can greatly improve the utilization rate of the epoxy resin and reduce the amount of epoxy resin scrap. In addition, when the one-piece casting is performed, a connecting strip 13 is reserved on the surface of the capacitor plastic package 1, which can facilitate the subsequent use of cutting to separate the one-piece capacitor plastic package 1 to meet production requirements. The capacitor chip 4 is made of ceramic material, so that the first capacitor chip 3 and the second capacitor chip 4 have higher stability, are not easily affected by external factors, and have excellent high-frequency response capabilities to meet the requirements of high response speed. By making the first pin 5, the second pin 6 and the third pin 8 of copper sheet, the first pin 5, the second pin 6 and the third pin 8 have excellent conductivity, high stability, are not easily deformed by temperature, and are easy to mold and manufacture and corrosion-resistant. By bending one end of the first pin 5, the second pin 6 and the third pin 8 toward the bottom of the capacitor plastic package 1, it can The space occupied by the capacitor plastic package 1 mounted on the circuit board is saved. By setting the indicating mark 14, the first pin 5, the second pin 6 and the third pin 8 are respectively set to high potential and low potential. The indicating mark 14 can be easily marked and positioned, so as to facilitate the installation of the capacitor plastic package 1 on the circuit board. At the same time, the setting of the reflective strip makes the indicating mark 14 more recognizable. By matching the height of the notch 11 and the connecting block 12, when the notch 11 and the connecting block 12 are connected, the connecting block 12 can be tightly attached to the first capacitor chip 3 and the second capacitor chip 4, thereby improving the stability of the connection.

[0037] For example, certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criteria for distinction. For example, "including" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to". "Approximately" means that within an acceptable error range, those skilled in the art can solve technical problems within a certain error range and basically achieve technical effects.

[0038] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such product or system. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the product or system including the elements.

[0039] The above description shows and describes several preferred embodiments of the present invention, but as mentioned above, it should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the invention concept described herein through the above teachings or the technology or knowledge of the relevant field. Changes and variations made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A chip capacitor with a dual-chip stacking and parallel connection design, comprising a capacitor plastic package (1), characterized in that: A dual-chip capacitor structure (2) is arranged inside the capacitor plastic package (1), and the dual-chip capacitor structure (2) comprises a first capacitor chip (3) and a second capacitor chip (4), the second capacitor chip (4) is arranged above the first capacitor chip (3), a first pin (5) is arranged on the second capacitor chip (4), a second pin (6) is arranged on the first capacitor chip (3), a capacitor conductor (7) is fixedly installed between the first capacitor chip (3) and the second capacitor chip (4), and a third pin (8) connected to the capacitor conductor (7) is arranged between the first capacitor chip (3) and the second capacitor chip (4).

2. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: A boss (9) is fixedly mounted on the bottom of the first capacitor chip (3) and the top of the second capacitor chip (4), and a limiting ring (10) adapted to the boss (9) is fixedly mounted on one end of the first pin (5) and the second pin (6).

3. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: The top and bottom of the capacitor conductor (7) are both provided with slots (11), and one end of the third pin (8) is fixedly mounted with a connection block (12) adapted to the slot (11).

4. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: The boss (9) and the limiting ring (10) as well as the notch (11) and the connecting block (12) are connected by bonding with conductive adhesive.

5. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: The capacitor plastic package body (1) is made of epoxy resin and has a connecting strip (13) arranged on its surface.

6. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: The first capacitor chip (3) and the second capacitor chip (4) are made of ceramic material, and the first pin (5), the second pin (6) and the third pin (8) are made of strip copper sheets.

7. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: The tail ends of the first pin (5), the second pin (6) and the third pin (8) are located in the same horizontal plane.

8. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: One end of the first pin (5), the second pin (6) and the third pin (8) passes through the capacitor plastic package (1) and is bent toward the bottom of the capacitor plastic package (1) and is attached to the bottom wall of the capacitor plastic package (1).

9. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: An indicator mark (14) is arranged on the top of the capacitor plastic package body (1), and a reflective sticker is arranged on the surface of the indicator mark (14).

10. The chip capacitor with a double-chip stacking and parallel connection design according to claim 1, characterized in that: The indicator (14) is configured as a groove, a convex block, a number, a symbol, etc., and the height of the notch (11) matches that of the connecting block (12).

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