PoP packaging structure and manufacturing method thereof

Abstract

Example embodiments relate to a PoP package structure and a method of manufacturing a PoP package structure. The PoP packaging structure comprises the components of a substrate; a first package disposed on the substrate; a second package disposed on the first package; the first heat conduction layer is arranged between the first packaging part and the second packaging part; the second heat conduction layer is arranged on the second packaging piece; and a thermal interface material layer disposed between the first package and the substrate. The first thermally conductive layer is in contact with the thermal interface material layer through a via through the first package, and the second thermally conductive layer is in contact with the first thermally conductive layer through a via through the second package. Therefore, heat generated by the first package can be transferred downwards to the substrate through the first heat conduction layer and the thermal interface material layer, and / or can be transferred upwards to the surface of the second package through the first heat conduction layer and the second heat conduction layer. Therefore, the heat dissipation performance of the PoP packaging structure can be effectively improved.

Description

Technical Field

[0001] Example embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. Background Art

[0002] Due to the rapid development of the electronics industry and user needs, electronic devices are becoming smaller and lighter, and therefore, highly integrated semiconductor chips as core components of electronic devices have become beneficial. In addition, as mobile products are widely used, small multifunctional electronic devices have become beneficial. Therefore, a PoP (Package-on-Package) packaging structure has been proposed in which an upper package having a different function from a lower package is stacked on a lower package. Summary of the invention

[0003] Example embodiments are directed to improving heat dissipation of a PoP packaging structure.

[0004] Example embodiments relate to a PoP package structure that improves heat dissipation performance through a combination of a heat dissipation member disposed between an SOC package and a memory package, a heat dissipation member between the SOC package and a PCB board, and a heat dissipation member on a surface of the memory package.

[0005] Furthermore, some example embodiments relate to a method of manufacturing the PoP package structure.

[0006] According to some example embodiments of the present disclosure, a PoP package structure may include: a substrate; a first package disposed on the substrate and including a first base substrate, a first chip located on the first base substrate, and a first molding layer located on the first base substrate and encapsulating or at least partially encapsulating the first chip; a second package located on the first package and including a second base substrate, a second chip located on the second base substrate, and a second molding layer located on the second base substrate and encapsulating or at least partially encapsulating the second chip; a first heat conductive layer located between an upper surface of the first package and a lower surface of the second package; and a thermal interface material layer located between the lower surface of the first package and an upper surface of the substrate. The first heat conductive layer contacts the thermal interface material layer through a via defined in the first package.

[0007] According to some example embodiments, the first heat conductive layer may include a heat conductive insulating material.

[0008] According to some example embodiments, the PoP package structure may further include a second heat conducting layer located on an upper surface of the second package. The second heat conducting layer may contact the first heat conducting layer through a via hole penetrating the second package.

[0009] According to some example embodiments, the second heat conductive layer may include a heat conductive insulating material.

[0010] According to some example embodiments, the first heat conductive layer and the second heat conductive layer may include the same material as each other.

[0011] According to some example embodiments, the first heat conductive layer and the second heat conductive layer may include different materials from each other.

[0012] According to some example embodiments, an upper surface of the second heat conductive layer is at the same level (or height) as an upper surface of the second package.

[0013] According to some example embodiments, a thermal interface material layer may include a thermally conductive matrix and a phase change composite material dispersed in the thermally conductive matrix.

[0014] According to some example embodiments, the thermally conductive matrix may have insulating properties.

[0015] According to some example embodiments, a phase change composite material may include a phase change material and a wrapping material wrapping the phase change material.

[0016] According to some example embodiments, a method for manufacturing a PoP package structure may include: preparing a first package, the first package including a first base substrate, a first chip located on the first base substrate, and a first molding layer located on the first base substrate and encapsulating or at least partially encapsulating the first chip; performing a drilling process on the first package to form a first via hole penetrating the first package; coating a thermally conductive insulating material on an upper surface of the first package to form a first thermally conductive layer; coating a phase change composite material on an upper surface of a substrate; combining the first package having the first thermally conductive layer formed on its upper surface and the substrate having the phase change composite material coated on its upper surface with each other; preparing a second package, the second package including a second base substrate, a second chip located on the second base substrate, and a second molding layer located on the second base substrate and encapsulating or at least partially encapsulating the second chip; combining the second package with the first package bonded to the substrate with each other; and filling a thermally conductive matrix in a space between the substrate and the first package to form a thermal interface material layer. The first thermally conductive layer contacts the thermal interface material layer through the first via hole.

[0017] According to some example embodiments, the method may further include, after forming the first heat-conducting layer, performing an etching process on an upper surface of the first heat-conducting layer to form a first recess.

[0018] According to some example embodiments, the method may further include: performing an etching process on the upper surface of the second package to form a second recess; performing a drilling process on the second package to form a second via hole penetrating the second package; and coating a thermally conductive insulating material on the upper surface of the second package to form a second thermally conductive layer. The second thermally conductive layer fills the second recess and the second via hole, and contacts the first thermally conductive layer through the second via hole.

[0019] According to some example embodiments, the first heat conducting layer and the second heat conducting layer may include the same heat conducting insulating material as each other.

[0020] According to some example embodiments, the first heat conductive layer and the second heat conductive layer may include thermally conductive insulating materials different from each other.

[0021] According to some example embodiments, an upper surface of the second heat conducting layer is at the same level as an upper surface of the second package.

[0022] According to some example embodiments, the thermally conductive matrix may have insulating properties.

[0023] According to some example embodiments, a phase change composite material may include a phase change material and a wrapping material wrapping the phase change material. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other aspects, features and other advantages of example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0025] Figure 1 A PoP packaging structure is shown.

[0026] Figure 2 A PoP packaging structure according to some example embodiments of the present disclosure is shown; Figure 3 shows a PoP packaging structure according to some example embodiments of the present disclosure; and Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I and Figure 4J Operations in a method of manufacturing a PoP package structure according to some example embodiments of the present disclosure are illustrated. DETAILED DESCRIPTION

[0027] Example embodiments of the present disclosure are described with reference to the accompanying drawings. However, the example embodiments may be implemented in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, the example embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concepts disclosed herein to those of ordinary skill in the art. Throughout the specification, the same components are represented by the same reference numerals, and for the sake of brevity of description, their repeated descriptions may be omitted.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0029] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various example embodiments. However, it is apparent that various example embodiments can be implemented without these specific details or with one or more equivalent arrangements.

[0030] Figure 1 A PoP package structure 1 is shown, which may include a substrate SUB and a system-on-chip (SOC) package 10 and a memory package 20 sequentially stacked in a vertical direction on the substrate SUB. During operation, the SOC package 10 will generate heat, which should be dissipated. However, the heat dissipation area of ​​the PoP package structure 1 is relatively small, the heat generated by the SOC package 10 is difficult to dissipate, and the temperature in the PoP package structure 1 will rise, resulting in the formation of hot spots. This may eventually lead to packaging failures in the PoP package structure 1, thereby affecting the packaging performance.

[0031] Figure 2 A PoP packaging structure according to some example embodiments of the present disclosure is shown.

[0032] Reference Figure 2 According to some example embodiments, the PoP package structure 2 may include a substrate SUB and a system-on-chip (SOC) package 10 and a memory package 20 sequentially stacked in a vertical direction on the substrate SUB. However, the arrangement of the PoP package structure is not limited thereto. For example, in some example embodiments, the PoP package structure may include three or more semiconductor packages sequentially stacked in a vertical direction on the substrate SUB, and the type of a suitable semiconductor package may be selected without limitation.

[0033] The substrate SUB may be a printed circuit board (PCB). For example, the substrate SUB may be a single-layer printed circuit board or a multi-layer printed circuit board. However, example embodiments are not limited thereto. In some example embodiments, for example, the substrate SUB may include an upper bonding pad (not shown) disposed on an upper surface, a lower bonding pad disposed on a lower surface, and an internal lead disposed inside the substrate SUB to electrically connect the upper bonding pad and the lower bonding pad.

[0034] In some example embodiments, the substrate SUB may include at least one material selected from phenolic resin, epoxy resin, and polyimide. The substrate SUB may include, for example, at least one material selected from flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene oxide, bismaleimide triazine (BT), polyamide, cyanate ester, polyimide, and liquid crystal polymer. However, example embodiments are not necessarily limited thereto.

[0035] A plurality of pads and / or conductive traces may be provided on the upper surface of the substrate SUB. In an embodiment, the conductive traces may include signal traces or ground traces for input / output connection of the SOC package 10 and the memory package 20. The pads are provided on the upper surface of the substrate SUB and are connected to the corresponding conductive traces.

[0036] The SOC package 10 may be a three-dimensional (3D) semiconductor package and includes a first base substrate 101, a system-on-chip chip 102, system-on-chip chip solder balls 103 electrically connecting the system-on-chip chip 102 to internal leads disposed in the first base substrate 101, and a first molding layer 104 disposed on the first base substrate 101 and encapsulating or at least partially encapsulating the system-on-chip chip 102 and the system-on-chip chip solder balls 103 on the first base substrate 101.

[0037] In some example embodiments, the system-on-chip chip 102 may include a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller, etc., but example embodiments are not limited thereto. The system-on-chip chip 102 may be disposed on the upper surface of the first base substrate 101 and spaced apart from the substrate SUB. The system-on-chip chip 102 may be manufactured using, for example, a flip chip technology.

[0038] The SOC package 10 may be connected to the upper surface of the substrate SUB through external solder balls 105 disposed on the lower surface of the first base substrate 101 .

[0039] In some example embodiments, the first base substrate 101 may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a structure including a single crystal silicon substrate and a single crystal epitaxial layer grown therefrom. However, example embodiments are not limited thereto.

[0040] In some example embodiments, the system-on-chip chip solder balls 103 and the external solder balls 105 may include a solder material. In some example embodiments, the solder material may be or may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof. However, in other example embodiments, the system-on-chip chip solder balls 103 and the external solder balls 105 may include other materials.

[0041] In some example embodiments, the first mold layer 104 may be or may include a UV-curable polymer or a thermally-curable polymer. For example, the first mold layer 104 may be or may include a non-conductive material such as epoxy molding compound (EMC), Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), etc. However, example embodiments are not necessarily limited thereto. The first mold layer 104 may be applied or formed on the substrate while in a liquid or fluid state, and may then be cured by a chemical reaction or similar process.

[0042] The memory package 20 may include a dynamic random access memory (DRAM) package and / or other suitable memory packages. In some example embodiments, the memory package 20 may include a second base substrate 201, a memory chip 202, a bonding wire 203 electrically connecting the memory chip 202 to an upper surface of the second base substrate 201 facing away from the substrate SUB, and a second mold layer 204 disposed or formed on the second base substrate 201. The second mold layer 204 may encapsulate or at least partially encapsulate the memory chip 202 and the bonding wire 203 on the second base substrate 201.

[0043] In some example embodiments, the memory chip 202 may include a volatile memory chip (such as a dynamic random access memory (DRAM) or a static random access memory (SRAM)) or a non-volatile memory chip (such as a phase change random access memory (PcRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). However, example embodiments are not limited thereto. The memory chip 202 may be disposed on an upper surface of the second base substrate 201 that is away from the substrate SUB. The memory chip 202 may be attached to the second base substrate 201 using an adhesive. In some example embodiments, the memory chip 202 may be electrically connected to the second base substrate 201 using bonding wires 203 and bonding pads. However, example embodiments are not limited thereto, and example embodiments may be variously modified according to application and / or design.

[0044] The memory package 20 may be connected to the SOC package 10 through inter-chip solder balls 205 disposed on a lower surface of the second base substrate 201 (eg, a surface of the second base substrate 201 facing the substrate SUB).

[0045] In some example embodiments, similar to the first base substrate 101, the second base substrate 201 may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a structure including a single crystal silicon substrate and a single crystal epitaxial layer grown therefrom. However, in other example embodiments, the second base substrate 201 may include other materials according to application and / or design.

[0046] The first base substrate 101 and the second base substrate 201 may be electrically connected to each other through the inter-chip solder balls 205 and the connecting solder balls 106, wherein the inter-chip solder balls 205 may be disposed between the second base substrate 201 of the memory package 20 and the first mold layer 104 of the SOC package 10, and the connecting solder balls 106 may penetrate the first mold layer 104 and may be connected to the inter-chip solder balls 205 and the bonding pads on the first base substrate 101. The connecting solder balls 106 may be connected between the first base substrate 101 and the second base substrate 201, and are distributed around the periphery of the system-on-chip chip 102 to achieve physical connection and signal connection between the first base substrate 101 and the second base substrate 201.

[0047] The bonding pads that may be disposed on the surface of the memory chip 202 that is opposite to the system-on-chip chip 102 (e.g., the upper surface of the memory chip 202) may be electrically connected to the bonding pads disposed on the upper surface of the second base substrate 201 through the bonding wires 203. In some example embodiments, the bonding wires 203 may be copper wires, aluminum wires, silver wires, gold wires, etc. However, example embodiments are not limited thereto, and the bonding wires 203 may be or may include any conductive material depending on the application and / or design.

[0048] In some example embodiments, similar to the first mold layer 104, the second mold layer 204 may be or may include a UV-curable polymer or a thermally-curable polymer. For example, the second mold layer 204 may include a non-conductive material such as epoxy molding compound (EMC), Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), etc. However, example embodiments are not limited thereto. The second mold layer 204 may be applied to the substrate while in a liquid or fluid state, and may then be cured by a chemical reaction or other similar processes.

[0049] In some example embodiments, the heat conductive layer 30 may be disposed between the SOC package 10 and the memory package 20. In some example embodiments, the heat conductive layer 30 may be disposed between the upper surface of the SOC package 10 and the lower surface of the memory package 20. In some example embodiments, the heat conductive layer 30 may be disposed between the lower surface of the second base substrate 201 of the memory package 20 and the upper surface of the first mold layer 104 of the SOC package 10, and may extend to the lower surface of the first base substrate 101 through the via 107 penetrating the SOC package 10. In an embodiment, the heat conductive layer 30 may contact the SOC package 10. In some example embodiments, the heat conductive layer 30 may fill only a portion (e.g., a lower portion) of the space between the second base substrate 201 of the memory package 20 and the first mold layer 104 of the SOC package 10. In some other example embodiments, the heat conductive layer 30 may fill the entire space between the second base substrate 201 of the memory package 20 and the first mold layer 104 of the SOC package 10. In some example embodiments, the number of vias 107 in the SOC package 10 may be increased or decreased, and / or the location in the SOC package 10 may be changed, depending on the application and / or design.

[0050] In some example embodiments, in order to improve or maximize the heat dissipation capability, the heat conductive layer 30 may cover the side surface of the first mold layer 104 in addition to covering the entire upper surface of the first mold layer 104. However, example embodiments are not limited thereto. In some example embodiments, the heat conductive layer 30 may partially cover the upper surface of the first mold layer 104. For example, the heat conductive layer 30 may cover only a portion of the upper surface of the first mold layer 104 that may vertically overlap with the system-on-chip chip 102. Therefore, according to the application and / or design, the position of the heat conductive layer 30 may be changed, and / or the size of the heat conductive layer 30 may be increased or decreased.

[0051] The heat conducting layer 30 may be or may include an insulating material having a high thermal conductivity (e.g., a high thermal conductivity insulating material), so that the heat generated by the SOC package 10 can be dissipated through the heat conducting layer 30 or relatively easily conducted to the first base substrate 101 and the second base substrate 201 for effective heat dissipation. The heat conducting layer 30 may limit or minimize or prevent a short circuit between the first base substrate 101 and the second base substrate 201, and improve heat conduction. In some example embodiments, in order to limit or minimize or prevent a short circuit between connection points, the heat conducting layer 30 may limit the use of conductive materials such as metals therein. For example, the heat conducting layer 30 may not include any conductive material, or the conductive material may be present in a relatively small amount to provide poor conductive properties. In some example embodiments, the thermal conductivity of the high thermal conductivity insulating material may be greater than 1 W / mK (or about 1 W / mK). In some other example embodiments, the thermal conductivity may be higher: 2 W / mK (or about 2 W / mK). However, example embodiments are not limited thereto, and the thermal conductivity may vary according to the needs of the application and / or design. In some example embodiments, the high thermal conductivity insulating material may be or may include aluminum nitride, aluminum oxide, silicon nitride, graphene, thermally conductive silicone grease, combinations thereof, and the like. However, example embodiments are not limited thereto, and other thermally conductive materials may be used. In some example embodiments, in addition to or as an alternative to the high thermal conductivity insulating material, the thermally conductive layer 30 may also be or may include a material such as a metal thermally conductive plate. When a metal thermally conductive plate is used, an additional insulating layer may be provided on the outside of the metal thermally conductive plate in order to limit, minimize, or avoid a short circuit condition.

[0052] In some example embodiments, the thermally conductive layer 30 may have a viscosity that improves or enhances the bonding between the second base substrate 201 of the memory package 20 and the first mold layer 104 of the SOC package 10. Additionally or alternatively, the thermally conductive layer 30 may be elastic (or have elasticity), and the thermally conductive layer 30 may be elastically deformed when an external force or pressure is applied thereto. As a result, when the thermally conductive layer 30 occupies the space between the second base substrate 201 and the first mold layer 104, the gap may be limited, and the thermally conductive layer 30 may provide a relatively stable connection between the second base substrate 201 and the first mold layer 104. In some example embodiments, the thermally conductive layer 30 may be a thermally conductive glue block, which not only has elasticity and viscosity, but also has a relatively high thermal conductivity, while providing electrical insulation. However, example embodiments are not limited thereto, and other materials may be used as the thermally conductive layer 30 according to the needs of the application and / or design. It will be understood that for the purpose of discussion, unless otherwise specified, "insulation" used herein may refer to electrical insulation.

[0053] The thermal interface material layer 40 may be disposed between the SOC package 10 (e.g., the first base substrate 101) and the substrate SUB, and may contact the thermally conductive layer 30 through the via 107 to provide thermal conduction. In some example embodiments, the thermal interface material layer 40 may be disposed between the lower surface of the SOC package 10 and the upper surface of the substrate SUB. The thermal interface material layer 40 may be or may include a thermally conductive matrix 42 and / or a phase change composite material 44 dispersed in the thermally conductive matrix 42. In some example embodiments, the combination of the thermally conductive matrix 42 and the phase change composite material 44 may provide a more effective or improved thermal conduction effect. However, example embodiments are not limited thereto. For example, in some other example embodiments, the thermal interface material layer 40 may include only the thermally conductive matrix 42. In some example embodiments, in order to avoid or minimize or limit a short circuit between the first base substrate 101 and the substrate SUB, the thermally conductive matrix 42 may be insulating, and in order to achieve good or improved thermal conduction, the thermally conductive matrix 42 may have a relatively high thermal conductivity. In addition, the thermal interface material layer 40 may also adhere or bond or attach the SOC package 10 to the upper surface of the substrate SUB, and therefore, the thermally conductive matrix 42 may have viscosity. Further, the thermally conductive matrix 42 may have elasticity. In some example embodiments, the thermal interface material layer 40 may be elastically deformed when an external force or pressure is applied thereto. As a result, when the thermal interface material layer 40 occupies the space between the first base substrate 101 and the substrate SUB, the gap may be limited, and the thermal interface material layer 40 may provide a relatively stable connection between the first base substrate 101 and the substrate SUB.

[0054] In some example embodiments, the thermally conductive matrix 42 of the thermal interface material layer 40 may be similar to the high thermally conductive insulating material of the thermally conductive layer 30. In some example embodiments, the thermally conductive matrix 42 of the thermal interface material layer 40 may be a material having a higher fluidity than the high thermally conductive insulating material of the thermally conductive layer 30. In some example embodiments, in order to improve the bottom filling, the thermally conductive matrix 42 having a higher fluidity may be beneficial. In some example embodiments, in order to achieve improved heat conduction efficiency, the thermally conductive matrix 42 may have a relatively high thermal conductivity (e.g., greater than 1 W / mK (or about 1 W / mK)). The thermally conductive matrix 42 may include, for example, thermal grease, but in some example embodiments, other thermally conductive materials may be used.

[0055] In some example embodiments, the phase change composite material 44 used in the thermal interface material layer 40 may include a phase change material 45 and a wrapping material 46 that wraps or encloses or surrounds the phase change material.

[0056] In some example embodiments, the phase change material 45 may have the ability to change its physical state within a certain temperature range, thereby releasing or absorbing a relatively large amount of heat during the phase change, and achieving a heating or cooling effect. Taking the solid-liquid phase change as an example, when heated to the melting temperature, a phase change from solid to liquid occurs, and during the melting process, the phase change material 45 absorbs and stores a large amount of latent heat. By including the phase change material 45 in the thermally conductive matrix, the ability of the phase change material 45 to change the physical state can be used to significantly improve the heat dissipation capacity of the PoP packaging structure. The phase change material 45 is selected from a material with a low phase change temperature and a large phase change latent heat. In some example embodiments, the phase change material 45 may be a phase-change liquid. For example, the phase change material 45 may be R-134a or R113, etc., with a maximum boiling point between 60°C (or about 60°C) and 70°C (or about 70°C). However, the example embodiments are not limited thereto, and the properties of the phase change material 45 may be changed according to the application and / or design.

[0057] In some example embodiments, the wrapping material 46 may increase or improve the thermal conductivity of the phase change material 45 and prevent, reduce or minimize leakage of the phase change material 45. The wrapping material 46 may be or may include, for example, a metal (e.g., copper, aluminum, etc.), but is not limited thereto. In some example embodiments where the phase change composite material 44 includes a metal outer layer (e.g., the phase change composite material 44 is a liquid metal phase change material), the phase change composite material 44 may have high thermal conductivity and high heat dissipation efficiency.

[0058] In the thermal interface material layer 40 , the content of the phase change composite material 44 is not specifically limited, but may be determined according to the volume of the phase change material 45 and the capacity of the packaging material 46 .

[0059] In some example embodiments, the heat conductive layer 30 is in contact with the second base substrate 201, and thus, the heat generated by the system-on-chip chip 102 may be transferred upward to the second base substrate 201 through the heat conductive layer 30 (generally, indicated by arrow B) and dissipated. The heat conductive layer 30 may extend to the lower surface of the first base substrate 101 through the via 107 penetrating the SOC package 10, and may be in contact with the thermal interface material layer 40 disposed between the SOC package 10 (e.g., the first base substrate 101) and the substrate SUB. Therefore, the heat generated by the system-on-chip chip 102 may be transferred downward to the first base substrate 101 and the substrate SUB through the heat conductive layer 30 (generally, indicated by arrow A) and dissipated. In some example embodiments, since the thermal conductivity of the thermal interface material layer 40 is greater than the thermal conductivity of the second base substrate 201, the heat generated by the system-on-chip chip 102 may tend to be transferred downward to achieve relatively rapid heat dissipation.

[0060] In some example embodiments, the thermal conductive layer 30 can maintain contact between the SOC package 10 and the second base substrate 201. The thermal interface material layer 40 can maintain contact between the first base substrate 101 and the thermal conductive layer 30 and the substrate SUB. Therefore, the internal contact thermal resistance of the PoP package structure 2 can be reduced and the heat dissipation efficiency can be improved.

[0061] Figure 3 A PoP package structure 3 according to some example embodiments of the present disclosure is shown.

[0062] Figure 3 The PoP package structure 3 can be compared with Figure 2 The PoP package structure is the same as 2, so you can refer to Figure 2 For the best understanding, the same reference numerals denote the same elements and will not be described in detail. In the PoP package structure 3 , the heat conducting layer 30 may include a lower heat conducting layer 31 and an upper heat conducting layer 32 .

[0063] Reference Figure 3 , the lower heat-conducting layer 31 may be disposed between the SOC package 10 and the memory package 20. In some example embodiments, the lower heat-conducting layer 31 may be disposed between the upper surface of the SOC package 10 and the lower surface of the memory package 20. In some example embodiments, the lower heat-conducting layer 31 may be disposed between the second base substrate 201 of the memory package 20 and the first mold layer 104 of the SOC package 10, and may extend through the via 107 penetrating the SOC package 10 to the lower surface of the first base substrate 101 to be connected to the thermal interface material layer 40.

[0064] In some example embodiments, the upper heat conductive layer 32 may be disposed on an upper surface of the memory package 20 (eg, the second molding layer 204 ), and may pass through one or more via holes 207 (eg, the second molding layer 204 ) penetrating the memory package 20 . Figure 3 The upper heat conducting layer 32 may be provided or formed such that its upper surface is at the same level (or height) as the upper surface of the memory package 20 (e.g., the upper surface of the second molding layer 204). In some example embodiments, the upper heat conducting layer 32 may be provided or formed in a recess 211 formed in the upper surface of the second molding layer 204.

[0065] The lower heat conducting layer 31 and the upper heat conducting layer 32 can be the same as those mentioned above. Figure 2 The heat conducting layer 30 described is the same. Therefore, for the sake of brevity of description, its description is omitted.

[0066] In some example embodiments, the lower heat conductive layer 31 and the upper heat conductive layer 32 may include the same high thermal conductive insulating material as each other, or may include different high thermal conductive insulating materials from each other.

[0067] In some example embodiments, the lower heat-conducting layer 31 and the upper heat-conducting layer 32 may cover the surface of the SOC package 10 and the memory package 20, and may penetrate the SOC package 10 and the memory package 20 (e.g., the first base substrate 101 and the second base substrate 201). The heat-conducting materials inside the SOC package 10 and the memory package 20 may be connected to each other (e.g., connected in series), so that a heat dissipation path may be formed. In this way, the heat generated by the system-on-chip chip 102 may not only be transferred upward to the second base substrate 201 and the upper heat-conducting layer 32 through the lower heat-conducting layer 31 (generally, indicated by arrow B) to achieve heat dissipation, but also may be transferred downward to the first base substrate 101, the thermal interface material layer 40, and the substrate SUB through the lower heat-conducting layer 31 (generally, indicated by arrow A) to achieve heat dissipation. As a result, the heat dissipation performance of the PoP packaging structure may be further improved.

[0068] FIG. 4A to FIG. 4J Operations in a method of manufacturing a PoP package structure according to some example embodiments of the present disclosure are shown. For the purpose of description, FIG. 4A to FIG. 4J The manufacturing method shown in Figure 3 The PoP package structure 3 is manufactured and referenced Figure 3 It is understood that for additional embodiments of the method, FIG. 4A to FIG. 4J Additional operations may be provided before, during, and after the operations in the process, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable, or two or more operations may be performed simultaneously.

[0069] Reference Figure 3 and Figure 4A , a SOC package 10 may be provided.

[0070] The SOC package 10 may be a three-dimensional (3D) semiconductor package and may include a first base substrate 101, a system-on-chip chip 102, system-on-chip chip solder balls 103 electrically connecting the system-on-chip chip 102 to internal leads disposed in the first base substrate 101, a first molding layer 104 disposed or formed on the first base substrate 101 and encapsulating or at least partially encapsulating the system-on-chip chip 102 and the system-on-chip chip solder balls 103 on the first base substrate 101, external solder balls 105 disposed on a lower surface of the first base substrate 101 opposite to the system-on-chip chip 102, and connecting solder balls 106 distributed around the periphery of the system-on-chip chip 102 and penetrating the first molding layer 104 and connected to the internal leads in the first base substrate 101.

[0071] A drilling process may be performed on the SOC package 10 to form a via 107 in the SOC package 10. The via 107 may extend through the entire SOC package 10. In some example embodiments, the via 107 may extend from the upper surface of the first mold layer 104 to the lower surface of the first base substrate 101. In some example embodiments, in order to achieve improved heat conduction, the size (e.g., cross-sectional area) of at least a portion of the via 107 in the first base substrate 101 may be greater than the size of the via 107 in the first mold layer 104. However, example embodiments are not limited thereto, and the via size may be changed according to the needs of the application and / or design.

[0072] Reference Figure 3 and Figure 4B , a high thermal conductive insulating material may be coated or formed on the upper surface of the SOC package 10 to form a lower thermal conductive layer 31 .

[0073] During the coating or forming process, the high thermal conductive insulating material may fill the via hole 107 formed in the SOC package 10. In addition, the high thermal conductive insulating material may also be coated or formed on the side surface of the SOC package 10.

[0074] In some example embodiments, the high thermal conductivity insulating material may have improved thermal conductivity and insulation, and may be or may include thermally conductive insulating rubber, alumina ceramic, boron nitride ceramic, etc. However, other materials having desired thermal conductivity and insulation may also be used.

[0075] In some example embodiments, the thickness of the high thermal conductivity insulating material coated on the upper surface of the SOC package 10 may be less than or equal to the gap between the SOC package 10 and the memory package 20. In some example embodiments, the thickness of the high thermal conductivity insulating material coated on the upper surface of the SOC package 10 may be equal to the spacing between the SOC package 10 and the memory package 20 (e.g., completely fill the gap between the SOC package 10 and the memory package 20).

[0076] Reference Figure 3 , Figure 4C and Figure 4D A photoresist pattern 51 having a plurality of openings 53 may be formed on the lower heat conducting layer 31 by first forming a photoresist layer on the lower heat conducting layer 31 and then patterning the photoresist layer to produce a plurality of openings 53. The lower heat conducting layer 31 may be partially removed using the photoresist pattern 51 as an etching mask to form a first recess 55 in the lower heat conducting layer 31. The lower heat conducting layer 31 may be partially removed by a dry etching process. However, other methods may also be used to form the first recess 55.

[0077] The width of the first recess 55 may be determined in consideration of the width of the inter-chip solder ball 205. The position of the first recess 55 may be determined in consideration of the position of the inter-chip solder ball 205. The first recess 55 may be formed to penetrate the lower heat conduction layer 31.

[0078] Reference Figure 4E , the photoresist pattern can be removed or stripped.

[0079] Reference Figure 3 and Figure 4F , a substrate SUB may be provided. In some example embodiments, the substrate SUB may be a printed circuit board (PCB). However, example embodiments are not limited thereto, and other types of substrates may also be used.

[0080] Next, the phase change composite material 44 may be coated on the substrate SUB. The phase change composite material 44 may be arranged on the substrate SUB by vacuum or capillary action. However, in other exemplary embodiments, the phase change composite material 44 may be adhered to or attached to the substrate SUB using an adhesive or other fastener.

[0081] In some example embodiments, Figure 3 As shown in , the position of the phase change composite material 44 on the substrate SUB may be determined based on the position of the external solder balls 105 of the SOC package 10 .

[0082] Reference Figure 3 and Figure 4G , you can Figure 4E The SOC package 10 formed in the Figure 4F The substrate SUB is formed in the process.

[0083] In an embodiment, the SOC package 10 may be positioned on an upper surface of the substrate SUB. For example, external solder balls 105 of the SOC package 10 may be connected to internal leads of the substrate SUB.

[0084] Reference Figure 3 and Figure 4H , a memory package 20 may be provided.

[0085] In some example embodiments, the memory package 20 may include a second base substrate 201, a memory chip 202, a bonding wire 203 electrically connecting the memory chip 202 to an upper surface of the second base substrate 201 facing away from the substrate SUB, a second mold layer 204 disposed on the second base substrate 201 and encapsulating or at least partially encapsulating the memory chip 202 and the bonding wire 203 on the second base substrate 201, and an inter-chip solder ball 205 disposed on a lower surface of the second base substrate 201 facing away from the memory chip 202.

[0086] Next, the memory package 20 may be mounted on Figure 4G In some example embodiments, the inter-chip solder balls 205 of the memory package 20 may be formed in the recesses of the lower heat conducting layer 31 and may be connected to the connection solder balls 106 of the SOC package 10 and the system-on-chip chip 102.

[0087] Reference Figure 3 and Fig. 4I , a photoresist layer may be formed on the second mold layer 204 and patterned to form a plurality of openings, and the second mold layer 204 exposed in the plurality of openings may be partially removed using the photoresist pattern as an etching mask to form recesses 211 in the second mold layer 204. The second mold layer 204 may be partially removed using a dry etching process. However, other suitable processes may also be used, and example embodiments have no limitation in terms of the processes used.

[0088] In the pattern having a plurality of openings, in order to avoid damaging the bonding wires 203 when etching the second mold layer 204 , the position and width of the recess 211 may be determined in consideration of the height and position of the bonding wires 203 .

[0089] In some example embodiments, the recess 211 may not penetrate the second mold layer 204. In other portions of the second mold layer 204, a via hole 207 penetrating the entire memory package 20 (e.g., the entire vertical thickness of the memory package 20) may be formed. In some example embodiments, the via hole 207 may be formed by a drilling process or the like.

[0090] However, in some example embodiments, a drilling process may be performed first to form the via hole 207 penetrating the entire memory package 20. Then, a photoresist process using a photoresist may be performed on the upper surface of the second mold layer 204 to form the recess 211 in the second mold layer 204.

[0091] Reference Figure 3 and Figure 4J , the photoresist pattern on the second mold layer 204 may be removed.

[0092] Next, a high thermal conductive insulating material may be coated or formed on the upper surface of the memory package 20 to form an upper thermal conductive layer 32 .

[0093] During coating or forming, the high thermal conductive insulating material may fill the recess 211 formed in the memory package 20, and may pass through the via 207 and contact the lower thermal conductive layer 31. In addition, the high thermal conductive insulating material may also be coated or formed on the side surface of the memory package 20.

[0094] Next, a thermally conductive matrix 42 may be filled between the SOC package 10 and the substrate SUB so that the thermally conductive matrix 42 covers the phase change composite material 44. In some example embodiments, a thermal interface material layer 40 may be formed. In some example embodiments, the thermally conductive matrix 42 may include, for example, thermal grease, but example embodiments are not limited thereto, and other thermally conductive materials may be used. In some example embodiments, the filling operation may be performed by an electroplating process or a screen printing process, but example embodiments are not limited thereto, and other suitable processes may be used.

[0095] use FIG. 4A to FIG. 4J The operations shown in the figure can produce Figure 3 PoP packaging structure with improved heat dissipation performance 3.

[0096] To manufacture Figure 3 In addition to the above operations, the PoP package structure 3 shown in FIG. 4 may further perform operations such as curing the thermally conductive matrix 42 and / or thinning the upper thermally conductive layer 32 and / or the lower thermally conductive layer 31 to reduce the thickness of the high thermally conductive insulating material. However, other suitable operations for reducing the thickness of the high thermally conductive insulating material are also within the scope of the present disclosure.

[0097] In other example embodiments, the Figure 4F operation, while Figure 4J In the embodiment, the thermal conductive matrix 42 and the phase change composite material 44 are simultaneously filled in the space between the SOC package 10 and the substrate SUB. In addition, the order in which the SOC package 10, the memory package 20 and the substrate SUB are combined with each other can be changed. For example, the thermal conductive matrix 42 and the phase change composite material 44 can be first filled in the space between the SOC package 10 and the substrate SUB. Figure 4E The SOC package 10 and the memory package 20 are combined with each other, and then Figure 4F The substrates SUB are bonded to each other.

[0098] FIG. 4A to FIG. 4JThe manufacturing method according to the example embodiment described is directed to a heat dissipation process by transferring heat generated by the system-on-chip chip 102 upward to the surface of the memory package 20 through the lower heat conductive layer 31 and downward to the substrate SUB through the lower heat conductive layer 31 . Figure 2 The PoP package structure 2 shown in FIG. 2 can be used in some aspects with FIG. 4A to FIG. 4J The same process as shown in is used for manufacturing, and for the sake of brevity, its detailed description is omitted here. Figure 2 In the PoP package structure 2 shown in FIG. 1 , the heat generated by the system-on-chip chip 102 can be transferred downward to the substrate SUB through the heat-conducting layer 30 to achieve heat dissipation, but cannot be transferred upward to the surface of the memory package 20 through the heat-conducting layer 30 .

[0099] According to some example embodiments of the present disclosure, in a PoP package structure, a high thermal conductivity insulating material may cover the surface of the SOC package 10 and the memory package 20, and a vertical series channel may be formed by a via penetrating the SOC package 10 and the memory package 20 (e.g., the first base substrate 101 and the second base substrate 201). The thermally conductive materials (e.g., thermally conductive insulating materials) inside the SOC package 10 and the memory package 20 may be connected in series. The lower portion of the SOC package 10 may be coated with a thermal interface material layer 40 formed of a thermally conductive matrix 42 (e.g., thermally conductive silicone grease) and a phase change composite material 44. Therefore, the heat generated by the system-on-chip chip 102 may be transferred downward to the substrate SUB through the lower thermal conductive layer 31 and the thermal interface material layer 40, and / or may be transferred upward to the surface of the memory package 20 through the lower thermal conductive layer 31 and the upper thermal conductive layer 32 penetrating the memory package 20. Thus, the heat dissipation performance of the PoP package structure may be improved.

[0100] It will be understood that when an element such as a layer, film, region, or substrate (or base) is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "on" another element, it can be above or below or adjacent to the other element (e.g., horizontally adjacent).

[0101] As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. When a statement such as "at least one of..." is placed after a column of elements, the entire element is modified, rather than the individual elements in the column. For example, "at least one of A, B, and C" and similar language (e.g., "at least one of the group consisting of A, B, and C", "at least one of A, B, or C") can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0102] It will be understood that, herein, elements and / or their properties may be described as being "same" or "equal" to other elements, and it will also be understood that elements and / or their properties described herein as being "equivalent", "identical" or "equal" to other elements may be "equivalent", "identical" or "equal" or "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or their properties. Elements and / or their properties that are "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or their properties will be understood to include elements and / or their properties that are equivalent, identical or equal to other elements and / or their properties within manufacturing tolerances and / or material tolerances. Elements and / or their properties that are equivalent or substantially equivalent and / or identical or substantially identical to other elements and / or their properties may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition. Although the terms "same", "equal" or "equivalent" may be used in the description of some example embodiments, it will be understood that there may be some imprecision. Thus, when one element, value, and / or property is referred to as being the same as another element, value, and / or property, it should be understood that the element, value, and / or property is the same as the other element, value, and / or property within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0103] When the term "about (approximately)" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about (approximately)" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified by "about (approximately)" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as in increments of 0.1%.

[0104] Although several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The examples given are considered illustrative rather than restrictive, and are not intended to be limited to the details given herein. For example, various elements or components may be combined or integrated in another system, or certain features may be omitted or not implemented.

Claims

1. A PoP packaging structure, comprising: substrate; A first package is located on the substrate and includes a first base substrate, a first chip located on the first base substrate, and a first molding layer located on the first base substrate and encapsulating the first chip; a second package located on the first package and comprising a second base substrate, a second chip located on the second base substrate, and a second molding layer located on the second base substrate and at least partially encapsulating the second chip; A first heat-conducting layer is located between an upper surface of the first package and a lower surface of the second package; as well as The thermal interface material layer is located between the lower surface of the first package and the upper surface of the substrate, The first heat conducting layer passes through a via hole defined in the first package and contacts the thermal interface material layer.

2. The PoP packaging structure according to claim 1, wherein: The first thermally conductive layer includes a thermally conductive insulating material.

3. The PoP packaging structure according to claim 1, further comprising: A second heat conducting layer is located on the upper surface of the second package, The second heat-conducting layer contacts the first heat-conducting layer through a via hole penetrating the second package.

4. The PoP packaging structure according to claim 3, wherein: The second thermally conductive layer includes a thermally conductive insulating material.

5. The PoP packaging structure according to claim 1, wherein: The thermal interface material layer comprises a thermal conductive matrix and a phase change composite material dispersed in the thermal conductive matrix.

6. The PoP packaging structure according to claim 5, wherein: The phase change composite material comprises a phase change material and a wrapping material wrapping the phase change material.

7. A method for manufacturing a PoP packaging structure, the method comprising: preparing a first package, the first package comprising a first base substrate, a first chip located on the first base substrate, and a first molding layer located on the first base substrate and at least partially encapsulating the first chip; performing a drilling process on the first package to form a first via hole penetrating the first package; coating a thermally conductive insulating material on an upper surface of the first package to form a first thermally conductive layer; coating a phase change composite material on an upper surface of a substrate; Combining a first package having a first heat-conducting layer formed on its upper surface and a substrate having a phase-change composite material coated on its upper surface; preparing a second package, the second package comprising a second base substrate, a second chip located on the second base substrate, and a second molding layer located on the second base substrate and at least partially encapsulating the second chip; bonding the second package and the first package bonded to the substrate to each other; as well as Filling a thermally conductive matrix in the space between the substrate and the first package to form a thermal interface material layer, The first heat-conducting layer passes through the first via hole and contacts the thermal interface material layer.

8. The method according to claim 7, further comprising: After forming the first heat conducting layer, an etching process is performed on an upper surface of the first heat conducting layer to form a first recess.

9. The method according to claim 7, further comprising: performing an etching process on the upper surface of the second package to form a second recess; performing a drilling process on the second package to form a second via hole penetrating the second package; as well as coating a thermally conductive insulating material on the upper surface of the second package to form a second thermally conductive layer, The second heat conducting layer fills the second recess and the second via hole, and passes through the second via hole to contact the first heat conducting layer.

10. The method according to claim 7, wherein: The phase change composite material comprises a phase change material and a wrapping material wrapping the phase change material.

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