Sensorless SiC MOSFET Hard Switching Loss Measurement Method and System

Abstract

The application discloses a SiC MOSFET hard switching loss measurement method and system without current sensor, cancels current measurement on the basis of a double-pulse measurement method, and obtains a current waveform by analyzing voltage waveform variation characteristics. Measurement of a drain-source voltage is very simple, does not cause influence on layout and volume of a converter, and measurement time is very short. The method can be popularized to any topology with an equivalent half-bridge commutation loop.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a sensorless method and system for measuring the hard switching losses of SiC MOSFETs. Background Technology

[0002] SiC MOSFETs possess excellent electrical and thermal performance. Compared to Si devices, they exhibit lower switching losses and allow for higher switching frequencies, thereby reducing passive device size and achieving higher efficiency and power density, making them widely used in automotive, aerospace, and military applications. However, SiC devices remain a major source of power converter losses, and accurate assessment of these losses significantly impacts cooling systems. Device losses are categorized into conduction losses and switching losses. Conduction losses can be calculated from the on-resistance given in the datasheet; however, switching losses are not easily obtained because they are also affected by the drive circuit, complementary transistors, and parasitic parameters of the power loop. Therefore, even under identical operating conditions, actual losses often differ from, and can vary considerably from, the results given in the datasheet.

[0003] Currently, there are two main methods for measuring switching losses: electrical measurement and thermal measurement. Electrical measurement primarily involves a double-pulse test to measure the drain-source voltage and drain-source current of the device. Switching loss is calculated as the integral of the voltage-current product over a defined switching time. The advantage of this method is its short measurement time and minimal external equipment requirements. However, its disadvantages include the need for high-bandwidth probes and oscilloscopes due to the faster switching speed of SiC devices, as well as the need to correct for the time delay between voltage and current probes. Thermal measurement determines the total loss by measuring the heat dissipation of the device under test without measuring the transient switching process, thus requiring less bandwidth from the measurement equipment. However, it relies heavily on the accuracy of the thermal resistance network model and the extraction of conduction losses, and the measurement time is very long. A common drawback of both methods is that the loss measurement results are only applicable to the prototype used in the test and cannot be applied to actual power converters, because even with the same switching devices, the power circuit and drive circuit are unlikely to be completely identical. Building a test platform in an actual converter is also impractical. Thermal measurements require large heat sinks, and the converter design does not reserve space for additional measurement equipment. Current probes in electrical measurements are limited by bandwidth and power device packaging, making a coaxial shunt a better choice. However, it is intrusive, introducing additional parasitic inductance and altering the converter's original power circuit. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method and system for measuring the hard switching loss of SiCMOSFET without current sensor, which addresses the shortcomings of the prior art and measures the hard switching loss of the device without affecting the size of the converter or the power circuit.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a sensorless SiC MOSFET hard switching loss measurement method, which uses a dual-pulse test platform for measurement. The dual-pulse test platform includes a half-bridge circuit, the two ends of which are connected to a DC source; the half-bridge circuit includes two SiC MOSFETs connected in series in phase; the upper SiC MOSFET of the half-bridge circuit is connected in parallel with the load inductor; the method includes:

[0006] The hard-turn-off loss of a SiC MOSFET can be calculated using the following formula:

[0007]

[0008] The hard-turn-on loss of a SiC MOSFET can be calculated using the following formula:

[0009]

[0010] Among them, t vr_off It is the voltage rise time during turn-off, V dc The DC source voltage is t. vr_off It is the voltage rise time t when the lower transistor is turned off. cf_off It is the time when the current drops rapidly when the lower transistor is turned off, V dc It is the DC bus voltage, I load It is the magnitude of the load current at the moment of switching, Q oss1 It is the amount of charge stored in the junction capacitance of the upper transistor;

[0011] t cr_on It is the rapid rise time of the current when the lower transistor of the half-bridge circuit turns on, t rr_on It is the reverse recovery time, t vf_on It is the rapid voltage drop time when the lower transistor of the half-bridge circuit turns on, ΔV max This is the maximum value of the voltage across the parasitic inductance of the circuit when the drain-source current rises rapidly during hard turn-on. As an inventive concept, this invention also provides a sensorless SiC MOSFET hard switching loss measurement system, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the steps of the above method.

[0012] Compared with existing technologies, the advantages of this invention are as follows: This invention can reduce the impact of measurement equipment on the overall layout and design of the converter, and also reduce the measurement time. Based on the dual-pulse measurement method, this invention eliminates current measurement and obtains the current waveform by analyzing the voltage waveform change characteristics. The measurement of drain-source voltage is very simple, does not affect the layout and size of the converter, and the measurement time is very short. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the equivalent circuit of a dual-pulse test platform;

[0014] Figure 2(a) is a simplified schematic diagram of the hard shutdown process;

[0015] Figure 2(b) is a simplified schematic diagram of the hard-opening process;

[0016] Figure 2(c) shows the waveform of the hard shutdown process;

[0017] Figure 2(d) shows the waveform during the hard-opening process;

[0018] Figure 3 (a) is a simplified schematic diagram of the hard-shutdown waveform;

[0019] Figure 3 (b) is a simplified schematic diagram of the hard-turn-on waveform;

[0020] Figure 4 The actual voltage waveform and its fitting function;

[0021] Figure 5(a) shows R g =1Ω,I ds =20A,V ds Comparison of the proposed method and experimental results under operating conditions of 500-800V;

[0022] Figure 5(b) shows R g =1Ω,I ds =5~20A,V ds Comparison of the proposed method and experimental results under 800V operating conditions;

[0023] Figure 5(c) shows R g =4.7Ω,I ds =5~20A,V ds Comparison of the proposed method and experimental results under 800V operating conditions;

[0024] Figure 5(d) shows R g =1Ω,I ds =5~20A,V ds =800V, comparison of the proposed method with experimental results after increasing the parasitic inductance of the power circuit;

[0025] Figure 5(e) shows R g =1Ω,I ds =15~60A,V ds =800V, the proposed method and experimental results were compared after replacing the device under test. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The working principle of the proposed method is analyzed based on a dual-pulse test circuit.

[0028] The equivalent circuit of the dual-pulse test platform is as follows: Figure 1 As shown, this includes SiC devices S1 and S2, and device package lead inductance L. s1 L s2 L d1 L d2 Device junction capacitance C ds1 C ds2 Decoupling capacitor C de and its parasitic inductance L de PCB circuit inductance L PCB(Dev-Dec) L PCB(Dec-Bus) Load inductance L load DC source V dc For convenience, L will be used below. σ Replace L PCB(Dev-Dec) L de L d1 and L s1 The sum, as shown in equation (1). The drain-source voltage and drain-source current of the device under test are named v. ds2 and i ds2 The principle of the dual-pulse test is as follows: two pulse drive signals are sent to the tube under test S2. The first pulse charges the load inductor to a specified current. By observing the turn-off time of the first pulse and the turn-on time of the second pulse, the hard-switching characteristics of the device under specified voltage and current can be obtained.

[0029] L σ =L PCB(Dev-Dec) +L de +L d1 +L s1 (1)

[0030] A simplified schematic diagram of the hard turn-off process is shown in Figure 2(a), and the corresponding voltage and current waveforms are shown in Figure 2(c).

[0031] Before t1: the lower transistor S2 is turned on, the DC source charges the load inductor, the load current rises linearly, and reaches the set current value at time t1.

[0032] Between t1 and t2: the load current is divided into two parts; one part still flows through the channel of S2 and to the junction capacitance C. ds2 During charging, another portion flows through the junction capacitance C of S1. ds1 This causes the voltage across its terminals to drop. At time t2, v ds2 Reaching bus voltage, C ds1 The charge is completely discharged.

[0033] Between t2 and t3: The channel current of the lower transistor S2 gradually decreases until it reaches zero; the body diode of the upper transistor S1 conducts, and its current gradually increases to the load current. The large rate of current change results in a large voltage component across the parasitic inductance of the circuit. This voltage, along with the DC bus voltage, is applied to S2, causing v... ds2 A voltage overshoot occurs, and the magnitude of the overshoot voltage is:

[0034]

[0035] After t3: The load current is fully commutated to the body diode of S1, and the junction capacitance C ds2 It resonates at a high frequency with the parasitic inductance of the circuit, and the resonant frequency is

[0036]

[0037] Furthermore, it is worth noting that the equivalent circuit between the two points measured by the voltage probe at this time is the package lead inductance L. d2 L s2 junction capacitance C ds2 The series connection. At the resonant frequency f r Below this, the overall structure is capacitive. Therefore, the drain-source current i ds2 Leading drain-source voltage v ds2 Ninety degrees.

[0038] A simplified schematic diagram of the hard-opening process is shown in Figure 2(b), and the corresponding voltage and current waveforms are shown in Figure 2(d).

[0039] Before t4: The load inductor current freewheels through the body diode of the upper transistor S1.

[0040] Between t4 and t5: The channel of the lower diode S2 is turned on, and the load current gradually migrates from the body diode of S1. At this time, a large additional voltage component is generated on the parasitic inductance of the circuit, which cancels out the DC bus voltage, making v ds2 The voltage is lower than the bus voltage, and its expression is the same as that of equation (2). At time t5, the load current is completely transferred.

[0041] Between t5 and t6: The charge stored in the body diode of S1 is released, forming a reverse recovery current, which flows through S2 along with the load current. At this time, the voltage v across S2 is... ds2The voltage remains relatively high. Reverse recovery ends at time t6.

[0042] Between t6 and t7: the junction capacitance C of S2 ds2 Discharge through its own channel, while decoupling capacitor C de The junction capacitance C of S1 ds1 Charging. ds2 It drops rapidly, falling to zero at time t7.

[0043] After t7: The DC source continues to charge the load inductor, accompanied by the parasitic capacitance C. ds1 It resonates with the parasitic inductance of the circuit.

[0044] At this point, the equivalent circuit between the two points measured by the voltage probe is the package lead inductance L. d2 L s2 and on-resistance R ds(on) Because of the high resonant frequency and low on-resistance, the series connection of the two elements is close to a purely inductive circuit. Therefore, the drain-source voltage v0 is... ds2 Leading drain-source current i ds2 Ninety degrees.

[0045] The analysis of the commutation process reveals a correlation between the voltage and current changes at each stage. Therefore, the current waveform can be derived by analyzing the voltage waveform.

[0046] The loss measurement method of this invention is described based on the above analysis of the commutation process:

[0047] The voltage and current waveforms are fitted using a phased function. To simplify the fitting function, the zero point of the abscissa for each phase is established at its own starting point.

[0048] Simplified diagram of hard-shutdown waveform as follows Figure 3 As shown in (a).

[0049] During the t1 to t2 phase, the load current supplies C ds2 Charging and C ds1 Discharge, v ds2 Approximately linear increase, i ds2 Equals the load current minus the current supplied to C ds1 The discharge current decreases linearly at a small rate of change. Figure 3 The area of ​​the purple shaded region in (a) is equal to C. ds1 The amount of stored charge can be obtained from the datasheet. The voltage-current fitting function expression and the magnitude of the loss at this stage are as follows:

[0050]

[0051] Where t vr_offIt is the voltage rise time during turn-off, which can be approximated as v. ds2 From 5% to 100% V dc Time spent.

[0052] During the t2 to t3 phase, v ds2 Ignoring the oscillation voltage, it is approximated as the DC side voltage V. dc i ds2 It decreases linearly to zero with a relatively large rate of change. The voltage and current functional expressions and the magnitude of the loss during this stage are as follows:

[0053]

[0054] Where t cf_off It is the time when the channel current drops rapidly during turn-off, which can be considered as the time from t vr_off End to i ds2 The time taken for the current to drop to zero. However, since the current waveform is not actually acquired, the current zero-crossing point needs to be found through voltage characteristics. As mentioned above, after time t3 (i.e., when the channel is completely turned off), the loop parasitic inductance and junction capacitance C... ds2 Resonance occurs. Therefore, the zero-crossing point of the corresponding current is half a resonance cycle preceding the first trough of the voltage oscillation waveform.

[0055] The expression for calculating hard turn-off loss is as follows:

[0056]

[0057] Simplified diagram of hard-on waveform as follows Figure 3 As shown in (b).

[0058] During the t4 to t5 phase, the load current rapidly shifts to the S2 channel, i ds2 The voltage rises approximately linearly. The voltage drop across the parasitic inductance of the loop is ΔV(t). The voltage-current function expressions and the magnitude of the losses during this stage are as follows:

[0059]

[0060] Where t cr_on It is the rapid rise time of the channel current of S2 when it is turned on, which can be considered as the time from v ds2 Equal to 95% of V dc to i ds2 This equals the time taken by the load current. ds2 The timing of load current arrival also needs to be obtained through voltage change characteristics. Decoupling capacitors are typically ceramic or film capacitors with low parasitic inductance, and are placed close to the half-bridge. Therefore, L σ Approximately equal to L s1 +L d1 According to the principle of magnetic flux conservation, the integral of ΔV(t) over time equals L.σ with I load The product of t. Solve the simultaneous equations based on this to find t. cr_on As shown in the following formula

[0061]

[0062] During the t5 to t6 phase, the body diode of S1 is reverse biased and withstands a small reverse voltage, releasing the charge stored during forward conduction, while the voltage of S2 remains at V. dc -ΔV max During the t6 to t7 phase, S1 reverse recovery ends, and the junction capacitance C... ds1 The charging current and the load current are superimposed and flow through the channel of S2, the junction capacitance C ds2 The charge is released through the internal channel of S2, v ds2 The decrease is approximately linear. Since the reverse recovery current is small, only the junction capacitance C is considered during the t5 to t7 stage. ds1 Charging current. The actual waveform shows that i0 is the charging current during this stage. ds2 Approximating a sine wave with a DC component superimposed on half a cycle, the current fitting function expression is:

[0063]

[0064] The actual voltage waveform approximates the upper base and legs of a right trapezoid, and is quite close to a cubic function, such as... Figure 4 As shown. To reduce the number of undetermined coefficients in the fitted function, the center of symmetry of the cubic function lies on the ordinate axis. The cubic function passes through (0, V). dc -ΔV max ) and (t rr_on +t vf_on Two points (0, 0) are given, and the slope of the slope is at t. rr_on When the time interval is zero, we can obtain the simultaneous equations (10). The undetermined coefficients are obtained as equation (11).

[0065]

[0066] The loss expression for stage t5 to t7 is as follows:

[0067]

[0068] Where t rr_on t vf_on These are the reverse recovery time and v. ds2 Rapid descent time. t rr_on It can be considered as starting from t cr_on The end of the string to v ds2 The time it takes for the price to start to plummet, t vf_on It can be considered as starting from v ds2 It started to plummet to Vds2 equal to 5% of V dc The time spent.

[0069] The expression for calculating hard turn-on loss is as follows:

[0070]

[0071] From the expressions for calculating hard turn-off and hard turn-on losses, we can see that the variable V dc and I load Determined by actual working conditions, variable Q oss1 Provided by the device datasheet, the remaining variables are obtained entirely from voltage measurements, without the need for a current sensor.

[0072] As shown in Figure 5, experimental results demonstrate that the sensorless SiCMOSFET hard switching loss measurement method provided in this embodiment of the invention can measure the hard switching loss of the device without using a current probe or affecting the converter size and layout. The measurement error of the total loss is within 5%, meeting the accuracy requirements.

[0073] Example 2

[0074] Embodiment 2 of the present invention provides a measurement system corresponding to Embodiment 1 above. The measurement system can be a processing device for a client, such as a mobile phone, a laptop, a tablet computer, a desktop computer, etc., to execute the method of the above embodiments.

[0075] The measurement system of this embodiment includes a memory, a processor, and a computer program stored in the memory; the processor executes the computer program in the memory to implement the steps of the method of Embodiment 1 described above.

[0076] In some implementations, the memory may be high-speed random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device.

[0077] In other implementations, the processor can be any type of general-purpose processor, such as a central processing unit (CPU) or a digital signal processor (DSP), and there is no limitation here.

[0078] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0079] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A current sensorless SiC MOSFET hard switching loss measurement method, measured by a double pulse test platform, the double pulse test platform comprising a half-bridge circuit, the half-bridge circuit being connected with a direct current source at both ends; the half-bridge circuit comprising two SiC MOSFETs connected in series in phase; the SiC MOSFET on the half-bridge circuit is connected in parallel with a load inductance; characterized in that, The method comprises: The SiC MOSFET hard-off loss is calculated by using the following formula: The SiC MOSFET hard-on loss is calculated by using the following formula: Wherein, V dc is the DC source voltage, t vr_off is the voltage rise time when the lower tube is off, t cf_off is the current fast drop time when the lower tube is off, V dc is the DC bus voltage, I load is the load current size at the switching moment, Q oss1 is the charge amount stored by the upper tube junction capacitor; t cr_on is the current fast rise time when the lower transistor of the half-bridge circuit is turned on, t rr_on is the reverse recovery time, t vf_on is the voltage fast fall time when the lower transistor of the half-bridge circuit is turned on, ΔV max is the maximum voltage on the loop parasitic inductance when the drain-source current rapidly rises during the hard turn-on.

2. The current-sensor-less SiC MOSFET hard switching loss measurement method according to claim 1, characterized by, t vr_off for v ds2 from 5% v dc to 100% v dc time spent; v ds2 for the drain-source voltage of the lower transistor.

3. The current sensor-less SiC MOSFET hard switching loss measurement method according to claim 1 or 2, characterized by, t cf_off To find the time taken for the drain-source current i vr_off to fall to zero at the end of the time interval t ds2 .

4. The current sensor-less SiC MOSFET hard switching loss measurement method according to claim 1 or 2, characterized by, t rr_on From t cr_on The end time to the drain-source voltage v of the lower transistor ds2 The time it takes for the price to start to plummet, t vf_on It is the drain-source voltage V of the lower transistor. ds2 It started to plummet to V ds2 Equal to 5% V dc The time spent.

5. The current-sensor-less SiC MOSFET hard switching loss measurement method of claim 1, wherein, t cr_on is the drain-source voltage v ds2 equal to 95% V dc is the drain-source current i ds2 is the time taken by the load current.

6. A current sensor-less SiC MOSFET hard switching loss measurement system comprising a memory, a processor, and a computer program stored on the memory; wherein, The processor executes the computer program to realize the steps of the method in any one of claims 1-5.

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