Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a plurality of semiconductor block structures arranged along a first direction, and a signal line lead-out structure located on at least one side end region of the semiconductor block structure. The signal line lead-out structure comprises a plurality of signal lines extending along a second direction and arranged at intervals along a third direction. The signal line comprises a main extension part and a lead-out end part located at at least one end of the main extension part. In the signal line lead-out structure, the orthogonal projections of the lead-out end parts of any two signal lines on a substrate do not overlap, and the orthogonal projections of the main extension parts of any two signal lines on the substrate overlap. In the third direction and from the side close to the substrate to the side away from the substrate, the lengths of the signal lines decrease in turn or increase in turn. The process flow of the semiconductor structure is short, the manufacturing cost is low, and each signal line is easy to lead out.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Memory is widely used in mobile devices such as mobile phones and tablet computers due to its small size, high integration level and fast transmission speed. For example, a 2T0C (2 Transistor 0 Capacitor) uses two vertical structure transistors as a unit structure, one of which is connected to the gate of the other, and the gate capacitance is used to store charge and change the transistor transconductance to store information. This structure can increase the storage density by continuously increasing the number of stacked layers in the vertical direction without reducing the critical size, but it needs to make each layer of device before making the next layer of device, which has a long process flow, high cost, and difficulty in signal line extraction.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The present disclosure provides a semiconductor structure and a preparation method thereof, which can shorten the process flow, reduce the manufacturing cost, and facilitate the extraction of each signal line.

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided, which is prepared on a substrate, and includes a plurality of semiconductor block structures arranged at intervals along a first direction, each semiconductor block structure including two side end regions in the first direction, at least one side end region of each semiconductor block structure being provided with a signal line extraction structure, the signal line extraction structure including:

[0006] a plurality of signal lines extending along a second direction and arranged at intervals along a third direction, the first direction and the second direction being parallel to the plane on which the substrate lies, the first direction intersecting the second direction, and the third direction being perpendicular to the plane on which the substrate lies; each signal line including a main extension part and an extraction end part at at least one end of the main extension part; in the signal line extraction structure, the projection of the extraction end parts of any two signal lines on the substrate does not overlap, and the projection of the main extension parts of any two signal lines on the substrate does overlap; in the third direction and from the side close to the substrate to the side away from the substrate, the length of each signal line decreases or increases in turn;

[0007] The semiconductor block structure comprises a plurality of semiconductor shared units arranged along the second direction and the third direction, the semiconductor shared units comprise first storage units and second storage units, the first storage units and the second storage units are distributed in mirror image along the first direction, the first storage units and the second storage units share the same source-drain unit layer, the first storage units and the second storage units each comprise a first transistor and a second transistor, a first gate of the first transistor is connected with the signal line, and the first transistor and the second transistor are both ring channel structure transistors with the channel parallel to the plane where the substrate is located.

[0008] In an example embodiment of the present disclosure, the signal line lead-out structure further comprises:

[0009] a connection line connected with the lead-out end of the signal line, the connection line extends along the third direction, and adjacent two connection lines are insulated;

[0010] In the third direction and from the side close to the substrate to the side away from the substrate, when the length of each signal line decreases in turn, the connection line is connected with the side of the lead-out end away from the substrate; or, in the third direction and from the side close to the substrate to the side away from the substrate, when the length of each signal line increases in turn, the connection line is connected with the side of the lead-out end close to the substrate.

[0011] In an example embodiment of the present disclosure, the two side end regions of the semiconductor block structure are each provided with the signal line lead-out structure; each signal line comprises two lead-out ends located at two ends of the main body extension part, and the size of each lead-out end in the second direction is the same.

[0012] In an example embodiment of the present disclosure, the material of the signal line comprises polysilicon, and the lead-out surface of at least the lead-out end of the signal line is provided with a metal silicide layer.

[0013] In an example embodiment of the present disclosure, the lead-out end is provided with a metal silicide layer on the side surface away from the center of the semiconductor block structure along the second direction.

[0014] In an example embodiment of the present disclosure, the signal line is provided with a metal silicide layer on the side surface away from the center of the semiconductor block structure along the first direction.

[0015] In an example embodiment of the present disclosure, the signal line is a word line, and the material of the metal silicide layer is CoSi2, TiSi2 or NiSi.

[0016] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising the following steps:

[0017] providing a substrate;

[0018] manufacturing a plurality of semiconductor block structures on the substrate, the semiconductor block structures being arranged along a first direction and comprising two side end regions in the first direction, at least one side end region of the semiconductor block structures being provided with a signal line lead-out structure;

[0019] wherein the method for manufacturing the signal line lead-out structure comprises:

[0020] forming a laminated structure on the signal line lead-out structure region of the substrate, the laminated structure comprising insulating material layers and conductive material layers alternately laminated along a third direction multiple times; wherein a projection of the signal line lead-out structure region of the substrate and the side end region of the semiconductor block structures on the substrate overlaps, the insulating material layers and the conductive material layers both extend along a second direction, the first direction and the second direction are both parallel to the plane where the substrate is located, the first direction intersects the second direction, and the third direction is perpendicular to the plane where the substrate is located;

[0021] processing the laminated structure by using a trimming etching process to form a plurality of signal lines extending along the second direction and arranged along the third direction, the signal lines comprising a main body extension and a lead-out end portion located at at least one end of the main body extension; in the signal line lead-out structure, the normal projection of the lead-out end portions of any two signal lines on the substrate does not overlap, and the normal projection of the main body extensions of any two signal lines on the substrate overlaps; in the third direction and from the side close to the substrate to the side away from the substrate, the length of each signal line decreases in turn.

[0022] In an exemplary embodiment of the present disclosure, the number of conductive material layers is n, the number of insulating material layers is n+1, and n>2; in the third direction, each of the conductive material layers is defined as the 1st to nth conductive material layer from top to bottom, and each of the insulating material layers is defined as the 1st to n+1th insulating material layer from top to bottom; processing the laminated structure by using a trimming etching process to form a plurality of signal lines extending along the second direction and arranged along the third direction comprises the following steps:

[0023] S1, forming a first pattern mask layer on the laminated structure, the length of the first pattern mask layer in the second direction is less than the length of the 1st conductive material layer, and the normal projection of the first pattern mask layer on the laminated structure does not overlap with at least one end portion of the 1st conductive material layer;

[0024] S2, using the first patterned mask layer as a mask, the first insulating material layer and the first conductive material layer are etched to expose at least one end of the second insulating material layer, forming a first patterned stacked structure;

[0025] S3, a second pattern mask layer is formed on the first patterned stacked structure. The length of the second pattern mask layer in the second direction is less than the length of the first conductive material layer remaining after the previous etching, and the orthographic projection of the second pattern mask layer on the substrate does not overlap with at least one end of the first conductive material layer remaining after the previous etching.

[0026] S4, using the second patterned mask layer as a mask, the exposed second layer of insulating material and the second layer of conductive material are etched to expose at least one end of the next layer of insulating material, forming a second patterned stacked structure;

[0027] Repeat steps S3-S4 until at least one end of the nth insulating material layer is exposed, forming the (n-1)th patterned stacked structure; each of the remaining conductive material layers after etching is used as a signal line, at least one exposed end of the signal line is used as the lead-out end, and the portion of the signal line that is not the lead-out end is used as the main body extension.

[0028] In one exemplary embodiment of this disclosure, the method for fabricating the signal line lead-out structure further includes:

[0029] A cover layer is formed on the side of each lead-out end away from the substrate;

[0030] The cover layer is etched to form a plurality of connection holes penetrating the cover layer along the third direction, wherein the orthographic projections of different connection holes on the substrate at least partially overlap with the orthographic projections of different lead-out ends on the substrate;

[0031] Conductive material is deposited within the connection hole to form a connection wire.

[0032] In one exemplary embodiment of this disclosure, the signal line is made of polysilicon, the surface of the lead-out end away from the substrate is the lead-out surface, and the method for fabricating the signal line lead-out structure further includes:

[0033] Remove the insulating material layer covering each of the lead-out ends in the (n-1)th patterned stack-up structure to expose the lead-out surfaces of the lead-out ends in the signal lines and the side surfaces of the signal lines away from the center of the semiconductor block structure along the second direction;

[0034] A metal silicide layer is formed on the leading-out surface of the leading-out end portion and the side surface of the signal line away from the center of the semiconductor block structure in the second direction.

[0035] In an exemplary embodiment of the present disclosure, the material of the signal line comprises polysilicon, the leading-out surface of the leading-out end portion away from the surface of the substrate, and the insulating material filled between two adjacent semiconductor block structures, and the preparation method of the signal line leading-out structure further comprises:

[0036] The insulating material layer covering the leading-out surface of each leading-out end portion and the insulating material between two adjacent semiconductor block structures in the n-1 patterning layer structure are removed to expose the leading-out surface of each leading-out end portion, the side surface of the signal line away from the center of the semiconductor block structure in the second direction, and the side surface of each signal line away from the center of the semiconductor block structure in the first direction;

[0037] A metal silicide layer is formed on the leading-out surface of the leading-out end portion, the side surface of the signal line away from the center of the semiconductor block structure in the second direction, and the side surface of the signal line away from the center of the semiconductor block structure in the first direction.

[0038] The semiconductor structure and the preparation method thereof of the present disclosure, a plurality of semiconductor block structures can be distributed on the surface of the substrate in the first direction parallel to the substrate. During the process, a plurality of semiconductor block structures can be formed at the same time. In this process, there is no need to wait for the process of the previous semiconductor block structure to be completed before forming another semiconductor block structure. The process flow is shorter and the manufacturing cost is lower. At the same time, in the signal line leading-out structure of each semiconductor block structure, the orthogonal projection of the leading-out end portion of any two signal lines on the substrate does not overlap, and the orthogonal projection of the main body extension of any two signal lines on the substrate overlaps. In the third direction and from the side close to the substrate to the side away from the substrate, the length of each signal line decreases or increases in turn, so that each signal line arranged in the third direction is in a stepped shape. The stepped signal line structure extends in the second direction and is arranged in the first direction. The signal line leading-out of a plurality of semiconductor block structures arranged in the first direction is realized. Moreover, the leading-out end portion of each signal line is exposed, which can facilitate subsequent preparation of a connection line for electrically leading out the signal line on each leading-out end portion at the same time through the same process, which helps to further shorten the process flow and reduce the manufacturing cost. In addition, the stepped design allows the signal line to be arranged more closely in the third direction, which helps to improve the space utilization.

[0039] The semiconductor structure and the preparation method thereof, the material of the signal line in the signal line lead-out structure includes polysilicon, which avoids the problem that the use of metal material (for example, tungsten / titanium nitride) causes defects or metal residues when forming a stepped signal line structure by etching; a metal silicide layer is formed on at least the lead-out surface of the lead-out end portion, which reduces the contact resistance between the signal line and the connecting line, and realizes low-resistance connection.

[0040] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0041] The drawings incorporated into the specification and forming part of the specification, show embodiments consistent with the present disclosure, and together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative labor for those skilled in the art.

[0042] Figure 1 It is a schematic diagram of the semiconductor structure in the embodiment of the present disclosure.

[0043] Figure 2 It is a schematic diagram of the semiconductor common unit structure in the embodiment of the present disclosure.

[0044] Figure 3 It is a schematic diagram of the metal silicide layer covering the lead-out surface of the lead-out end portion in the embodiment of the present disclosure.

[0045] Figure 4 It is a schematic diagram of the metal silicide layer covering the lead-out surface of the lead-out end portion and the two side surfaces distributed along the second direction in the lead-out end portion in the embodiment of the present disclosure.

[0046] Figure 5 It is a schematic diagram of the metal silicide layer covering the lead-out surface of the lead-out end portion, the two side surfaces distributed along the second direction in the lead-out end portion, and the side surface of the signal line away from the center of the semiconductor block structure along the first direction in the embodiment of the present disclosure.

[0047] Figure 6 It is a schematic diagram of the structure after step S1201 is completed in the embodiment of the present disclosure.

[0048] Figure 7 It is a schematic diagram of the insulating filling layer in the embodiment of the present disclosure.

[0049] Figure 8 It is a schematic diagram of the sub-pattern in the embodiment of the present disclosure.

[0050] Figure 9 It is a schematic diagram of the first opening and the signal line containing groove in the embodiment of the present disclosure.

[0051] Figure 10 is along Figure 9 is a cross-sectional view along the AA direction.

[0052] Figure 11 is a schematic view of the insulating material in the embodiment of the present disclosure.

[0053] Figure 12 is a schematic view after step S220 is completed in the embodiment of the present disclosure.

[0054] Figure 13 is a schematic view of the Xth pattern mask layer in the embodiment of the present disclosure.

[0055] Figure 14 is a schematic view of the cover layer in the embodiment of the present disclosure.

[0056] Figure 15 is a schematic view of the connection hole in the embodiment of the present disclosure.

[0057] Figure 16 is a cross-sectional view of the connection line in the embodiment of the present disclosure.

[0058] Explanation of reference signs:

[0059] 1, substrate; 100, semiconductor block structure; 2, first memory cell; 3, second memory cell; 4, source-drain layer; 410, source-drain cell layer; 10, first transistor; 101, first gate; 102, first gate dielectric layer; 103, first semiconductor layer; 20, second transistor; 201, second gate; 202, second gate dielectric layer; 203, second semiconductor layer; 5, signal line; 51, main body extension; 52, lead-out end; 53, metal silicide layer; 510, conductive material layer; 6, first bit line; 7, second bit line; 8, insulating material; 9, protective layer; 1030, stacked structure; 301, insulating material layer; 302, semiconductor material layer; 303, insulating filling layer; 30, connection line; 40, patterned film layer stacked structure; 401, first pattern; 402, second pattern; 4021, sub-pattern; 403, first opening; 404, first transistor accommodating groove; 405, signal line accommodating groove; 50, etching stop layer; 60, cover layer; 61, connection hole; 70, Xth pattern mask layer; x, first direction; y, second direction; z, third direction. DETAILED DESCRIPTION

[0060] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example implementations to those skilled in the art. Like reference numerals refer to like elements throughout the various figures, and thus a detailed description of the same will not be repeated. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0061] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not intended to be limiting. It is to be understood that if the icon were turned over, such that the upper component became the lower component, the described "upper" component would then become the "lower" component. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" on the other structure or that the structure is "indirectly" on the other structure via another structure.

[0062] The terms "a", "an", "the", "said", and "at least one" are used to refer to one or more elements / components / etc.; the terms "comprises", "comprising", "has", "having", "includes", "including", "contains", "containing" and "consists of are used to mean including, but not limited to, the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels, and do not imply any order, quantity, or importance.

[0063] With the rapid development of the semiconductor industry, the demand for storage density of memory is increasing. However, the traditional 1T1C (i.e., one transistor and one capacitor) structure faces severe challenges in improving storage density. The key size reduction is limited by the lithography capability limit of the lithography machine, and it is difficult to continue to reduce. At the same time, the 1T1C structure is difficult to realize three-dimensional stacking, and the improvement of storage density is severely restricted by the key size. In order to break this bottleneck, the research focus of those skilled in the art is turned to the 2T0C (i.e., two transistors, no capacitor) structure. The existing vertical structure of 2T0C DRAM memory, the transistor channel in the storage unit is perpendicular to the substrate, and the storage density is significantly improved by sequentially stacking the storage functional layer. However, the process flow of the sequentially stacked storage functional layer is long, and the manufacturing cost is high.

[0064] The semiconductor structure provided by the embodiments of the present disclosure is prepared on a substrate 1, Figure 1 A schematic diagram of the semiconductor structure of the present disclosure is shown, as Figure 1As shown, the semiconductor structure includes a plurality of semiconductor block structures 100 arranged in the first direction x, the semiconductor block structure 100 includes two side end regions in the first direction x, at least one side end region of the semiconductor block structure 100 is provided with a signal line lead-out structure, the signal line lead-out structure includes:

[0065] a plurality of signal lines 5 extending in the second direction y and arranged in the third direction z, the first direction x and the second direction y are both parallel to the plane where the substrate 1 is located, the first direction x intersects the second direction y, and the third direction z is perpendicular to the plane where the substrate 1 is located; the signal line 5 includes a main extension part 51 and a lead-out end part 52 located at at least one end of the main extension part 51; in the signal line lead-out structure, the orthogonal projection of the lead-out end part 52 of any two signal lines 5 on the substrate 1 does not overlap, and the orthogonal projection of the main extension part 51 of any two signal lines 5 on the substrate 1 overlaps; in the third direction z and from the side close to the substrate 1 to the side away from the substrate 1, the length of each signal line 5 decreases or increases in turn.

[0066] It should be noted that the signal line lead-out structure is arranged according to the side end region structure of the semiconductor block structure 100, if both side end regions of the semiconductor block structure 100 have signal line structures to be led out, one signal line lead-out structure needs to be arranged in each side end region; if only one side end region of the semiconductor block structure 100 has a signal line structure to be led out, only one signal line lead-out structure needs to be arranged.

[0067] The semiconductor structure of the present disclosure, a plurality of semiconductor block structures 100 can be distributed on the surface of the substrate 1 in the first direction x parallel to the substrate 1, in the process, a plurality of semiconductor block structures 100 can be formed at the same time, in this process, there is no need to wait for the previous semiconductor block structure 100 to be processed before forming another semiconductor block structure 100, the process flow is shorter, and the manufacturing cost is lower. At the same time, since the orthogonal projection of the lead-out end part 52 of any two signal lines 5 on the substrate 1 does not overlap, and the orthogonal projection of the main extension part 51 of any two signal lines 5 on the substrate 1 overlaps; in the third direction z and from the side close to the substrate 1 to the side away from the substrate 1, the length of each signal line 5 decreases or increases in turn, so that each signal line 5 arranged in the third direction z is in a stepped shape, the stepped signal line structure extends in the second direction y and is arranged in the first direction x, realizing the signal line lead-out of a plurality of semiconductor block structures arranged in the first direction x. And the lead-out end part 52 of each signal line 5 is exposed, which can facilitate subsequent preparation of a connection line 30 for electrically leading out the signal line 5 on each lead-out end part 52 at the same time through the same process, which helps to further shorten the process flow and reduce the manufacturing cost. In addition, the stepped design allows the signal lines 5 to be arranged more closely in the third direction z, which helps to improve the space utilization.

[0068] The following describes the parts of the semiconductor structure of the present disclosure and the specific details thereof:

[0069] In an exemplary embodiment of the present disclosure, the semiconductor block structure 100 can include a plurality of semiconductor shared cell structures on the substrate 1, wherein: the substrate 1 can be in a flat plate structure, for example, it can be a flat plate structure. The substrate 1 can be in a rectangular, circular, oval, polygonal or irregular shape, and its material can be a semiconductor material, for example, its material can be silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not specially limited here. As shown in the figure, the semiconductor shared cell structure can include a first storage unit 2 and a second storage unit 3, the first storage unit 2 and the second storage unit 3 can be formed on the substrate 1, and the first storage unit 2 and the second storage unit 3 can both be 2T0C (i.e., including two transistors, no capacitor) structure, the first storage unit 2 can be distributed in mirror image along the first direction x with the second storage unit 3, the first direction x can be parallel to the surface of the substrate 1, and the first storage unit 2 can share the same source-drain cell layer 410 with the second storage unit 3, which can reduce the area of the region where the first storage unit 2 and the second storage unit 3 are located, improve the device integration, and further improve the storage density of the memory. Figure 2

[0070] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 As shown in the figure, the first storage unit 2 and the second storage unit 3 each include a first transistor 10 and a second transistor 20, wherein:

[0071] ​The first transistor 10 is located above the top surface of the substrate 1. The first transistor 10 can be a CAA (Channel-All-Around) structure transistor, and the channel is parallel to the plane of the substrate 1 and can extend along the first direction x. The first transistor 10 can include a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103. The first gate 101 can be in the form of a strip and can extend along the first direction x. The material of the first gate 101 can be a conductive material, for example, the material of the first gate 101 can be IZO (Indium Zinc Oxide) or polysilicon. The first gate dielectric layer 102 can conformally cover the sidewalls and one end of the first gate 101. The material of the first gate dielectric layer 102 can be a material with high dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, or a mixture thereof, of course, other materials are also possible, which are not listed one by one here. The first semiconductor layer 103 can conformally cover the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 can include a first source-drain region, a first channel region, and a second source-drain region distributed along the first direction x in sequence. The first source-drain region is located on the side of the first channel region away from the source-drain unit layer 410, and the second source-drain region is located on the side of the first channel region close to the source-drain unit layer 410. The material of the first semiconductor layer 103 can cooperate with the material of the first gate 101; for example, when the material of the first semiconductor layer 103 is IGZO (Indium Gallium Zinc Oxide), the material of the first gate 101 is IZO (Indium Zinc Oxide) or polysilicon.

[0072] Optionally, the material of the first semiconductor layer 103 of the present disclosure is IGZO (Indium Gallium Zinc Oxide). Compared with the traditional single-crystal silicon as the material of the first semiconductor layer 103, the material of the first semiconductor layer 103 in the present disclosure is IGZO (Indium Gallium Zinc Oxide), because the off-state current of the IGZO thin film transistor (TFT) is extremely small, which can significantly reduce the leakage speed of the 2T0C DRAM storage unit, help to reduce the power consumption of the device, and improve the reliability of the device.

[0073] The second transistor 20 can also be located above the top surface of the substrate 1, the second transistor 20 can be a CAA structure transistor and the channel is parallel to the plane where the substrate 1 is located, and can extend along the first direction x. The second transistor 20 can be distributed along the first direction x side by side with the first transistor 10, that is, the second transistor 20 and the first transistor 10 are distributed laterally on the surface of the substrate 1. The second transistor 20 can include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203, the second gate 201 can be in the form of a strip and can extend along the first direction x, for example, the second gate 201 and the first gate 101 can be distributed in sequence along the first direction x, the material of the second gate 201 can be a conductive material, for example, it can be indium zinc oxide (IZO) or polysilicon, the material of the second gate 201 and the material of the first gate 101 can be the same or different, for example, the material of the second gate 201 and the first gate 101 can both be polysilicon; or the material of the second gate 201 is indium zinc oxide (IZO) and the material of the first gate 101 is polysilicon. The second gate dielectric layer 202 can conformally cover the sidewall of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the material of the second gate dielectric layer 202 can be a material with high dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof, of course, it can also be other materials, which are not listed one by one here. It should be noted that the material of the second gate dielectric layer 202 can be the same as the material of the first gate dielectric layer 102. The second semiconductor layer 203 can conformally cover the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source-drain region, a second channel region and a fourth source-drain region distributed in sequence along the first direction x, wherein the third source-drain region is located on one side of the second channel region away from the source-drain unit layer 410, and the fourth source-drain region is located on one side of the second channel region close to the source-drain unit layer 410; the material of the second semiconductor layer 203 and the material of the second gate 201 can cooperate with each other; for example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 can be indium gallium zinc oxide (IGZO); when the material of the second gate 201 is polysilicon, the material of the second semiconductor layer 203 can be single crystal silicon. In some embodiments of the present disclosure, the material of the second semiconductor layer 203 can be the same as the material of the first semiconductor layer 103, for example, the material of the second semiconductor layer 203 and the material of the first semiconductor layer 103 can both be indium gallium zinc oxide.

[0074] In an example embodiment of the present disclosure, the first transistor 10 can be a write transistor, the second transistor 20 can be a read transistor, the second source-drain region of the first transistor 10 can be conductively connected to the second gate 201 of the second transistor 20 through a semiconductor material (for example, indium zinc oxide), the charge in the gate capacitance of the second transistor 20 (i.e., the read transistor) is changed by the first transistor 10 (i.e., the write transistor), thereby affecting the resistance state between the source-drain of the second transistor 20 (i.e., the read transistor), so as to realize the distinction between "0" and "1".

[0075] In an example embodiment of the present disclosure, the source-drain unit layer 410 can extend in a direction perpendicular to the substrate 1, i.e., the plane where the source-drain unit layer 410 is located is perpendicular to the first direction x, the fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 are respectively connected to opposite sides of the source-drain unit layer 410 along the first direction x, and such design can ensure that the signal paths and conditions received by the first storage unit 2 and the second storage unit 3 are consistent, which helps to reduce reading errors and data inconsistency caused by signal transmission differences.

[0076] In some embodiments of the present disclosure, a plurality of semiconductor shared unit structures can be arranged along the second direction y and the third direction z, for example, the plurality of semiconductor shared unit structures can form a plurality of shared unit structure groups arranged along the third direction z, and each shared unit structure group can include a plurality of semiconductor shared unit structures arranged along the second direction y.

[0077] The second direction y is parallel to the substrate 1 and intersects the first direction x, for example, the second direction y can be perpendicular to the first direction x, and the third direction z is perpendicular to the first direction x and the second direction y. It should be noted that parallel can be absolute parallel or approximately parallel; similarly, perpendicular can be absolute perpendicular or approximately perpendicular. In the manufacturing process, there will inevitably be deviations, and in the present disclosure, due to the limitations of the manufacturing process, the angle deviation may occur, so that the angle between the first direction x (or the second direction y) and the surface of the substrate 1 has a certain deviation, or the angle between the third direction z and the first direction x (or the second direction y) has a certain deviation, as long as the angle deviation is within a preset range, the first direction x (or the second direction y) can be considered parallel to the surface of the substrate 1; or the third direction z can be considered perpendicular to the first direction x (or the second direction y). For example, the preset range can be 10°, i.e., when the angle between the first direction x (or the second direction y) and the surface of the substrate 1 is within the range of less than or equal to 10°, the first direction x (or the second direction y) can be considered parallel to the surface of the substrate 1; when the angle between the third direction z and the first direction x (or the second direction y) is within the range of greater than or equal to 80° and less than or equal to 100°, the third direction z can be considered perpendicular to the first direction x (or the second direction y).

[0078] In an example embodiment of the present disclosure, please continue to refer to Figure 1 As shown, the semiconductor block structure 100 can further include a plurality of first bit lines 6 extending along the third direction z and arranged along the first direction x and the second direction y, and a plurality of second bit lines 7 extending along the third direction z and arranged along the first direction x and the second direction y, each first bit line 6 wraps the outer periphery of a row of first source-drain regions arranged along the third direction z in the same plane; each second bit line 7 wraps the outer periphery of a row of third source-drain regions arranged along the third direction z in the same plane.

[0079] For example, the semiconductor common block structure can include a plurality of bit line groups spaced along the second direction y, each bit line group can include two first bit lines 6, which can be spaced along the first direction x, one of the two first bit lines 6 can wrap the outer periphery of a row of first source-drain regions arranged along the third direction z in each first storage unit 2 in a plurality of common cell structure groups arranged along the third direction z; the other first bit line 6 can wrap the outer periphery of a row of first source-drain regions arranged along the third direction z in each second storage unit 3 in a plurality of common cell structure groups arranged along the third direction z. It should be noted that different semiconductor common cell structures arranged along the second direction y are respectively provided with a bit line group, and each first bit line 6 in different bit line groups can be spaced and distributed in parallel along the second direction y.

[0080] Please continue to refer to Figure 1 As shown, each bit line group can further include two second bit lines 7, which can be spaced along the first direction x, one of the two second bit lines 7 can wrap the outer periphery of a row of third source-drain regions arranged along the third direction z in each first storage unit 2 in a plurality of common cell structure groups arranged along the third direction z; the other second bit line 7 can wrap the outer periphery of a row of third source-drain regions arranged along the third direction z in each second storage unit 3 in a plurality of common cell structure groups arranged along the third direction z. It should be noted that each second bit line 7 in different bit line groups can be spaced and distributed in parallel along the second direction y.

[0081] In an example embodiment of the present disclosure, please continue to refer to Figure 1As shown, the semiconductor block structure 100 includes 2 side end regions in the first direction x, and each of the 2 side end regions has signal line structures to be led out, so that the semiconductor block structure 100 is provided with signal line leading-out structures in the 2 side end regions, and each of the signal line leading-out structures includes a plurality of signal lines 5 extending along the second direction y and spaced apart along the third direction z, i.e., the regions where the signal lines 5 in the semiconductor block are located are the side end regions. For example, each common cell structure group can include two signal lines 5, and the two signal lines 5 can be spaced apart along the first direction x, one of the two signal lines 5 can be in contact with the end portions of a row of first gates 101 arranged along the second direction y and not covered by the first gate dielectric layer 102 in all the first storage cells 2 in the same common cell structure group, and the other signal line 5 can be in contact with the end portions of a row of first gates 101 arranged along the second direction y and not covered by the first gate dielectric layer 102 in all the second storage cells 3 in the same common cell structure group. The signal lines 5 connected to the first storage cells 2 in the common cell structure groups arranged along the third direction z can be spaced apart along the third direction z. For example, the signal lines 5 can be word lines. The material of the signal lines 5 can be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, titanium nitride or polysilicon, and of course, the material of the signal lines 5 can also be other materials with good conductivity, which are not listed here.

[0082] In some embodiments of the present disclosure, the signal line 5 can include a main body extension 51 and a leading end portion 52 at at least one end of the main body extension 51, in the signal line leading-out structure, the leading end portions 52 of any two signal lines 5 do not overlap in the orthographic projection on the substrate 1, and the main body extensions 51 of any two signal lines 5 overlap in the orthographic projection on the substrate 1, and in the third direction z and from the side close to the substrate 1 to the side away from the substrate 1, the lengths of the signal lines 5 decrease in turn or increase in turn. That is, at least one end of the plurality of signal lines 5 arranged along the third direction z is stepped, and at this time, the leading end portions 52 of the signal lines 5 are exposed.

[0083] In an exemplary embodiment of the present disclosure, the semiconductor block structure 100 is provided with signal line leading-out structures in the 2 side end regions, and each signal line leading-out structure includes 2 leading end portions 52 at both ends of the main body extension 51 in the second direction y, and the size of each leading end portion 52 in the second direction y is the same. For example, the size of the two leading end portions 52 in the same signal line 5 in the second direction y is the same, and the size of the leading end portions 52 in different signal lines 5 in the second direction y is also the same.

[0084] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1As shown, the signal line lead-out structure also includes a connecting line 30, which is connected to the lead-out end 52 of the signal line 5. That is, each lead-out end 52 is provided with a corresponding connecting line 30. The material of the connecting line 30 can be a conductive material, for example, it can be titanium nitride or a combined titanium nitride and tungsten film structure, and the signal can be transmitted to the lead-out end 52 of the signal line 5 through the connecting line 30. For example, the connecting line 30 can extend in a third direction z, and adjacent connecting lines 30 are insulated from each other. When the signal line 5 includes two lead-out ends 52, both lead-out ends 52 are provided with connecting lines 30.

[0085] In one exemplary embodiment of this disclosure, the signal line 5 can be electrically led out simultaneously via two connecting lines 30. During signal transmission, the two connecting lines 30 allow for a more uniform signal distribution, helping to reduce signal reflection and attenuation during transmission, thereby improving the integrity and stability of signal transmission. Simultaneously, the design of having connecting lines 30 at both ends can, to some extent, balance the electromagnetic field distribution around the signal line 5, reducing the impact of external electromagnetic interference on signal transmission and improving the circuit's anti-interference capability.

[0086] In one exemplary embodiment of this disclosure, when the length of each signal line 5 decreases sequentially in the third direction z, from the side closest to substrate 1 to the side furthest from substrate 1, the connecting line 30 is connected to the side of the lead-out end 52 furthest from substrate 1. Alternatively, when the length of each signal line 5 increases sequentially in the third direction z, from the side closest to substrate 1 to the side furthest from substrate 1, the connecting line 30 is connected to the side of the lead-out end 52 closest to substrate 1. Different connecting lines 30 may be distributed in parallel and all extend along the third direction z.

[0087] In one exemplary embodiment of this disclosure, both the first gate 101 and the signal line 5 are made of polysilicon, and a metal silicide layer 53 (e.g., ...) can be formed at least on the lead-out surface of the lead-out end 52 of the signal line 5. Figure 3 As shown, a metal silicide layer 53 may be provided on the lead-out surface of the lead-out end 52 of the signal line 5 (i.e., the side of the lead-out end 52 that connects to the connecting line 30). The connecting line 30 may contact and connect with the surface of the metal silicide layer 53 that is away from the lead-out surface. The design of the metal silicide layer 53 can help reduce the contact resistance between the connecting line 30 and the lead-out end 52, achieve a low-resistance connection, and improve signal transmission efficiency. The material of the metal silicide layer 53 may be CoSi2, TiSi2, or NiSi, etc.

[0088] In one exemplary embodiment of this disclosure, such as Figure 4 As shown, a metal silicide layer 53 is provided on the side of the lead-out end 52 away from the center of the semiconductor block structure 100 along the second direction y; or, as Figure 5As shown, the signal line 5 is provided with a metal silicide layer 53 on the side surface thereof away from the center of the semiconductor block structure 100 along the first direction x. The provision of the metal silicide layer 53 helps to reduce the resistance of the signal line 5 itself and the contact resistance between the signal line 5 and the surrounding structure, improve the transmission efficiency of the current in the signal line 5, and reduce the energy loss.

[0089] In an exemplary embodiment of the present disclosure, the signal line 5 is provided with a metal silicide layer 53 on the side surface of the lead-out end portion 52 thereof away from the center of the semiconductor block structure 100 along the second direction y, on the side surface of the lead-out end portion 52 thereof away from the center of the semiconductor block structure 100 along the second direction y, and on the side surface of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x. In this way, the resistance of the signal line 5 itself and the contact resistance between the signal line 5 and the surrounding structure can be greatly reduced, the transmission efficiency of the signal in the transmission line can be improved, and the power consumption can be reduced.

[0090] The read and write processes of the semiconductor structure of the present disclosure are described below.

[0091] The write "1" process can be performed by applying a positive voltage (greater than the threshold voltage Vth) to the write word line WWL (i.e., the signal line 5) through the connection line 30 to turn on the first transistor 10 (i.e., the write transistor), and applying a positive voltage to the write bit line WBL to inject charges into the gate capacitance (i.e., the storage node) of the second transistor 20 (i.e., the read transistor). After the charge injection, the positive voltage applied to the write word line WWL and the positive voltage applied to the write bit line WBL are removed, and the "1" state is saved. The read "1" process can be performed by applying a read voltage to the drain of the second transistor 20 (i.e., the read transistor), and since there are charges stored in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a low resistance state, a large current is obtained, and the read "1" process is completed after amplification and identification by the peripheral circuit. The write "0" process can be performed by applying a positive voltage (greater than the threshold voltage Vth) to the write word line WWL through the connection line 30 to turn on the first transistor 10 (i.e., the write transistor), and applying a negative voltage to the write bit line WBL to extract charges from the gate capacitance (i.e., the storage node) of the second transistor 20 (i.e., the read transistor). After the charge extraction, the positive voltage applied to the write word line WWL and the negative voltage applied to the write bit line WBL are removed, and the "0" state is saved. The read "0" process can be performed by applying a read voltage to the drain of the second transistor 20 (i.e., the read transistor), and since there are no charges in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a high resistance state, a small current is obtained, and the read "0" process is completed after amplification and identification by the peripheral circuit.

[0092] The present disclosure also provides a preparation method of a semiconductor structure, which is used to prepare the semiconductor structure in any of the above embodiments. The preparation method can include steps S110 and S120, wherein:

[0093] In step S110, a substrate 1 is provided.

[0094] Step S120, a plurality of semiconductor block structures 100 are prepared on the substrate 1, the semiconductor block structures 100 include 2 side end regions in the first direction x, and at least one side end region of the semiconductor block structures 100 is provided with a signal line leading-out structure;

[0095] The preparation method of the signal line leading-out structure (i.e., step S120) includes:

[0096] Step S210, a laminated structure is formed in the signal line leading-out structure region of the substrate 1, the laminated structure includes insulating material layers and conductive material layers alternately laminated multiple times along the third direction z; wherein the projection of the signal line leading-out structure region of the substrate 1 and the side end region of the semiconductor block structure 100 on the substrate 1 overlaps, the insulating material layers and the conductive material layers both extend along the second direction y, the first direction x and the second direction y are both parallel to the plane where the substrate 1 is located, the first direction x intersects the second direction y, and the third direction z is perpendicular to the plane where the substrate 1 is located;

[0097] Step S220, a trimming etching process is used to process the laminated structure to form a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z, the signal lines 5 include main body extension parts 51 and leading-out end parts 52 located at at least one end of the main body extension parts 51; in the signal line leading-out structure, the normal projection of the leading-out end parts 52 of any two signal lines 5 on the substrate 1 does not overlap, the normal projection of the main body extension parts 51 of any two signal lines 5 on the substrate 1 overlaps, and the length of each signal line 5 decreases in order from the side close to the substrate 1 to the side away from the substrate 1 in the third direction z.

[0098] The preparation method of the semiconductor structure of the present disclosure can simultaneously form a plurality of semiconductor block structures 100, and in this process, there is no need to wait for the previous semiconductor block structure 100 process to be completed before forming another semiconductor block structure 100, so the process flow is shorter and the manufacturing cost is lower. At the same time, since the normal projection of the leading-out end parts 52 of any two signal lines 5 on the substrate 1 does not overlap, the normal projection of the main body extension parts 51 of any two signal lines 5 on the substrate 1 overlaps, and the length of each signal line 5 decreases in order or increases in order from the side close to the substrate 1 to the side away from the substrate 1 in the third direction z, so that each signal line 5 arranged along the third direction z is in a stepped shape, the stepped signal line structure extends along the second direction y and is arranged at intervals along the first direction x, and the signal line leading-out of the plurality of semiconductor block structures arranged at intervals along the first direction x is realized. Moreover, the leading-out end part 52 of each signal line 5 is exposed, which can facilitate the subsequent preparation of the connection lines 30 for electrically leading out the signal lines 5 on the leading-out end parts 52 at the same time through the same process, and this helps to further shorten the process flow and reduce the manufacturing cost.

[0099] The steps and specific details of the method for preparing the semiconductor structure of the present disclosure are described in detail as follows:

[0100] In step S110, a substrate 1 is provided.

[0101] The substrate 1 can be in a flat plate structure, for example, it can be a flat plate structure. The substrate 1 can be in a rectangular, circular, oval, polygonal or irregular shape, and the material thereof can be a semiconductor material, for example, the material thereof can be silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not specially limited herein.

[0102] In step S120, a plurality of semiconductor block structures 100 are prepared on the substrate 1 and arranged at intervals along a first direction x, the semiconductor block structure 100 includes two side end regions in the first direction x, and at least one side end region of the semiconductor block structure 100 is provided with a signal line lead-out structure.

[0103] In some embodiments of the present disclosure, forming the semiconductor block structure 100 can include steps S1201-S1207, in which:

[0104] In step S1201, an insulating material layer 301 and a semiconductor material layer 302 are sequentially and alternately deposited on the substrate 1, and a protective layer 9 can also be formed on the surface of the topmost insulating material layer 301. The material of the insulating material layer 301 can be silicon oxide, and the material of the protective layer 9 can be silicon nitride. The structure formed by the insulating material layer 301, the semiconductor material layer 302 and the protective layer 9 together can be defined as a film layer stack structure. The film layer stack structure can be subjected to a patterning process to form a patterned film layer stack structure 40, the pattern of the patterned film layer stack structure 40 includes a plurality of first patterns 401 extending along the first direction x and spaced apart along the second direction y, and a plurality of second patterns 402 extending along the second direction y and spaced apart along the first direction x; the first patterns 401 and the second patterns 402 overlap. In an embodiment of the present disclosure, the structure after step S1201 is as shown in Figure 6 .

[0105] In an exemplary embodiment of the present disclosure, as shown in Figure 7 , the insulating material can be filled in the patterned film layer stack structure 40, the insulating material can fill the gaps in the patterned film layer stack structure 40, and the insulating material and the insulating material layer 301 together constitute an insulating filling layer 303. After forming the insulating filling layer 303, a protective material can be deposited on the surface of the insulating filling layer 303 and the patterned film layer stack structure 40, and the newly deposited protective material can together with the original protective layer 9 constitute a new protective layer 9.

[0106] In step S1202, a plurality of first openings 403 are formed through the patterned film layer stack structure 40, the protective layer 9 and the insulating filling layer 303 along the third direction z, the first openings 403 are arranged one by one corresponding to the second patterns 402, and the first openings 403 divide the corresponding second patterns 402 into two sub-patterns 4021 which are distributed side by side along the first direction x, as shown in FIG. 12B; as shown in FIG. 12C, the semiconductor material layer 302 is etched laterally to both sides through the first openings 403 to form a plurality of first transistors and signal line containing grooves, the first transistors and signal line containing grooves include a row of first transistor containing grooves 404 extending along the first direction x and arranged along the second direction y, and a signal line containing groove 405 extending along the second direction y and communicating with the row of first transistor containing grooves 404. Figure 8 Figure 9 Figure 10

[0107] In step S1203, the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer (not shown in the figure) are sequentially deposited in the first transistor and signal line containing grooves; the first semiconductor layer 103 covers the side walls and the bottom surface of the first transistor and signal line containing grooves, the first gate dielectric layer 102 covers the surface of the first semiconductor layer 103, and the first gate material layer fills the remaining space of the first transistor and signal line containing grooves; in this process, in order to facilitate the process and ensure that the first gate material layer can fill the first transistor and signal line containing grooves, the first semiconductor layer 103 can be made to cover the surface of the protective layer 9 at the same time, and the first gate material layer can be made to fill the first openings 403, and then the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer located on the top of the protective layer 9 and in the first openings 403 can be removed, the first gate material layer in the signal line containing groove 405 can be used as the conductive material layer 510, and the first gate material layer in the first transistor containing groove 404 can be used as the first gate 101, the first gate 101, the first gate dielectric layer 102 and the first semiconductor layer 103 together constitute the first transistor 10, and the first semiconductor layer 103 on the first gate 101 in the first transistor 10 includes a first source-drain region, a first channel region and a second source-drain region which are distributed along the first direction x in sequence.

[0108] In an exemplary embodiment of the present disclosure, as shown in FIG. 12D, after the first transistor 10, the second transistor 20 and the conductive material layer 510 are formed, the first openings 403 can be filled with an insulating material 8 to close the first openings 403. Figure 11

[0109] In an exemplary embodiment of the present disclosure, forming the semiconductor block structure 100 further includes:

[0110] ​​​​In step S1204, a plurality of second openings are formed through the patterned film layer stack structure 40 along the third direction z, the second openings are located at the middle positions between two adjacent first openings 403, and the second openings are parallel to the plane in which the second direction y and the third direction z lie.

[0111] In step S1205, portions of the insulating filling layer 303 are etched away laterally to both sides through the second openings to form a second gate 201 of a second transistor 20, and then a second gate dielectric layer 202 and a second semiconductor layer 203 are sequentially deposited, the second gate dielectric layer 202 conformally covers the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10, and the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source-drain region, a second channel region and a fourth source-drain region which are sequentially distributed along the first direction x.

[0112] In step S1206, the second openings are closed by filling the insulating material between the adjacent second transistors 20, a plurality of third openings are formed through the insulating material along the third direction z, the third openings are located in the second openings, and the third openings expose the fourth source-drain region in the second transistor 20, and a source-drain layer 4 can be formed in the third openings. The third openings are parallel to the plane in which the second direction y and the third direction z lie.

[0113] In an exemplary embodiment of the present disclosure, forming the semiconductor block structure 100 further includes:

[0114] In step S1207, a plurality of first bit line accommodation holes and second bit line accommodation holes extending along the third direction z are formed, a first bit line 6 is formed in each first bit line accommodation hole, and a second bit line 7 is formed in each second bit line accommodation hole; each first bit line 6 covers the outer periphery of a row of first source-drain regions arranged in the same plane along the third direction z, and each second bit line 7 covers the outer periphery of a row of third source-drain regions arranged in the same plane along the third direction z.

[0115] In an exemplary embodiment of the present disclosure, the method for manufacturing the signal lead-out structure can include steps S210 and S220, wherein:

[0116] In step S210, a layer stack structure 1030 is formed in the signal line lead-out structure region of the substrate 1 (see FIG. 11 for details), Figure 8 The layer stack structure 1030 includes a plurality of insulating material layers 301 and a plurality of conductive material layers 510 which are alternately stacked along the third direction z; the projection of the signal line lead-out structure region of the substrate 1 and the side end region of the semiconductor block structure 100 on the substrate 1 overlap, the insulating material layers 301 and the conductive material layers 510 both extend along the second direction y, the first direction x and the second direction y are both parallel to the plane in which the substrate 1 lies, the first direction x intersects the second direction y, and the third direction z is perpendicular to the plane in which the substrate 1 lies.

[0117] The region where the conductive material layer 510 and the insulating material layer 301 in the layer stack structure 1030 are stacked is a side end region of the semiconductor block structure 100, and can also be named as a signal line lead-out structure region. The structure formed by alternately stacking the insulating material layer 301 and the conductive material layer 510 in the process of steps S1201-S1203 can be the layer stack structure 1030 in step S210. It needs to be noted that when the surface of the insulating material layer 301 at the topmost position is formed with the protective layer 9, the protective layer 9 can also be part of the layer stack structure 1030. That is, the preparation details of the layer stack structure 1030 in step S210 can refer to steps S1201-S1203, which will not be described here.

[0118] In step S220, a trim-etch process is used to process the layer stack structure 1030 to form a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z, the signal lines 5 including a main body extension part 51 and a lead-out end part 52 at at least one end of the main body extension part 51; in the signal line lead-out structure, the orthogonal projections of the lead-out end parts 52 of any two signal lines 5 on the substrate 1 do not overlap, and the orthogonal projections of the main body extension parts 51 of any two signal lines 5 on the substrate 1 overlap; in the third direction z and from the side close to the substrate 1 to the side away from the substrate 1, the lengths of the signal lines 5 decrease in turn.

[0119] The layer stack structure 1030 can be processed by a trim-etch process to convert a plurality of conductive material layers 510 extending along the second direction y and arranged along the third direction z into a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z. In the third direction z, the ends of the plurality of signal lines 5 can be stepped, and in adjacent two signal lines 5, in the direction from the side close to the substrate 1 to the side away from the substrate 1, the signal line 5 at the upper layer exposes the lead-out end part 52 of the signal line 5 at the lower layer. In the present disclosure, the structure after step S220 is as shown in FIG. 2B. Figure 12

[0120] In an exemplary embodiment of the present disclosure, the number of layers of the conductive material layer 510 in the semiconductor block structure 100 is n layers, the number of layers of the insulating material layer 301 is n+1 layers, and n>2; in the third direction z, each conductive material layer 510 can be defined as the 1st to nth layer of conductive material layer 510 from top to bottom, and each insulating material layer 301 can be defined as the 1st to n+1th layer of insulating material layer 301 from top to bottom; processing the layer stack structure 1030 by a trim-etch process to form a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z (i.e., step S120) can include the following steps: ​

[0121] S1, forming a first pattern mask layer on the laminated structure 1030, the length of the first pattern mask layer in the second direction y is less than the length of the first layer of conductive material layer 510, and the orthographic projection of the first pattern mask layer on the laminated structure 1030 does not overlap with at least one end of the first layer of conductive material layer 510.

[0122] In an exemplary embodiment of the present disclosure, before forming the first pattern mask layer, an etching stop layer 50 can be formed on the surface of the laminated structure 1030, a mask material layer can be formed on the surface of the etching stop layer 50, the mask material layer includes a plurality of mask patterns extending along the second direction y and spaced along the first direction x, the orthographic projection of the mask pattern on the substrate 1 is completely coincident with the orthographic projection of the laminated structure 1030 on the substrate 1, and the mask material layer with the mask pattern can etch the etching stop layer 50 (when the laminated structure 1030 also includes the protective layer 9, etching the protective layer 9 at the same time) to form an opening exposing the first layer of insulating material layer 301. Subsequently, the mask material layer can be removed, and the first pattern mask layer can be formed on the surface of the etching stop layer 50. In the second direction y, the length of the first pattern mask layer is less than the length of the conductive material layer 510, and the orthographic projection of the first pattern mask layer on the laminated structure does not overlap with at least one end of the first layer of conductive material layer 510. For example, in the second direction y, the first pattern mask layer can be located in the middle region of the laminated structure 1030, and the orthographic projection of the first pattern mask layer on the laminated structure does not overlap with both ends of the first layer of conductive material layer 510.

[0123] S2, etching the first layer of insulating material layer 301 and the first layer of conductive material layer 510 with the first pattern mask layer as a mask to expose at least one end of the second layer of insulating material layer 301, and form a first patterned laminated structure.

[0124] In some embodiments of the present disclosure, the material of the first gate 101 and the conductive material layer 510 can be polysilicon, and the first layer of insulating material layer 301 and the first layer of conductive material layer 510 can be etched with a non-isotropic etching process with the first pattern mask layer as a mask to expose at least one end of the second layer of insulating material layer 301, and the etched structure can be defined as a first patterned laminated structure. Compared with the conventional scheme in which the material of the conductive material layer 510 is tungsten and silicon nitride, the polysilicon in the present application is easy to be etched, the process difficulty is smaller, and after the etching is completed, there is no metal residue and defect, and the device reliability is higher.

[0125] It should be noted that in the non-isotropic etching process, the etching stop layer 50 and the protective layer 9 can be used to protect the film layer structure of the region other than the laminated structure 1030 in the semiconductor block structure 100 to prevent damage to other structures in the etching process.

[0126] S3, forming a second patterned mask layer on the first patterned stack structure, the length of the second patterned mask layer in the second direction y is less than the length of the first layer of conductive material 510 remaining after the last etching, and the orthogonal projection of the second patterned mask layer on the substrate 1 does not overlap with at least one end of the first layer of conductive material 510 remaining after the last etching.

[0127] In some embodiments of the present disclosure, the first patterned mask layer can be removed before forming the second patterned mask layer, thereby exposing the surface of the first patterned stack structure, and then forming a second patterned stack structure on the first patterned stack structure. In the second direction y, the length of the second patterned stack structure can be less than the length of the first layer of conductive material 510 in the first patterned stack structure, and the orthogonal projection of the second patterned mask layer on the substrate 1 does not overlap with at least one end of the first layer of conductive material 510 in the first patterned stack structure. For example, in the second direction y, the second patterned mask layer can be located in the middle region of the first patterned stack structure, and the orthogonal projection of the second patterned mask layer on the first patterned stack structure does not overlap with both ends of the first layer of conductive material 510.

[0128] In some embodiments of the present disclosure, the first patterned mask layer can be removed before forming the second patterned mask layer, thereby exposing the surface of the first patterned stack structure, and then forming a second patterned stack structure on the first patterned stack structure. In the second direction y, the length of the second patterned stack structure can be less than the length of the first layer of conductive material 510 in the first patterned stack structure, and the orthogonal projection of the second patterned mask layer on the substrate 1 does not overlap with at least one end of the first layer of conductive material 510 in the first patterned stack structure. For example, in the second direction y, the second patterned mask layer can be located in the middle region of the first patterned stack structure, and the orthogonal projection of the second patterned mask layer on the first patterned stack structure does not overlap with both ends of the first layer of conductive material 510.

[0129] S4, etching the exposed second layer of insulating material 301 and the second layer of conductive material 510 with the second patterned mask layer as a mask to expose at least one end of the next layer of insulating material 301, thereby forming a second patterned stack structure.

[0130] During the etching of the second layer of insulating material 301 and the second layer of conductive material 510, the film layer structure of the regions other than the stack structure 1030 in the semiconductor block structure 100 can still be protected by the etching stop layer 50 and the protective layer 9 to prevent damage to other structures during the etching process.

[0131] Steps S3-S4 are repeated until at least one end of the nthinsulating material layer 301 is exposed, forming an (n-1)thpatterned stack structure; each conductive material layer 510 remaining after etching is used as a signal line 5, and the area of each signal line 5 that does not overlap with other signal lines 5 is used as an exposed end 52. After the (n-1)thpatterned stack structure is formed, the insulating material layer 301 on the exposed end 52 of each signal line 5 can be removed, thereby exposing the exposed end 52 of each signal line 5. The part of each signal line 5 other than the exposed end 52 can be used as a main extension 51. Figure 13 A schematic diagram of the Xthpatterned mask layer 70 deposited when the Xthetching is performed in the embodiments of the present disclosure is shown.

[0132] In the present disclosure, the insulating material layer 301 and the conductive material layer 510 are etched layer by layer downward by repeating steps S3 and S4 until at least one end of the nthinsulating material layer 301 is exposed. Each time steps S3 and S4 are repeated, a new patterned stack structure is formed, and during each repetition of steps S3 and S4, the end of each conductive material layer 510 that has been etched before is etched again, thereby causing the end of each conductive material layer 510 to be simultaneously inwardly retracted during each etching process. Each conductive material layer 510 in the (n-1)thpatterned stack structure can be used as a signal line 5, and the end of each signal line 5 is arranged in a stepped manner.

[0133] In an exemplary embodiment of the present disclosure, the method for preparing the signal line exposed structure further includes steps S310-S330, wherein:

[0134] Step S310: forming a covering layer 60 on the side of each exposed end 52 away from the substrate 1.

[0135] The material of the covering layer 60 is the same as that of the insulating material layer 301, for example, both the material of the covering layer 60 and the material of the insulating material layer 301 are silicon oxide. The covering layer 60 can be formed on the side of the exposed end 52 away from the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In the embodiments of the present disclosure, the structure after step S310 is as shown in Figure 14

[0136] Step S320: etching the covering layer 60 to form a plurality of connection holes 61 penetrating the covering layer 60 along the third direction z, and the orthogonal projection of each connection hole 61 on the substrate 1 at least partially overlaps with the orthogonal projection of a different exposed end 52 on the substrate 1.

[0137] ​A mask layer can be formed on the covering layer 60, and the mask layer can be etched to form a plurality of mask holes penetrating through the covering layer 60 along the third direction z. The covering layer 60 can be etched at the mask holes by a non-isotropic etching process to form a plurality of connection holes 61 penetrating through the covering layer 60 along the third direction z. The connection holes 61 can be distributed one-to-one corresponding to the lead-out end portions 52. For example, each connection hole 61 can expose each lead-out end portion 52, respectively. The shape of the cross section of the connection hole 61 can be circular, elliptical, rectangular, polygonal, or irregular, which is not particularly limited here. It should be noted that the mask layer can be removed after the connection hole 61 is formed, and then the etching stop layer or the protective layer 9 at the top of the layer stack structure 1030 is exposed. In the embodiment of the present disclosure, the structure after step S320 is as shown in FIG. 31. Figure 15

[0138] Step S330, depositing a conductive material in the connection hole 61 to form a connection line 30.

[0139] The conductive material can be a material with strong conductivity, which can include one material or two materials. For example, the conductive material can be titanium nitride and / or tungsten. For example, the conductive material can include titanium nitride and tungsten, and a titanium nitride layer covering the sidewalls and the bottom of the connection hole 61 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc. In this process, in order to facilitate the process, the titanium nitride layer can also cover the etching stop layer or the protective layer 9 at the top of the layer stack structure 1030. Subsequently, tungsten can be filled in the connection hole 61 with the titanium nitride layer by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc. The tungsten can fill the connection hole 61, and in this process, in order to facilitate the process, the tungsten can also cover the surface of the titanium nitride layer at the top of the layer stack structure 1030. It should be noted that after the tungsten fills the connection hole 61, the titanium nitride layer, the tungsten, and the etching stop layer at the top of the stack structure can be removed by etching back or grinding, etc., and the titanium nitride layer and the tungsten in the connection hole 61 can be flush with the surface of the protective layer 9 away from the substrate 1 and the end portion of the substrate 1. The remaining titanium nitride layer and tungsten in the connection hole 61 can be used as the connection line 30. In the embodiment of the present disclosure, the structure after step S330 is as shown in FIG. 32. Figure 16

[0140] In an exemplary embodiment of the present disclosure, the surface of the lead-out end portion 52 away from the substrate 1 can be used as a lead-out surface; in the n-1 patterned layer stack structure, the surface of each lead-out surface is covered with an insulating material layer 301. After forming the n-1 patterned layer stack structure and before forming the covering layer 60, the method for manufacturing the signal line lead-out structure of the present disclosure further includes steps S410 and S420, wherein:

[0141] ​​Step S410, removing the insulating material layer 301 covering the lead-out end portion 52 in the n-1th patterned layer stack to expose the lead-out surface of the lead-out end portion 52 and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y.

[0142] The insulating material layer 301 on the lead-out surface can be removed by wet etching or dry etching, thereby exposing the lead-out surface and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y.

[0143] Step S420, forming a metal silicide layer 53 on the lead-out surface of the lead-out end portion 52 and the side surface away from the center of the semiconductor block structure 100 in the second direction y.

[0144] The material of the metal silicide layer 53 can be CoSi2, TiSi2 or NiSi, etc. The material of the connection line 30 is a conductive material, for example, a composite structure of a titanium nitride layer covering a tungsten core shaft, and the titanium nitride layer serves as an electron barrier layer. The metal layer can be formed on the lead-out surface and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc. The metal layer can be treated by a thermal annealing process to diffuse metal ions in the metal layer into the signal line 5, thereby forming a metal silicide layer 53 at the junction of the metal layer and the signal line 5. Then, the unreacted metal layer can be removed, and the metal silicide layer 53 formed on the lead-out surface of the lead-out end portion 52 and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y is reserved.

[0145] Taking CoSi2 as an example of the material of the metal silicide layer 53, a cobalt material layer can be formed on the lead-out surface and the side surface away from the center of the semiconductor block structure 100 in the second direction y. The cobalt ions can diffuse into the lead-out end portion 52 by a thermal annealing process, and the cobalt ions can combine with silicon in the signal line 5 to form a silicon cobalt bond, thereby forming a CoSi2 layer at the junction of the cobalt material layer and the signal line 5. Then, the unreacted cobalt material layer can be removed.

[0146] In an exemplary embodiment of the present disclosure, the surface of the lead-out end portion 52 away from the surface of the substrate 1 can be taken as the lead-out surface, and the surface of each lead-out surface is covered with an insulating material layer 301 in the n-1th patterned layer stack. The gap between the adjacent two semiconductor blocks is filled with an insulating material 8. After forming the n-1th patterned layer stack and before forming the cover layer 60, the preparation method of the signal line lead-out structure of the present disclosure further includes steps S510 and S520, wherein:

[0147] In step S510, the insulating material layer 301 covering the lead-out surface of the lead-out end portion 52 and the insulating material 8 between the two adjacent semiconductor blocks in the n-1th patterned layer stack are removed to expose the lead-out surface, the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y, and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the first direction x.

[0148] In some embodiments of the present disclosure, the insulating material 8 filled between the two adjacent semiconductor blocks is made of the same material as the insulating material layer 301 on the lead-out surface, and the insulating material layer 301 covering the lead-out surface in the n-1th patterned layer stack and the insulating material 8 between the semiconductor block structure 100 can be removed simultaneously by the same etching process, thereby exposing the lead-out surface and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y. For example, the insulating material layer 301 on the lead-out surface and the insulating material 8 between the semiconductor block structure 100 can be removed by wet etching.

[0149] In step S520, a metal silicide layer 53 is formed on the lead-out surface of the lead-out end portion 52, the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y, and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the first direction x.

[0150] The material of the connection line 30 is a conductive material, for example, a composite structure of a tungsten core shaft coated with a titanium nitride layer, and the titanium nitride layer serves as an electron barrier layer. A metal layer can be formed on the lead-out surface, the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y, and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the first direction x by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the metal layer can be treated by a thermal annealing process to diffuse metal ions in the metal layer into the signal line 5, thereby forming a metal silicide layer 53 at the junction of the metal layer and the signal line 5. Then, the unreacted metal layer can be removed, and the metal silicide layer 53 formed on the lead-out surface of the lead-out end portion 52, the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the second direction y, and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 in the first direction x is retained. For example, when the material of the metal silicide layer 53 is CoSi2, the material of the metal layer can be cobalt; when the material of the metal silicide layer 53 is TiSi2, the material of the metal layer can be titanium; and when the material of the metal silicide layer 53 is NiSi, the material of the metal layer can be nickel.

[0151] After the metal silicide layer 53 is formed, step S310 can be performed, i.e., after the metal silicide layer 53 is formed, the cover layer 60 can be formed, when step S320 is performed, the formed connection hole 61 can expose the metal silicide layer 53 on the lead-out surface, when step S330 is performed, the end of the formed connection line 30 close to the substrate 1 side is in contact with the metal silicide layer 53 on the lead-out surface. The metal silicide layer 53 on the lead-out surface can help to reduce the resistance between the connection line 30 and the lead-out end 52, improve the signal transmission efficiency; at the same time, the design of the metal silicide layer 53 on the side surface of the lead-out end 52 away from the center of the semiconductor block structure 100 along the second direction y and the metal silicide layer 53 on the side surface of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x helps to reduce the resistance of the signal line 5 itself and the contact resistance between the signal line 5 and the surrounding structure, improve the transmission efficiency of the current in the signal line 5, and reduce energy loss.

[0152] It is noted that, although the steps of the method for preparing the semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0153] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within known or customary practice in the art to which the present disclosure pertains. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, said semiconductor structure being fabricated on a substrate, characterized in that, The semiconductor structure includes a plurality of semiconductor block structures spaced apart along a first direction. Each semiconductor block structure includes two side regions in the first direction. At least one side region of each semiconductor block structure is provided with a signal line lead-out structure, which includes: Multiple signal lines extending along a second direction and spaced apart along a third direction, wherein both the first and second directions are parallel to the plane of the substrate, the first direction intersects the second direction, and the third direction is perpendicular to the plane of the substrate; each signal line includes a main extension and a lead-out end located at at least one end of the main extension; in the signal line lead-out structure, the orthographic projections of the lead-out ends of any two signal lines on the substrate do not overlap, while the orthographic projections of the main extensions of any two signal lines on the substrate overlap; in the direction of the third direction and from the side closer to the substrate to the side farther from the substrate, the length of each signal line decreases or increases sequentially. The semiconductor block structure includes a plurality of semiconductor common units arranged along the second direction and the third direction. The semiconductor common unit includes a first memory unit and a second memory unit. The first memory unit and the second memory unit are arranged side by side in a mirror image along the first direction. The first memory unit and the second memory unit share the same source and drain cell layer. The first memory unit and the second memory unit both include a first transistor and a second transistor. The first gate of the first transistor is connected to the signal line. The first transistor and the second transistor are both all-around channel structure transistors and the channel is parallel to the plane of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The signal line lead-out structure also includes: A connecting wire connected to the lead end of the signal line, the connecting wire extending along the third direction, and adjacent two connecting wires being insulated from each other; When the length of each signal line decreases sequentially in the direction upward from the third side and from the side near the substrate to the side away from the substrate, the connecting line is connected to the side of the lead-out end away from the substrate; or, when the length of each signal line increases sequentially in the direction upward from the third side and from the side near the substrate to the side away from the substrate, the connecting line is connected to the side of the lead-out end near the substrate.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor block structure has signal line lead-out structures on both sides; each signal line includes two lead-out ends located at both ends of the main body extension, and each lead-out end has the same size in the second direction.

4. The semiconductor structure according to claim 1, characterized in that, The signal line is made of polysilicon, and at least the lead-out surface of the signal line at the lead-out end is provided with a metal silicide layer.

5. The semiconductor structure according to claim 4, characterized in that, The lead-out end has a metal silicide layer on its side away from the center of the semiconductor block structure along the second direction.

6. The semiconductor structure according to claim 4, characterized in that, The signal line has a metal silicide layer on its side away from the center of the semiconductor block structure along the first direction.

7. The semiconductor structure according to any one of claims 4-6, characterized in that, The signal line is a word line, and the material of the metal silicide layer is CoSi2, TiSi2, or NiSi.

8. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A plurality of semiconductor block structures are prepared on the substrate and spaced apart along a first direction. Each semiconductor block structure includes two side end regions in the first direction, and at least one side end region of the semiconductor block structure is provided with a signal line lead-out structure. The method for fabricating the signal line lead-out structure includes: A stacked structure is formed in the signal line lead-out structure region of the substrate. The stacked structure includes an insulating material layer and a conductive material layer that are alternately stacked multiple times along a third direction. The projections of the signal line lead-out structure region of the substrate and the side end region of the semiconductor block structure on the substrate overlap. Both the insulating material layer and the conductive material layer extend along a second direction. Both the first direction and the second direction are parallel to the plane of the substrate. The first direction intersects the second direction. The third direction is perpendicular to the plane of the substrate. The stacked structure is processed using a trimming etching process to form multiple signal lines extending along the second direction and spaced apart along the third direction. Each signal line includes a main extension and a lead-out end located at at least one end of the main extension. In the signal line lead-out structure, the orthographic projections of the lead-out ends of any two signal lines on the substrate do not overlap, while the orthographic projections of the main extensions of any two signal lines on the substrate do overlap. In the third direction and from the side closer to the substrate to the side farther from the substrate, the length of each signal line decreases sequentially.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The number of conductive material layers is n, and the number of insulating material layers is n+1, where n>2. In the third direction, each conductive material layer is defined from top to bottom as the 1st to nth conductive material layer, and each insulating layer is defined from top to bottom as the 1st to n+1th insulating material layer. A trimming etching process is used to process the stacked structure to form multiple signal lines extending along the second direction and spaced apart along the third direction, including the following steps: S1, a first pattern mask layer is formed on the stacked structure, the length of the first pattern mask layer in the second direction is less than the length of the first conductive material layer, and the orthographic projection of the first pattern mask layer on the stacked structure does not overlap with at least one end of the first conductive material layer; S2, using the first patterned mask layer as a mask, the first insulating material layer and the first conductive material layer are etched to expose at least one end of the second insulating material layer, forming a first patterned stacked structure; S3, a second pattern mask layer is formed on the first patterned stacked structure. The length of the second pattern mask layer in the second direction is less than the length of the first conductive material layer remaining after the previous etching, and the orthographic projection of the second pattern mask layer on the substrate does not overlap with at least one end of the first conductive material layer remaining after the previous etching. S4, using the second patterned mask layer as a mask, the exposed second layer of insulating material and the second layer of conductive material are etched to expose at least one end of the next layer of insulating material, forming a second patterned stacked structure; Repeat steps S3-S4 until at least one end of the nth insulating material layer is exposed, forming the (n-1)th patterned stacked structure. Each of the remaining conductive material layers after etching is used as a signal line, at least one exposed end of the signal line is used as the lead-out end, and the portion of the signal line that is not the lead-out end is used as the main body extension.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, The method for preparing the signal line lead-out structure further includes: A cover layer is formed on the side of each lead-out end away from the substrate; The cover layer is etched to form a plurality of connection holes penetrating the cover layer along the third direction, wherein the orthographic projections of different connection holes on the substrate at least partially overlap with the orthographic projections of different lead-out ends on the substrate; Conductive material is deposited within the connection hole to form a connection wire.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that, The signal line is made of polycrystalline silicon, and the surface of the lead-out end away from the substrate is the lead-out surface. The method for fabricating the signal line lead-out structure further includes: Remove the insulating material layer covering each of the lead-out ends in the (n-1)th patterned stack-up structure to expose the lead-out surfaces of the lead-out ends in the signal lines and the side surfaces of the signal lines away from the center of the semiconductor block structure along the second direction; A metal silicide layer is formed on the lead-out surface of the lead-out end and on the side surface away from the center of the semiconductor block structure along the second direction.

12. The method for preparing a semiconductor structure according to claim 9, characterized in that, The signal line is made of polycrystalline silicon, the surface of the lead-out end away from the substrate is the lead-out surface, and the space between two adjacent semiconductor block structures is filled with insulating material. The method for fabricating the signal line lead-out structure further includes: Remove the insulating material layer covering the lead-out surfaces of each of the lead-out ends and the insulating material between two adjacent semiconductor block structures in the (n-1)th patterned stack-up structure to expose each lead-out surface, the side of the signal line away from the center of the semiconductor block structure along the second direction, and the side of each signal line away from the center of the semiconductor block structure along the first direction; A metal silicide layer is formed on the lead-out surface of the lead-out end, the side of the signal line away from the center of the semiconductor block structure along the second direction, and the side of the signal line away from the center of the semiconductor block structure along the first direction.

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