Three-dimensional dynamic random access memory and method of manufacturing the same

Abstract

The application discloses a three-dimensional dynamic random access memory and a manufacturing method thereof, and relates to the technical field of memory, which is used for improving the storage density of the dynamic random access memory, increasing the contact area between the source region and the drain region of the transistor and the contact structure or the capacitor, reducing the contact resistance, and improving the leakage. The three-dimensional dynamic random access memory comprises a plurality of storage units distributed in a three-dimensional array and a medium structure for isolating different storage units. Each storage unit comprises a transistor and a capacitor. The transistor comprises a gate, a gate medium layer, a channel region, a source region and a drain region. The length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are recessed inward relative to the side walls of the corresponding first medium part to form notches. The source region and the drain region are covered on the inner walls of the notches. The manufacturing method of the three-dimensional dynamic random access memory is used for manufacturing the three-dimensional dynamic random access memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory technology, and in particular to a three-dimensional dynamic random access memory and a manufacturing method thereof. BACKGROUND

[0002] In a computer system, memory is a key component for storing data and programs. Dynamic random access memory (DRAM) as an important memory type plays a key role in modern computer architecture. Dynamic random access memory includes a 1T1C memory cell structure. The memory cell of such dynamic random access memory is composed of a transistor and a capacitor connected to the source or drain of the transistor. The capacitor is used to store electric charge, and the transistor is used to control access to the capacitor. Such dynamic random access memory also includes a word line connected to the gate of the transistor, and a bit line connected to the source region or drain region of the transistor. When accessing data of a certain memory cell, the word line connected to the memory cell is selected, and a voltage is input on the word line to turn on the transistor. After the transistor is turned on, the bit line connected to the memory cell is selected to complete the selection of the memory cell and allow access to the electric charge in the capacitor. However, since the capacitor will gradually leak electricity, resulting in a decrease in stored electric charge, dynamic random access memory needs to be refreshed regularly (usually every few milliseconds) to maintain the validity of the data. The refresh operation reads the data in each memory cell and rewrites it to replenish the lost electric charge in the capacitor.

[0003] In the prior art, the memory cells of dynamic random access memory are arrayed in the horizontal direction of the wafer, i.e., two-dimensional dynamic random access memory. However, the development of computer systems has put forward higher requirements for the density of dynamic random access memory, and the density of two-dimensional dynamic random access memory is limited by the process and cannot meet the density requirements. SUMMARY

[0004] The present application aims to provide a three-dimensional dynamic random access memory and a manufacturing method thereof, which is used to improve the storage density of dynamic random access memory, increase the contact area between the source region and the drain region included in the transistor and the contact structure or the capacitor, respectively, reduce the contact resistance, and improve the leakage.

[0005] To achieve the above object, in a first aspect, the present application provides a three-dimensional dynamic random access memory, comprising: a plurality of memory cells arranged in a three-dimensional array, and a medium structure for isolating different memory cells. The plurality of memory cells arranged in a three-dimensional array comprises a plurality of memory layers spaced apart along a first direction, each memory layer comprising a plurality of memory groups spaced apart along a second direction, and each memory group comprising a plurality of memory cells arranged along a third direction. The first direction, the second direction and the third direction are different from each other. Each memory cell comprises: a transistor and a capacitor. The medium structure comprises a first medium part between two transistors spaced apart along the first direction. The transistor comprises: a gate, a gate medium layer, a channel region, a source region and a drain region. The length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are recessed inward relative to the side walls of the corresponding first medium part to form a notch. The source region and the drain region are respectively arranged on the two sides along the length direction and cover the inner walls of the notch; the gate medium layer is located between the gate and the channel region, the source region and the drain region respectively. The capacitor is electrically connected to the source region or the drain region of the transistor.

[0006] With the above technical solution, the three-dimensional dynamic random access memory provided by the present application not only has a plurality of memory groups spaced apart along the second direction in the same layer, but also comprises a plurality of memory layers spaced apart along the first direction, at this time the plurality of memory cells are arranged in a three-dimensional array. Compared with the two-dimensional dynamic random access memory having only a single memory layer, each memory layer in the present application can form a structure similar to the prior art two-dimensional dynamic random access memory, and the plurality of memory layers stacked along the first direction in the present application can make the storage density of the three-dimensional dynamic random access memory provided by the present application increase exponentially, effectively solving the problem of low density of the two-dimensional dynamic random access memory.

[0007] In addition, in the three-dimensional dynamic random access memory provided by the application, the channel region of the transistor includes two side walls along the length direction, which are recessed inward relative to the side walls of the corresponding first medium part, forming a notch. The source region and the drain region are respectively arranged on both sides along the length direction and cover the inner walls of the notch. In other words, the source region and the drain region of the transistor are not only arranged on the inner walls of the notch along the length direction of the channel region, but also cover the inner walls of the notch along the first direction. By arranging in this way, compared with the size of the source region and the drain region of the transistor in the prior art which only extends along the length direction of the channel region, the source region and the drain region of the transistor provided by the application can additionally have a part covering the inner walls of the notch along the first direction, i.e. have a larger geometric size in the second direction, have a larger area of the source region and the drain region, and thus increase the contact area between the source region and the contact structure or the capacitor and the contact area between the drain region and the contact structure or the capacitor, which is beneficial to reduce the contact resistance between the source region and the contact structure or the capacitor and the contact resistance between the drain region and the contact structure or the capacitor, improve the speed of the transistor, improve the storage performance of each storage unit, and improve the leakage current.

[0008] As a possible implementation, the ratio of the height of the notch to the width of the notch is greater than or equal to 0.1 and less than or equal to 10. The height of the notch is parallel to the first direction, and the width of the notch is parallel to the second direction.

[0009] With the above technical solution, when the height of the notch and the width of the notch are within the above range, the notch has a larger surface area, and because the source region and the drain region cover the inner walls of the notch, compared with the prior art, the source region and the drain region in the application also have an additional surface area in the height direction of the notch, i.e. the first direction, thereby increasing the contact area between the source region and the contact structure or the capacitor and the contact area between the drain region and the contact structure or the capacitor, which is beneficial to reduce the contact resistance between the source region and the contact structure or the capacitor and the contact resistance between the drain region and the contact structure or the capacitor, improve the speed of the transistor, and improve the leakage current. Moreover, it can also prevent the size of the notch from being too large, so as to ensure that the lateral etching width of the first medium layer and the gate layer arranged on the first medium layer, i.e. the width of the notch, is not too large when forming the notch in the process of manufacturing the three-dimensional dynamic random access memory provided by the application, thereby reducing the difficulty of lateral etching and improving the yield of manufacturing the three-dimensional dynamic random access memory provided by the application.

[0010] As a possible implementation, the ratio of the length of the channel region to the thickness of the channel region is greater than or equal to 10 and less than or equal to 1000. The thickness direction of the channel region is parallel to the first direction.

[0011] In the case of the above technical solution, the source region and the drain region in the prior art extend from the sidewall of the channel region only in the second direction. When the length-width ratio of the channel region is within the above range, if the source region and the drain region only extend in the second direction, the size of the source region and the drain region is small. If the size of the source region and the drain region is increased by simply increasing the extension length of the source region and the drain region in the second direction, the source region and the drain region are prone to collapse. Based on this, in the present application, the source region and the drain region not only cover the inner wall of the notch in the second direction, but also cover the inner wall of the notch in the first direction. At this time, not only the area of the source region and the drain region can be increased, but also the risk of collapse of the source region and the drain region can be prevented, further improving the yield of the three-dimensional dynamic random access memory.

[0012] As a possible implementation, the ratio of the thickness of the channel region to the width of the notch is greater than or equal to 0.1 and less than or equal to 10. The width of the notch is parallel to the second direction.

[0013] In the case of the above technical solution, the transistor provided by the present application still has the source region area and the drain region area provided by the prior art at both ends of the length direction of the channel region. In combination with the foregoing, the transistor provided by the present application further includes the source region area and the drain region area in the first direction. The source region area and the drain region area of the transistor provided by the present application are larger than the source region area and the drain region area of the transistor in the prior art. For the beneficial effects of the present application, please refer to the foregoing, which will not be repeated here.

[0014] As a possible implementation, the material of the channel region includes indium gallium zinc oxide.

[0015] In the case of the above technical solution, indium gallium zinc oxide has a relatively high carrier mobility, which can make the transistor provided by the present application have faster signal transmission and switching speed, thereby improving the working efficiency and response speed of the three-dimensional dynamic random access memory provided by the present application. Moreover, the current of the transistor with the channel region material including indium gallium zinc oxide in the off state is very small, which helps to reduce the power consumption of the three-dimensional dynamic random access memory provided by the present application, and prolong the battery life of the electronic device using the three-dimensional dynamic random access memory provided by the present application. It can also reduce the demand for heat dissipation systems, thereby improving the reliability and stability of the electronic device using the three-dimensional dynamic random access memory provided by the present application. At the same time, when manufacturing the three-dimensional dynamic random access memory provided by the present application, the channel region of the indium gallium zinc oxide material can be made by low-temperature process. The low-temperature process can reduce the demand for expensive high-temperature equipment and complex process steps, thereby reducing the cost; it can also reduce the risk of thermal damage to the three-dimensional memory, thereby improving the yield of the chip. In addition, although the channel region material is indium gallium zinc oxide, the structure strength of the channel region is relatively low, but the channel region manufactured by the present application is not suspended in the manufacturing process, and will not collapse due to the relatively low structure strength of the channel region.

[0016] As a possible implementation, the source region, the drain region and the channel region are integrally continuous.

[0017] In the case of the above technical solution, the source region, the drain region and the channel region can be formed in the same process when manufacturing the three-dimensional dynamic random access memory provided by the application, which can reduce the process steps, reduce the manufacturing cost and improve the yield.

[0018] As a possible implementation, the gate includes a first gate and a second gate arranged on both sides of the channel region along the first direction.

[0019] In the case of the above technical solution, the transistor provided by the application is a double-gate transistor. The conventional transistor has only one gate to control the current in the channel region, while the transistor provided by the application has two gates. The double-gate transistor can have twice the gate control area in the same channel region area, which can effectively improve the control ability of the gate to the channel region, making the control of the carriers in the channel region by the gate more precise and flexible, and can more effectively adjust the conduction and cutoff of the current, thereby improving the switching performance of the transistor provided by the application, effectively suppressing the short channel effect, and being beneficial to further reducing the size of the transistor provided by the application, thereby improving the storage density of the three-dimensional dynamic random access memory provided by the application. For example, under low voltage operation, the double-gate transistor can more accurately control the current to achieve faster switching conversion, which is beneficial to reducing the power consumption of the three-dimensional dynamic random access memory provided by the application.

[0020] As a possible implementation, the three-dimensional dynamic random access memory further includes a contact structure. When the transistor includes a source region and a drain region, the source region is electrically connected to the capacitor, and the drain region is electrically connected to the contact structure; or when the transistor includes a source region and a drain region, the drain region is electrically connected to the capacitor, and the source region is electrically connected to the contact structure. The dielectric structure further includes a second dielectric part and a third dielectric part. The second dielectric part is located between two capacitors spaced apart along the third direction and between two contact structures spaced apart along the third direction. The third dielectric part is located between two transistors spaced apart along the third direction.

[0021] In the case of the above technical solution, the second dielectric part and the third dielectric part electrically isolate the plurality of storage units spaced apart along the second direction, so that the plurality of storage units spaced apart along the second direction can be accessed individually.

[0022] As a possible implementation, the capacitor includes a first electrode, a dielectric layer and a second electrode. The dielectric layer is located between the first electrode and the second electrode. Each first electrode is filled in a corresponding recess. The dielectric layer and the second electrode are arranged between two adjacent transistors spaced along the second direction. The dielectric layers included in different capacitors spaced along the first direction are integrally continuous, and the second electrodes included in different capacitors spaced along the first direction are integrally continuous.

[0023] In the above technical solution, the first electrode can also be reused as the source electrode or the drain electrode of the transistor provided by the application, and also as one of the electrode plates of the capacitor included in the storage unit provided by the application. The transistor and the capacitor are connected to form a storage unit of a dynamic random access memory of a transistor and a capacitor (1T1C). In addition, the integrally continuous second electrode and the dielectric layer can simultaneously form the dielectric layers of different capacitors and simultaneously form the second electrodes of different capacitors when manufacturing the three-dimensional dynamic random access memory provided by the application, thereby reducing the process steps of separately forming the dielectric layers and the second electrodes of different capacitors, and being beneficial to reducing costs and improving yield.

[0024] In a second aspect, the application further provides a manufacturing method of a three-dimensional dynamic random access memory, which includes: forming a plurality of storage units arranged in a three-dimensional array; the plurality of storage units arranged in a three-dimensional array include a plurality of storage layers spaced along a first direction, each storage layer includes a plurality of storage groups spaced along a second direction, and each storage group includes a plurality of storage units distributed along a third direction; the first direction, the second direction and the third direction are different from each other; each storage unit includes a transistor and a capacitor; a dielectric structure for isolating different storage units is formed; the dielectric structure includes a first dielectric part located between two transistors spaced along the first direction; the transistor includes a gate, a gate dielectric layer, a channel region, a source region and a drain region; the length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are recessed inwardly relative to the side walls of the corresponding first dielectric part to form a recess; the source region and the drain region are respectively arranged on the two sides along the length direction and cover the inner walls of the recess; and the gate dielectric layer is located between the gate and the channel region, the source region and the drain region.

[0025] Compared with the prior art, the manufacturing method of the three-dimensional dynamic random access memory provided by the application has the same beneficial effects as the three-dimensional dynamic random access memory of the above technical solution, which will not be repeated here.

[0026] As a possible implementation, forming a plurality of memory cells in a three-dimensional array, and forming a dielectric structure for isolating different memory cells includes: forming a stack structure, and a second dielectric portion penetrating the stack structure; the stack structure includes a plurality of stack units stacked along a first direction; each stack unit includes a first dielectric layer, and a stack layer on the first dielectric layer; the stack layer includes a second dielectric layer and a gate stacked along a second direction; the material of the first dielectric layer is different from the material of the second dielectric layer; the stack structure is provided with a first via group and a second via group spaced along a third direction; the first via group and the second via group each include a plurality of vias spaced along the third direction; the second dielectric portion is arranged between two vias adjacent along the first direction in the same first via group, and arranged between two vias adjacent along the first direction in the same second via group; the first dielectric portion includes the first dielectric layer. Next, the edge portion of each gate layer is selectively removed to form a notch. Next, the second dielectric layer is selectively etched to form a third dielectric portion with the remaining second dielectric layer; the third dielectric portion is between two transistors spaced along the third direction; the dielectric structure includes the first dielectric portion, the second dielectric portion and the third dielectric portion. Next, a gate dielectric layer is deposited to cover the outer periphery of the gate; and a channel region, a source region and a drain region are deposited on the gate dielectric layer. Next, a contact structure is formed in each via included in the first via group, and a first electrode of a capacitor is formed in the portion of each via included in the second via group corresponding to the notch. Next, a dielectric layer and a second electrode are sequentially formed in each via included in the second via group; the capacitor includes the first electrode, the dielectric layer and the second electrode.

[0027] In the technical solution, the first medium part includes all the first medium layers, and the second medium part removed completely is a pre-occupying structure of the channel region. After being removed, the gate medium layer covering the outer periphery of the gate electrode is deposited, and then the channel region, the source region and the drain region are deposited on the gate medium layer. In the prior art, in the process of manufacturing the transistor, the sacrificial layer stacked on both sides of the channel region is removed, and then the gate medium layer and the gate electrode are formed on both sides of the channel region along the first direction and the second direction. At this time, the channel region is suspended, and the channel region is a semiconductor material with relatively low structural strength. In the case that the storage unit has a small geometric size, the channel region of the semiconductor material with a large aspect ratio along the second direction may collapse, causing the transistor to deform, thereby reducing the performance of the storage unit and even causing the storage unit to fail to work normally, and reducing the yield. Based on this, in the process of manufacturing the three-dimensional dynamic random access memory, after the second medium layer is selectively etched to form the third medium part with the remaining second medium layer, the gate electrode is suspended. Compared with the channel region material, the gate electrode material has higher structural strength and is less likely to collapse due to a large aspect ratio along the second direction in the case that the storage unit has a small geometric size. The manufacturing method of the three-dimensional dynamic random access memory provided by the application can ensure the structural regularity of the transistor, thereby ensuring the normal operation and stable performance of the storage unit manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided by the application, and improving the yield.

[0028] As a possible implementation, forming the stack structure and the second medium part penetrating the stack structure includes: forming a stack material layer. Next, a third via group and a fourth via group penetrating the stack material layer are formed; the aperture pattern of the third via group is the same as the top pattern of the second medium layer. Next, the second medium part filled in the third via group and the fourth via group is formed.

[0029] In the technical solution, compared with the prior art, the three-dimensional dynamic random access memory manufacturing method provided by the application has the same beneficial effects as the three-dimensional dynamic random access memory of the above technical solution, which will not be repeated here.

[0030] As a possible implementation, the aperture of each via included in the first via group is greater than or equal to 30 nm and less than or equal to 3000 nm.

[0031] In the technical solution, the aperture of each via included in the first via group is greater than or equal to 30 nm and less than or equal to 3000 nm.

[0032] As a possible implementation, the aperture of each via included in the second via group is greater than or equal to 50 nm and less than or equal to 5000 nm.

[0033] In the above technical solution, the aperture is not too small, so that the process requirement of etching and photolithography is not too high, and the cost is reduced. The aperture is not too small, so that the capacitor area is not too small, and the refresh frequency is not too high, and the power consumption is reduced. The aperture is not too large, so that the area is not too large, and the storage density is increased. In the manufacturing of the first electrode and the contact structure, the material layer of the first electrode and the contact structure is deposited on the surface of the three-dimensional dynamic random access memory, and then etched to form the first electrode and the contact structure. The material layer fills each via of the first via group, but only forms on the inner wall of each via of the second via group. In the subsequent etching process, only the material layer on the top of each via of the first via group and the inner wall of each via of the second via group is removed. In this process, the mask is not needed, the process steps are reduced, the cost is reduced, and the yield is improved. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0035] Figure 1 A schematic diagram of the three-dimensional dynamic random access memory according to an embodiment of the application;

[0036] Figure 2 A schematic diagram of the formation of the stack material layer according to an embodiment of the application;

[0037] Figure 3 A schematic diagram of the formation of the third via group and the fourth via group according to an embodiment of the application;

[0038] Figure 4 A schematic diagram of the formation of the second dielectric part according to an embodiment of the application;

[0039] Figure 5 A schematic diagram of the formation of the first via group and the second via group according to an embodiment of the application;

[0040] Figure 6 A schematic diagram of the formation of the notch according to an embodiment of the application;

[0041] Figure 7 A schematic diagram for removing the second dielectric layer in the embodiment of the present application;

[0042] Figure 8 A schematic diagram for forming the gate dielectric layer in the embodiment of the present application;

[0043] Figure 9 A schematic diagram for forming the channel layer in the embodiment of the present application along the first direction and the second direction;

[0044] Figure 10 A schematic diagram for forming the electrode layer in the embodiment of the present application along the first direction and the second direction;

[0045] Figure 11 A schematic diagram for forming the first electrode and the contact structure in the embodiment of the present application along the first direction and the second direction;

[0046] Figure 12 A schematic diagram for forming the dielectric layer and forming the second electrode in the embodiment of the present application.

[0047] Reference signs:

[0048] 100 - memory cell, 101 - channel region, 102 - source region, 103 - drain region, 104 - notch, 105 - channel layer, 110 - gate, 111 - first gate, 112 - second gate, 120 - gate dielectric layer, 130 - contact structure, 140 - transistor;

[0049] 200 - capacitor, 201 - first electrode, 202 - dielectric layer, 203 - second electrode, 204 - electrode layer;

[0050] 310 - first dielectric part, 311 - first dielectric layer, 320 - second dielectric part, 331 - second dielectric layer, 332 - third dielectric part;

[0051] 410 - first via group, 420 - second via group, 430 - third via group, 440 - fourth via group. DETAILED DESCRIPTION

[0052] In order to make the technical problems to be solved by the embodiments of the present application, the technical solutions and beneficial effects more clearly understood, the embodiments of the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, and are not used to limit the embodiments of the present application.

[0053] It should be noted that when an element is referred to as being "fixed" or "set up" on another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or indirectly connected to the other element.

[0054] In addition, the terms "first", "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more than two, unless otherwise explicitly specified and limited. The meaning of "several" is one or more than one, unless otherwise explicitly specified and limited.

[0055] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right" and the like indicate the orientation or positional relationship shown in the drawings, and are only used for the purpose of facilitating the description of the embodiments of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0056] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0057] In a computer system, memory is a key component for storing data and programs. Dynamic Random Access Memory (DRAM) as an important memory type plays a key role in modern computer architecture. Dynamic Random Access Memory includes a 1T1C memory cell structure. The memory cell of such Dynamic Random Access Memory is composed of a transistor and a capacitor connected to the source or drain of the transistor. The capacitor is used to store electric charge, and the transistor is used to control access to the capacitor. Such Dynamic Random Access Memory also includes a word line connected to the gate of the transistor, and a bit line connected to the source or drain region of the transistor which is not connected to the capacitor. When accessing data of a certain memory cell, the word line connected to the memory cell is selected, and a voltage is input on the word line to turn on the transistor. After the transistor is turned on, the bit line connected to the memory cell is selected to complete the selection of the memory cell and allow access to the electric charge in the capacitor. However, since the capacitor will gradually leak electricity, resulting in a decrease in stored electric charge, Dynamic Random Access Memory needs to be refreshed regularly (usually every few milliseconds) to maintain the validity of the data. The refresh operation reads the data in each memory cell and rewrites it to replenish the lost electric charge in the capacitor.

[0058] In the prior art, the memory cells of Dynamic Random Access Memory are arrayed in the horizontal direction of the wafer, i.e. two-dimensional Dynamic Random Access Memory. In two-dimensional Dynamic Random Access Memory, transistors are arrayed on the wafer, and capacitors can be distributed in the same plane as the transistors in the same way, or can be arranged above or below the transistors to increase the storage density. However, the development of computer systems has put higher requirements on the density of Dynamic Random Access Memory, and the densities of the aforementioned two-dimensional Dynamic Random Access Memory are limited by the process. Both the transistors and the capacitors cannot be infinitely reduced to meet the density requirements.

[0059] To solve the above problems, please refer to Figure 1The embodiment of the present application provides a three-dimensional dynamic random access memory, which comprises a plurality of storage units 100 arranged in a three-dimensional array and a medium structure for isolating different storage units 100; the plurality of storage units 100 arranged in a three-dimensional array comprises a plurality of storage layers spaced apart along a first direction, each storage layer comprises a plurality of storage groups spaced apart along a second direction, and each storage group comprises a plurality of storage units 100 arranged along a third direction; the first direction, the second direction and the third direction are different from each other. Each storage unit 100 comprises a transistor 140 and a capacitor 200; the medium structure comprises a first medium part 310 between two transistors 140 spaced apart along the first direction. The transistor 140 comprises a gate 110, a gate medium layer 120, a channel region 101, a source region 102 and a drain region 103; the length direction of the channel region 101 is parallel to the second direction, and the two side walls of the channel region 101 along the length direction are recessed inward relative to the side walls of the corresponding first medium part 310 to form a notch 104; the source region 102 and the drain region 103 are respectively arranged on the two sides along the length direction and cover the inner walls of the notches 104; the gate medium layer 120 is between the gate 110 and the channel region 101, the source region 102 and the drain region 103 respectively. The capacitor 200 is electrically connected with the source region 102 or the drain region 103 of the transistor 140.

[0060] In the case of adopting the above technical solution, refer to Figure 1 The plurality of storage units 100 are arranged along the third direction to form a storage group, the plurality of storage groups are spaced apart along the second direction to form a storage layer, and the plurality of storage layers are spaced apart along the first direction to form the plurality of storage units 100 arranged in a three-dimensional array, thereby forming the three-dimensional dynamic random access memory provided by the embodiment of the present application. Compared with the prior art, the storage layer forms a structure similar to the two-dimensional dynamic random access memory of the prior art, but the plurality of stacked storage layers are stacked in the first direction, so that the storage density of the three-dimensional dynamic random access memory provided by the embodiment of the present application is increased by several times, thereby effectively solving the problem of low density of the two-dimensional dynamic random access memory.

[0061] In addition, refer to Figure 1In the storage unit 100 included in the three-dimensional dynamic random access memory provided by the embodiment of the present application, the two sidewalls of the channel region 101 of the transistor 140 along the length direction are recessed inwardly relative to the sidewalls of the corresponding first dielectric part 310, forming a recess 104; the source region 102 and the drain region 103 are respectively arranged on the two sides along the length direction and cover the inner walls of the recess 104. In other words, the source region 102 and the drain region 103 of the transistor 140 are not only arranged on the inner walls of the recess 104 along the length direction of the channel region 101, but also cover the inner walls of the recess 104 along the first direction. By such an arrangement, compared with the size of the source region 102 and the drain region 103 of the transistor 140 in the prior art which only extends out relative to the length direction of the channel region 101, the source region 102 and the drain region 103 of the transistor 140 provided by the embodiment of the present application can additionally have a part covering the inner walls of the recess 104 along the first direction, i.e. have a larger geometric size in the second direction, have a larger area of the source region 102 and the drain region 103, and thus increase the contact area between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200 respectively, which is conducive to reducing the contact resistance between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200 respectively, improving the speed of the transistor 140, and improving the leakage current.

[0062] In actual application, the embodiment of the present application does not make specific limitation on the specific arrangement direction and distribution of the different storage units 100, as long as the different storage units 100 are distributed in a three-dimensional array. As for the specific directions of the above-mentioned first direction, the second direction and the third direction, this place does not make specific limitation, as long as the directions of any two of the above-mentioned three are different.

[0063] For example, the first direction is the height direction of the three-dimensional dynamic random access memory provided by the embodiment of the present application, secondly, the second direction and the third direction can be determined according to the distribution of different storage units 100 in the same storage layer. For example, please refer to Figure 1 When the different storage units 100 in the same storage layer are distributed in a rectangular array, the second direction and the third direction can be the directions of the length and the width of the rectangular array respectively. For another example, when the different storage units 100 in the same storage layer are distributed in a parallelogram array, the second direction and the third direction can be the directions of two adjacent sides of the parallelogram array respectively. In another example, for another example, when the different storage units 100 in the same storage layer are distributed in a concentric circular array, the second direction and the third direction can be the radial direction and the circumferential direction of the concentric circular array respectively. It can be understood that when the distribution mode of the storage units in the same storage layer is different, the second direction and the third direction can be changed along with the distribution.

[0064] In actual application, the embodiment of the present application does not limit the specific shape and distribution of the medium structure, as long as it can isolate different storage units 100.

[0065] Specifically, please refer to Figure 1 The medium structure includes a first medium part 310 between two transistors 140 distributed along the first direction. The first medium part 310 protrudes the channel region 101 in the second direction to form a notch 104.

[0066] In actual application, the embodiment of the present application does not limit the material of the first medium part 310, as long as it can isolate and insulate the gate 110 included in the two adjacent transistors 140 along the first direction. For example, the first medium part 310 can use silicon oxide or silicon nitride. The first medium layer 311 can also use a combination of multiple materials, as long as it can be realized in the process.

[0067] As for the distance between the two adjacent first medium parts 310, it can be understood that it is determined by the size of the transistor along the first direction between the two adjacent first medium parts 310. For example, the distance between the two adjacent first medium parts 310 can be 5nm-500nm.

[0068] As for the thickness of the first medium part 310, the embodiment of the present application does not limit it, as long as it can isolate and insulate the gate 110 included in the two adjacent transistors 140 along the first direction. For example, the thickness of the first medium part 310 can be 10nm-1000nm.

[0069] As for the shape of the notch 104, please refer to Figure 1 The bottom of the notch 104 is composed of the sidewall of the gate 110 and the channel region 101 along the first direction; the sidewall of the notch 104 is composed of the opposite surface of the protruding part of the first medium part 310 on both sides of the transistor 140 in the first direction, and is composed of the structure arranged along the third direction to isolate the two storage units 100 in the third direction.

[0070] It can be understood that the three-dimensional dynamic random access memory provided by the embodiment of the present application also includes a plurality of contact structures 130 which can be used as data lines or bit lines, and a second medium part 320 which isolates the contact structures 130 distributed along the third direction. Each contact structure 130 is connected to the source region 102 or the drain region 103 of the transistor 140 included in the plurality of storage units 100 along the first direction, and is connected to the source region 102 or the drain region 103 of the transistor 140 included in the two adjacent storage units 100 along the second direction. The second medium part 320 penetrates the three-dimensional dynamic random access memory provided by the embodiment of the present application to completely isolate the two adjacent contact structures 130 along the third direction.

[0071] In actual application, the material of the contact structure 130 is not limited, and can be determined according to the performance and manufacturing process requirements of the three-dimensional dynamic random access memory provided by the embodiment of the present application. For example, the material of the contact structure 130 can be at least one of copper, aluminum, chromium, and tungsten.

[0072] In actual application, the material of the second dielectric part 320 is not limited, and only needs to meet the requirement that the second dielectric part 320 is structured and insulated in two adjacent through holes included in the first through hole group 410 arranged on both sides of the second dielectric part 320 in the third direction, and the requirement that the second dielectric part 320 is structured and insulated in two adjacent through holes included in the second through hole group 420 arranged on both sides of the second dielectric part 320 in the third direction.

[0073] It should be noted that the material of the first dielectric part 310 and the material of the second dielectric part 320 can be the same or different, and can be determined according to the process during manufacturing.

[0074] It can be understood that, referring to Figure 1 , in the third direction, the dielectric structure includes a third dielectric part 332, and the third dielectric part 332 is located between two transistors 140 spaced apart in the third direction. The third dielectric part 332 at least electrically isolates the channel regions 101 of the two transistors 140 spaced apart in the third direction, so as to facilitate separate access to two adjacent memory cells 100 including two adjacent transistors 140 distributed in the third direction. The gates 110 of the two transistors 140 spaced apart in the third direction are connected to each other to form a word line of the three-dimensional dynamic random access memory provided by the embodiment of the present application. Moreover, in the third direction, the gate 110 region between the two transistors 140 spaced apart does not recess into the first dielectric part 310, and the side wall of the third dielectric part 332 is flush with the side wall of the recess 104 in the third direction, and the gate dielectric layer 120 is also arranged on the side wall of the recess 104 in the third direction, thereby further increasing the contact area of the source region 102 and the drain region 103 with the capacitor 200 or the contact structure 130.

[0075] Regarding the material of the third dielectric part 332, it is different from the material of the first dielectric part 310 and the material of the second dielectric part 320, and please refer to the subsequent content for the purpose of selective etching of the third dielectric part 332. For example, in the case that the materials of the first dielectric part 310 and the second dielectric part 320 are the same and are both silicon oxide, the third dielectric part 332 can be silicon nitride.

[0076] It can be understood that, referring to Figure 1The three-dimensional dynamic random access memory provided by the embodiment of the present application comprises each memory cell 100, each memory cell 100 comprises a transistor 140 and a capacitor 200, so as to form a 1T1C dynamic random access memory structure.

[0077] In the actual application process, the connection relationship between the transistor 140 and the capacitor 200 included in the memory cell 100 is not specifically limited by the embodiment of the present application, and can be determined according to the conductive type of the transistor 140 and the actual demand. For example, when the source region 102 and the drain region 103 included in the transistor 140 are connected, the source region 102 is electrically connected with the capacitor 200, and the drain region 103 is electrically connected with the contact structure 130; or, please refer to Figure 1 When the source region 102 and the drain region 103 included in the transistor 140 are connected, the drain region 103 is electrically connected with the capacitor 200, and the source region 102 is electrically connected with the contact structure 130.

[0078] It should be noted that the embodiment of the present application provides only the case that the drain region 103 is electrically connected with the capacitor 200, and the source region 102 is electrically connected with the contact structure 130, but it does not mean that only the above connection relationship can be. The specific connection relationship between the source region 102 and the drain region 103 in the transistor 140 and the contact structure 130 and the capacitor 200 can be referred to the foregoing, when the drain region 103 is electrically connected with the capacitor, the source region 102 is electrically connected with the contact structure.

[0079] It can be understood that in the third direction, the second medium part 320 also isolates the capacitors 200 included in the plurality of memory cells 100, so as to realize the isolation of the data stored in the plurality of memory cells 100.

[0080] Please refer to Figure 1 The transistor 140 comprises a gate 110, a gate dielectric layer 120, a channel region 101, a source region 102 and a drain region 103.

[0081] In terms of structure, the length direction of the channel region 101 is parallel to the second direction, and the two sidewalls of the channel region 101 along the length direction are recessed inwardly relative to the sidewalls of the corresponding first dielectric part 310 to form the notch 104; the source region 102 and the drain region 103 are respectively arranged on the two sides along the length direction and cover the inner walls of the notch 104; and the gate dielectric layer 120 is located between the gate 110 and the channel region 101, the source region 102 and the drain region 103. Since the channel region 101, the source region 102 and the drain region 103 are formed after the gate 110, the three-dimensional dynamic random access memory provided by the embodiment of the present application will not be suspended during manufacturing, which is beneficial to prevent collapse due to the low structural strength of the channel region 101, the source region 102 and the drain region 103, thereby ensuring the structural regularity of the transistor 140, thereby ensuring the normal operation and performance stability of the memory cell 100 manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided by the present application, and thereby improving the yield.

[0082] In actual application, the structure of the gate 110 of the transistor 140 is not specifically limited in the embodiment of the present application, and can be determined according to the performance requirements of the three-dimensional dynamic random access memory provided by the embodiment of the present application. The structure of the gate 110 of the transistor 140 can be a conventional single-gate transistor or a double-gate transistor, or other possible gate 110 structures.

[0083] Exemplarily, the transistor 140 is a conventional single-gate transistor. In the first direction, the gate 110 is arranged on the first dielectric part 310, the gate dielectric layer 120 is arranged on the gate 110, and the channel region 101, the source region 102 and the drain region 103 are simultaneously arranged on the gate 110 and the first dielectric part 310.

[0084] Exemplarily, the transistor 140 is a double-gate transistor. Please refer to Figure 1In the first direction, the first gate 111 and the second gate 112 included in the gate 110 are arranged on two adjacent layers of the first dielectric part 310 respectively, and the edges of the first gate 111 and the second gate 112 are recessed into the first dielectric part 310 along the second direction to form the notch 104, that is, the projection of the first gate 111 and the second gate 112 in the second direction is smaller than the projection of the first dielectric part 310 in the second direction. Between the two adjacent layers of the first dielectric part 310, the gate dielectric layer 120 covering the outer periphery of the gate 110 is arranged on the first gate 111, the second gate 112 and the inner wall of the notch 104, and the channel region 101, the source region 102 and the drain region 103 covering the outer periphery of the gate dielectric layer 120 are arranged on the gate dielectric layer 120. The gate 110, the gate dielectric layer 120, the channel region 101, the source region 102 and the drain region 103 form the transistor 140. The transistor 140 provided by the embodiment of the present application has two gates 110, and the double-gate transistor can have a larger gate control area under the condition of the same channel region 101 area, so that the control ability of the gate 110 to the channel region 101 can be effectively improved, which makes the control of the carriers in the channel region 101 by the gate 110 more accurate and flexible, and the on and off of the current can be more effectively adjusted, so that the switching performance of the transistor 140 provided by the embodiment of the present application is improved. For example, under low-voltage operation, the double-gate transistor can more accurately control the current to realize faster switching conversion, which is beneficial to reduce the power consumption of the three-dimensional dynamic random access memory provided by the embodiment of the present application. Moreover, the transistor 140 provided by the embodiment of the present application is a double-gate transistor, which can effectively suppress the short channel effect, which is beneficial to further reduce the size of the transistor 140 provided by the embodiment of the present application, so as to improve the storage density of the three-dimensional dynamic random access memory provided by the embodiment of the present application.

[0085] As to the connection relationship of the source region 102, the drain region 103 and the channel region 101, they can be simultaneously manufactured and integrally continuous; or the source region 102, the drain region 103 and the channel region 101 can be formed separately, the source region 102 and the channel region 101 are connected at the bottom of one notch 104, and the drain region 103 and the channel region 101 are connected at the bottom of another notch 104.

[0086] Optionally, the source region 102, the drain region 103 and the channel region 101 are integrally continuous, in which case, when the three-dimensional dynamic random access memory provided by the embodiment of the present application is manufactured, the source region 102, the drain region 103 and the channel region 101 can be formed in the same process, so that the process steps can be reduced, the manufacturing cost can be reduced, and the yield can be improved.

[0087] In actual application, the material of the channel region 101 is not specifically limited, as long as the performance of the material can meet the speed requirement of the three-dimensional dynamic random access memory provided by the embodiment of the application. The material of the channel region 101 can be common silicon material, or high electron mobility material such as germanium, silicon germanium, and indium gallium zinc oxide, so as to reduce the resistivity of the channel region 101 and improve the speed of the transistor 140.

[0088] Optionally, the material of the channel region 101 includes indium gallium zinc oxide. In this case, the indium gallium zinc oxide has relatively high carrier mobility, which means that the speed of the electron moving in the material is fast, so that the transistor 140 provided by the embodiment of the application has faster signal transmission and switching speed, thereby improving the working efficiency and response speed of the three-dimensional dynamic random access memory provided by the embodiment of the application. The current of the transistor 140 with the channel region 101 of indium gallium zinc oxide is very small in the off state, which helps to reduce the power consumption of the three-dimensional dynamic random access memory provided by the embodiment of the application, improve the battery endurance time of the electronic device applying the three-dimensional dynamic random access memory provided by the embodiment of the application, and reduce the demand for the heat dissipation system, thereby improving the reliability and stability of the electronic device applying the three-dimensional dynamic random access memory provided by the embodiment of the application. At the same time, in the manufacturing of the three-dimensional dynamic random access memory provided by the embodiment of the application, the channel region 101 of the indium gallium zinc oxide material can be made by low-temperature process, which can reduce the demand for expensive high-temperature equipment and complex process steps, and can reduce the cost; and can reduce the risk of thermal damage to the three-dimensional memory, thereby improving the yield of the chip.

[0089] In actual application, the material of the source region 102 and the drain region 103 can be different from the material of the channel region 101, or can be the same as the material of the channel region 101, which is not specifically limited by the embodiment of the application, as long as it can meet the design requirement and process requirement of the three-dimensional dynamic random access memory provided by the embodiment of the application. When the material of the source region 102 and the drain region 103 is the same as the material of the channel region 101, it is beneficial to form an integrated and continuous source region 102, drain region 103 and channel region 101, or to form the source region 102, drain region 103 and channel region 101 separately. When the material of the source region 102 and the drain region 103 is different from the material of the channel region 101, it is beneficial to form the source region 102, drain region 103 and channel region 101 separately.

[0090] In practical application, the material of the gate dielectric layer 120 is not limited in the embodiment, and can be used in the three-dimensional dynamic random access memory provided by the embodiment. For example, high dielectric constant material including hafnium dioxide can be used to reduce the thickness of the gate dielectric layer 120, thereby reducing the height of the suspended structure in manufacturing the transistor 140, avoiding the structural damage caused by the suspended structure, improving the yield, and increasing the storage density.

[0091] In practical application, the material of the gate 110 is not limited in the embodiment, and the parameters of the material of the gate 110 can meet the design and process requirements of the three-dimensional dynamic random access memory provided by the embodiment. For example, the material of the gate 110 can be copper, aluminum or tungsten. Alternatively, the material of the gate 110 is tungsten, because tungsten is stable and not easy to diffuse to other structures, and the shape of tungsten is not easy to change under the high temperature process in manufacturing the three-dimensional dynamic random access memory provided by the embodiment, thereby ensuring the performance of the three-dimensional dynamic random access memory provided by the embodiment.

[0092] In addition, referring to Figure 1 , regarding the recess 104, the source region 102 and the drain region 103 are arranged on the inner wall of the recess 104, and the inner wall surface area of the recess 104 is the contact area between the source region 102 and the drain region 103 and the contact structure or the capacitor, so that the shape of the recess 104 is limited as follows to reduce the contact resistance between the source region 102 and the drain region 103 and the contact structure or the capacitor.

[0093] Specifically, referring to Figure 1, the ratio of the height of the recess 104 to the width of the recess 104 is greater than or equal to 0.1 and less than or equal to 10. The height of the recess 104 is parallel to the first direction, and the width of the recess 104 is parallel to the second direction. In this case, when the height of the recess 104 to the width of the recess 104 is within the above range, the recess 104 has a larger surface area, and the source region 102 and the drain region 103 cover the inner wall of the recess 104, respectively, and compared with the prior art, the source region 102 and the drain region 103 in the application have additional surface area in the height direction of the recess 104, i.e., the first direction, thereby increasing the contact area between the source region 102 and the contact structure 130 or the capacitor 200, respectively, and between the drain region 103 and the contact structure 130 or the capacitor 200, respectively, which is beneficial to reduce the contact resistance between the source region 102 and the contact structure 130 or the capacitor 200, respectively, and between the drain region 103 and the contact structure 130 or the capacitor 200, respectively, and improve the speed of the transistor 140 and the leakage current. Moreover, it also prevents the size of the recess 104 from being too large, and ensures that during the process of manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the application, when the recess 104 is formed, the lateral etching width of the first dielectric portion 310 and the gate 110 layer disposed on the first dielectric portion 310, i.e., the width of the recess 104, is not too large, which reduces the difficulty of lateral etching, thereby improving the yield of manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the application.

[0094] Further, please refer to Figure 1 , the ratio of the length of the channel region 101 to the thickness of the channel region 101 is greater than or equal to 10 and less than or equal to 1000. The thickness direction of the channel region 101 is parallel to the first direction. In this case, in the prior art, the source region 102 and the drain region 103 extend from the sidewall of the channel region 101 along the second direction, and when the ratio of the length of the channel region 101 to the width of the channel region 101 is within the above range, if the source region 102 and the drain region 103 only extend along the second direction, the size of the source region 102 and the drain region 103 is small, and if the size of the source region 102 and the drain region 103 is increased by simply increasing the extension length of the source region 102 and the drain region 103 along the second direction, the source region 102 and the drain region 103 are very easy to collapse. Based on this, in the embodiment of the application, the source region 102 and the drain region 103 not only can cover the inner wall of the recess 104 along the second direction, but also can cover the inner wall of the recess 104 along the first direction, at this time, not only the area of the source region 102 and the drain region 103 can be increased, but also the risk of collapse of the source region 102 and the drain region 103 can be prevented, which further improves the yield of the three-dimensional dynamic random access memory.

[0095] Further, a ratio of a thickness of the channel region 101 to a width of the recess 104 is greater than or equal to 0.1 and less than or equal to 10. The width of the recess 104 is parallel to the second direction. In this case, the transistor 140 provided by the embodiment of the present application still has the source region 102 area and the drain region 103 area provided by the prior art at both ends of the channel region 101 in the length direction, and in combination with the foregoing, the transistor 140 provided by the embodiment of the present application further includes the source region 102 area and the drain region 103 area along the first direction. The source region 102 area and the drain region 103 area of the transistor 140 provided by the embodiment of the present application are greater than the source region 102 area and the drain region 103 area of the transistor 140 provided by the prior art, and the beneficial effects thereof have been described above and will not be described here again.

[0096] Further, each transistor 140 includes two recesses 104 distributed along the second direction, and the source region 102 and the drain region 103 are respectively formed in the two recesses 104, and other structures connected to the source region 102 or the drain region 103.

[0097] Please refer to Figure 1 The capacitor 200 includes the first electrode 201, the dielectric layer 202, and the second electrode 203. The dielectric layer 202 is located between the first electrode 201 and the second electrode 203; each first electrode 201 is filled in the corresponding recess 104. The dielectric layer 202 and the second electrode 203 are arranged between the adjacent two transistors 140 distributed along the second direction.

[0098] Please refer to Figure 1 The drain region 103 is in electrical contact with the contact structure 130, and the source region 102 is in electrical contact with the first electrode 201.

[0099] Please refer to Figure 1 The first electrode 201 can be reused as the source electrode or the drain electrode of the transistor 140 provided by the embodiment of the present application to connect the transistor 140 and the capacitor 200.

[0100] It can be understood that if the ratio of the height of the recess 104 to the width of the recess 104 is large, the dielectric layer 202 and the second electrode 203 can also be arranged in the recess 104 to increase the area of the capacitor 200 and thus increase the amount of the capacitor 200, which is beneficial to reduce the refresh frequency of the three-dimensional dynamic random access memory provided by the present application and thus reduce the power consumption.

[0101] As to the material of the first electrode 201 and the material of the contact structure 130, they can be different or the same, which can be determined according to the performance of the three-dimensional dynamic random access memory provided by the embodiment of the present application and the manufacturing process requirement. Alternatively, the material of the first electrode 201 and the material of the contact structure 130 are the same, which can be formed in the same step when manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the present application, so as to reduce the process steps, improve the yield and reduce the cost. In addition, the material of the first electrode 201 and the material of the contact structure 130 can be selected from all metal materials used in semiconductor manufacturing, such as copper, aluminum, tungsten, etc.

[0102] In addition, the dielectric layers 202 included in the different capacitors 200 spaced apart along the first direction can be separated from each other or integrated and continuous; the second electrodes 203 included in the different capacitors 200 spaced apart along the first direction can be separated from each other or integrated and continuous. The relationship of the dielectric layers 202 included in the different capacitors 200 spaced apart along the first direction and the relationship of the second electrodes 203 included in the different capacitors 200 spaced apart along the first direction can be determined according to the area requirement of the capacitors 200 and the manufacturing process, which is not limited in the present application.

[0103] Exemplarily, referring to Figure 2 to Figure 12 , the dielectric layers 202 included in the different capacitors 200 spaced apart along the first direction are integrated and continuous, and the second electrodes 203 included in the different capacitors 200 spaced apart along the first direction are integrated and continuous. The second dielectric part 320 is arranged between the two capacitors 200 spaced apart along the third direction and between the two contact structures 130 spaced apart along the third direction. In this case, the dielectric layers 202 included in the different capacitors 200 spaced apart along the first direction are integrated and continuous, and the second electrodes 203 included in the different capacitors 200 spaced apart along the first direction are integrated and continuous, so that the insulating layer formed in the different capacitors 200 spaced apart along the first direction is not needed, the volume occupation of the insulating layer is reduced, which is beneficial to further reduce the size of the storage unit 100 provided by the embodiment of the present application, so as to improve the storage density of the three-dimensional dynamic random access memory provided by the embodiment of the present application; at the same time, the integrated and continuous second electrodes 203 and the dielectric layers 202 can make the dielectric layers 202 of the different capacitors 200 formed at the same time and the second electrodes 203 of the different capacitors 200 formed at the same time when manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the present application, so as to reduce the process steps of separately forming the dielectric layers 202 and the second electrodes 203 of the different capacitors 200, which is beneficial to reduce the cost and improve the yield.

[0104] In addition, referring to Figure 5The sizes of the transistor 140 and the capacitor 200 included in different storage units 100 can be the same or different, and can be determined according to the design of the performance of the different storage units 100. Optionally, the sizes of the transistor 140 and the capacitor 200 included in different storage units 100 are the same, so that the different storage units 100 have the same performance, and the electronic system to which the three-dimensional dynamic random access memory is applied can perform access operations on the three-dimensional dynamic random access memory.

[0105] The sizes of other parts of the three-dimensional dynamic random access memory are not specifically limited in the embodiments of the present application, as long as the process precision and other performance requirements such as insulation performance are met.

[0106] In the second aspect, the embodiments of the present application further provide a manufacturing method of a three-dimensional dynamic random access memory, which is used to manufacture the three-dimensional dynamic random access memory provided in the first aspect, and includes: forming a plurality of storage units 100 in a three-dimensional array; the plurality of storage units 100 in the three-dimensional array include a plurality of storage layers spaced apart along a first direction, each storage layer includes a plurality of storage groups spaced apart along a second direction, and each storage group includes a plurality of storage units 100 distributed along a third direction; the first direction, the second direction and the third direction are different from each other; each storage unit 100 includes a transistor 140 and a capacitor 200; a medium structure for isolating different storage units 100 is formed; the medium structure includes a first medium part 310 located between two transistors 140 spaced apart along the first direction; the transistor 140 includes a gate 110, a gate medium layer 120, a channel region 101, a source region 102 and a drain region 103; the length direction of the channel region 101 is parallel to the second direction, and the two side walls of the channel region 101 along the length direction are recessed inward relative to the side walls of the corresponding first medium part 310 to form a notch 104; the source region 102 and the drain region 103 are respectively arranged on the two sides along the length direction and cover the inner walls of the notches 104; and the gate medium layer 120 is located between the gate 110 and the channel region 101, the source region 102 and the drain region 103.

[0107] Specifically, the order of forming the storage unit 100 and the medium structure is not specifically limited in the manufacturing method, and the two can be formed at the same time.

[0108] Compared with the prior art, the manufacturing method of the three-dimensional dynamic random access memory has the same beneficial effects as the three-dimensional dynamic random access memory described above, and details are not repeated here.

[0109] The following will be described according to Figure 2 The process of manufacturing the three-dimensional dynamic random access memory is described with reference to the schematic diagram of the operation shown. Exemplarily, the manufacturing method of the three-dimensional dynamic random access memory comprises the following steps:

[0110] As shown in Figure 3 The stack structure and the second medium part 320 penetrating the stack structure are formed; the stack structure comprises a plurality of stack units arranged in layers along a first direction; each stack unit comprises a first medium layer 311 and a stack layer on the first medium layer 311; the stack layer comprises a second medium layer 331 and a gate 110 stacked in layers; the material of the first medium layer 311 is different from the material of the second medium layer 331; a first via group 410 and a second via group 420 are arranged in the stack structure along a second direction; the first via group 410 and the second via group 420 each comprise a plurality of vias arranged in a third direction; the second medium part 320 is arranged between two vias adjacent in the first direction in the same first via group 410 and arranged between two vias adjacent in the first direction in the same second via group 420; the first medium part 310 comprises the first medium layer 311.

[0111] Specifically, the first medium layer 311 is used to form the first medium part 310 to isolate the memory cells 100 along the first direction. For information about the material and thickness of the first medium layer 311, please refer to the relevant description of the first medium part 310, which will not be repeated here.

[0112] Regarding the stack layer included in the stack structure, the stack layer comprises the second medium layer 331 and the gate 110 stacked in layers, the second medium layer 331 as a sacrificial layer pre-occupies the channel region 101 and the gate medium layer 120, so as to facilitate the subsequent formation of the channel region 101 and the gate medium layer 120; the second medium layer 331 also serves as an isolation layer to insulate and separate the channel region 101 and the gate medium layer 120 of the adjacent transistors 140 distributed along the third direction after the third medium part 332 is formed. For the materials of the second medium layer 331, the first gate 111 and the second gate 112 included in the gate 110 and their beneficial effects, please refer to the relevant description of the first aspect, which will not be repeated here.

[0113] Exemplarily, the stack layer comprises the first gate 111, the second medium layer 331 and the second gate 112 arranged along the first direction, and the first gate 111 and the second gate 112 form the gate 110 to facilitate the subsequent formation of the double-gate transistor structure.

[0114] It can be understood that the stack layer can also only comprise one gate 110 and one second medium layer 331 to form a conventional transistor 140 or a back-gate transistor. The specific structure of the stack layer can be formed according to the requirements of the transistor 140 structure of the first aspect, which will not be repeated here.

[0115] It should be noted that, along the first direction, the two outermost layers of the stack structure are the first dielectric layers 311, and the thickness of the two outermost first dielectric layers 311 of the stack structure can be greater than the first dielectric layers 311 located inside the stack structure, so as to protect the stack structure and other structures formed subsequently.

[0116] Each via of the first via group 410 is used to form a contact structure 130 in the via. Each via of the second via group 420 is used to form a capacitor 200 in the via.

[0117] The shape of each via of the first via group 410 can be a cylindrical hole, a prism hole, or other possible shapes. As for the size of each via of the first via group 410, embodiments of the present application do not make specific limitations thereon, as long as the contact structure 130 can be formed in the first via.

[0118] Optionally, the aperture of each via of the first via group 410 can be greater than or equal to 30 nm and less than or equal to 3000 nm. In this case, it can be avoided that the process requirements of etching and photolithography are too high due to too small aperture, which leads to high cost, and it is beneficial to reduce the cost; it can also be avoided that the contact structure 130 is difficult to form uniformly on the hole wall or difficult to form the contact structure 130 due to too small aperture. It can also be avoided that too much area is occupied due to too large aperture, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured by embodiments of the present application.

[0119] It should be noted that the contact structure 130 formed in each via of the first via group 410 can be arranged in the inner wall of the via in a barrel shape to form a barrel-shaped bit line; or the contact structure 130 can be arranged in each via of the first via group 410 in a column shape to fill the via and form a column-shaped bit line.

[0120] The shape of each via of the second via group 420 can be a cylindrical hole, a prism hole, or other possible shapes. As for the size of each via of the second via group 420, embodiments of the present application do not make specific limitations thereon, as long as the capacitor 200 can be formed in the second via.

[0121] The aperture of each via of the second via group 420 is greater than or equal to 50 nm and less than or equal to 5000 nm. In this case, it can be avoided that the process requirements of etching and photolithography are too high due to too small aperture, which leads to high cost, and it is beneficial to reduce the cost; it can also be avoided that the area of the capacitor 200 formed due to too small aperture is small, thereby reducing the retention time of the capacitor 200, leading to higher refresh frequency, leading to power consumption rising, thereby reducing the power consumption of the three-dimensional dynamic random access memory manufactured by embodiments of the present application. It can also be avoided that too much area is occupied due to too large aperture, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured by embodiments of the present application.

[0122] It should be noted that the medium layer 202 and the second electrode 203 formed in each via hole included in the second via hole group 420 can be both barrel-shaped arranged in the inner wall of the via hole; or the medium layer 202 is barrel-shaped arranged in the inner wall of the via hole, and the second electrode 203 is column-shaped arranged to fill each via hole included in the first via hole group 410.

[0123] It should be noted that the hole diameter of the via hole is defined as the hole diameter of a cylindrical hole with the same radial cross-sectional area as the via hole.

[0124] In the third direction, the second medium part 320 separates each via hole included in the first via hole group 410, and also separates the contact structure 130 formed in the subsequent process step. In the third direction, the second medium part 320 separates each via hole included in the second via hole group 420, and also separates the capacitor 200 formed in the subsequent process step.

[0125] In actual application, the hole diameter of each via hole included in the first via hole group 410 and the hole diameter of each via hole included in the second via hole group 420 are not specifically limited, as long as the performance requirements of the structure arranged in the via hole can be met

[0126] In actual application, the method for forming the stack structure and the second medium part 320 penetrating the stack structure is not specifically limited, and can be determined according to the number of storage layers of the three-dimensional dynamic random access memory provided by the embodiment of the present application and the manufacturing process.

[0127] In an example, the method for forming the stack structure and the second medium part 320 penetrating the stack structure can include the following steps:

[0128] First, referring to Figure 4 , a deposition process or an epitaxy process is used to form a stack material layer. The stack material layer includes a stack structure including a plurality of layers of stack units arranged in a stack along a first direction, and each stack unit includes a first medium layer 311 and a stack layer on the first medium layer 311.

[0129] Second, referring to Figure 5, a third via group 430 and a fourth via group 440 are formed by lithography and etching, etc. The aperture pattern of the third via group 430 is the same as the top pattern of the second dielectric layer 331 between two vias in the same first via group 410 along the first direction. The aperture pattern of the fourth via group 440 is the same as the top pattern of the second dielectric layer 331 between two vias in the same second via group 420 along the first direction. The third via group 430 and the fourth via group 440 are formed for the subsequent step of forming the second dielectric part 320, which is used to isolate two vias in the same first via group 410 along the first direction and to isolate two vias in the same second via group 420 along the first direction. It can be understood that the aperture pattern of the first via group 410 and the aperture pattern of the third via group 430 are alternately arranged along the second direction, and the aperture pattern of the second via group 420 and the aperture pattern of the fourth via group 440 are alternately arranged along the second direction.

[0130] In the third step, please refer to Figure 6 The second dielectric part 320 filled in the third via group 430 and the fourth via group 440 is formed by deposition, etc. The material of the second dielectric part 320 is described in the first aspect, which is not repeated here.

[0131] In the fourth step, please refer to Figure 7 The first via group 410 and the second via group 420 are formed by lithography and etching, etc. The first via group 410 and the second via group 420 form the stack structure.

[0132] In another example, the above-mentioned method of forming the stack structure and the second dielectric part 320 penetrating the stack structure can also be to form a part of the stack material layer and form the first via group 410 and the second via group 420, then form another part of the stack material layer and form the first via group 410 and the second via group 420; repeat the above process to finally form the stack structure.

[0133] Next, please refer to Figure 8 The edge part of the first gate 111 and the second gate 112 is selectively removed by selective etching, etc. to form the notch 104 and the stack structure. The size of the notch 104 and its beneficial effects are described in the first aspect, which is not repeated here.

[0134] Next, please refer to Figure 9The second dielectric layer 331 is selectively removed by a process such as selective etching, so that the remaining second dielectric layer 331 forms a third dielectric portion 332 and forms a suspended area for forming the channel region 101. The suspended area is located between two transistors 140 along the third direction, with the two third dielectric portions 332 located between the two transistors 140 along the first direction.

[0135] Next, refer to Figure 10 A gate dielectric layer 120 is deposited on the entire surface of the stack structure by a thin film deposition process. The material of the gate dielectric layer 120 and its beneficial effects are described in the corresponding description of the first aspect, which will not be repeated here.

[0136] Next, refer to Figure 11 A channel layer 105 is deposited on the entire surface of the stack structure by a thin film deposition process. The channel layer 105 completely fills the suspended area and forms the channel region 101. The material of the channel layer 105 and its beneficial effects are described in the corresponding description of the channel region 101 of the first aspect, which will not be repeated here.

[0137] Next, refer to Figure 12 An electrode layer 204 is deposited on the entire surface of the stack structure by a thin film deposition process. The electrode layer 204 is processed into the first electrode 201 and the contact structure 130 in subsequent steps. The material of the electrode layer 204 and its beneficial effects are described in the corresponding description of the channel region 101 of the first aspect, which will not be repeated here.

[0138] Next, refer to Figure 12 The channel layer 105, the gate dielectric layer 120 and the electrode layer 204 located in each via of the second via group 420 are removed by processes such as photolithography and etching, only the part located in the notch 104 near each via of the second via group 420 is reserved. The part of the channel layer 105 located in the notch 104 near each via of the second via group 420 forms the drain region 103, and the part of the electrode layer 204 located in the notch 104 near each via of the second via group 420 forms the first electrode 201. The part of the channel layer 105 located in the notch 104 near each via of the first via group 410 forms the source region 102, and the electrode layer 204 located in each via of the first via group 410 forms the contact structure 130.

[0139] It should be noted that the drawings provided by the embodiments of the present application only illustrate the case that the drain region 103 is electrically connected with the capacitor 200 and the source region 102 is electrically connected with the contact structure 130, but it does not mean that only the above connection relationship can be used. The specific connection relationship between the source region 102 and the drain region 103 in the transistor 140 and the contact structure 130 and the capacitor 200 can be referred to the foregoing description, when the drain region 103 is electrically connected with the capacitor, the source region 102 is electrically connected with the contact structure.

[0140] Next, referring to Figure 12 , a dielectric layer 202 is formed in each via included in the second via group 420 by using a thin film deposition process.

[0141] Next, referring to Figure 12 , a second electrode 203 is formed in each via included in the second via group 420 by using a thin film deposition process, and the second electrode 203 is also formed on the dielectric layer 202.

[0142] It should be noted that when the gate dielectric layer 120, the channel layer 105, the electrode layer 204, the dielectric layer 202 and the second electrode 203 are formed by using a thin film deposition process, the same process such as atomic layer deposition can be used, which is beneficial to continuous processing using the same equipment, thereby reducing the damage to the three-dimensional dynamic random access memory manufactured by the embodiments of the present application when the three-dimensional dynamic random access memory is transferred between the equipment used for different processes, thereby improving the yield.

[0143] In the case of using the above technical solution, referring to ​The first medium part 310 includes the second medium layer 331 as a pre-occupancy structure of the channel region 101 after the first medium layer 31 is partially removed, and the gate medium layer 120 covering the outer periphery of the gate 110, the channel region 101, the source region 102 and the drain region 103 are sequentially deposited after the removal. In the prior art, in the process of manufacturing the transistor 140, the sacrificial layer stacked on both sides of the channel region 101 is removed first, and then the gate medium layer 120 and the gate 110 are formed on both sides of the channel region 101 along the first direction and the second direction. At this time, the channel region 101 is suspended, and the channel region 101 is a semiconductor material with relatively low structural strength. In the case that the storage unit 100 has a small geometric size, the channel region 101 of the semiconductor material with a large aspect ratio along the second direction will collapse, causing the transistor 140 to deform, thereby reducing the performance of the storage unit 100 and even causing the storage unit 100 to malfunction. Therefore, in the manufacturing process of the three-dimensional dynamic random access memory, the second medium layer 331 is selectively etched to form the third medium part 332 after the remaining second medium layer 331 is formed. Compared with the material of the channel region 101, the material of the gate 110 has higher structural strength and is less likely to collapse due to a large aspect ratio along the second direction in the case that the storage unit 100 has a small geometric size. The manufacturing method of the three-dimensional dynamic random access memory provided by the present application can ensure the structural regularity of the transistor 140, thereby ensuring the normal operation and performance stability of the storage unit 100 manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided by the present application, and improving the yield.

[0144] In addition, please refer to ​ In the process of thin film deposition, after the second electrode 203 is formed in each through hole included in the second through hole group 420, a planarization process including chemical mechanical polishing can be used to polish the outer surface of the three-dimensional dynamic random access memory manufactured by the embodiment of the present application along the first direction, the second direction and the third direction, and remove the gate medium layer 120, the channel layer 105, the electrode layer 204, the medium layer 202 and the second electrode 203, so as to ensure that the plurality of storage units 100 distributed in a three-dimensional array provided by the embodiment of the present application are insulated from each other on the outer surface of the three-dimensional dynamic random access memory.

[0145] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0146] The above merely illustrates the specific implementation of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the embodiments of the present application, which should be covered in the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A three-dimensional dynamic random access memory, characterized by, The three-dimensional dynamic random access memory comprises: a plurality of storage units distributed in a three-dimensional array, and a medium structure for isolating different storage units; the plurality of storage units distributed in a three-dimensional array comprises a plurality of storage layers spaced apart along a first direction, each of the storage layers comprises a plurality of storage groups spaced apart along a second direction, and each of the storage groups comprises a plurality of storage units distributed along a third direction; the first direction, the second direction and the third direction are different from each other; each of the storage units comprises a transistor and a capacitor; the medium structure comprises a first medium part between two transistors spaced apart along the first direction; the transistor comprises a gate, a gate medium layer, a channel region, a source region and a drain region; the length direction of the channel region is parallel to the second direction, and the two sidewalls of the channel region along the length direction are recessed inward relative to the sidewalls of the corresponding first medium part to form notches; the source region and the drain region are respectively arranged on the two sides of the channel region along the length direction and cover the inner walls of the notches; the gate medium layer is located between the gate and the channel region, the source region and the drain region respectively; the capacitor is electrically connected to the source region or the drain region of the transistor.

2. The three-dimensional dynamic random access memory of claim 1, wherein, the ratio of the height of the notch to the width of the notch is greater than or equal to 0.1 and less than or equal to 10; the height of the notch is parallel to the first direction, and the width of the notch is parallel to the second direction; and / or, the ratio of the length of the channel region to the thickness of the channel region is greater than or equal to 10 and less than or equal to 1000; the thickness direction of the channel region is parallel to the first direction; and / or, the ratio of the thickness of the channel region to the width of the notch is greater than or equal to 0.1 and less than or equal to 10; the width of the notch is parallel to the second direction.

3. The 3D DRAM of claim 1, wherein, the material of the channel region comprises indium gallium zinc oxide; and / or, the source region, the drain region and the channel region are integrally continuous.

4. The 3D DRAM of claim 1, wherein, the gate comprises a first gate and a second gate arranged on the two sides of the channel region along the first direction.

5. The 3D DRAM of claim 1, wherein, The three-dimensional dynamic random access memory further comprises a contact structure; wherein, when the source region and the drain region included in the transistor, the source region is electrically connected to the capacitor, the drain region is electrically connected to the contact structure; or, when the source region and the drain region included in the transistor, the drain region is electrically connected to the capacitor, the source region is electrically connected to the contact structure; the medium structure further comprises a second medium part and a third medium part; the second medium part is located between two capacitors spaced apart along the third direction and between two contact structures spaced apart along the third direction; the third medium part is located between two transistors spaced apart along the third direction.

6. The 3D DRAM of claim 5, wherein, the capacitor comprises a first electrode, a medium layer and a second electrode; the medium layer is located between the first electrode and the second electrode; each of the first electrodes fills in the corresponding notch; the medium layer and the second electrode are arranged between two adjacent transistors spaced apart along the second direction; The dielectric layers of different capacitors spaced along the first direction are integrally continuous, and the second electrodes of different capacitors spaced along the first direction are integrally continuous.

7. A method of manufacturing a three-dimensional dynamic random access memory, characterized by, Comprise: forming a plurality of memory cells in a three-dimensional array; the plurality of memory cells in a three-dimensional array comprises a plurality of memory layers spaced along a first direction, each memory layer comprising a plurality of memory groups spaced along a second direction, each memory group comprising a plurality of memory cells distributed along a third direction; the first direction, the second direction and the third direction are different from each other; each memory cell comprises a transistor and a capacitor; forming a dielectric structure for isolating different memory cells; the dielectric structure comprises a first dielectric part between two transistors spaced along the first direction; the transistor comprises a gate, a gate dielectric layer, a channel region, a source region and a drain region; the length direction of the channel region is parallel to the second direction, and the sidewalls of the channel region along the length direction are inwardly recessed relative to the sidewalls of the corresponding first dielectric part to form notches; the source region and the drain region are respectively arranged on the two sides of the length direction and cover the inner walls of the notches; the gate dielectric layer is between the gate and the channel region, the source region and the drain region respectively.

8. The method of manufacturing a three-dimensional dynamic random access memory according to claim 7, wherein, forming a plurality of memory cells in a three-dimensional array, and forming the dielectric structure for isolating different memory cells comprises: forming a stack structure and a second dielectric part penetrating the stack structure; the stack structure comprises a plurality of stack units arranged in layers along a first direction; each stack unit comprises a first dielectric layer and a stack layer on the first dielectric layer; the stack layer comprises a second dielectric layer and a gate stacked in layers; the material of the first dielectric layer is different from the material of the second dielectric layer; the stack structure has a first via group and a second via group spaced along the second direction; the first via group and the second via group each comprise a plurality of vias spaced along the third direction; the second dielectric part is arranged between two vias adjacent along the first direction in the same first via group and between two vias adjacent along the first direction in the same second via group; the first dielectric part comprises the first dielectric layer; selectively removing the edge portion of each gate to form the notches; selectively etching the second dielectric layer to form a third dielectric part from the remaining second dielectric layer; the third dielectric part is between two transistors spaced along the third direction; the dielectric structure comprises the first dielectric part, the second dielectric part and the third dielectric part; depositing a gate dielectric layer covering the outer periphery of the gate; and depositing a channel region, a source region and a drain region on the gate dielectric layer; forming a contact structure in each via of the first via group, and forming a first electrode of a capacitor in the portion of each via of the second via group corresponding to the notch; A dielectric layer and a second electrode are sequentially formed in each of the through holes included in the second through hole group; and the capacitor includes the first electrode, the dielectric layer, and the second electrode.

9. The method of manufacturing a three-dimensional dynamic random access memory according to claim 8, wherein, The formation of the stack structure and the second dielectric portion penetrating through the stack structure includes: forming a stack material layer; forming a third through hole group and a fourth through hole group penetrating through the stack material layer; the aperture pattern of the third through hole group is the same as the top pattern of the second dielectric layer between two through holes adjacent in the first direction in the same first through hole group; the aperture pattern of the fourth through hole group is the same as the top pattern of the second dielectric layer between two through holes adjacent in the first direction in the same second through hole group; forming the second dielectric portion filled in the third through hole group and the fourth through hole group; forming the first through hole group and the second through hole group penetrating through the stack material layer.

10. The method of manufacturing a three-dimensional dynamic random access memory according to claim 8, wherein, The aperture of each through hole included in the first through hole group is greater than or equal to 30 nm and less than or equal to 3000 nm; And / or, the aperture of each through hole included in the second through hole group is greater than or equal to 50 nm and less than or equal to 5000 nm.

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