Semiconductor structure and preparation method thereof

Abstract

The present application relates to a semiconductor structure and a method for fabricating the same. The semiconductor structure comprises: a substrate; a stacked structure located on the substrate and comprising alternating stacked semiconductor doped layers and a first isolation layer, with the semiconductor doped layers disposed on both sides of the first isolation layer along the stacking direction; a gate structure extending from the stacked structure to the substrate; a storage structure extending from the stacked structure to the substrate and surrounding the gate structure; and a channel layer located within the first isolation layer between adjacent semiconductor doped layers and surrounding the storage structure. Embodiments of the present application can effectively prevent leakage between the source and drain of a single memory cell, thereby improving the performance of flash memory devices.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Flash memory devices are non-volatile memory devices, meaning data is not lost even when power is turned off. They offer advantages such as high read and write speeds and low power consumption. To increase device integration density and reduce manufacturing costs, three-dimensional flash memory devices have emerged in related technologies.

[0003] However, the performance of existing flash memory devices still needs to be improved. Summary of the Invention

[0004] Based on this, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same to improve the performance of flash memory devices.

[0005] A semiconductor structure comprising:

[0006] substrate;

[0007] A stacked structure, located on the substrate, comprising alternately stacked semiconductor doped layers and first isolation layers, wherein the number of layers of the first isolation layer is greater than or equal to 1, and both sides of the first isolation layer along the stacking direction have the semiconductor doped layer;

[0008] a gate structure, extending through the stack structure to the substrate;

[0009] a storage structure, penetrating the stacked structure to the substrate and surrounding the gate structure;

[0010] The channel layer is located between adjacent semiconductor doping layers, is surrounded by the first isolation layer, and surrounds the storage structure.

[0011] In one embodiment, the stacked structure has a non-step region and a step region, the step region exposes a portion of the upper surface of each semiconductor doping layer to form a step plane, and the gate structure and the storage structure penetrate the stacked structure in the non-step region.

[0012] In one embodiment, the semiconductor structure further includes metal silicide and sidewall spacers, wherein the metal silicide is located on the step plane, and the sidewall spacers are located on the step sidewalls of the stacked structure.

[0013] In one embodiment, the semiconductor structure further includes a passivation layer, a bit line plug and a select line plug, the passivation layer covers the stacked structure, the storage structure and the gate structure, the bit line plug and the select line plug pass through the passivation layer and are alternately distributed on each layer of the semiconductor doping layer.

[0014] In one embodiment, the thickness of each of the semiconductor doping layers corresponding to the bit line plugs increases sequentially from top to bottom, and / or the thickness of each of the semiconductor doping layers corresponding to the select line plugs increases sequentially from top to bottom.

[0015] In one embodiment, the storage structure includes a tunneling layer, a charge trapping layer and a blocking layer arranged in sequence from the channel layer to the gate structure; the gate structure includes a high dielectric constant layer and a gate, and the high dielectric constant layer covers the surface of the storage structure and surrounds the gate.

[0016] In one embodiment, the substrate includes a second isolation layer, and the stacked structure, the storage structure, and the gate structure are located on the second isolation layer.

[0017] A method for preparing a semiconductor structure, comprising:

[0018] Providing a substrate, and forming a stacked material layer on the substrate, wherein the stacked material layer includes alternating semiconductor doping material layers and first isolation material layers, wherein the number of the first isolation material layers is greater than or equal to 1, and the semiconductor doping material layers are present on both sides of the first isolation material layer along a stacking direction;

[0019] Etching the stacked material layer to form a gate hole penetrating to the substrate;

[0020] Carving back each first isolation material layer through the gate hole to form a surrounding groove surrounding the gate hole;

[0021] forming a channel layer in the surrounding groove;

[0022] A storage structure is formed on the sidewall of the gate hole, and a gate structure is formed on the surface of the storage structure.

[0023] In one embodiment, forming a channel layer in the surrounding trench includes:

[0024] performing epitaxial growth on the semiconductor doping material layer exposed by the gate hole and the surrounding groove to form a channel material layer, wherein the channel material layer fills the surrounding groove and covers the side surface of the semiconductor doping material layer;

[0025] The channel material layer outside the surrounding groove is removed to form the channel layer.

[0026] In one embodiment, the stacked structure has a non-step region and a step region, and the gate hole is formed in the non-step region;

[0027] After sequentially forming a storage structure and a gate structure in the gate hole, the method further includes:

[0028] The stacked material layer located in the step area is etched to form a stacked structure with steps in the step area. The remaining semiconductor doping material layer after etching forms a semiconductor doping layer, and the remaining first isolation material layer forms a first isolation layer. After etching, the step area exposes part of the upper surface of each semiconductor doping layer to form a step plane.

[0029] In one embodiment, after etching the stacked material layer in the step region to form a stacked structure having steps in the step region, the method further includes:

[0030] Metal silicide is formed on the surface of the semiconductor doping layer exposed in the step area.

[0031] In one embodiment, forming a metal silicide on the surface of the semiconductor doping layer exposed in the step region includes:

[0032] forming side walls on the step sidewalls of the step area;

[0033] The metal silicide is formed on the step surface.

[0034] In one embodiment, after forming the metal silicide on the surface of the semiconductor doping layer exposed in the step region, the method further comprises:

[0035] forming a passivation material layer covering the metal silicide, the stacked structure, the storage structure, and the gate structure;

[0036] Etching the passivation material layer to form bit line contact holes and select line contact holes that are alternately arranged and extend to each layer of the metal silicide, and the remaining passivation material layer forms a passivation layer;

[0037] A bit line plug is formed in the bit line contact hole, and a select line plug is formed in the select line contact hole.

[0038] In one embodiment, the thickness of each of the semiconductor doping layers corresponding to the bit line plugs increases sequentially from top to bottom, and / or the thickness of each of the semiconductor doping layers corresponding to the select line plugs increases sequentially from top to bottom.

[0039] In one embodiment, forming a storage structure on the sidewall of the gate hole and forming a gate structure on the surface of the storage structure includes:

[0040] forming a storage structure material layer on the surface of the structure obtained after forming the channel layer, wherein the storage structure material layer includes a tunneling material layer, a charge trapping material layer, and a blocking material layer formed in sequence, and forming a high dielectric constant material layer on the surface of the blocking material layer;

[0041] Removing the storage structure material layer and the high dielectric constant material layer located at the bottom of the gate hole and on the upper surface of the stacked material layer to form a storage structure and a high dielectric constant layer, wherein the storage structure includes a tunneling layer, a charge trapping layer and a blocking layer;

[0042] The remaining gate hole is filled with a gate to form the gate structure, wherein the gate structure includes the high dielectric constant layer and the gate.

[0043] In the aforementioned semiconductor structure and fabrication method, the channel layer within the first isolation layer can form a memory cell with the memory structure and the portion of the gate structure facing it. Simultaneously, the semiconductor doped layers on both sides of the channel layer are connected to the channel layer, thereby forming the source and drain of the memory cell, respectively. In this case, adjacent memory cells in the stacking direction can share a common source or drain.

[0044] The source and drain of the same memory cell can be effectively isolated by the first isolation layer, thereby effectively preventing leakage between the source and the drain, thereby improving the performance of the flash memory device.

[0045] Furthermore, when the semiconductor structure includes multiple first isolation layers and multiple channel layers within the first isolation layers, a three-dimensional stack of multi-layer memory cells can be formed. The sources (or drains) of adjacent memory cells can be effectively isolated by the two first isolation layers therebetween, thereby effectively preventing crosstalk between adjacent memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0048] Figures 2 to 9 Schematic diagram of the cross-sectional structure of the structure obtained in each step of the preparation process of the semiconductor structure provided in one embodiment, wherein: Figure 9 FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor structure provided in one embodiment.

[0049] Description of reference numerals:

[0050] 100-substrate, 110-second isolation layer, 200-stacked structure, 210-semiconductor doped layer, 220-first isolation layer, 201-stacked material layer, 211-semiconductor doped material layer, 221-first isolation material layer, 300-channel layer, 301-channel material layer, 400-storage structure, 410-tunneling layer, 420-charge trapping layer, 430-blocking layer, 500-gate structure, 510-high dielectric constant layer, 520-gate, 600-metal silicide, 700-sidewall, 800-passivation layer, 910-bit line plug, 920-select line plug, 10-gate hole, 20-surrounding groove. DETAILED DESCRIPTION

[0051] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0053] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0054] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0055] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] In one embodiment, see Figure 1 A method for preparing a semiconductor structure is provided, which can be used to prepare a flash memory device. The flash memory device may include, but is not limited to, a NOR device. For example, the flash memory device may also be a NAND device.

[0057] The method comprises the following steps:

[0058] Step S10: providing a substrate 100 and forming a stacked material layer 201 on the substrate 100. The stacked material layer 201 includes alternating semiconductor doping material layers 211 and first isolation material layers 221. The number of first isolation material layers 221 is greater than or equal to 1, and both sides of the first isolation material layer 221 along the stacking direction have semiconductor doping material layers 211. Figure 2 ;

[0059] Step S20, etching the stacked material layer 201 to form a gate hole 10 penetrating the substrate 100, see Figure 3 Figure (a) in the figure;

[0060] Step S30, back-etching the first isolation material layer 221 through the gate hole 10 to form a surrounding groove 20 surrounding the gate hole 10, see Figure 3 Figure (b) in the figure;

[0061] Step S40: forming a channel layer 300 in the surrounding trench 20. Figure 5 ;

[0062] In step S50, a storage structure 400 is formed on the sidewall of the gate hole 10, and a gate structure 500 is formed on the surface of the storage structure 400. Figure 6 .

[0063] In step S10, the base 100 may include a substrate (not shown). The substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include a Si / SiGe, Si / SiC, a silicon-on-insulator (SOI) substrate, or a silicon germanium-on-insulator substrate.

[0064] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0065] As an example, see Figure 2 The base 100 may include a substrate (not shown) and a second isolation layer 110 formed on the substrate. A stacked material layer 201 may be formed on the second isolation layer 110, thereby effectively isolating the substrate from subsequently formed memory cells via the second isolation layer 110. The material of the second isolation layer 110 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0066] When the stacked material layer 201 is formed on the substrate 100 , the semiconductor doping material layer 211 and the first isolation material layer 221 may be repeatedly and alternately formed on the substrate 100 through a deposition process.

[0067] The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0068] As an example, both the top layer and the bottom layer of the stacked material layer 201 may be semiconductor doping material layers 211 .

[0069] Meanwhile, the material of the semiconductor doping material layer 211 may include but is not limited to polysilicon. The material of the first isolation material layer 221 may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON).

[0070] In step S20, refer to Figure 3 As shown in FIG. 2 (a), a first patterned photoresist can be formed on the stacked material layer 201. The first patterned photoresist has a first opening. The first opening can define the size and position of the gate hole 10. Then, based on the first patterned photoresist, the stacked material layer 201 is dry-etched, etc., to form the gate hole 10. The first patterned photoresist can then be removed.

[0071] It should be noted that in order to make the figure clear, Figures 3 to 9 FIG. 1 is a partial cross-sectional view of the gate hole 10 and other related structures obtained during the semiconductor structure preparation process.

[0072] In step S30, please refer to Figure 3 As shown in FIG. 5( b ), each first isolation material layer 221 between the semiconductor doping material layers 211 can be etched back from the gate hole 10 by wet etching, thereby forming a surrounding groove 20 surrounding the gate hole 10 .

[0073] At this time, a layer of surrounding grooves 20 can be formed in each first isolation material layer 221. The surrounding grooves 20 of each layer are arranged at intervals along the stacking direction, and the semiconductor doping material layer 211 is located between adjacent surrounding grooves 20.

[0074] In step S40 , a channel layer is formed in the surrounding trench. The material of the channel layer 300 is a semiconductor material, which may be the same as or different from the material of the semiconductor doping material layer 211 .

[0075] The channel layer 300 may fill the surrounding trench 20 (see Figure 5 ), or may not fill up the surrounding trench 20 (not shown). The filling degree of the channel layer 300 in the surrounding trench 20 is not limited here.

[0076] In step S50 , the memory structure 400 may be formed first, and then the gate structure 500 may be formed.

[0077] When the channel layer 300 completely fills the surrounding trench 20, the memory structure 400 and the gate structure 500 can be formed only in the gate hole 10. When the channel layer 300 does not completely fill the surrounding trench 20, the memory structure 400 and the gate structure 500 can be formed in the gate hole 10 and extend into the surrounding trench 20.

[0078] The storage structure 400 is located between the gate structure 500 and the channel layer 300, thereby enabling charge storage. The channel layer 300, the storage structure 400, and the portion of the gate structure 500 facing it can form a memory cell. Simultaneously, the semiconductor doping material layers 211 on both sides of the channel layer 300 along the stacking direction are connected to the channel layer 300, thereby respectively forming the source and drain of the memory cell. In this case, adjacent memory cells in the stacking direction can share a source or drain.

[0079] In this embodiment, semiconductor doping material layers 211 and first isolation material layers 221 are alternately formed on the substrate 100, and then after forming the gate hole 10, the first isolation material layer 221 is etched back to form a surrounding groove 20, and a channel layer 300 is formed in the surrounding groove 20. The channel layer 300 can form a storage unit with the storage structure 400 and the gate structure 500. At the same time, the source and drain of the same storage unit can be effectively isolated by the first isolation material layer 221, thereby effectively preventing leakage between the source and the drain, thereby improving the performance of the flash memory device. Moreover, when multiple channel layers are formed by forming multiple first isolation material layers, a three-dimensional stacked multi-layer storage unit can be formed. The sources (or drains) of adjacent layers of storage units can be effectively isolated by two layers of first isolation material layers 221 between them, thereby effectively preventing crosstalk between adjacent storage units.

[0080] In one embodiment, step S40 may include:

[0081] Step S41 , epitaxially growing the semiconductor doping material layer 211 exposed on the gate hole 10 and the surrounding groove 20 to form a channel material layer 301 ;

[0082] In step S42 , the channel material layer 301 outside the surrounding trench 20 is removed to form a channel layer 300 . The channel layer 300 fills the surrounding trench 20 .

[0083] In step S41, refer to Figure 3 Figure (b) and Figure 4 Homoepitaxial growth can be performed on the surface of the semiconductor doping material layer 211 exposed in the gate hole 10 and the surrounding groove 20, thereby forming a channel material layer 301 made of the same material as the semiconductor doping material layer 211. For example, when the material of the semiconductor doping material layer 211 is polysilicon, the channel material layer 301 can be a semiconductor silicon layer.

[0084] Heteroepitaxial growth may also be performed on the surface of the semiconductor doping material layer 211 exposed in the gate hole 10 and surrounding the trench 20, thereby forming a channel material layer 301 made of a material different from that of the semiconductor doping material layer 211. For example, when the semiconductor doping material layer 211 is made of polysilicon, the channel material layer 301 may be a semiconductor silicon germanium layer, etc.

[0085] After epitaxial growth, the channel material layer 301 can fill the surrounding trench 20 and cover the sidewalls of the semiconductor doping material layer 211 . Meanwhile, the channel material layer 301 can also be located on the upper surface of the top semiconductor doping material layer 211 .

[0086] In step S42, refer to Figure 5 The channel material layer 301 on the upper surface of the top semiconductor doping material layer 211 and the channel material layer 301 on the sidewall of the gate hole 10 can be removed together by etching. After etching, the channel layer 300 is formed around the remaining channel material layer 301 in the groove 20.

[0087] In this embodiment, the channel layer 300 having the same or similar structure as the semiconductor doping material layer 211 can be effectively formed by epitaxial growth, thereby effectively reducing the contact resistance between the two.

[0088] Of course, in other embodiments, the channel layer 300 may be formed by other methods. For example, the channel material layer 301 may be formed by chemical vapor deposition or atomic layer deposition, and then the channel material layer 301 outside the surrounding groove 20 is removed to form the channel layer 300.

[0089] In one embodiment, see Figure 5 as well as Figure 6 , step S50 includes:

[0090] Step S51, forming a storage structure material layer (not shown) on the surface of the structure obtained after forming the channel layer 300. The storage structure material layer includes a tunneling material layer, a charge trapping material layer, and a blocking material layer formed in sequence, and a high dielectric constant material layer is formed on the surface of the blocking material layer.

[0091] Step S52 , removing the storage structure material layer and the high dielectric constant material layer located at the bottom of the gate hole 10 and on the upper surface of the stacked material layer 201 to form a storage structure 400 and a high dielectric constant layer 510 . The storage structure 400 includes a tunneling layer 410 , a charge trapping layer 420 , and a blocking layer 430 .

[0092] In step S53 , the remaining gate holes 10 are filled with gates 520 to form a gate structure 500 . The gate structure 500 includes a high-k dielectric layer 510 and a gate 520 .

[0093] In step S51, a tunneling material layer, a charge-trapping material layer, and a blocking material layer are sequentially formed on the upper surface of the stacked material layer 201 after the channel layer 300 is formed, on the sidewalls of the channel layer 300, on the sidewalls of the gate hole 10, and on the bottom of the gate hole 10. A high-k dielectric constant material layer is then formed on the surface of the blocking material layer.

[0094] The material of the tunneling material layer may include but is not limited to oxide, the material of the charge trapping material layer may include but is not limited to nitride, the material of the blocking material layer may include but is not limited to oxide, and the material of the high dielectric constant material layer may include but is not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3), etc.

[0095] In step S52, the storage structure material layer and the high-k dielectric material layer located at the bottom of gate hole 10 and on the upper surface of stacked material layer 201 can be removed by anisotropic etching methods such as dry etching. The remaining storage structure material layer after etching forms storage structure 400. The remaining tunneling material layer forms tunneling layer 410, the remaining charge-trapping material layer forms charge-trapping layer 420, and the remaining blocking material layer forms blocking layer 430. Simultaneously, the remaining high-k dielectric material layer forms high-k dielectric layer 510.

[0096] In this case, the memory structure 400 includes a tunneling layer 410, a charge trapping layer 420, and a blocking layer 430. In other embodiments, the form of the memory structure 400 may also be different from this.

[0097] In step S53, the gate hole 10 after the memory structure 400 and the high-k dielectric layer 510 are filled and formed, and a gate material layer covering the upper surface of the stacked material layer 201 is formed. The gate material layer on the upper surface of the stacked material layer 201 is then removed by chemical mechanical polishing (CMP) or other methods to form a gate 520. The gate 520 can be connected to a word line in the wiring layer.

[0098] In one embodiment, the stacked structure 200 has a non-step region and a step region, and the gate hole 10 is formed in the non-step region.

[0099] After step S50, the method further includes:

[0100] Step S60, see Figure 7, the stacked material layer 201 located in the step area is etched to form a stacked structure 200 with steps in the step area. The remaining semiconductor doping material layer 211 after etching forms a semiconductor doping layer 210, and the remaining first isolation material layer 221 forms a first isolation layer 220. After etching, the step area exposes part of the upper surface of each semiconductor doping layer 210 to form a step plane.

[0101] At this time, the semiconductor doping material layer 211 and the first isolation material layer 221 located in the step area may be etched sequentially from top to bottom through a photolithography process, thereby forming a plurality of steps.

[0102] Each time a step is formed, a second patterned photoresist layer can be first formed. Then, the semiconductor doping material layer 211 is etched based on the second patterned photoresist to form the semiconductor doping layer 210 of the step. Then, the first isolation material layer 221 is etched based on the second patterned photoresist and the semiconductor doping layer 210 of the step to form the first isolation layer 220 of the step. Then, the second patterned photoresist is removed.

[0103] When the bottom layer of the stacked material layer is the semiconductor doping material layer 211 , when forming the last step, the bottommost step can be formed after etching the semiconductor doping material layer 211 .

[0104] It is understandable that, in the process of forming each step, when forming a step located at a non-top layer, the formed second patterned photoresist can cover the non-step area and the previously formed upper step, thereby protecting the upper step.

[0105] At this time, because the semiconductor doping material layer 211 and the first isolation material layer 221 are made of very different materials, they can serve as etch stop layers for each other during the etching process to form multiple steps. When etching the semiconductor doping material layer 211, the first isolation material layer 221 located therebelow serves as the etch stop layer, and when etching the first isolation material layer 221, the semiconductor doping material layer 211 located therebelow serves as the etch stop layer. This effectively ensures the etching stop position and prevents over-etching. Therefore, at this time, the step plane can be effectively positioned on the semiconductor doping layer 210.

[0106] In one embodiment, after step S60, the method further includes:

[0107] Step S70, see Figure 8 , a metal silicide 600 is formed on the surface of the semiconductor doping layer 210 exposed in the step region.

[0108] The metal silicide 600 can effectively reduce the contact resistance between the semiconductor doping layer 210 and the subsequently formed bit line plugs and select line plugs.

[0109] As an example, step S70 may include:

[0110] Step S71, forming a sidewall 700 on the sidewall of the step area;

[0111] In step S72 , a metal silicide 600 is formed on the stepped surface.

[0112] In step S71, a spacer material layer (not shown) can be formed on the surface of the structure obtained in the previous step by a deposition process such as atomic layer deposition or chemical vapor deposition. Then, the spacer material layer located on the horizontal surface, that is, the spacer material layer located on the upper surface of the structure and on the step plane is removed by anisotropic etching such as dry etching, thereby forming a spacer 700 located on the sidewall of the step.

[0113] The material of the spacer 700 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0114] After the spacer 700 is formed on the sidewall of the step, only the semiconductor doping layer 210 located on the plane of the step is exposed.

[0115] In step S72, a metal material layer can be formed on the surface of the structure after the spacer 700 is formed by physical vapor deposition (such as magnetron sputtering), so that each step plane is covered by the metal material layer. Then, the structure with the metal material layer is thermally annealed, so that the metal atoms in the metal material layer and the silicon atoms in the semiconductor doping layer 210 diffuse into each other, thereby forming a metal silicide 600. Afterwards, the remaining unreacted metal material layer can be removed.

[0116] At this time, by forming the sidewall spacer 700 first, the metal silicide 600 is formed only on the step plane, thereby more effectively preventing leakage between adjacent semiconductor doping layers 210 .

[0117] Of course, since adjacent semiconductor doping layers 210 located in the step region are isolated by the first isolation layer 220 , in some examples, the sidewall spacer 700 may not be formed before forming the metal silicide 600 , and this is not limited here.

[0118] In one embodiment, see Figure 9 , after step S70, further comprising:

[0119] Step S81 , forming a passivation material layer covering the metal silicide 600 , the stacked structure 200 , the memory structure 400 , and the gate structure 500 ;

[0120] Step S82 , etching the passivation material layer to form bit line contact holes and select line contact holes that are alternately arranged and extend onto each layer of metal silicide 600 , and the remaining passivation material layer forms a passivation layer 800 ;

[0121] In step S83 , a bit line plug 910 is formed in the bit line contact hole, and a select line plug 920 is formed in the select line contact hole.

[0122] In step S81, a passivation material layer may be formed by a deposition process. The material of the passivation material layer may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON).

[0123] In step S82, a third patterned photoresist may be formed on the surface of the passivation material layer. The third patterned photoresist may have a third opening. The third opening may be opposite to the position of the step plane.

[0124] Then, based on the third patterned photoresist, the passivation material layer is etched to form a plurality of through holes extending to the metal silicide 600 located on each step plane. The plurality of through holes include bit line contact holes and select line contact holes arranged alternately.

[0125] After the passivation material layer is etched, the remaining passivation material layer forms a passivation layer 800 .

[0126] In step S83 , a conductive material layer may be formed on the bit line contact hole, the select line contact hole, and the upper surface of the passivation material layer by using processes such as magnetron sputtering, electroplating, or chemical vapor deposition.

[0127] The material of the conductive material layer may include but is not limited to cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0128] Then, the conductive material layer on the upper surface of the passivation material layer can be removed by chemical mechanical polishing (CMP) or the like. The remaining conductive material layer in the bit line contact hole forms a bit line plug 910 , and the conductive material layer in the select line contact hole forms a select line plug 920 .

[0129] As an example, in step S82, while etching the passivation material layer to form bit line contact holes and select line contact holes, word line interconnection holes extending to the gate structure 500 may also be formed. In step S83, while forming the bit line plugs 910 and the select line plugs 920, word line plugs 930 filling the word line interconnection holes may also be formed.

[0130] The bit line plug 910 and the select line plug 920 may be connected to a bit line and a select line of a certain wiring layer, respectively, and the word line plug 930 may be connected to a word line of another wiring layer.

[0131] At this time, each layer of memory cells can be connected to the bit line through the bit line plug 910, thereby facilitating the formation of a 3D NOR device.

[0132] Meanwhile, when the stacked structure 200 having a step in the step region is formed, the passivation layer 800 fills the etched-away area of ​​the step region, thereby allowing the bit line plugs 910 and the select line plugs 920 to be formed within the passivation layer 800. In this case, the passivation layer 800 can effectively isolate the bit line plugs 910, the select line plugs 920, and the bit line plugs 910 and the select line plugs 920.

[0133] Of course, in other embodiments, a stacked structure 200 without steps may also be formed.

[0134] At this time, for example, after forming the gate structure 500 in step S50, the stacked material layer 201 can be etched to form bit line contact holes and select line contact holes that penetrate each semiconductor doping material layer 211. The remaining stacked material layer 201 after etching forms the stacked structure 200. The remaining semiconductor doping material layer 211 forms the semiconductor doping layer 210, and the remaining first isolation material layer 221 forms the first isolation layer 220.

[0135] Next, a sidewall protective layer, such as an oxide, is formed on the sidewalls of the bit line contact holes and the select line contact holes. A metal silicide is then formed at the bottoms of the bit line contact holes and the select line contact holes. Finally, the bit line contact holes and the select line contact holes are filled with a bit line plug 910 and a select line plug 920, respectively.

[0136] In one embodiment, see Figure 9 The thickness of each semiconductor doping layer 210 corresponding to the bit line plug 910 increases sequentially from top to bottom, and / or the thickness of each semiconductor doping layer 210 corresponding to the select line plug 920 increases sequentially from top to bottom.

[0137] The lower the number of layers of the semiconductor doping layer 210 corresponding to the bit line plug 910 is, the longer the length of the bit line plug 910 is, resulting in a greater resistance of the bit line plug 910 .

[0138] At this time, the thickness of each semiconductor doping layer 210 corresponding to the bit line plug 910 increases from top to bottom, so that the semiconductor doping layer 210 with a lower number of layers, that is, the closer to the bottom, has a larger cross-sectional area for transmitting current, and thus the resistance of the semiconductor doping layer 210 with a lower number of layers is lower, which can compensate for the resistance difference between the bit line plugs 910.

[0139] Meanwhile, the lower the number of layers of the semiconductor doping layer 210 corresponding to the selection line plug 920 is, the longer the length of the selection line plug 920 is, resulting in a greater resistance of the selection line plug 920 .

[0140] At this time, the thickness of each semiconductor doping layer 210 corresponding to the selection line plug 920 is increased from top to bottom, so that the semiconductor doping layer 210 with a lower number of layers has a larger cross-sectional area for transmitting current, and thus the semiconductor doping layer 210 with a lower number of layers has a lower resistance, which can compensate for the resistance difference between the selection line plugs 920.

[0141] At the same time, as an example, when the thickness of each semiconductor doping layer 210 connected to the bit line plug 910 increases sequentially from top to bottom, and the thickness of each semiconductor doping layer 210 connected to the select line plug 920 increases sequentially from top to bottom, it is also possible to set all the semiconductor doping layers 210 in the stacked structure 200 so that every two semiconductor doping layers 210 from top to bottom (or from bottom to top) form a group, and the semiconductor doping layers 210 in the same group have the same thickness. Of course, in other examples, the thickness of the semiconductor doping layers 210 in the same group may also be different. For example, it is also possible to set all the semiconductor doping layers 210 in the stacked structure 200 so that the thickness of each semiconductor doping layer 210 increases sequentially from top to bottom.

[0142] In other embodiments, the diameters of the bit line contact holes corresponding to the different semiconductor doping layers 210 from top to bottom may be gradually increased, thereby causing the diameters of the bit line plugs 910 corresponding to the different semiconductor doping layers 210 from top to bottom to gradually increase, thereby compensating for the resistance difference between the bit line plugs 910. And / or, the diameters of the select line contact holes corresponding to the different semiconductor doping layers 210 from top to bottom may be gradually increased, thereby causing the diameters of the select line plugs 920 corresponding to the different semiconductor doping layers 210 from top to bottom to gradually increase, thereby compensating for the resistance difference between the select line plugs 920.

[0143] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0144] In one embodiment, a semiconductor structure is provided that can be used to prepare a flash memory device. The flash memory device may include, but is not limited to, a NOR device. For example, the flash memory device may also be a NAND device.

[0145] See also Figure 9 The semiconductor structure includes: a substrate 100 , a stacked structure 200 , a gate structure 500 , a storage structure 400 and a channel layer 300 .

[0146] The base 100 may include a substrate. The substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include a Si / SiGe, Si / SiC, a silicon-on-insulator (SOI) substrate, or a silicon germanium-on-insulator substrate.

[0147] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0148] The stacked structure 200 is located on the substrate 100 and includes alternately stacked semiconductor doped layers 210 and first isolation layers 220. The number of first isolation layers 220 is greater than or equal to 1, and both sides of the first isolation layer 220 along the stacking direction have semiconductor doped layers 210.

[0149] The material of the semiconductor doping layer 210 may include, but is not limited to, polysilicon. The material of the first isolation layer 220 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0150] The gate structure 500 and the storage structure 400 both penetrate the stacked structure 200 to the substrate 100. Meanwhile, the storage structure 400 surrounds the gate structure 500 for charge storage.

[0151] The channel layer 300 is located between adjacent semiconductor doping layers 210 , is surrounded by the first isolation layer 220 , and surrounds the memory structure 400 .

[0152] The material of the channel layer 300 may be the same as or different from that of the semiconductor doping layer 210. For example, when the material of the semiconductor doping layer 210 is polysilicon, the channel layer 300 may be a semiconductor silicon layer or a semiconductor silicon germanium layer.

[0153] In this embodiment, the channel layer 300 located within the first isolation layer 220 can form a memory cell together with the memory structure 400 and the portion of the gate structure 500 that faces it. Simultaneously, the semiconductor doped layers 210 on both sides of the channel layer 300 are connected to the channel layer 300, thereby respectively forming the source and drain of the memory cell. In this case, adjacent memory cells in the stacking direction can share a source or drain.

[0154] The source and drain of the same memory cell can be effectively isolated by the first isolation layer 220 , thereby effectively preventing leakage between the source and the drain.

[0155] Furthermore, when the semiconductor structure includes multiple first isolation layers and multiple channel layers within the first isolation layers, a three-dimensional stack of multi-layer memory cells can be formed. The sources (or drains) of adjacent memory cells can be effectively isolated by the two first isolation layers 220 therebetween, thereby effectively preventing crosstalk between adjacent memory cells.

[0156] In one embodiment, the stacked structure 200 has a non-step region and a step region. The step region exposes a portion of the upper surface of each semiconductor doping layer 210 to form a step plane. The gate structure 500 and the memory structure 400 penetrate the stacked structure 200 in the non-step region.

[0157] In one embodiment, the semiconductor structure further includes a metal silicide 600 and a spacer 700 . The metal silicide 600 is located on the step plane, and the spacer 700 is located on the step sidewall of the stacked structure 200 .

[0158] The material of the spacer 700 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0159] The provision of the sidewall spacer 700 can more effectively prevent leakage between adjacent semiconductor doping layers 210 .

[0160] In one embodiment, the semiconductor structure further includes a passivation layer 800 , a bit line plug 910 , and a select line plug 920 .

[0161] The passivation layer 800 covers the stacked structure 200, the memory structure 400, and the gate structure 500. The material of the passivation layer 800 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). The bit line plugs 910 and the select line plugs 920 penetrate the passivation layer 800 and are alternately distributed on each semiconductor doped layer 210.

[0162] When the stacked structure has a step, and a metal silicide 600 is formed on the step plane, and the step sidewalls have sidewalls 700, the passivation layer 800 also covers the metal silicide 600 and the sidewalls 700. In addition, the bit line plugs 910 and the select line plugs 920 can be alternately distributed on each layer of metal silicide 600. Of course, the stacked structure may also not have a step.

[0163] The bit line plug 910 may be connected to the bit line. The material of the bit line plug 910 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0164] The select line plug 920 may be connected to the select line. The material of the select line plug 920 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). As an example, the material of the select line plug 920 may be the same as that of the bit line plug 910.

[0165] At this point, each layer of memory cells can be connected to the bit line through the bit line plug 910, thereby facilitating the formation of a 3D NOR device. At the same time, the passivation layer 800 can effectively isolate the bit line plugs 910, the select line plugs 920, and the bit line plugs 910 and select line plugs 920.

[0166] In one embodiment, the thickness of each semiconductor doping layer 210 corresponding to the bit line plug 910 increases sequentially from top to bottom, and / or the thickness of each semiconductor doping layer 210 corresponding to the select line plug 920 increases sequentially from top to bottom.

[0167] The lower the number of layers of the semiconductor doping layer 210 corresponding to the bit line plug 910 is, ie, the closer it is to the substrate, the longer the bit line plug 910 is, resulting in a greater resistance of the bit line plug 910 .

[0168] At this time, the thickness of each semiconductor doping layer 210 corresponding to the bit line plug 910 increases from top to bottom, so that the semiconductor doping layer 210 with a lower number of layers has a larger cross-sectional area for transmitting current, and thus the semiconductor doping layer 210 with a lower number of layers has a lower resistance, which can compensate for the resistance difference between the bit line plugs 910.

[0169] Meanwhile, the lower the number of layers of the semiconductor doping layer 210 corresponding to the selection line plug 920 is, the longer the length of the selection line plug 920 is, resulting in a greater resistance of the selection line plug 920 .

[0170] At this time, the thickness of each semiconductor doping layer 210 connected to the selection line plug 920 is increased from top to bottom, so that the semiconductor doping layer 210 with lower layers has a larger cross-sectional area for transmitting current, and thus the semiconductor doping layer 210 with lower layers has a lower resistance, which can compensate for the resistance difference between the selection line plugs 920.

[0171] At the same time, as an example, when the thickness of each semiconductor doping layer 210 connected to the bit line plug 910 increases sequentially from top to bottom, and the thickness of each semiconductor doping layer 210 connected to the select line plug 920 increases sequentially from top to bottom, it is also possible to set all the semiconductor doping layers 210 in the stacked structure 200 so that every two semiconductor doping layers 210 from top to bottom (or from bottom to top) form a group, and the semiconductor doping layers 210 in the same group have the same thickness. Of course, in other examples, the thickness of the semiconductor doping layers 210 in the same group may also be different. For example, it is also possible to set all the semiconductor doping layers 210 in the stacked structure 200 so that the thickness of each semiconductor doping layer 210 increases sequentially from top to bottom.

[0172] In one embodiment, the memory structure 400 includes a tunneling layer 410 , a charge trapping layer 420 , and a blocking layer 430 sequentially arranged from the channel layer 300 to the gate structure 500 . The gate structure 500 includes a high dielectric constant layer 510 and a gate 520 .

[0173] The material of the tunneling layer 410 may include but is not limited to oxide, the material of the charge trapping layer 420 may include but is not limited to nitride, the material of the blocking layer 430 may include but is not limited to oxide, and the material of the high dielectric constant layer 510 may include but is not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3), etc.

[0174] In one embodiment, the substrate 100 includes a second isolation layer 110. The material of the second isolation layer 110 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). The material of the second isolation layer 110 may be the same as or different from the material of the first isolation layer 220.

[0175] As an example, the base 100 may further include a substrate, and the second isolation layer 110 may be located on the substrate. The stacked structure 200, the memory structure 400, and the gate structure 500 are located on the second isolation layer 110, thereby effectively isolating the substrate from the memory cell through the second isolation layer 110.

[0176] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0177] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; A stacked structure, located on the substrate, comprising alternately stacked semiconductor doped layers and first isolation layers, wherein the number of layers of the first isolation layer is greater than or equal to 1, and both sides of the first isolation layer along the stacking direction have the semiconductor doped layer; a gate structure, extending through the stack structure to the substrate; a storage structure, penetrating the stacked structure to the substrate and surrounding the gate structure; The channel layer is located between adjacent semiconductor doping layers, is surrounded by the first isolation layer, and surrounds the storage structure.

2. The semiconductor structure according to claim 1, wherein: The stack structure has a non-step region and a step region. The step region exposes a portion of the upper surface of each semiconductor doping layer to form a step plane. The gate structure and the storage structure penetrate the stack structure in the non-step region.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes a metal silicide and a sidewall, wherein the metal silicide is located on the step plane, and the sidewall is located on the step sidewall of the stacked structure.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a passivation layer, a bit line plug and a selection line plug. The passivation layer covers the stacked structure, the storage structure and the gate structure. The bit line plug and the selection line plug penetrate the passivation layer and are alternately distributed on each layer of the semiconductor doping layer.

5. The semiconductor structure according to claim 4, wherein: The thickness of each of the semiconductor doping layers corresponding to the bit line plugs increases sequentially from top to bottom, and / or the thickness of each of the semiconductor doping layers corresponding to the select line plugs increases sequentially from top to bottom. The semiconductor structure according to claim 1 , wherein: The storage structure includes a tunneling layer, a charge trapping layer and a blocking layer arranged in sequence from the channel layer to the gate structure; the gate structure includes a high dielectric constant layer and a gate, and the high dielectric constant layer covers the surface of the storage structure and surrounds the gate.

7. The semiconductor structure according to claim 1, wherein: The substrate includes a second isolation layer, and the stack structure, the storage structure, and the gate structure are located on the second isolation layer.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming a stacked material layer on the substrate, wherein the stacked material layer includes alternating semiconductor doping material layers and first isolation material layers, wherein the number of the first isolation material layers is greater than or equal to 1, and the semiconductor doping material layers are present on both sides of the first isolation material layer along a stacking direction; Etching the stacked material layer to form a gate hole penetrating to the substrate; Carving back each first isolation material layer through the gate hole to form a surrounding groove surrounding the gate hole; forming a channel layer in the surrounding groove; A storage structure is formed on the sidewall of the gate hole, and a gate structure is formed on the surface of the storage structure.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The forming of the channel layer in the surrounding groove includes: performing epitaxial growth on the semiconductor doping material layer exposed by the gate hole and the surrounding groove to form a channel material layer, wherein the channel material layer fills the surrounding groove and covers the side surface of the semiconductor doping material layer; The channel material layer outside the surrounding groove is removed to form the channel layer.

10. The method for preparing a semiconductor structure according to claim 8, wherein: The stacked material layer has a non-step region and a step region, and the gate hole is formed in the non-step region; After sequentially forming a storage structure and a gate structure in the gate hole, the method further includes: The stacked material layer located in the step area is etched to form a stacked structure with steps in the step area. The remaining semiconductor doping material layer after etching forms a semiconductor doping layer, and the remaining first isolation material layer forms a first isolation layer. After etching, the step area exposes part of the upper surface of each semiconductor doping layer to form a step plane.

11. The method for preparing a semiconductor structure according to claim 10, wherein: After etching the stacked material layer located in the step region to form a stacked structure having steps in the step region, the method further includes: Metal silicide is formed on the surface of the semiconductor doping layer exposed in the step area.

12. The method for preparing a semiconductor structure according to claim 11, wherein: The forming of metal silicide on the surface of the semiconductor doping layer exposed in the step region comprises: forming side walls on the step sidewalls of the step area; The metal silicide is formed on the step surface.

13. The method for preparing a semiconductor structure according to claim 11, wherein: After forming metal silicide on the surface of the semiconductor doping layer exposed in the step region, the method further includes: forming a passivation material layer covering the metal silicide, the stacked structure, the storage structure, and the gate structure; Etching the passivation material layer to form bit line contact holes and select line contact holes that are alternately arranged and extend to each layer of the metal silicide, and the remaining passivation material layer forms a passivation layer; A bit line plug is formed in the bit line contact hole, and a select line plug is formed in the select line contact hole.

14. The method for preparing a semiconductor structure according to claim 13, wherein: The thickness of each of the semiconductor doping layers corresponding to the bit line plugs increases sequentially from top to bottom, and / or the thickness of each of the semiconductor doping layers corresponding to the select line plugs increases sequentially from top to bottom.

15. The method for preparing a semiconductor structure according to claim 8, wherein: The step of forming a storage structure on the sidewall of the gate hole and forming a gate structure on the surface of the storage structure includes: forming a storage structure material layer on the surface of the structure obtained after forming the channel layer, wherein the storage structure material layer includes a tunneling material layer, a charge trapping material layer, and a blocking material layer formed in sequence, and forming a high dielectric constant material layer on the surface of the blocking material layer; Removing the storage structure material layer and the high dielectric constant material layer located at the bottom of the gate hole and on the upper surface of the stacked material layer to form a storage structure and a high dielectric constant layer, wherein the storage structure includes a tunneling layer, a charge trapping layer and a blocking layer; The remaining gate hole is filled with a gate to form the gate structure, wherein the gate structure includes the high dielectric constant layer and the gate.

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