A silicon carbide stepped trench MOSFET and a manufacturing method thereof

Abstract

The present invention discloses a silicon carbide stepped trench MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor drain region, a semiconductor drift region, a second-conductivity-type semiconductor well region, a first-conductivity-type semiconductor source region, a second-conductivity-type semiconductor contact region, a first trench, a first-conductivity-type carrier diffusion layer, a second trench, a second-conductivity-type semiconductor shielding region, a gate dielectric layer, a gate electrode, an interlayer dielectric layer, a contact hole, a source metal electrode, and a drain metal electrode. The present invention reduces the device's specific on-resistance (Ron,sp) by forming a first-conductivity-type semiconductor carrier diffusion layer (CSL) at the bottom and partial regions of the sidewalls of the first trench. A second-conductivity-type semiconductor shielding region, short-circuited to the source metal electrode, is formed across the entire bottom and sidewalls of the second trench. This significantly reduces the gate oxide electric field compared to a shielding region introduced only at the trench bottom, thereby improving device reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a silicon carbide stepped trench MOSFET and a manufacturing method thereof. Background Art

[0002] The band gap of silicon carbide is about three times that of silicon, the breakdown field strength is about 10 times that of silicon, the thermal conductivity is about 3 times that of silicon, and its electron saturation drift velocity is about one order of magnitude higher than that of silicon. These excellent properties of silicon carbide make it an ideal material for power electronic devices.

[0003] For silicon carbide MOSFETs, researchers first developed a planar structure. With the continuous pursuit of excellent electrical performance, it was found that the JFET resistance and low channel mobility of planar MOSFETs restricted the continued improvement of the performance of silicon carbide planar MOSFETs. As a result, researchers gradually turned to the development of silicon carbide trench MOSFETs. Trench MOSFETs eliminate JFET resistance, and the mobility of their vertical channels is about twice that of horizontal channels. Therefore, silicon carbide trench MOSFETs greatly alleviate the contradiction between device breakdown voltage (BV) and specific on-resistance (Ron,sp) compared to silicon carbide planar MOSFETs.

[0004] A key issue with silicon carbide trench MOSFETs is that when the device is operating in a blocking state, the gate oxide electric field gathers at the corners of the bottom of the trench. The high gate oxide electric field can affect the reliability of the device. The present invention prepares a surrounding semiconductor shielding area around the second trench, which can significantly reduce the gate oxide electric field. The surrounding semiconductor shielding area is prepared using a self-aligned process without adding an additional mask.

[0005] The information disclosed in this background technology section is only intended to deepen the understanding of the overall background technology of the present invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art. Summary of the Invention

[0006] In view of the problems existing in the prior art, the purpose of the present invention is to provide a silicon carbide stepped trench MOSFET and a manufacturing method thereof, so as to solve the problem of gate oxide electric field at the bottom corner of the high trench of the silicon carbide trench MOSFET in the blocking state.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A silicon carbide stepped trench MOSFET, comprising:

[0009] a semiconductor drain region, which is a semiconductor material heavily doped with the first conductivity type;

[0010] a semiconductor drift region, which is a lightly doped semiconductor material of a first conductivity type;

[0011] A second conductive type semiconductor well region located at a top of the semiconductor drift region;

[0012] a first conductive type semiconductor source region located in the middle of the top of the second conductive type semiconductor well region;

[0013] a second conductive type semiconductor contact region located at a top of the second conductive type semiconductor well region and away from a middle position;

[0014] a first trench located in the middle of the semiconductor drift region and extending from the semiconductor source region into the semiconductor drift region;

[0015] A first conductive type carrier diffusion layer is located between the second conductive type semiconductor well region and the second conductive type semiconductor shielding region;

[0016] a second groove disposed directly below the first groove;

[0017] The second conductive type semiconductor shielding region surrounds the second trench;

[0018] a gate dielectric layer, located on inner walls of the first trench and the second trench;

[0019] a gate electrode located on the gate dielectric layer of the first trench and the second trench;

[0020] an interlayer dielectric layer located above the gate electrode; a contact hole is provided in the interlayer dielectric layer;

[0021] A source metal electrode, located above the interlayer dielectric layer, and forming an ohmic contact with the semiconductor source region and the semiconductor contact region through the contact hole;

[0022] The drain metal electrode is located below the semiconductor drain region and forms an ohmic contact with the semiconductor drain region.

[0023] Furthermore, the first trench has a width of W1 and a depth of T1, and the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric.

[0024] Furthermore, the width of the first conductive type carrier diffusion layer is W2, which is prepared by adjusting the ion implantation angle and the rotation angle. Its doping concentration is less than the doping concentration of the semiconductor well region, and the ion implantation is performed in self-alignment with the first trench without adding an additional mask.

[0025] Furthermore, the width of the second trench is W3, and the depth thereof is T3, and the sum of T1 and T3 is no greater than the thickness of the drift region.

[0026] Furthermore, the width of the second conductive type semiconductor shielding region is W4, which is prepared by adjusting the ion implantation angle and the rotation angle, surrounds the second trench, and is short-circuited with the source metal. Its doping concentration is 1 to 100 times the concentration of the semiconductor well region, and the ion implantation is self-aligned with the second trench without adding an additional mask.

[0027] Furthermore, the width W1 of the first trench is greater than the sum of the width W3 of the second trench and twice the width W4 of the shielding region, that is, W1>W3+2×W4.

[0028] Furthermore, the gate electrode is isolated from the adjacent SIC epitaxial layer by a gate dielectric layer, and the material of the gate electrode is heavily doped polysilicon or metal.

[0029] Furthermore, for an N-channel silicon carbide trench MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; for a P-channel silicon carbide trench MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0030] A method for manufacturing a silicon carbide stepped trench MOSFET comprises the following steps:

[0031] S1. Prepare a semiconductor drain region heavily doped with a first conductive type semiconductor material, wherein the concentration of impurity atoms in the crystal is 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3 A low-doped semiconductor drift region is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 pieces / cm 3 -9.5×10 16 pieces / cm 3 ;

[0032] S2, implanting aluminum atoms into the top of the semiconductor drift region to form a second conductive type semiconductor well region, with an implantation dose of 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted at the top middle position of the second conductive type semiconductor well region with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region is formed between the first conductive type semiconductor source region and the second conductive type semiconductor well region, and then a high concentration of aluminum atoms is implanted at the top of the second conductive type semiconductor well region and away from the middle position to form a second conductive type semiconductor body contact region;

[0033] S3. Depositing a layer of silicon oxide or a combination of silicon oxide and polysilicon as a hard mask layer HM1 above the active area, then etching a window in the hard mask, and then etching the semiconductor drift region by dry-coupled plasma etching, reactive ion etching, or a combination of the two, to form a first trench with a width W1 and a depth T1, wherein the depth T1 is greater than the sum of the thickness of the semiconductor well region and the gate dielectric thickness;

[0034] S4. A carrier diffusion layer with a width of W2 is formed outside the first trench by adjusting the ion implantation angle and the rotation angle, wherein the ion implantation is performed using the first trench as a self-alignment, so no additional mask is introduced to prepare the carrier diffusion layer; a lead-out position area of ​​the semiconductor shielding region is defined by photoresist, and then a lead-out end of the second conductive type semiconductor shielding region is prepared by adjusting the ion implantation angle and the rotation angle;

[0035] S5. A second hard mask layer HM2 is formed on the hard mask layer HM1 and the carrier diffusion layer. Then, a window is self-aligned and etched on the hard mask layer HM2 using the first trench as a self-aligned etching method to form a sidewall of HM2. Therefore, no additional mask is added to the window of the hard mask layer HM2.

[0036] S6. Etching the semiconductor drift region in the window area defined by the hard mask layer HM2 by dry coupled plasma etching, reactive ion etching, or a combination thereof to form a second trench with a width W3 and a depth T3, where the sum of T1 and T3 is no greater than the thickness of the drift region;

[0037] S7. Using the hard mask layer as a barrier, adjust the ion implantation angle and the rotation angle to prepare a second conductive type semiconductor shielding region with a width of W4, which surrounds the second trench and is short-circuited with the source metal. The semiconductor shielding region has a concentration 1 to 100 times that of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the second trench, thereby ensuring that the second trench is surrounded by the semiconductor shielding region. The semiconductor shielding region needs to be connected to the source metal, either as a whole semiconductor shielding region or as a staged semiconductor shielding region.

[0038] S8. Remove the hard mask and form a gate dielectric layer by deposition or oxidation. The gate dielectric layer is made of silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide, or a combination of these materials, with a thickness of 0.02-1 µm. Then, form a gate electrode on the gate dielectric layer. The gate electrode is made of heavily doped polysilicon or metal.

[0039] S9, depositing a certain thickness of non-doped silicon oxide and borophosphosilicate glass above the gate electrode to form an interlayer dielectric layer with a thickness of 0.4-1µm, and then etching a through hole in the interlayer dielectric layer to form a contact hole;

[0040] S10. Deposit and etch a front metal on the interlayer dielectric to form a source metal electrode; deposit a conductive metal below the semiconductor drain region to form a drain metal electrode. Both the source and drain metals form ohmic contacts with the semiconductor.

[0041] Furthermore, taking the strip cell as an example, there are three ways to short-circuit the second conductive type semiconductor shielding region (9) with the source metal:

[0042] The first is that when the device is in the on state, the conductive channels on the left and right sides of the first trench are conductive;

[0043] The second type is that the semiconductor shielding area on the right side of the first trench is distributed in a single-side phase, that is, the conductive channel on the right side of the first trench is partially conductive, while the channel on the left side is fully conductive;

[0044] The third method is to prepare a whole semiconductor shielding area on the right side of the first trench, that is, the conductive channel on the right side of the first trench is completely non-conductive, while the channel on the left side is completely conductive.

[0045] Furthermore, based on step S2, a first conductive type carrier diffusion layer (16) is prepared by high energy injection, and then steps S3-S10 are repeated to finally form a primitive cell structure. By introducing a long first conductive type carrier diffusion layer (16) below the semiconductor well region, it is helpful to further reduce the specific on-resistance of the device.

[0046] By adopting the above technical solution, the present invention has the following beneficial effects:

[0047] The present application designs a silicon carbide stepped trench MOSFET and a manufacturing method thereof. The structure is designed with a semiconductor shielding region surrounding the second trench, so that the new structure can achieve a lower gate oxide electric field at the corner of the bottom of the trench in the blocking state, thereby improving device reliability; at the same time, the characteristic of the semiconductor shielding region being connected to the source metal enables the surrounding shielding region to eliminate the entire second trench and reduce the gate-drain overlap area in the local area of ​​the bottom of the first trench, thereby reducing the gate-drain capacitance (Cgd) and reducing switching power consumption; further, the carrier diffusion layer at the step position can reduce the specific on-resistance (Ron,sp); further, the step position where the first trench contacts the second trench introduces a new electric field peak, which can improve the breakdown voltage (BV) of the device; further, the second layer hard mask HM2 window opening, carrier diffusion layer preparation, and semiconductor shielding region all adopt self-alignment process without adding additional mask plates. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 Schematic diagram of the three-dimensional structure of the primitive cell of Example 1 of the present application;

[0050] Figure 2 This is a schematic diagram of a two-dimensional cross-section unit cell along line BB' of Example 1 of the present application;

[0051] Figure 3 This is a schematic diagram of a two-dimensional cross-section of a unit cell along line AA' in Example 1 of the present application;

[0052] Figure 4 This is a schematic diagram of the initial structure of Example 1 of the present application;

[0053] Figure 5 1 is a schematic structural diagram of forming an active area in Example 1 of the present application;

[0054] Figure 6 This is a schematic structural diagram of forming a first groove in Example 1 of the present application;

[0055] Figure 7 This is a schematic structural diagram of a carrier diffusion layer formed in Example 1 of the present application;

[0056] Figure 8 This is a schematic structural diagram of the lead-out terminal of the semiconductor shielding region formed in Example 1 of the present application;

[0057] Figure 9 2 is a schematic structural diagram of forming a window of the hard mask HM2 in Example 1 of the present application;

[0058] Figure 10 This is a schematic structural diagram of forming a second groove in Example 1 of the present application;

[0059] Figure 11 This is a schematic structural diagram of a semiconductor shielding region formed in Example 1 of the present application;

[0060] Figure 12 This is a schematic diagram of forming a gate structure according to Example 1 of the present application;

[0061] Figure 13 This is a schematic structural diagram of a contact hole formed in Example 1 of the present application;

[0062] Figure 14 This is a schematic diagram of the structure of the metal electrode formed in Example 1 of the present application;

[0063] Figure 15 This is a schematic top view of the structure of three types of semiconductor shielding regions formed in Example 2 of the present application;

[0064] Figure 16 This is a schematic diagram of a two-dimensional cross-section of a primitive cell formed in Example 3 of the present application;

[0065] Figures 1 to 16 The regions in the figure are marked as follows: (1) - semiconductor drain region, (2) - semiconductor drift region, (3) - second conductive type semiconductor well region, (4) - first conductive type semiconductor source region, (5) - second conductive type semiconductor body contact region, (6) - first trench, (7) - first conductive type carrier diffusion layer, (8) - second trench, (9) - second conductive type semiconductor shielding region, (10) - gate dielectric layer, (11) - gate electrode, (12) - interlayer dielectric layer, (13) - contact hole, (14) - source metal electrode, (15) - drain metal electrode, (16) - first conductive type carrier diffusion layer. DETAILED DESCRIPTION

[0066] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0067] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention. Example 1

[0068] Figure 1-3 and Figure 14An embodiment shown includes: a semiconductor drain region 1, which is a heavily doped semiconductor material of the first conductivity type; a semiconductor drift region 2, which is a lightly doped semiconductor material of the first conductivity type; a second conductivity type semiconductor well region 3, which is located at the top of the semiconductor drift region; a first conductivity type semiconductor source region 4, which is located at the middle position of the top of the second conductivity type semiconductor well region; a second conductivity type semiconductor contact region 5, which is located at the top of the second conductivity type semiconductor well region and away from the middle position; a first trench 6, which is located in the middle position of the semiconductor drift region and extends from the semiconductor source region into the semiconductor drift region; a first conductivity type carrier diffusion layer 7, which is located at the second conductivity type type semiconductor well region and a second conductive type semiconductor shield region; a second trench 8 is placed directly below the first trench; a second conductive type semiconductor shield region 9 surrounds the second trench; a gate dielectric layer 10 is located on the inner walls of the first and second trenches; a gate electrode 11 is located on the gate dielectric layer of the first and second trenches; an interlayer dielectric layer 12 is located above the gate electrode; a contact hole 13 is provided in the interlayer dielectric layer; a source metal electrode 14 is located above the interlayer dielectric and forms an ohmic contact with the semiconductor source region and the semiconductor body contact region through the contact hole; a drain metal electrode 15 is located below the semiconductor drain region and forms an ohmic contact with the semiconductor drain region.

[0069] In the present application, the gate dielectric layer within the first and second trenches can be formed by thermal growth or deposition. The gate dielectric layer can be silicon oxide, a high-k dielectric such as silicon nitride, aluminum oxide, or hafnium oxide, or a combination of several materials. The new structure requires sacrificing a portion of the conductive channel to connect the semiconductor shielding area to the source metal. This can be done by connecting the entire semiconductor shielding area to the source metal or by connecting the semiconductor shielding area to the source metal in stages. If the semiconductor shielding area is not connected to the source metal, it will increase the device's turn-on power consumption and reduce the device's reliability.

[0070] In this specific embodiment, a first conductive type carrier diffusion layer is formed in the first trench by adjusting the ion injection angle and the rotation angle, and then a second trench is etched out. Subsequently, a second conductive type semiconductor shielding region is formed at the bottom and sidewall of the second trench by adjusting the ion injection angle and the rotation angle, wherein the ion injection of the carrier diffusion layer and the semiconductor shielding region adopts a self-aligned process without adding an additional mask.

[0071] exist Figure 4 In the embodiment shown, the semiconductor drain region 1 is a semiconductor material heavily doped with the first conductivity type, such as a crystal with an impurity atom concentration of 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3A low-doped semiconductor drift region 2 is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 pieces / cm 3 -9.5×10 16 pieces / cm 3 .

[0072] exist Figure 5 In the embodiment shown, aluminum atoms are implanted at the top of the semiconductor drift region to form a second conductive type semiconductor well region 3, with an implantation dose of 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted into the middle of the top of the second conductive type semiconductor well region with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region 4 is formed between the two regions, and then a high concentration of aluminum atoms is implanted at the top of the second conductive type semiconductor well region and away from the middle position to form a second conductive type semiconductor contact region 5.

[0073] exist Figure 6 In the illustrated embodiment, a layer of silicon oxide or a combination of silicon oxide and polysilicon is deposited above the active area as a hard mask layer (HM1), and then a window is etched in the hard mask. Subsequently, etching is performed in the semiconductor drift region by dry-coupled plasma etching, reactive ion etching, or a combination of the two to form a first trench 6 with a width W1 and a depth T1, wherein the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric.

[0074] exist Figure 7 In the embodiment shown, a carrier diffusion layer 7 with a width of W2 is formed outside the first trench by adjusting the ion implantation angle and the rotation angle, wherein the ion implantation is performed with the first trench as a self-alignment, so no additional mask is introduced in the preparation of the carrier diffusion layer.

[0075] exist Figure 8 In the embodiment shown, the lead-out position area of ​​the semiconductor shielding region is defined by photoresist, and then the lead-out end of the second conductive type semiconductor shielding region is prepared by adjusting the ion implantation angle and the rotation angle, as shown in FIG. Figure 8 (a) shows that the area covered by the photoresist is removed as shown in Figure 8 (b) shows that Figure 7 Stay consistent.

[0076] exist Figure 9In the embodiment shown, a second hard mask layer HM2 is prepared on the hard mask layer HM1 and the carrier diffusion layer, and then a window is self-aligned and etched on the hard mask layer HM2 using the first trench as a self-aligned etching to form the HM2 sidewall. Therefore, no additional mask is added to the window opening of the hard mask layer HM2.

[0077] exist Figure 10 In the embodiment shown, the semiconductor drift region is etched in the window area defined by the hard mask HM2 by dry-coupled plasma etching, reactive ion etching, or a combination of the two to produce a second trench 8 with a width W3 and a depth T3, where the sum of T1 and T3 is no greater than the thickness of the drift region.

[0078] exist Figure 11 In the illustrated embodiment, a second conductive type semiconductor shielding region 9 with a width of W4 is prepared by adjusting the ion implantation angle and the rotation angle with a hard mask layer as a barrier. The second conductive type semiconductor shielding region 9 surrounds the second trench and is short-circuited with the source metal. The semiconductor shielding region may have a concentration of 1 to 100 times that of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the second trench, thereby ensuring that the second trench is surrounded by the semiconductor shielding region. Furthermore, the semiconductor shielding region needs to be connected to the source metal. The entire semiconductor shielding region may be connected to the source metal, or the semiconductor shielding region distributed in stages may be connected to the source metal. If the semiconductor shielding region is not connected to the source metal, it will increase the turn-on power consumption of the device on the one hand, and reduce the reliability of the device on the other hand.

[0079] exist Figure 12 In the embodiment shown, the hard mask is removed and a gate dielectric layer 10 is formed by deposition or oxidation. The gate dielectric layer can be silicon oxide, or a high dielectric constant dielectric such as silicon nitride, aluminum oxide, hafnium oxide, or a combination of several materials. Its thickness can be 0.02-1µm. Then, a gate electrode 11 is prepared on the gate dielectric layer, where the gate electrode can be heavily doped polysilicon or metal.

[0080] exist Figure 13 In the embodiment shown, a certain thickness of undoped silicon oxide and borophosphosilicate glass is deposited above the gate electrode to form an interlayer dielectric layer 12, which is generally 0.4-1µm thick. Then, a through hole is etched in the interlayer dielectric layer to form a contact hole 13.

[0081] exist Figure 14 In the embodiment shown, a front metal is deposited and etched above the interlayer dielectric to form a source metal electrode 14. A conductive metal is deposited below the semiconductor drain region to form a drain metal electrode 15. Both the source and drain metals form ohmic contacts with the semiconductor. Example 2

[0082] exist Figure 15 In the embodiment shown, taking the strip cell as an example, there are three ways to short-circuit the semiconductor shielding region (9) surrounding the second trench with the source metal. The top view of the semiconductor shielding region and the source metal short-circuit in Example 1 is as follows: Figure 15 As shown in (a), when the device is operating in the on-state, the conductive channels on the left and right sides of the first trench are staged; the semiconductor shielding area (9) on the right side of the first trench can also be distributed in a single-side stage, as shown in the top view. Figure 15 As shown in (b), the conductive channel on the right side of the first trench is partially conductive, while the left side channel is fully conductive; further, a whole semiconductor shielding region (9) can be prepared on the right side of the first trench, as shown in the top view. Figure 15 (c) That is, the conductive channel on the right side of the first trench is completely non-conductive, while the channel on the left side is completely conductive. Example 3

[0083] exist Figure 16 In the embodiment shown, in Example 1 Figure 5 On the basis of the above, a first conductive type carrier diffusion layer (16) is prepared by high energy injection, and its structure is as follows Figure 16 (a), then repeat Example 1 in Example 3 Figures 6 to 13 Process steps, the final cell structure is as follows Figure 16 (b) It not only inherits the advantages of the structure in embodiment 1, but also the structure in embodiment 3 introduces a long first conductive type carrier diffusion layer (16) under the semiconductor well region, which helps to further reduce the specific on-resistance of the device.

[0084] In summary, the present application discloses a silicon carbide stepped trench MOSFET and a manufacturing method thereof, wherein a first conductive type semiconductor carrier diffusion layer (CSL) is prepared in a local area of ​​the bottom and sidewall of the first trench to reduce the device's specific on-resistance (Ron,sp); further, a second conductive type semiconductor shielding region short-circuited with the source metal electrode is prepared in the entire area of ​​the bottom and sidewall of the second trench, which can significantly reduce the gate oxide electric field compared to the shielding region introduced only at the bottom of the trench, thereby improving device reliability; further, the shielding region connected to the source metal can eliminate the second trench's entire The gate-drain overlap area in the local area at the bottom of the first trench is reduced to reduce the gate-drain capacitance (Cgd), thereby reducing the switching power consumption of the device; further, the first conductive type semiconductor carrier diffusion layer and the second conductive type semiconductor shielding region are respectively prepared by a trench self-aligned ion implantation process without adding an additional mask; further, the stepped position where the first trench contacts the second trench introduces a new electric field peak, which can improve the breakdown voltage (BV) of the device; therefore, the present invention not only optimizes the static and dynamic electrical performance parameters of the device, but also optimizes the reliability of the device.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide step trench MOSFET, characterized in that: include: A semiconductor drain region (1) is a heavily doped semiconductor material of a first conductivity type; A semiconductor drift region (2) is a lightly doped semiconductor material of a first conductivity type; A second conductive type semiconductor well region (3), located at the top of the semiconductor drift region (2); A first conductive type semiconductor source region (4) located in the middle of the top of the second conductive type semiconductor well region (3); A second conductive type semiconductor contact region (5), located at the top of the second conductive type semiconductor well region (3) and away from the middle; A first trench (6) is located in the middle of the semiconductor drift region (2) and extends from the semiconductor source region into the semiconductor drift region; a first conductive type carrier diffusion layer (7), located between the second conductive type semiconductor well region (3) and the second conductive type semiconductor shielding region (9); a second groove (8) disposed directly below the first groove (6); The second conductive type semiconductor shielding region (9) surrounds the second trench (8); a gate dielectric layer (10), located on inner walls of the first trench (6) and the second trench (8); A gate electrode (11) located on the gate dielectric layer of the first trench (6) and the second trench (8); an interlayer dielectric layer (12) located above the gate electrode (11); a contact hole (13) is provided in the interlayer dielectric layer (12); A source metal electrode (14), located above the interlayer dielectric layer (12), and forming an ohmic contact with the semiconductor source region and the semiconductor contact region through the contact hole (13); A drain metal electrode (15), which is located below the semiconductor drain region (1) and forms an ohmic contact with the semiconductor drain region (1); The second conductive type semiconductor shielding region (9) is short-circuited with the source end metal.

2. The silicon carbide step trench MOSFET according to claim 1, wherein: The first trench (6) has a width of W1 and a depth of T1, and the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric layer.

3. The silicon carbide step trench MOSFET according to claim 1, wherein: The width of the first conductive type carrier diffusion layer (7) is W2, and it is prepared by adjusting the ion implantation angle and the rotation angle, and its doping concentration is less than the doping concentration of the semiconductor well region, and the ion implantation is performed in self-alignment with the first trench without adding an additional mask.

4. The silicon carbide step trench MOSFET according to claim 2, wherein: The width of the second trench (8) is W3, and its depth is T3, and the sum of T1 and T3 is not greater than the thickness of the drift region.

5. The silicon carbide step trench MOSFET according to claim 1, wherein: The width of the second conductive type semiconductor shielding region (9) is W4, which is prepared by adjusting the ion implantation angle and the rotation angle. The doping concentration is 1 to 100 times the concentration of the semiconductor well region, and the ion implantation is performed in a self-aligned manner with the second trench (8) without adding an additional mask.

6. The silicon carbide step trench MOSFET according to claim 1, wherein: The width W1 of the first groove (6) is greater than the sum of the width W3 of the second groove (8) and twice the width W4 of the shielding area, that is, W1>W3+2×W4.

7. The silicon carbide step trench MOSFET according to claim 1, wherein: The gate electrode (11) is isolated from the adjacent SiC epitaxy by a gate dielectric layer, and the material of the gate electrode (11) is heavily doped polysilicon or metal; For an N-channel silicon carbide trench MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; for a P-channel silicon carbide trench MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

8. A method for manufacturing a silicon carbide step trench MOSFET according to any one of claims 1 to 7, characterized in that: The steps include: S1, preparing a semiconductor drain region (1) heavily doped with a first conductive type semiconductor material, wherein the concentration of impurity atoms in the crystal is 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3 A low-doped semiconductor drift region (2) is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 pieces / cm 3 -9.5×10 16 pieces / cm 3 ; S2, implanting aluminum atoms at the top of the semiconductor drift region (2) to form a second conductive type semiconductor well region (3), with an implantation dose of 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted into the middle of the top of the second conductive type semiconductor well region (3) with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region (4) is formed between the first and second conductive type semiconductor well regions (3), and then a high concentration of aluminum atoms is injected into the top of the second conductive type semiconductor well region (3) and away from the middle position to form a second conductive type semiconductor body contact region (5); S3, depositing a layer of silicon oxide or a combination of silicon oxide and polysilicon as a hard mask layer HM1 above the active area, then etching a window in the hard mask layer HM1, and then etching the semiconductor drift region by dry coupled plasma etching, reactive ion etching, or a combination of the two, to form a first trench (6) with a width W1 and a depth T1, wherein the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric layer; S4, forming a carrier diffusion layer (7) with a width of W2 outside the first trench by adjusting the ion implantation angle and the rotation angle, wherein the ion implantation is performed with the first trench as a self-alignment, so that no additional mask is introduced in the preparation of the carrier diffusion layer; defining the lead position area of ​​the semiconductor shielding region by photoresist, and then preparing the second conductive type semiconductor shielding region lead end by adjusting the ion implantation angle and the rotation angle; S5. A second hard mask layer HM2 is formed on the hard mask layer HM1 and the carrier diffusion layer. Then, a window is self-aligned and etched on the hard mask layer HM2 using the first trench as a self-aligned etching method to form a sidewall of HM2. Therefore, no additional mask is added to the window of the hard mask layer HM2. S6, etching the semiconductor drift region in the window area defined by the hard mask layer HM2 by dry coupled plasma etching, reactive ion etching, or a combination of the two, to produce a second trench (8) with a width W3 and a depth T3, wherein the sum of T1 and T3 is not greater than the thickness of the drift region; S7, using the hard mask layers HM1 and HM2 as barriers, by adjusting the ion implantation angle and the rotation angle, a second conductive type semiconductor shielding region (9) with a width of W4 is prepared, which surrounds the second trench (8) and is short-circuited with the source metal. The semiconductor shielding region has a concentration of 1 to 100 times that of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the second trench, thereby ensuring that the second trench is surrounded by the semiconductor shielding region. The semiconductor shielding region needs to be connected to the source metal, either the entire semiconductor shielding region is connected to the source metal, or the semiconductor shielding region distributed in stages is connected to the source metal. S8, removing the hard mask layers HM1 and HM2, forming a gate dielectric layer (10) by deposition or oxidation, wherein the gate dielectric layer is a silicon oxide, silicon nitride, aluminum oxide or hafnium oxide dielectric, or a combination of several materials, and has a thickness of 0.02-1µm, and then forming a gate electrode (11) on the gate dielectric layer, wherein the gate electrode is heavily doped polysilicon or metal; S9, depositing a certain thickness of non-doped silicon oxide and boron phospho-silicate glass above the gate electrode to form an interlayer dielectric layer (12) with a thickness of 0.4-1µm, and then etching a through hole in the interlayer dielectric layer to form a contact hole (13); S10, depositing and etching a front metal on the interlayer dielectric to form a source metal electrode (14); depositing a conductive metal below the semiconductor drain region to form a drain metal electrode (15), with both the source and drain metals forming ohmic contacts with the semiconductor.

9. The method for manufacturing a silicon carbide step trench MOSFET according to claim 8, wherein: Taking the strip cell as an example, there are three ways to short-circuit the second conductive type semiconductor shielding area (9) with the source metal: The first is that when the device is in the on state, the conductive channels on the left and right sides of the first trench are conductive; The second type is that the semiconductor shielding area on the right side of the first trench is distributed in a single-side phase, that is, the conductive channel on the right side of the first trench is partially conductive, while the channel on the left side is fully conductive; The third method is to prepare a whole semiconductor shielding area on the right side of the first trench, that is, the conductive channel on the right side of the first trench is completely non-conductive, while the channel on the left side is completely conductive.

10. The method for manufacturing a silicon carbide step trench MOSFET according to claim 8, wherein: On the basis of step S2, a first conductive type carrier diffusion layer (16) is prepared by high energy injection, and then steps S3-S10 are repeated to finally form a primitive cell structure. By introducing a long first conductive type carrier diffusion layer (16) below the semiconductor well region, it helps to further reduce the specific on-resistance of the device.

Images