A silicon carbide stepped trench MOSFET and a manufacturing method thereof

Abstract

The present invention discloses a silicon carbide stepped trench MOSFET and a manufacturing method thereof, comprising: a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor body contact region, a first conductive type carrier diffusion layer, a first trench, a second conductive type semiconductor shielding region, a second trench, a gate dielectric layer, a gate electrode, an interlayer dielectric layer, a contact hole, a source metal electrode and a drain metal electrode; the present application discloses that a first conductive type semiconductor carrier diffusion layer is prepared at the bottom of the semiconductor well region to reduce the specific on-resistance of the device; a second conductive type semiconductor shielding region short-circuited with the source metal electrode is prepared in the entire area of ​​the bottom and sidewall of the first trench, which can significantly reduce the gate oxide electric field compared with the shielding region introduced only at the bottom of the trench, thereby improving the reliability of the device; the present invention not only optimizes the static and dynamic electrical performance parameters of the device, but also optimizes the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a silicon carbide stepped trench MOSFET and a manufacturing method thereof. Background Art

[0002] The band gap of silicon carbide is about three times that of silicon, the breakdown field strength is about 10 times that of silicon, the thermal conductivity is about 3 times that of silicon, and its electron saturation drift velocity is about one order of magnitude higher than that of silicon. These excellent properties of silicon carbide make it an ideal material for power electronic devices.

[0003] For silicon carbide MOSFETs, researchers first developed a planar structure. With the continuous pursuit of excellent electrical performance, it was found that the JFET resistance and low channel mobility of planar MOSFETs restricted the continued improvement of the performance of silicon carbide planar MOSFETs. As a result, researchers gradually turned to the development of silicon carbide trench MOSFETs. Trench MOSFETs eliminate JFET resistance, and the mobility of their vertical channels is about twice that of horizontal channels. Therefore, silicon carbide trench MOSFETs greatly alleviate the contradiction between device breakdown voltage (BV) and specific on-resistance (Ron,sp) compared to silicon carbide planar MOSFETs.

[0004] A key issue with silicon carbide trench MOSFETs is that when the device is operating in a blocking state, the gate oxide electric field gathers at the corners of the bottom of the trench. The high gate oxide electric field can affect the reliability of the device. The present invention prepares a surrounding semiconductor shielding area around the second trench, which can significantly reduce the gate oxide electric field. The surrounding semiconductor shielding area is prepared using a self-aligned process without adding an additional mask.

[0005] The information disclosed in this background technology section is only intended to deepen the understanding of the overall background technology of the present invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art. Summary of the Invention

[0006] In view of the problems existing in the prior art, the purpose of the present invention is to provide a silicon carbide stepped trench MOSFET and a manufacturing method thereof, so as to solve the problem of gate oxide electric field at the bottom corner of the high trench of the silicon carbide trench MOSFET in the blocking state.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A silicon carbide stepped trench MOSFET, comprising:

[0009] a semiconductor drain region, which is a semiconductor material heavily doped with the first conductivity type;

[0010] a semiconductor drift region, which is a lightly doped semiconductor material of a first conductivity type;

[0011] A second conductive type semiconductor well region located at a top of the semiconductor drift region;

[0012] a first conductive type semiconductor source region located in the middle of the top of the second conductive type semiconductor well region;

[0013] a second conductive type semiconductor body contact region located at a top of the second conductive type semiconductor well region and away from a middle position;

[0014] A first conductive type carrier diffusion layer is located between the second conductive type semiconductor well region and the second conductive type semiconductor shielding region;

[0015] a first trench located in the middle of the semiconductor drift region and extending from the semiconductor source region into the semiconductor drift region;

[0016] A second conductive type semiconductor shielding region surrounds the first trench;

[0017] The second groove is placed directly above the first groove;

[0018] The gate dielectric layer is located on the inner walls of the first trench and the second trench;

[0019] a gate electrode, located on the gate dielectric layer;

[0020] an interlayer dielectric layer, located above the gate electrode;

[0021] A contact hole is provided in the interlayer dielectric layer;

[0022] a source metal electrode, located above the interlayer dielectric layer and forming an ohmic contact with the semiconductor source region and the semiconductor body contact region through the contact hole;

[0023] The drain metal electrode is located below the semiconductor drain region and forms an ohmic contact with the semiconductor drain region.

[0024] Furthermore, the width of the first conductive type carrier diffusion layer is T1, which is prepared by global ion implantation or epitaxy, and its doping concentration is less than the doping concentration of the semiconductor well region. No additional mask is added in the preparation of the carrier diffusion layer.

[0025] Furthermore, the first trench has a width of W2 and a depth of T2; the depth T2 is smaller than the thickness of the semiconductor drift region and larger than the sum of the thickness of the semiconductor well region, the gate dielectric and the carrier diffusion layer.

[0026] Furthermore, the thickness of the second conductive type semiconductor shielding region is T3, which is prepared by adjusting the ion implantation angle and the rotation angle with the hard mask HM1 used to prepare the first trench as a barrier, and the semiconductor shielding region surrounds the first trench and is short-circuited with the source metal. Its doping concentration is 1 to 100 times that of the semiconductor well region, and the ion implantation is performed with the first trench as the self-alignment without adding an additional mask.

[0027] Furthermore, the width of the second trench is W5 and the depth is T5; the width W5 of the second trench is greater than the sum of the width W2 of the first trench and 2 times the width T3 of the second conductive type semiconductor shielding area, wherein the bottom of the second trench extends into the carrier diffusion layer, or the bottom of the second trench exceeds the bottom of the carrier diffusion layer, but the depth of the second trench is less than the depth of the first trench.

[0028] Furthermore, the gate dielectric layer in the first trench and the second trench is formed by thermal growth or prepared by deposition, and the gate dielectric layer is silicon oxide, silicon nitride, aluminum oxide or hafnium oxide, or a combination of several materials; the gate electrode is isolated from the adjacent SIC epitaxy by the gate dielectric layer, and the material of the gate electrode is heavily doped polysilicon or metal.

[0029] Furthermore, for an N-channel silicon carbide trench MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; for a P-channel silicon carbide trench MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0030] A method for manufacturing a silicon carbide stepped trench MOSFET comprises the following steps:

[0031] S1. Prepare a semiconductor drain region heavily doped with a first conductive type semiconductor material, wherein the concentration of impurity atoms in the crystal is 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3 A low-doped semiconductor drift region is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 pieces / cm 3 -9.5×10 16 pieces / cm 3 ;

[0032] S2, aluminum atoms are implanted at the top of the semiconductor drift region to form a second conductive type semiconductor well region, with an implantation dose of 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted into the middle of the top of the second conductive type semiconductor well region with an implantation dose of 1×1015 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region is formed between the first conductive type semiconductor source region and the second conductive type semiconductor well region, and then a high concentration of aluminum atoms is implanted at the top of the second conductive type semiconductor well region and away from the middle position to form a second conductive type semiconductor body contact region;

[0033] S3. Forming a first conductive type carrier diffusion layer by performing ion implantation on the entire region, wherein the ion implantation is performed as a general implantation, so no additional mask is introduced in the preparation of the carrier diffusion layer, and the carrier diffusion layer can also be prepared by epitaxy;

[0034] S4. Depositing a layer of silicon oxide or a combination of silicon oxide and polysilicon as a hard mask layer HM1 above the active area, then etching a window in the hard mask, and then etching the semiconductor drift region by dry-coupled plasma etching, reactive ion etching, or a combination of the two to form a first trench with a width W2 and a depth T2, wherein the depth T2 is less than the thickness of the semiconductor drift region and greater than the sum of the thickness of the semiconductor well region, the gate dielectric thickness, and the carrier diffusion layer;

[0035] S5. Using the hard mask layer HM1 as a barrier, a second conductive type semiconductor shielding region with a width of T3 is prepared by adjusting the ion implantation angle and the rotation angle. The second conductive type semiconductor shielding region surrounds the first trench and is short-circuited with the source metal. The semiconductor shielding region has a concentration 1 to 100 times that of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the first trench, thereby ensuring that the first trench is surrounded by the semiconductor shielding region. The semiconductor shielding region needs to be connected to the source metal, either as a whole semiconductor shielding region or as a staged semiconductor shielding region.

[0036] S6. Two micro-trenches with a width of T4 are defined in the hard mask layer HM2. Then, the semiconductor drift region is etched in the window area defined by the hard mask HM2 by dry-coupled plasma etching, reactive ion etching, or a combination of the two, to produce two micro-trenches with a width of T4 and a depth of T5. Then, the hard mask HM2 is removed to form a second trench with a width of W5 and a depth of T5. The width W5 of the second trench is greater than the sum of the width W2 of the first trench and twice the width T3 of the shielding region. The bottom of the second trench extends into the carrier diffusion layer, or the bottom of the second trench exceeds the bottom of the carrier diffusion layer, but the depth of the second trench is less than the depth of the first trench.

[0037] S7, covering the left side of the trench with photoresist PH, exposing the right side of the trench; by adjusting the ion implantation energy and the rotation angle, a second conductive type shielding region is also formed on the right side of the second trench, thereby short-circuiting the semiconductor shielding region at the bottom of the first trench with the semiconductor source region, and thus also short-circuiting with the semiconductor source metal electrode;

[0038] S8. Forming a gate dielectric layer by deposition or oxidation. The gate dielectric layer is made of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, or a combination of these materials. The thickness of the gate dielectric layer is 0.02-1µm. Then, a gate electrode is formed on the gate dielectric layer. The gate electrode is made of heavily doped polysilicon or metal.

[0039] S9, depositing a certain thickness of non-doped silicon oxide and borophosphosilicate glass above the gate electrode to form an interlayer dielectric layer with a thickness of 0.4-1µm, and then etching a through hole in the interlayer dielectric layer to form a contact hole;

[0040] S10. Deposit and etch a front metal on the interlayer dielectric to form a source metal electrode; deposit a conductive metal below the semiconductor drain region to form a drain metal electrode. Both the source and drain metals form ohmic contacts with the semiconductor.

[0041] Furthermore, taking a strip cell as an example, there are three ways to short-circuit the second conductive type semiconductor shielding region and the source metal:

[0042] The first is that when the device is operating in the on state, the conductive channel on the right side of the second trench is completely non-conductive;

[0043] The second type is that the semiconductor shielding area on the right side of the second trench is distributed in stages, that is, the conductive channel on the right side of the second trench is turned on in stages;

[0044] The third method is: second conductive type semiconductor shielding regions distributed in stages can be prepared on both the left and right sides of the second trench, so that the conductive channels on both the left and right sides of the second trench are both conductive in stages.

[0045] Furthermore, based on step S6, a first conductive type carrier diffusion layer with a width of T6 is prepared by adjusting the ion injection angle and the rotation angle. The first conductive type carrier diffusion layer surrounds the semiconductor shielding area near the first trench, and then steps S7-S10 are repeated to finally form a unit cell structure.

[0046] By adopting the above technical solution, the present invention has the following beneficial effects:

[0047] The present application designs a silicon carbide stepped trench MOSFET and a manufacturing method thereof. The structure is designed with a semiconductor shielding region surrounding the first trench, so that the new structure can achieve a lower gate oxide electric field at the corner of the bottom of the trench in the blocking state, thereby improving device reliability; at the same time, the characteristic of the semiconductor shielding region being connected to the source metal enables the surrounding shielding region to eliminate the entire first trench and reduce the gate-drain overlap area in the local area at the bottom of the second trench, thereby reducing the gate-drain capacitance (Cgd) and reducing switching power consumption; further, the carrier diffusion layer under the semiconductor well region can reduce the specific on-resistance (Ron,sp); further, the stepped position where the first trench contacts the second trench introduces a new electric field peak, which can improve the breakdown voltage (BV) of the device; further, no additional mask is added for the preparation of the carrier diffusion layer and the preparation of the semiconductor shielding region. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 is a schematic diagram of the 3D structure of Example 1 of the present application;

[0050] Figure 2 Schematic diagram of the unit cell structure along the AA' line cross section of Example 1 of the present application;

[0051] Figure 3 This is a schematic diagram of the initial structure of Example 1 of the present application;

[0052] Figure 4 1 is a schematic structural diagram of forming an active area in Example 1 of the present application;

[0053] Figure 5 This is a schematic structural diagram of a carrier diffusion layer formed in Example 1 of the present application;

[0054] Figure 6 This is a schematic structural diagram of the first groove of Example 1 of the present application;

[0055] Figure 7 This is a schematic structural diagram of a semiconductor shielding region formed in Example 1 of the present application;

[0056] Figure 8 This is a schematic structural diagram of forming a second groove in Example 1 of the present application;

[0057] Figure 9 This is a schematic structural diagram of the lead-out terminal of the semiconductor shielding region formed in Example 1 of the present application;

[0058] Figure 10 This is a schematic diagram of forming a gate structure according to Example 1 of the present application;

[0059] Figure 11 This is a schematic structural diagram of a contact hole formed in Example 1 of the present application;

[0060] Figure 12 This is a schematic diagram of the structure of the metal electrode formed in Example 1 of the present application;

[0061] Figure 13 This is a schematic diagram of a top view of the structure of three types of semiconductor shielding region lead-out terminals formed in Example 2 of the present application;

[0062] Figure 14 This is a key step in the formation of Example 3 of the present application and a schematic diagram of the original cell structure;

[0063] Figures 1 to 14 The regions in the figure are marked as follows: (1) - semiconductor drain region, (2) - semiconductor drift region, (3) - second conductive type semiconductor well region, (4) - first conductive type semiconductor source region, (5) - second conductive type semiconductor body contact region, (6) - first conductive type carrier diffusion layer, (7) - first trench, (8) - second conductive type semiconductor shielding region, (9) - second trench, (10) - gate dielectric layer, (11) - gate electrode, (12) - interlayer dielectric layer, (13) - contact hole, (14) - source metal electrode, (15) - drain metal electrode, (16) - first conductive type carrier diffusion layer. DETAILED DESCRIPTION

[0064] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0065] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention. Example 1

[0066] Figure 1 and Figure 2In one embodiment shown, a silicon carbide stepped trench MOSFET comprises: a semiconductor drain region 1, which is a heavily doped first conductivity type semiconductor material; a semiconductor drift region 2, which is a lightly doped first conductivity type semiconductor material; a second conductivity type semiconductor well region 3, which is located at the top of the semiconductor drift region; a first conductivity type semiconductor source region 4, which is located at the middle position at the top of the second conductivity type semiconductor well region; a second conductivity type semiconductor body contact region 5, which is located at the top of the second conductivity type semiconductor well region and away from the middle position; a first conductivity type carrier diffusion layer 6, which is located between the second conductivity type semiconductor well region and the second conductivity type semiconductor shielding region; a first trench 7, which Located in the middle of the semiconductor drift region, extending from the semiconductor source region into the semiconductor drift region; the second conductive type semiconductor shielding region 8 surrounds the second trench; the second trench 9 is placed directly above the first trench; the gate dielectric layer 10 is located on the inner wall of the first and second trenches; the gate electrode 11 is located on the gate dielectric layer of the first and second trenches; the interlayer dielectric layer 12 is located above the gate electrode; a contact hole 13 is provided in the interlayer dielectric layer; a source metal electrode 14 is located above the interlayer dielectric and forms an ohmic contact with the semiconductor source region and the semiconductor body contact region through the contact hole; a drain metal electrode 15 is located below the semiconductor drain region and forms an ohmic contact with the semiconductor drain region.

[0067] In this embodiment, a first conductive type carrier diffusion layer is formed by general implantation or epitaxy, and then a first trench is etched. Subsequently, a second conductive type semiconductor shielding region is formed at the bottom and sidewalls of the first trench by adjusting the ion implantation angle and the rotation angle, wherein no additional mask is added in the preparation of the carrier diffusion layer and the semiconductor shielding region.

[0068] exist Figure 3 In the embodiment shown, the semiconductor drain region 1 is a semiconductor material heavily doped with the first conductivity type, such as a crystal with an impurity atom concentration of 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3 A low-doped semiconductor drift region 2 is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 pieces / cm 3 -9.5×10 16 pieces / cm 3 .

[0069] exist Figure 4 In the embodiment shown, aluminum atoms are implanted at the top of the semiconductor drift region to form a second conductive type semiconductor well region 3, with an implantation dose of 5×10 11 pieces / cm 2-5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted into the middle of the top of the second conductive type semiconductor well region with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region 4 is formed between the two regions, and then a high concentration of aluminum atoms is implanted at the top of the second conductive type semiconductor well region and away from the middle position to form a second conductive type semiconductor body contact region 5.

[0070] exist Figure 5 In the embodiment shown, the carrier diffusion layer 6 is formed by performing ion implantation on the entire region, wherein the ion implantation is performed as a general implantation. Therefore, no additional mask is introduced in the preparation of the carrier diffusion layer, and the carrier diffusion layer can also be prepared by epitaxy.

[0071] exist Figure 6 In the illustrated embodiment, a layer of silicon oxide or a combination of silicon oxide and polysilicon is deposited above the active region as a hard mask layer (HM1), and then a window is etched in the hard mask. Subsequently, the semiconductor drift region is etched by dry-coupled plasma etching, reactive ion etching, or a combination of the two to form a first trench 7 with a width W2 and a depth T2. The depth T2 is less than the thickness of the semiconductor drift region and greater than the sum of the thickness of the semiconductor well region, the gate dielectric thickness, and the carrier diffusion layer.

[0072] exist Figure 7 In the embodiment shown, the hard mask layer HM1 is used as a barrier, and a second conductive type semiconductor shielding region 8 with a width of T3 is prepared by adjusting the ion implantation angle and the rotation angle. The second conductive type semiconductor shielding region 8 surrounds the first trench and is short-circuited with the source metal. The concentration of the semiconductor shielding region can be 1 to 100 times that of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the first trench, thereby ensuring that the first trench is surrounded by the semiconductor shielding region; further, the semiconductor shielding region needs to be connected to the source metal. The entire semiconductor shielding region can be connected to the source metal, or the semiconductor shielding region distributed in stages can be connected to the source metal. If the semiconductor shielding region is not connected to the source metal, it will increase the switching power consumption of the device on the one hand, and reduce the reliability of the device on the other hand.

[0073] exist Figure 8 In the embodiment shown, 8(a) defines two micro-grooves with a width of T4 in the hard mask layer HM2, and then etches the semiconductor drift region in the window area defined by the hard mask HM2 by dry coupled plasma etching, reactive ion etching, or a combination of the two, to produce two micro-grooves with a width of T4 and a depth of T5, as shown in FIG. Figure 8(b); then remove the hard mask HM2 to form a second trench with a width of W5 and a depth of T5, as shown in FIG. Figure 8 As shown in (c), the width W5 of the second trench is greater than the sum of the width W2 of the first trench and twice the width T3 of the shielding region, wherein the bottom of the second trench can extend into the carrier diffusion layer, and the bottom of the second trench can also exceed the bottom of the carrier diffusion layer, but the depth of the second trench is less than the depth of the first trench.

[0074] exist Figure 9 In the embodiment shown, Figure 9 (a) The left side of the trench is covered with photoresist PH, exposing the right side of the trench; by adjusting the ion implantation energy and the rotation angle, a second conductive type shielding region is also formed on the right side of the second trench, so that the semiconductor shielding region at the bottom of the first trench is short-circuited with the semiconductor source region, and thus also short-circuited with the semiconductor source metal electrode, as shown in FIG. Figure 9 (b)

[0075] exist Figure 10 In the embodiment shown, a gate dielectric layer 10 is formed by deposition or oxidation. The gate dielectric layer can be silicon oxide, or a high dielectric constant dielectric such as silicon nitride, aluminum oxide, hafnium oxide, or a combination of several materials. Its thickness can be 0.02-1µm. Then, a gate electrode 11 is prepared on the gate dielectric layer, where the gate electrode can be heavily doped polysilicon or metal.

[0076] exist Figure 11 In the embodiment shown, a certain thickness of undoped silicon oxide and borophosphosilicate glass is deposited above the gate electrode to form an interlayer dielectric layer 12, which is generally 0.4-1µm thick. Then, a through hole is etched in the interlayer dielectric layer to form a contact hole 13.

[0077] exist Figure 12 In the embodiment shown, a front metal is deposited and etched above the interlayer dielectric to form a source metal electrode 14. A conductive metal is deposited below the semiconductor drain region to form a drain metal electrode 15. Both the source and drain metals form ohmic contacts with the semiconductor. Example 2

[0078] exist Figure 13 In the embodiment shown, taking the strip cell as an example, there are three ways to short-circuit the semiconductor shielding region 8 on the right side of the second trench with the source metal. Figure 13 As shown in (a), the conductive channel on the right side of the second trench is completely non-conductive; the semiconductor shielding area 8 on the right side of the second trench can also be distributed in stages, as shown in the top view. Figure 13As shown in (b), the conductive channel on the right side of the second trench is staged; further, the second conductive type semiconductor shielding region 8 can be prepared on both the left and right sides of the second trench in a staged distribution, as shown in the top view. Figure 13 As shown in (c), the conductive channels on the left and right sides of the second trench are both turned on in stages. Example 3

[0079] exist Figure 14 In the embodiment shown, in Example 1 Figure 8 Based on (c), a first conductive type carrier diffusion layer 16 with a width of T6 is prepared by adjusting the ion implantation angle and the rotation angle. The doping concentration of the first conductive type carrier diffusion layer 16 can be close to or slightly lower than that of the first conductive type carrier diffusion layer 6. The first conductive type carrier diffusion layer 16 surrounds the semiconductor shielding region 8 near the first trench, as shown in FIG. Figure 14 (a); The subsequent process flow of Example 3 is the same as that of Example 1 Figures 9 to 13 The final primitive cell structure formed in Example 3 is as follows Figure 14 As shown in (b), it not only inherits the advantages of the structure in embodiment 1, but also the structure in embodiment 3 makes the area directly below the semiconductor shielding area and the left and right sides thereof low resistance areas, which helps to further reduce the specific conductor resistance of the device.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide step trench MOSFET, characterized in that: include: A semiconductor drain region (1) is a heavily doped semiconductor material of a first conductivity type; A semiconductor drift region (2) is a lightly doped semiconductor material of a first conductivity type; A second conductive type semiconductor well region (3), located at the top of the semiconductor drift region (2); A first conductive type semiconductor source region (4) located in the middle of the top of the second conductive type semiconductor well region (3); A second conductive type semiconductor body contact region (5), located at the top of the second conductive type semiconductor well region (3) and away from the middle; a first conductive type carrier diffusion layer (6), located between the second conductive type semiconductor well region (3) and the second conductive type semiconductor shielding region; a first trench (7) located in the middle of the semiconductor drift region (2) and extending from the semiconductor source region into the semiconductor drift region; A second conductive type semiconductor shielding region (8) surrounds the first trench (7); The second groove (9) is placed directly above the first groove (7); The gate dielectric layer (10) is located on the inner walls of the first trench (7) and the second trench (9); a gate electrode (11), located on the gate dielectric layer (10); an interlayer dielectric layer (12), located above the gate electrode (11); A contact hole (13) is provided in the interlayer dielectric layer (12); A source metal electrode (14), located above the interlayer dielectric layer (12), and forming an ohmic contact with the semiconductor source region and the semiconductor body contact region through the contact hole (13); A drain metal electrode (15), which is located below the semiconductor drain region (1) and forms an ohmic contact with the semiconductor drain region (1); The second conductive type semiconductor shielding region is short-circuited with the source terminal metal.

2. The silicon carbide step trench MOSFET according to claim 1, wherein: The width of the first conductive type carrier diffusion layer (6) is T1, and it is prepared by global ion implantation, i.e., general implantation, or by epitaxy, and its doping concentration is less than the doping concentration of the semiconductor well region, and no additional mask is added in the preparation of the carrier diffusion layer.

3. The silicon carbide step trench MOSFET according to claim 1, wherein: The first groove (7) has a width of W2 and a depth of T2; The depth T2 is smaller than the thickness of the semiconductor drift region and larger than the sum of the thickness of the semiconductor well region, the gate dielectric layer, and the carrier diffusion layer.

4. The silicon carbide step trench MOSFET according to claim 1, wherein: The thickness of the second conductive type semiconductor shielding region (8) is T3, and it is prepared by adjusting the ion implantation angle and the rotation angle using the hard mask layer HM1 used to prepare the first trench as a barrier. Its doping concentration is 1 to 100 times that of the semiconductor well region, and the ion implantation is performed in self-alignment with the first trench without adding an additional mask.

5. The silicon carbide step trench MOSFET according to claim 1, wherein: The width of the second trench (9) is W5, and the depth is T5; the width W5 of the second trench is greater than the sum of the width W2 of the first trench and twice the width T3 of the second conductive type semiconductor shielding region (8), wherein the bottom of the second trench extends into the carrier diffusion layer, or the bottom of the second trench exceeds the bottom of the carrier diffusion layer, but the depth of the second trench is less than the depth of the first trench.

6. The silicon carbide step trench MOSFET according to claim 1, wherein: The gate dielectric layer in the first trench (7) and the second trench (9) is formed by thermal growth or prepared by deposition, and the gate dielectric layer is silicon oxide, silicon nitride, aluminum oxide or hafnium oxide, or a combination of several materials; the gate electrode (11) is isolated from the adjacent SiC epitaxial by the gate dielectric layer, and the material of the gate electrode (11) is heavily doped polysilicon or metal.

7. The silicon carbide step trench MOSFET according to claim 1, wherein: For an N-channel silicon carbide trench MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; for a P-channel silicon carbide trench MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

8. A method for manufacturing a silicon carbide step trench MOSFET according to any one of claims 1 to 7, characterized in that: The steps include: S1, preparing a semiconductor drain region (1) heavily doped with a first conductive type semiconductor material, wherein the concentration of impurity atoms in the crystal is 1×10 19 pieces / cm 3 -3×10 20 pieces / cm 3 A low-doped semiconductor drift region (2) is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 pieces / cm 3 -9.5×10 16 pieces / cm 3 ; S2, aluminum atoms are injected into the top of the semiconductor drift region to form a second conductive type semiconductor well region (3), with an injection dose of 5×10 11 pieces / cm 2 -5×10 14 pieces / cm 2 Then, nitrogen atoms are implanted into the middle of the top of the second conductive type semiconductor well region with an implantation dose of 1×10 15 pieces / cm 2 -9×10 15 pieces / cm 2 A first conductive type semiconductor source region (4) is formed between the first conductive type semiconductor well region and the second conductive type semiconductor well region, and then a high concentration of aluminum atoms is injected into the top of the second conductive type semiconductor well region and away from the middle position to form a second conductive type semiconductor body contact region (5); S3, forming a first conductive type carrier diffusion layer (6) by performing ion implantation on the entire region, wherein the ion implantation is performed as a general implantation, so that no additional mask is introduced in the preparation of the carrier diffusion layer, or the carrier diffusion layer is prepared by epitaxy; S4, depositing a layer of silicon oxide or a combination of silicon oxide and polysilicon as a hard mask layer HM1 above the active region, then etching a window on the hard mask layer HM1, and then etching the semiconductor drift region by dry coupled plasma etching, reactive ion etching, or a combination of the two, to form a first trench (7) with a width W2 and a depth T2, wherein the depth T2 is less than the thickness of the semiconductor drift region and greater than the sum of the thickness of the semiconductor well region, the thickness of the gate dielectric, and the thickness of the carrier diffusion layer; S5, using the hard mask layer HM1 as a barrier, by adjusting the ion implantation angle and the rotation angle, a second conductive type semiconductor shielding region (8) with a width of T3 is prepared, which surrounds the first trench and is short-circuited with the source metal. The semiconductor shielding region has a concentration of 1 to 100 times that of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the first trench, thereby ensuring that the first trench is surrounded by the semiconductor shielding region. The semiconductor shielding region needs to be connected to the source metal, either the entire semiconductor shielding region is connected to the source metal, or the semiconductor shielding region distributed in stages is connected to the source metal. S6. Two micro-trenches with a width of T4 are defined in the hard mask layer HM2. Then, the semiconductor drift region is etched in the window area defined by the hard mask layer HM2 by dry-coupled plasma etching, reactive ion etching, or a combination thereof, to produce two micro-trenches with a width of T4 and a depth of T5. Then, the hard mask layer HM2 is removed to form a second trench with a width of W5 and a depth of T5. The width W5 of the second trench is greater than the sum of the width W2 of the first trench and twice the width T3 of the shielding region. The bottom of the second trench extends into the carrier diffusion layer, or the bottom of the second trench exceeds the bottom of the carrier diffusion layer, but the depth of the second trench is less than the depth of the first trench. S7, covering the left side of the trench with photoresist PH, exposing the right side of the trench; by adjusting the ion implantation energy and the rotation angle, a second conductive type shielding region is also formed on the right side of the second trench, thereby short-circuiting the semiconductor shielding region at the bottom of the first trench with the semiconductor source region, and thus also short-circuiting with the semiconductor source metal electrode; S8, forming a gate dielectric layer (10) by deposition or oxidation, wherein the gate dielectric layer is silicon oxide, silicon nitride, aluminum oxide or hafnium oxide, or a combination of several materials; the thickness of the gate dielectric layer is 0.02-1µm, and then forming a gate electrode (11) on the gate dielectric layer, wherein the gate electrode is heavily doped polysilicon or metal; S9, depositing a certain thickness of non-doped silicon oxide and boron phospho-silicate glass above the gate electrode to form an interlayer dielectric layer (12) with a thickness of 0.4-1µm, and then etching a through hole in the interlayer dielectric layer to form a contact hole (13); S10, depositing and etching a front metal on the interlayer dielectric to form a source metal electrode (14); depositing a conductive metal below the semiconductor drain region to form a drain metal electrode (15), with both the source and drain metals forming ohmic contacts with the semiconductor.

9. The method for manufacturing a silicon carbide step trench MOSFET according to claim 8, wherein: Taking the strip cell as an example, there are three ways to short-circuit the second conductive type semiconductor shielding region (9) with the source metal: The first is that when the device is operating in the on state, the conductive channel on the right side of the second trench is completely non-conductive; The second type is that the semiconductor shielding area on the right side of the second trench is distributed in stages, that is, the conductive channel on the right side of the second trench is turned on in stages; The third type is: a second conductive type semiconductor shielding region (8) distributed in stages is prepared on both the left and right sides of the second trench, so that the conductive channels on both the left and right sides of the second trench are both conducted in stages.

10. The method for manufacturing a silicon carbide step trench MOSFET according to claim 8, wherein: On the basis of step S6, a first conductive type carrier diffusion layer (16) with a width of T6 is prepared by adjusting the ion implantation angle and the rotation angle. The first conductive type carrier diffusion layer (16) surrounds the semiconductor shielding region (8) near the first trench, and then steps S7-S10 are repeated to finally form a primitive cell structure.

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