Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for preparing the same. The semiconductor device comprises a substrate, an epitaxial layer, a gate structure and a buried layer structure; the substrate has a first conductivity type, the epitaxial layer has a first conductivity type and is located on the surface of the substrate, the epitaxial layer comprises a first surface, and the first surface is provided with a gate trench; the gate structure is located inside the gate trench; the buried layer structure comprises a first buried layer and a second buried layer, the second buried layer has a first conductivity type, the first buried layer has a second conductivity type, and the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer, and the second buried layer is configured to reduce the width of the depletion region between the second buried layer and the first buried layer. The technical solution of the embodiment of the present invention can protect the gate oxide layer from being easily broken down, improve the reliability of the device, and ensure the on-state current of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Silicon carbide (SiC) trench gate metal oxide semiconductor field effect transistor (MOSFET) has the advantages of high current density, small cell spacing and fast switching speed, and has become the main research object of the new generation of SiC MOSFET.

[0003] In a SiC trench gate MOSFET, the electric field at the bottom of the trench and the corner of the trench is relatively high, resulting in a relatively high electric field on the gate oxide layer of the trench gate structure, which makes the gate oxide layer easily broken down. In order to protect the gate oxide layer from being broken down and improve the reliability of the MOSFET, the prior art proposes to use a double trench structure or an asymmetric structure to achieve the above effect. However, the use of an additional double source trench structure or an asymmetric structure will increase the process complexity or affect the on-state current of the device. Summary of the invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, so as to solve the problem that a gate oxide layer of a SiC trench gate structure MOSFET is easily broken down, resulting in low device reliability, and ensure the on-state current of the MOSFET.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] a substrate having a first conductivity type;

[0007] an epitaxial layer having the first conductivity type and being located on a surface of the substrate, the epitaxial layer comprising a first surface, the first surface being provided with a gate trench;

[0008] A gate structure, located inside the gate trench;

[0009] A buried layer structure, the buried layer structure comprising a first buried layer and a second buried layer, the second buried layer having the first conductivity type, the first buried layer having the second conductivity type, and the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer, the second buried layer being configured to reduce the width of the depletion region between the second buried layer and the first buried layer.

[0010] Optionally, the first buried layer includes a first sub-buried layer portion and a second sub-buried layer portion, the first sub-buried layer portion is located at a side of the bottom of the gate structure close to the substrate, the second sub-buried layer portion is located at a side of the first sub-buried layer portion away from the gate structure, and the second sub-buried layer portion is in contact with the first sub-buried layer portion;

[0011] The width of the first sub-buried layer portion is smaller than that of the second sub-buried layer portion; in a direction perpendicular to the thickness of the substrate, the second buried layer is arranged on at least one side of the second sub-buried layer portion.

[0012] Optionally, the first sub-buried layer portion has a first preset width on a side close to the gate structure, and has a second preset width on a side away from the gate structure, and the width of the first sub-buried layer portion is between the first preset width and the second preset width; the second sub-buried layer portion has a third preset width;

[0013] The first preset width is smaller than the third preset width, and the second preset width is smaller than or equal to the third preset width.

[0014] Optionally, the first preset width is smaller than the second preset width, and the width of the first sub-buried layer portion gradually increases from the first preset width to the second preset width.

[0015] Optionally, the second preset width is equal to the first preset width, and both the first preset width and the second preset width are smaller than the third preset width.

[0016] Optionally, the first buried layer further includes a third sub-buried layer portion;

[0017] The third sub-buried layer portion is located at a side of the second sub-buried layer portion away from the first sub-buried layer portion, and the third sub-buried layer portion is in contact with the second sub-buried layer portion;

[0018] The third sub-buried layer portion has a fourth preset width, and the fourth preset width is smaller than the third preset width.

[0019] Optionally, the gate structure includes two opposite side surfaces, and the semiconductor device further includes: a first doped region located on at least one side of the gate structure;

[0020] The second buried layer includes a fourth sub-buried layer portion and a fifth sub-buried layer portion; the fourth sub-buried layer portion includes a second surface and a third surface that are perpendicular to each other, and the fifth sub-buried layer portion includes a fourth surface and a fifth surface that are perpendicular to each other;

[0021] The second surface contacts the bottom of the first doped region, and the third surface contacts the second sub-buried layer portion in a direction perpendicular to the thickness of the substrate;

[0022] The fourth surface contacts the side surface of the first doped region, and the fifth surface contacts the fourth sub-buried layer portion;

[0023] Wherein, the first doped region has the second conductivity type.

[0024] Optionally, the semiconductor device further includes:

[0025] a second doped region having the first conductivity type and located on the first surface of the epitaxial layer;

[0026] a body region having the second conductivity type and located on a side of the second doped region away from the first surface;

[0027] A dielectric layer, located on a side of the epitaxial layer away from the substrate, wherein an orthographic projection of the dielectric layer on the substrate covers an orthographic projection of the gate structure on the substrate;

[0028] A source electrode is located on a side of the dielectric layer away from the epitaxial layer, and an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate;

[0029] A passivation layer, located on a side of the source electrode away from the epitaxial layer, and an orthographic projection of the passivation layer on the substrate covers an orthographic projection of the first doped region on the substrate;

[0030] The drain is located at a side of the substrate away from the epitaxial layer.

[0031] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0032] Providing a substrate; the substrate has a first conductivity type;

[0033] forming an epitaxial layer on the surface of the substrate; the epitaxial layer has the first conductivity type, and the epitaxial layer includes a first surface;

[0034] forming a buried layer structure in the epitaxial layer; the buried layer structure comprises a first buried layer and a second buried layer, the second buried layer has the first conductivity type, the first buried layer has the second conductivity type, the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer, and the second buried layer is configured to reduce the width of the depletion region between the second buried layer and the first buried layer;

[0035] forming a gate trench on the first surface;

[0036] A gate structure is formed inside the gate trench.

[0037] Optionally, the first buried layer includes a first sub-buried layer portion, a second sub-buried layer portion and a third sub-buried layer portion, and the second buried layer includes a fourth sub-buried layer portion and a fifth sub-buried layer portion;

[0038] The forming of a buried layer structure in the epitaxial layer comprises:

[0039] Performing ion implantation on the epitaxial layer to form the third buried sub-layer portion;

[0040] Performing ion implantation again on the epitaxial layer to form the second sub-buried layer portion and the fourth sub-buried layer portion; wherein the fourth sub-buried layer portion contacts the second sub-buried layer portion in a direction perpendicular to the substrate, and the third sub-buried layer portion contacts the second sub-buried layer portion in a thickness direction of the substrate;

[0041] forming the epitaxial layer again on a side of the second sub-buried layer portion and the fourth sub-buried layer portion away from the substrate;

[0042] Performing ion implantation again on the epitaxial layer to form the first sub-buried layer portion and the fifth sub-buried layer portion; wherein the first sub-buried layer portion is in contact with the second sub-buried layer portion, and the fifth sub-buried layer portion is in contact with the fourth sub-buried layer portion;

[0043] forming the epitaxial layer again on a side of the first sub-buried layer portion and the fifth sub-buried layer portion away from the substrate;

[0044] Before forming a gate trench in the epitaxial layer, the method further includes:

[0045] Performing ion implantation on the first surface to form a body region and a second doped region; wherein the second doped region is located on the first surface of the epitaxial layer, and the body region is located on a side of the second doped region away from the first surface;

[0046] After forming a gate trench in the epitaxial layer, the method further includes:

[0047] Performing ion implantation on the first surface to form a first doped region; the first doped region is located on at least one side of the gate trench;

[0048] The semiconductor device manufacturing method further includes:

[0049] forming a dielectric layer on a side of the epitaxial layer away from the substrate; the orthographic projection of the dielectric layer on the substrate covers the orthographic projection of the gate structure on the substrate;

[0050] A source electrode is formed on a side of the dielectric layer away from the epitaxial layer; an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate;

[0051] A passivation layer is formed on a side of the source electrode away from the epitaxial layer; the orthographic projection of the passivation layer on the substrate covers the orthographic projection of the first doped region on the substrate;

[0052] A drain is formed on a side of the substrate away from the epitaxial layer.

[0053] In the semiconductor device provided by the embodiment of the present invention, the epitaxial layer has a first conductivity type, a buried layer structure is arranged in the epitaxial layer, and the buried layer structure includes a first buried layer and a second buried layer, the first buried layer has the second conductivity type, and the second buried layer has the first conductivity type. And the ion doping concentration of the first buried layer and the ion doping concentration of the second buried layer are both higher than the ion doping concentration of the epitaxial layer, then the first buried layer and the epitaxial layer can form a depletion region around the gate structure, thereby shielding the higher electric field around the gate structure and protecting the gate oxide layer from being easily broken down. The formation of the depletion region by the first buried layer and the epitaxial layer will also hinder the flow of electrons in the semiconductor device and affect the on-state current of the semiconductor device. Therefore, a depletion region with a smaller width is formed between the second buried layer with a higher ion doping concentration and the first buried layer, which is conducive to ensuring the current conduction channel on both sides of the gate structure and increasing the on-state current of the semiconductor device. The first buried layer and the second buried layer are arranged in this way, which can have a good shielding effect on the higher electric field around the gate structure, which is conducive to improving the reliability of the semiconductor device, and can also ensure the current conduction channel in the semiconductor device and increase the on-state current of the semiconductor device.

[0054] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0057] Figure 2 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0058] Figure 3 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0059] Figure 4 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0060] Figure 5 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0061] Figure 6 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0062] Figure 7 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0063] Figure 8 is a schematic flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0064] Fig. 9 yes Figure 8 Schematic diagram of the cross-sectional structure corresponding to each step in the figure;

[0065] Fig.10 is a schematic diagram of a specific flow chart of step S130 in a method for preparing a semiconductor device according to an embodiment of the present invention;

[0066] Fig.11 is a schematic diagram of the cross-sectional structure corresponding to each step in step S130;

[0067] Fig.12 is a schematic cross-sectional structure diagram corresponding to the step before forming the gate trench;

[0068] Fig.13 is a schematic cross-sectional structure diagram corresponding to the step after forming the gate trench;

[0069] Fig.14 is a schematic flow chart of another method for preparing a semiconductor device according to an embodiment of the present invention;

[0070] Fig.15 It is a schematic diagram of the cross-sectional structure corresponding to step S160 to step S190. DETAILED DESCRIPTION

[0071] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0072] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0073] An embodiment of the present invention provides a semiconductor device. Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a substrate 10 , an epitaxial layer 11 , a gate structure 12 and a buried layer structure 13 .

[0074] The substrate 10 has a first conductivity type, the epitaxial layer 11 has the first conductivity type and is located on the surface of the substrate 10, the epitaxial layer 11 includes a first surface 111, and the first surface 111 is provided with a gate trench; the gate structure 12 is located inside the gate trench; the buried layer structure 13 includes a first buried layer 131 and a second buried layer 132, the second buried layer 132 has the first conductivity type, the first buried layer 131 has the second conductivity type, and the ion concentration of the second buried layer 132 is greater than the ion concentration of the epitaxial layer 11, and the second buried layer 132 is configured to reduce the depletion region width between the second buried layer 131 and the first buried layer 131.

[0075] Specifically, the substrate 10 can be a silicon carbide substrate with a high ion doping concentration. A silicon carbide film layer with a low ion doping concentration of the first conductivity type is grown on the surface of the substrate 10 to form an epitaxial layer 11. Exemplarily, the first conductivity type can be N-type or P-type, which is not limited here. In the embodiment of the present invention, the structure of the semiconductor device is described by taking the first conductivity type as N-type and the second conductivity type as P-type as an example. The surface of the epitaxial layer 11 away from the side of the substrate 10 is referred to as the first surface 111, and a gate trench is extended from the first surface 111 to the inside of the epitaxial layer 11, and the gate trench is filled with a gate structure 12. It should be noted that the gate trench is a process structure generated during the preparation of the semiconductor device, and therefore, Figure 1 The gate trench is not marked. The gate structure 12 includes a gate oxide layer 121 covering the bottom and sidewall of the gate trench and a gate 122 disposed on the side of the gate oxide layer 121 away from the gate trench, and the thickness of the gate oxide layer 121 at the bottom of the gate trench is greater than the thickness of the gate oxide layer 121 at the sidewall of the gate trench 22, thereby enhancing the breakdown resistance of the gate oxide layer 121 in the gate trench, which is beneficial to improving the reliability of the semiconductor device.

[0076] A buried layer structure 13 is also provided in the epitaxial layer 11, and the buried layer structure 13 includes a first buried layer 131 located at the bottom of the gate structure 12 and a second buried layer 132 located on at least one side of the first buried layer 131. Exemplarily, the first buried layer 131 can be a P-type heavily doped region, and the second buried layer 132 is an N-type heavily doped region. Since the first buried layer 131 and the epitaxial layer 11 form a depletion region, it is beneficial to shield the higher electric field at the bottom of the gate structure 12 to ensure that the gate oxide layer 121 in the gate structure 12 is not easily broken down. However, if the depletion region formed by the first buried layer 131 and the epitaxial layer 11 is too wide, it will hinder the flow of electrons and affect the on-state current of the semiconductor device. By providing a second buried layer 132 on at least one side of the first buried layer 131 in the thickness direction perpendicular to the substrate 10. Since the ion doping concentration of the second buried layer 132 is higher than that of the epitaxial layer 11, the width of the depletion region formed between the second buried layer 132 and the first buried layer 131 can be effectively reduced, providing a current conduction channel for the semiconductor device, thereby increasing the on-state current of the semiconductor device.

[0077] In the semiconductor device provided by the embodiment of the present invention, the epitaxial layer has a first conductivity type, a buried layer structure is arranged in the epitaxial layer, and the buried layer structure includes a first buried layer and a second buried layer, the first buried layer has the second conductivity type, and the second buried layer has the first conductivity type. And the ion doping concentration of the first buried layer and the ion doping concentration of the second buried layer are both higher than the ion doping concentration of the epitaxial layer, then the first buried layer and the epitaxial layer can form a depletion region around the gate structure, thereby shielding the higher electric field around the gate structure and protecting the gate oxide layer from being easily broken down. The formation of the depletion region by the first buried layer and the epitaxial layer will also hinder the flow of electrons in the semiconductor device and affect the on-state current of the semiconductor device. Therefore, a depletion region with a smaller width is formed between the second buried layer with a higher ion doping concentration and the first buried layer, which is conducive to ensuring the current conduction channel on both sides of the gate structure and increasing the on-state current of the semiconductor device. The first buried layer and the second buried layer are arranged in this way, which can have a good shielding effect on the higher electric field around the gate structure, which is conducive to improving the reliability of the semiconductor device, and can also ensure the current conduction channel in the semiconductor device and increase the on-state current of the semiconductor device.

[0078] Optionally, Figure 2 FIG. 1 is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention. Figure 2 As shown, the first buried layer 131 includes a first sub-buried layer portion 311 and a second sub-buried layer portion 312, the first sub-buried layer portion 311 is located at the bottom of the gate structure 12 close to the substrate 10, the second sub-buried layer portion 312 is located at the side of the first sub-buried layer portion 311 away from the gate structure 12, and the second sub-buried layer portion 312 is in contact with the first sub-buried layer portion 311; the width of the first sub-buried layer portion 311 is smaller than the width of the second sub-buried layer portion 312; in the thickness direction perpendicular to the substrate 10, the second buried layer 132 is arranged on at least one side of the second sub-buried layer portion 312.

[0079] Specifically, the first sub-buried layer portion 311 is arranged at a position close to the bottom of the gate structure 12, and the first sub-buried layer portion 311 is in contact with the bottom of the gate structure 12. Relative to the position of the first sub-buried layer portion 311, the second sub-buried layer portion 312 is arranged at a side away from the gate structure 12, and the second sub-buried layer portion 312 is in contact with the first sub-buried layer portion 311. By setting the first sub-buried layer portion 311 close to the bottom of the gate structure 12 to have a smaller width, the first sub-buried layer portion 311 with a higher ion doping concentration can form a wider depletion region with the epitaxial layer 11, which can shield the electric field at the bottom of the gate structure 12 to a certain extent, and can also ensure that the bottom of the gate structure 12 has a wider current conduction channel, thereby increasing the on-state current of the semiconductor device. By setting the second sub-buried layer 312 away from the bottom of the gate structure 12 to have a larger width, the electric field on both sides of the gate structure 12 can be shielded, which is beneficial to improving the shielding effect of the electric field around the gate structure 12, improving the breakdown resistance of the gate oxide layer 121, and further improving the reliability of the semiconductor device.

[0080] The width settings of the first sub-buried layer portion 311 and the second sub-buried layer portion 312 in the first buried layer 131 may include various situations. The following embodiments will specifically describe the possible situations of the widths of the first sub-buried layer portion 311 and the second sub-buried layer portion 312.

[0081] Optionally, Figure 3 FIG. 1 is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention. Figure 3 As shown, the first sub-buried layer portion 311 has a first preset width d1 on a side close to the gate structure 12, the first sub-buried layer portion 311 has a second preset width d2 on a side away from the gate structure 12, and the width of the first sub-buried layer portion 311 is between the first preset width d1 and the second preset width d2; the second sub-buried layer portion 312 has a third preset width; the first preset width d1 is smaller than the third preset width, and the second preset width d2 is smaller than or equal to the third preset width.

[0082] Specifically, the width of the first sub-buried layer portion 311 disposed near the gate structure 12 may be different at different positions, and different widths may produce different electric field shielding effects. Exemplarily, the first sub-buried layer portion 311 may have a first preset width d1 on one side close to the gate structure 12, and a second preset width d2 on the side away from the gate structure 12, and the widths of the first sub-buried layer portion 311 at different positions are between the first preset width d1 and the second preset width d2. The second sub-buried layer portion 312 has a smaller extension depth in the epitaxial layer 11, and has a uniform third preset width d3 at different positions. In order to ensure that the first sub-buried layer portion 311 has a certain shielding effect on the electric field around the gate structure 12, while also ensuring that the semiconductor device has a wider current conduction channel and increasing the on-state current, the first preset width d1 can be set to be smaller than the third preset width d3, and the second preset width d2 can be set to be smaller than or equal to the third preset width d3, so that the width of the first sub-buried layer portion 311 close to the gate structure 12 is smaller, which not only has a certain shielding effect on the electric field in the middle of the gate structure 12, but also can ensure the current flow on both sides of the gate structure 12, thereby increasing the on-state current of the semiconductor device.

[0083] It should be noted that the third preset width d3 of the second sub-buried layer portion 312 can be less than the width of the gate structure 12, or can be equal to the width of the gate structure 12, or can be greater than the width of the gate structure 12, and there is no restriction here. The larger the width of the first buried layer 131, the better the shielding effect of the higher electric field around the gate structure 12, but it will reduce the transmission channel of the on-state current, so that the on-state current is reduced. Therefore, the specific width of the first buried layer 131 can be set by the user according to the actual needs of the semiconductor device, and it only needs to meet the size relationship between the widths, and there is no restriction here.

[0084] Optionally, Figure 4 FIG. 1 is a cross-sectional structural diagram of another semiconductor device provided by an embodiment of the present invention. Figure 3 and Figure 4 The first preset width d1 is smaller than the second preset width d2, and the width of the first sub-buried layer portion 311 gradually increases from the first preset width d1 to the second preset width d2.

[0085] For example, the width of the first sub-buried layer portion 311 may be set between the first preset width d1 and the second preset width d2, and the width of the first sub-buried layer portion 311 gradually increases from the side close to the gate structure 12 to the side away from the gate structure 12, that is, the cross-sectional shape of the first sub-buried layer portion 311 may be a regular trapezoid, such as Figure 3 When the first preset width d1 is 0, the cross-sectional shape of the first sub-buried layer portion 311 may also be a triangle, as shown in FIG. Figure 4As shown in . It should be noted that the second preset width d2 of the first sub-buried layer portion 311 can be equal to the third preset width d3 of the second sub-buried layer portion 312, and the second preset width d2 can also be smaller than the third preset width d3, which is not limited here. In this way, the first sub-buried layer portion 311 close to the bottom of the gate structure 12 can shield the higher electric field in the middle of the gate structure 12, and can ensure the on-state current channel of the semiconductor device, thereby increasing the on-state current.

[0086] Optionally, based on the above embodiments, continue to refer to Figure 2 The second preset width d2 is equal to the first preset width d1, and both the first preset width d1 and the second preset width d2 are smaller than the third preset width d3.

[0087] Exemplarily, the second preset width d2 is set equal to the first preset width d1, that is, the widths of the first sub-buried layer portion 311 at different positions are equal. In this way, the first sub-buried layer portion 311 and the second sub-buried layer portion 312 form an inverted "T"-shaped cross-section, so that the first sub-buried layer portion 311 close to the bottom of the gate structure 12 can not only shield the electric field in the middle of the gate structure 12, but also ensure the current conduction channel on both sides of the gate structure 12, thereby increasing the on-state current.

[0088] Optionally, Figure 5 FIG. 1 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present invention. Figure 5 As shown, the first buried layer 131 further includes a third sub-buried layer portion 313 .

[0089] The third sub-buried layer portion 313 is located on a side of the second sub-buried layer portion 312 away from the first sub-buried layer portion 311, and the third sub-buried layer portion 313 contacts the second sub-buried layer portion 312; the third sub-buried layer portion 313 has a fourth preset width d4, which is smaller than the third preset width d3.

[0090] Specifically, a third sub-buried layer portion 313 is disposed on a side of the second sub-buried layer portion 312 away from the first sub-buried layer portion 311, and the extension depth of the first buried layer 131 in the epitaxial layer 11 is extended, which can further enhance the shielding effect of the first buried layer 131 on the higher electric field around the gate structure 12, thereby protecting the gate oxide layer 121 in the gate structure 12 from being easily broken down, which is beneficial to improving the reliability of the semiconductor device. The fourth preset width d4 at different positions of the third sub-buried layer portion 313 is set to be smaller than the third preset width d3 of the second sub-buried layer portion 312, which can ensure the transmission channel of the conduction current, thereby increasing the on-state current of the semiconductor device. Exemplarily, the fourth preset width d4 at different positions of the third sub-buried layer portion 313 can be set to be equal, that is, the third sub-buried layer portion 313 is set to be rectangular or strip-shaped. See also Figure 5The cross-sectional shape of the first buried layer 131 formed by the first sub-buried layer portion 311, the second sub-buried layer portion 312 and the third sub-buried layer portion 313 is in a cross shape, which can play a good shielding role for the higher electric field around the gate structure 12, protect the gate oxide layer 121 from being easily broken down, improve the reliability of the semiconductor device, and ensure that the semiconductor device has sufficient on-state current transmission channel, thereby increasing the on-state current and ensuring that the performance of the semiconductor device is not affected.

[0091] Optionally, Figure 6 FIG. 1 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present invention. Figure 6 As shown, the gate structure includes two opposite side surfaces, and the semiconductor device further includes: a first doped region 14 located on at least one side of the gate structure 12 .

[0092] The second buried layer 132 includes a fourth sub-buried layer portion 321 and a fifth sub-buried layer portion 322 ; the fourth sub-buried layer portion 321 includes a second surface 3211 and a third surface 3212 perpendicular to each other, and the fifth sub-buried layer portion 322 includes a fourth surface 3221 and a fifth surface perpendicular to each other.

[0093] The second surface 3211 contacts the bottom of the first doped region 14, and the third surface 3212 contacts the second sub-buried layer portion 312 in a thickness direction perpendicular to the substrate 10; the fourth surface 3221 contacts the side of the first doped region 14, and the fifth surface contacts the fourth sub-buried layer portion 321; wherein the first doped region 14 has a second conductivity type.

[0094] Specifically, the first doping region 14 may be a heavily doped region. In this embodiment, the first conductivity type of the epitaxial layer 11 is still described as N-type, and the second conductivity type of the first doping region 14 is P-type. The first doping region 14 may be provided on one side of the gate structure 12 perpendicular to the thickness direction of the substrate 10, or may be provided on both sides of the gate structure 12 perpendicular to the thickness direction of the substrate 10, without limitation; illustratively, Figure 6It shows the situation that the first doped region 14 is provided on both sides of the gate structure 12 in the direction perpendicular to the thickness of the substrate 10. The cross-sectional shapes of the fourth sub-buried layer portion 321 and the fifth sub-buried layer portion 322 in the second buried layer 132 are both rectangular, and the fourth sub-buried layer portion 321 is provided in the same layer as the second sub-buried layer portion 312. Exemplarily, the third surface 3212 in the fourth sub-buried layer portion 321 may be in contact with the second sub-buried layer portion 312, or there may be a small gap between the fourth sub-buried layer portion 321 and the second sub-buried layer portion 312, which is not limited here. The fourth sub-buried layer portion 321 has a higher ion doping concentration, so that it can form a conductive current transmission channel with the second sub-buried layer portion 312, which is beneficial to increase the on-state current. The fifth surface of the fifth sub-buried layer portion 322 is in contact with part of the second surface 3211 of the fourth sub-buried layer portion 321, and the fourth surface 3221 of the fifth sub-buried layer portion 322 is in contact with the side of the first doped region 14. Among them, Figure 6 The fifth surface is not marked in the figure. That is to say, the fourth sub-buried layer portion 321 and the fifth sub-buried layer portion 322 form a semi-enclosed structure, and semi-enclose the bottom surface of the first doped region 14 and the side portion close to the gate structure 12. Since the conductivity type of the first doped region 14 is different from the conductivity type of the second buried layer 132, and the first doped region 14 and the second buried layer 132 are both heavily doped regions, the width of the depletion region is reduced, and therefore, the conduction effect of the freewheeling diode formed in the area where the first doped region 14 contacts the second buried layer 132 is good. And the fourth sub-buried layer portion 321 and the fifth sub-buried layer portion 322 are set to semi-enclose the first doped region 14, which can further increase the contact area between the second buried layer 132 and the first doped region 14, thereby increasing the conduction current of the freewheeling diode.

[0095] Optionally, Figure 7 FIG. 1 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present invention. Figure 7 As shown, the semiconductor device further includes: a second doped region 15 , a body region 16 , a dielectric layer 17 , a source electrode 18 , a passivation layer 19 and a drain electrode 20 .

[0096] The second doped region 15 has a first conductivity type and is located on the first surface 111 of the epitaxial layer 11; the body region 16 has a second conductivity type and is located on a side of the second doped region 15 away from the first surface 111; the dielectric layer 17 is located on a side of the epitaxial layer 11 away from the substrate 10, and the orthographic projection of the dielectric layer 17 on the substrate 10 covers the orthographic projection of the gate structure 12 on the substrate 10; the source 18 is located on a side of the dielectric layer 17 away from the epitaxial layer 11, and the orthographic projection of the source 18 on the substrate 10 completely overlaps with the orthographic projection of the substrate 10; the passivation layer 19 is located on a side of the source 18 away from the epitaxial layer 11, and the orthographic projection of the passivation layer 19 on the substrate 10 covers the orthographic projection of the first doped region 14 on the substrate 10; the drain 20 is located on a side of the substrate 10 away from the epitaxial layer 11.

[0097] Specifically, a second doping region 15 and a body region 16 are provided on both sides of the gate structure 12, wherein the conductivity type of the body region 16 is the same as the conductivity type of the first doping region 14, and the conductivity type of the second doping region 15 is different from the conductivity type of the body region 16. Exemplarily, in this embodiment, the conductivity type of the body region 16 may be P-type, and the second doping region 15 may be an N-type heavily doped region. The body region 16 contacts the first doping region 14 and is electrically connected to the source 18 through the first doping region 14. The second doping region 15, as an active region of the semiconductor device, contacts the body region 16 to transmit the conduction current. A dielectric layer 17 is provided on the surface of the gate structure 12, so that the dielectric layer 17 covers the gate structure 12 and insulates the gate structure 12 from the source 18. A drain 20 is formed on the side of the substrate 10 away from the epitaxial layer 11, that is, on the back side of the substrate 10, thereby obtaining a complete semiconductor device.

[0098] An embodiment of the present invention also provides a method for preparing a semiconductor device. Figure 8 is a schematic flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, Fig. 9 yes Figure 8 Schematic diagram of the cross-sectional structure corresponding to each step in the process. Figure 8 and Fig. 9 The semiconductor device manufacturing method specifically comprises the following steps:

[0099] S110 , providing a substrate 10 , wherein the substrate 10 has a first conductivity type.

[0100] Exemplarily, the substrate may be an N-type heavily doped silicon carbide substrate.

[0101] S120 , forming an epitaxial layer 11 on the surface of the substrate 10 ; the epitaxial layer 11 has a first conductivity type, and the epitaxial layer 11 includes a first surface 111 .

[0102] Exemplarily, an N-type lightly doped silicon carbide epitaxial layer is formed by epitaxial growth on the surface of the substrate, and a surface of the epitaxial layer away from the substrate is the first surface.

[0103] S130. Form a buried layer structure 13 in the epitaxial layer 11; the buried layer structure 13 includes a first buried layer 131 and a second buried layer 132, the second buried layer 132 has a first conductivity type, the first buried layer 131 has a second conductivity type, and the ion concentration of the second buried layer 132 is greater than the ion concentration of the epitaxial layer 11, and the second buried layer 132 is configured to reduce the width of the depletion region between the second buried layer 132 and the first buried layer 131.

[0104] Exemplarily, ion implantation is performed from the first surface of the epitaxial layer to the inside using corresponding conductive ions, thereby forming a first buried layer and a second buried layer with a high ion doping concentration in the epitaxial layer. By providing the first buried layer and the epitaxial layer to form a depletion region around the gate structure, the high electric field around the gate structure can be shielded, the gate oxide layer is protected from being easily broken down, and the reliability of the semiconductor device is improved. While shielding the high electric field around the gate structure, by providing the second buried layer with a high ion doping concentration, the width of the formed depletion region is reduced, which is conducive to ensuring the current conduction channel on both sides of the gate structure and increasing the on-state current of the semiconductor device.

[0105] S140 , forming a gate trench 112 on the first surface 111 .

[0106] Exemplarily, etching is performed from the first surface of the epitaxial layer toward the inside to form a gate trench.

[0107] S150 , forming a gate structure 12 inside the gate trench 112 .

[0108] Exemplarily, a silicon oxide material is deposited inside the gate trench to form a gate oxide layer 121 , and a polysilicon material is filled inside the gate oxide layer to form a gate 122 .

[0109] In the semiconductor device preparation method provided by the embodiment of the present invention, by setting the first buried layer and the second buried layer with ion doping concentration higher than the epitaxial layer in the epitaxial layer, a depletion region can be formed by the first buried layer and the epitaxial layer, and the higher electric field in the middle of the gate structure can be shielded, which is beneficial to improving the reliability of the semiconductor device; at the same time, by setting the second buried layer, a depletion region with a smaller width is formed with the first buried layer, which ensures a sufficient conduction current transmission channel and can also increase the on-state current of the semiconductor device.

[0110] Optionally, based on the above embodiment, the first buried layer includes a first sub-buried layer portion, a second sub-buried layer portion and a third sub-buried layer portion, and the second buried layer includes a fourth sub-buried layer portion and a fifth sub-buried layer portion; Fig.10 is a specific flow chart of step S130 in a method for preparing a semiconductor device provided by an embodiment of the present invention, Fig.11 is a schematic diagram of the cross-sectional structure corresponding to each step in step S130. Fig.10 and Fig.11 The step S130 of forming a buried layer structure in the epitaxial layer specifically includes the following steps:

[0111] S131 , perform ion implantation on the epitaxial layer 11 to form a third buried sub-layer portion 313 .

[0112] Specifically, a first ion implantation is performed using P-type conductive ions at a middle position of a surface of the epitaxial layer away from the substrate, and the ion implantation depth is relatively deep, so as to form a third sub-buried layer portion.

[0113] S132, ion implantation is performed again on the epitaxial layer 11 to form a second sub-buried layer portion 312 and a fourth sub-buried layer portion 321; wherein the fourth sub-buried layer portion 321 is in contact with the second sub-buried layer portion 312, and the third sub-buried layer portion 313 is in contact with the second sub-buried layer portion 312 in the thickness direction of the substrate 10.

[0114] Exemplarily, a second ion implantation is performed using P-type conductive ions in the middle of the surface of the epitaxial layer away from the substrate side, and the ion implantation depth is shallow, to form a second sub-buried layer portion; and N-type conductive ions are used to implant ions in positions other than the middle of the surface of the epitaxial layer away from the substrate side to form a fourth sub-buried layer portion.

[0115] S133 , forming an epitaxial layer 11 again on the side of the second sub-buried layer portion 312 and the fourth sub-buried layer portion 321 away from the substrate 10 .

[0116] S134 , perform ion implantation again on the epitaxial layer 11 to form a first sub-buried layer portion 311 and a fifth sub-buried layer portion 322 ; wherein the first sub-buried layer portion 311 is in contact with the second sub-buried layer portion 312 , and the fifth sub-buried layer portion 322 is in contact with the fourth sub-buried layer portion 321 .

[0117] Exemplarily, P-type ion implantation is performed again in the middle of the surface of the newly formed epitaxial layer away from the substrate side to form a first sub-buried layer portion; and N-type ion implantation is performed again in the position other than the middle of the surface to form a fifth sub-buried layer portion.

[0118] S135 , forming an epitaxial layer 11 again on the side of the first sub-buried layer portion 311 and the fifth sub-buried layer portion 322 away from the substrate 10 .

[0119] Illustratively, after the buried layer structure is prepared, an epitaxial layer is formed again on the surfaces of the first sub-buried layer portion and the fifth sub-buried layer portion, and the surface thereof away from the substrate is the first surface.

[0120] Optionally, Fig.12 is a schematic diagram of the cross-sectional structure corresponding to the step before forming the gate trench, Fig.13 FIG. 1 is a schematic cross-sectional structure diagram corresponding to the step after forming the gate trench. Fig.12 and Fig.13 , before forming a gate trench in the epitaxial layer, further comprising:

[0121] Ion implantation is performed on the first surface 111 to form a body region 16 and a second doping region 15 ; wherein the second doping region 15 is located on the first surface 111 of the epitaxial layer 11 , and the body region 16 is located on a side of the second doping region 15 away from the first surface 111 .

[0122] For example, see Fig.12 , P-type conductive ions are implanted into the first surface at a relatively deep implantation depth to form a body region, and N-type conductive ions are implanted into the first surface at a relatively shallow implantation depth to form a second doped region.

[0123] After forming a gate trench in the epitaxial layer, the process further includes:

[0124] Ion implantation is performed on the first surface 111 to form a first doped region 14; the first doped region 14 is located on at least one side of the gate trench 112;

[0125] Specifically, P-type conductive ions are implanted into the first surface, and the implantation depth is relatively deep, so as to form a first doped region on at least one side of the gate trench. Fig.13 The figure shows a situation where the first doping regions are formed on both sides of the gate trench.

[0126] Optionally, Fig.14 is a schematic flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Fig.15 is a schematic diagram of the cross-sectional structure corresponding to step S160-step S190. Fig.14 and Fig.15 , the semiconductor device manufacturing method further includes the following steps:

[0127] S160 , forming a dielectric layer 17 on a side of the epitaxial layer 11 away from the substrate 10 ; the orthographic projection of the dielectric layer 17 on the substrate 10 covers the orthographic projection of the gate structure 12 on the substrate 10 .

[0128] Exemplarily, an insulating material is deposited on the first surface of the epitaxial layer to form a dielectric layer, so that the dielectric layer covers the gate structure and exposes the first doped region, so that the first doped region achieves ohmic contact with the source.

[0129] S170 , forming a source electrode 18 on a side of the dielectric layer 17 away from the epitaxial layer 11 ; the orthographic projection of the source electrode 18 on the substrate 10 completely overlaps with the orthographic projection of the substrate 10 .

[0130] Exemplarily, a metal material is deposited on the surface of the dielectric layer to form the source electrode.

[0131] S180 , forming a passivation layer 19 on a side of the source 18 away from the epitaxial layer 11 ; the orthographic projection of the passivation layer 19 on the substrate 10 covers the orthographic projection of the first doped region 14 on the substrate 10 .

[0132] Exemplarily, silicon nitride material is deposited on the surface of the source, the silicon nitride 191 at the position corresponding to the first doped region is etched to retain, and a polyimide layer 192 is formed on the surface of the silicon nitride to wrap the silicon nitride to form a passivation layer.

[0133] S190 , forming a drain 20 on a side of the substrate 10 away from the epitaxial layer 11 .

[0134] Exemplarily, a metal material is deposited on the back side of the substrate to form a drain.

[0135] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type and being located on a surface of the substrate, the epitaxial layer comprising a first surface, the first surface being provided with a gate trench; A gate structure, located inside the gate trench; A buried layer structure, the buried layer structure comprising a first buried layer and a second buried layer, the second buried layer having the first conductivity type, the first buried layer having the second conductivity type, the ion concentration of the second buried layer being greater than the ion concentration of the epitaxial layer, and the second buried layer being configured to reduce a depletion region width between the second buried layer and the first buried layer; The first buried layer includes a first sub-buried layer portion and a second sub-buried layer portion, the first sub-buried layer portion is located at a side of the bottom of the gate structure close to the substrate, the second sub-buried layer portion is located at a side of the first sub-buried layer portion away from the gate structure, and the second sub-buried layer portion is in contact with the first sub-buried layer portion; A width of the first sub-buried layer portion is smaller than a width of the second sub-buried layer portion.

2. The semiconductor device according to claim 1, wherein: In a direction perpendicular to the thickness of the substrate, the second buried layer is disposed on at least one side of the second sub-buried layer portion.

3. The semiconductor device according to claim 2, characterized in that The first sub-buried layer portion has a first preset width on a side close to the gate structure, and has a second preset width on a side away from the gate structure, and the width of the first sub-buried layer portion is between the first preset width and the second preset width; the second sub-buried layer portion has a third preset width; The first preset width is smaller than the third preset width, and the second preset width is smaller than or equal to the third preset width.

4. The semiconductor device according to claim 3, characterized in that The first preset width is smaller than the second preset width, and the width of the first sub-buried layer portion gradually increases from the first preset width to the second preset width.

5. The semiconductor device according to claim 3, characterized in that The second preset width is equal to the first preset width, and both the first preset width and the second preset width are smaller than the third preset width.

6. The semiconductor device according to claim 4 or 5, characterized in that: The first buried layer further includes a third sub-buried layer portion; The third sub-buried layer portion is located at a side of the second sub-buried layer portion away from the first sub-buried layer portion, and the third sub-buried layer portion is in contact with the second sub-buried layer portion; The third sub-buried layer portion has a fourth preset width, and the fourth preset width is smaller than the third preset width.

7. The semiconductor device according to claim 2, characterized in that The gate structure includes two opposite sides, and the semiconductor device further includes: a first doped region located on at least one side of the gate structure; The second buried layer includes a fourth sub-buried layer portion and a fifth sub-buried layer portion; the fourth sub-buried layer portion includes a second surface and a third surface that are perpendicular to each other, and the fifth sub-buried layer portion includes a fourth surface and a fifth surface that are perpendicular to each other; The second surface contacts the bottom of the first doped region, and the third surface contacts the second sub-buried layer portion in a direction perpendicular to the thickness of the substrate; The fourth surface contacts the side surface of the first doped region, and the fifth surface contacts the fourth sub-buried layer portion; Wherein, the first doped region has the second conductivity type.

8. The semiconductor device according to claim 7, characterized in that Also includes: a second doped region having the first conductivity type and located on the first surface of the epitaxial layer; a body region having the second conductivity type and located on a side of the second doped region away from the first surface; A dielectric layer, located on a side of the epitaxial layer away from the substrate, wherein an orthographic projection of the dielectric layer on the substrate covers an orthographic projection of the gate structure on the substrate; A source electrode is located on a side of the dielectric layer away from the epitaxial layer, and an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate; A passivation layer, located on a side of the source electrode away from the epitaxial layer, and an orthographic projection of the passivation layer on the substrate covers an orthographic projection of the first doped region on the substrate; The drain is located at a side of the substrate away from the epitaxial layer.

9. A method for preparing a semiconductor device, for preparing the semiconductor device according to any one of claims 1 to 8, characterized in that: The semiconductor device preparation method comprises: Providing a substrate; the substrate has a first conductivity type; forming an epitaxial layer on the surface of the substrate; the epitaxial layer has the first conductivity type, and the epitaxial layer includes a first surface; forming a buried layer structure in the epitaxial layer; the buried layer structure comprises a first buried layer and a second buried layer, the second buried layer has the first conductivity type, the first buried layer has the second conductivity type, the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer, and the second buried layer is configured to reduce the width of the depletion region between the second buried layer and the first buried layer; forming a gate trench on the first surface; A gate structure is formed inside the gate trench.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The first buried layer includes a first sub-buried layer portion, a second sub-buried layer portion and a third sub-buried layer portion, and the second buried layer includes a fourth sub-buried layer portion and a fifth sub-buried layer portion; The forming of a buried layer structure in the epitaxial layer comprises: Performing ion implantation on the epitaxial layer to form the third buried sub-layer portion; Performing ion implantation again on the epitaxial layer to form the second sub-buried layer portion and the fourth sub-buried layer portion; wherein the fourth sub-buried layer portion contacts the second sub-buried layer portion in a direction perpendicular to the substrate, and the third sub-buried layer portion contacts the second sub-buried layer portion in a thickness direction of the substrate; forming the epitaxial layer again on a side of the second sub-buried layer portion and the fourth sub-buried layer portion away from the substrate; Performing ion implantation again on the epitaxial layer to form the first sub-buried layer portion and the fifth sub-buried layer portion; wherein the first sub-buried layer portion is in contact with the second sub-buried layer portion, and the fifth sub-buried layer portion is in contact with the fourth sub-buried layer portion; forming the epitaxial layer again on a side of the first sub-buried layer portion and the fifth sub-buried layer portion away from the substrate; Before forming a gate trench in the epitaxial layer, the method further includes: Performing ion implantation on the first surface to form a body region and a second doped region; wherein the second doped region is located on the first surface of the epitaxial layer, and the body region is located on a side of the second doped region away from the first surface; After forming a gate trench in the epitaxial layer, the method further includes: Performing ion implantation on the first surface to form a first doped region; the first doped region is located on at least one side of the gate trench; The semiconductor device manufacturing method further includes: forming a dielectric layer on a side of the epitaxial layer away from the substrate; the orthographic projection of the dielectric layer on the substrate covers the orthographic projection of the gate structure on the substrate; A source electrode is formed on a side of the dielectric layer away from the epitaxial layer; an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate; A passivation layer is formed on a side of the source electrode away from the epitaxial layer; the orthographic projection of the passivation layer on the substrate covers the orthographic projection of the first doped region on the substrate; A drain is formed on a side of the substrate away from the epitaxial layer.

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