Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for preparing the same. The semiconductor device comprises: a substrate, an epitaxial layer, a gate structure, a first doped region and a buried layer structure; the epitaxial layer has a first conductivity type and is located on the surface of the substrate; the first doped region has a second conductivity type; the buried layer structure is located on the side of the first doped region close to the substrate; the buried layer structure comprises at least two buried layers arranged in a stacked manner, each buried layer comprising a first buried layer and a second buried layer; the first buried layer has the second conductivity type, and the second buried layer has the first conductivity type; the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer; wherein the widths of at least two first buried layers are different; along the direction from the epitaxial layer to the substrate, the widths of each first buried layer decrease in sequence. The technical solution of the embodiment of the present invention can shield the electric field around the gate structure, protect the gate oxide layer from being easily broken down, improve the reliability of the device, and ensure the on-state current of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Silicon carbide (SiC) trench gate metal oxide semiconductor field effect transistor (MOSFET) has the advantages of high current density, small cell spacing and fast switching speed, and has become the main research object of the new generation of SiC MOSFET.

[0003] In a SiC trench gate MOSFET, the electric field at the bottom of the trench and the corner of the trench is relatively high, resulting in a relatively high electric field on the gate oxide layer of the trench gate structure, which makes the gate oxide layer easily broken down. In order to protect the gate oxide layer from being broken down and improve the reliability of the MOSFET, the prior art proposes to use a double trench structure or an asymmetric structure to achieve the above effect. However, the use of an additional double source trench structure or an asymmetric structure will increase the process complexity or affect the on-state current of the device. Summary of the invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, so as to solve the problem that a gate oxide layer of a SiC trench gate structure MOSFET is easily broken down, resulting in low device reliability, and ensure the on-state current of the MOSFET.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] a substrate having a first conductivity type;

[0007] an epitaxial layer having the first conductivity type and being located on a surface of the substrate, the epitaxial layer comprising a first surface, the first surface being provided with a gate trench;

[0008] A gate structure, located inside the gate trench;

[0009] A first doped region, located on at least one side of the gate structure, the first doped region having a second conductivity type;

[0010] a buried layer structure, located on a side of the first doped region close to the substrate; the buried layer structure comprises at least two buried layer portions arranged in a stacked manner, each of the buried layer portions comprises a first buried layer and a second buried layer, the second buried layer being located on a side of the first buried layer; the first buried layer has the second conductivity type, the second buried layer has the first conductivity type, and the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer;

[0011] Among them, at least two layers of the first buried layers have different widths; and along the direction from the epitaxial layer to the substrate, the widths of the first buried layers decrease in sequence.

[0012] Optionally, a side of the first buried layer close to the first doped region has a first preset width, and a side of the first buried layer away from the first doped region has a second preset width;

[0013] In two adjacent first buried layers, the second preset width close to the first doping region is greater than the first preset width far from the first doping region.

[0014] Optionally, in the first buried layer, the first preset width is greater than the second preset width;

[0015] Alternatively, in the first buried layer, the first preset width is equal to the second preset width.

[0016] Optionally, the stacked first buried layers are distributed axially symmetrically.

[0017] Optionally, the number of the first buried layers ranges from 2 to 4 layers, and the thickness of each of the first buried layers ranges from 0.3 to 1 μm.

[0018] Optionally, the thickness of the second buried layer is equal to the thickness of the first buried layer in the same layer;

[0019] In two adjacent buried layer portions, the sum of the first preset width away from the first doping region and the width of the second buried layer is equal to the second preset width close to the first doping region.

[0020] Optionally, the semiconductor device further includes:

[0021] a second doped region, located on the first surface of the epitaxial layer;

[0022] a body region, located at a side of the second doped region away from the first surface;

[0023] A dielectric layer, located on a side of the epitaxial layer away from the substrate, wherein an orthographic projection of the dielectric layer on the substrate covers an orthographic projection of the gate structure on the substrate;

[0024] A source electrode is located on a side of the dielectric layer away from the epitaxial layer, and an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate;

[0025] A passivation layer, located on a side of the source electrode away from the epitaxial layer, wherein an orthographic projection of the passivation layer on the substrate covers at least a portion of an orthographic projection of the first doped region on the substrate;

[0026] The drain is located at a side of the substrate away from the epitaxial layer.

[0027] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0028] Providing a substrate; the substrate has a first conductivity type;

[0029] forming an epitaxial layer on the surface of the substrate; the epitaxial layer has the first conductivity type, and the epitaxial layer includes a first surface;

[0030] A buried layer structure is formed in the epitaxial layer; the buried layer structure comprises at least two buried layer portions arranged in a stacked manner, each buried layer portion comprises a first buried layer and a second buried layer, and the second buried layer is located on a side of the first buried layer;

[0031] Performing ion implantation on the first surface to form a first doped region; the first doped region is located on a side of the buried layer structure away from the substrate; the first doped region has a second conductivity type;

[0032] forming a gate trench on the first surface;

[0033] forming a gate structure inside the gate trench;

[0034] Among them, the first buried layer has the second conductivity type, and the second buried layer has the first conductivity type; the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer; the widths of at least two layers of the first buried layers are different; along the direction from the epitaxial layer to the substrate, the widths of each first buried layer decrease successively.

[0035] Optionally, forming a buried layer structure in the epitaxial layer includes:

[0036] Performing ion implantation on the epitaxial layer to form a buried layer;

[0037] forming the epitaxial layer again on a side of the buried layer away from the substrate;

[0038] The steps of ion implantation and forming the epitaxial layer are repeatedly performed until the buried layer structure is formed.

[0039] Optionally, before the ion implantation into the first surface to form the first doped region, the method further comprises:

[0040] Performing ion implantation on the first surface to form a body region and a second doped region; wherein the second doped region is located on the first surface of the epitaxial layer, and the body region is located on a side of the second doped region away from the first surface;

[0041] The semiconductor device manufacturing method further includes:

[0042] forming a dielectric layer on a side of the epitaxial layer away from the substrate; the orthographic projection of the dielectric layer on the substrate covers the orthographic projection of the gate structure on the substrate;

[0043] A source electrode is formed on a side of the dielectric layer away from the epitaxial layer; an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate;

[0044] A passivation layer is formed on a side of the source electrode away from the epitaxial layer; the orthographic projection of the passivation layer on the substrate covers at least a portion of the orthographic projection of the first doped region on the substrate;

[0045] A drain is formed on a side of the substrate away from the epitaxial layer.

[0046] The semiconductor device provided by the embodiment of the present invention has an epitaxial layer with a first conductivity type, a first doping region is arranged on at least one side of the gate structure, and a buried layer structure is arranged on the side of the first doping region close to the substrate. The buried layer structure includes at least two buried layer parts arranged in layers, each buried layer part includes a first buried layer and a second buried layer, the first buried layer has the second conductivity type, the second buried layer has the first conductivity type, and the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer. Along the direction from the epitaxial layer to the substrate, the width of each first buried layer decreases successively, forming a stepped super junction structure with a deeper depth extending into the epitaxial layer, thereby effectively shielding the higher electric field at the bottom and sidewall of the gate structure, protecting the gate oxide layer from being easily broken down; and providing a shorter path for the current flowing upward from the bottom of the buried layer structure, thereby providing a current conduction channel, which is conducive to increasing the on-state current of the semiconductor device. At the same time, a second buried layer is arranged on the side of the first buried layer, and the doping concentration of the second buried layer is higher than that of the epitaxial layer, which can effectively reduce the width of the depletion region formed by the second buried layer and the first buried layer, which is conducive to reducing the on-resistance and increasing the on-state current of the semiconductor device.

[0047] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1is a schematic cross-sectional structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0050] Figure 2 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0051] Figure 3 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0052] Figure 4 is a schematic cross-sectional structural diagram of another semiconductor device provided according to an embodiment of the present invention;

[0053] Figure 5 is a schematic flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0054] Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure corresponding to each step in the figure;

[0055] Figure 7 is a schematic diagram of a specific flow chart of step S130 in a method for preparing a semiconductor device according to an embodiment of the present invention;

[0056] Figure 8 is a schematic cross-sectional structural diagram corresponding to each specific step in step S130 provided according to an embodiment of the present invention;

[0057] Fig. 9 is a schematic cross-sectional structural diagram corresponding to the step before forming the first doping region;

[0058] Fig.10 is a schematic flow chart of another method for preparing a semiconductor device according to an embodiment of the present invention;

[0059] Fig.11 It is a schematic diagram of the cross-sectional structure corresponding to step S170 to step S200. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] An embodiment of the present invention provides a semiconductor device. Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a substrate 100 , an epitaxial layer 200 , a gate structure 300 , a first doped region 400 and a buried layer structure 500 .

[0063] The substrate 100 has a first conductivity type; the epitaxial layer 200 has a first conductivity type and is located on the surface of the substrate 100, the epitaxial layer 200 includes a first surface 201, and the first surface 201 is provided with a gate trench; the gate structure 300 is located inside the gate trench; the first doped region 400 is located on at least one side of the gate structure 300, and the first doped region 400 has a second conductivity type; the buried structure 500 is located on a side of the first doped region 400 close to the substrate 100; the buried structure 500 includes at least two layers of buried portions 510 arranged in a stacked manner, each layer of the buried portion 510 includes a first buried layer 511 and a second buried layer 512, and the second buried layer 512 is located on the side of the first buried layer 511; the first buried layer 511 has the second conductivity type, the second buried layer 512 has the first conductivity type, and the ion concentration of the second buried layer 512 is greater than the ion concentration of the epitaxial layer 200.

[0064] Among them, at least two first buried layers 511 have different widths; along the direction from the epitaxial layer 200 to the substrate 100 , the widths of the first buried layers 511 decrease successively.

[0065] Specifically, the substrate 100 can be a silicon carbide substrate with a high ion doping concentration. A silicon carbide film layer with a low ion doping concentration is grown on the surface of the substrate 100 to form an epitaxial layer 200. Exemplarily, the first conductivity type can be N-type or P-type, which is not limited here. In the embodiment of the present invention, the structure of the semiconductor device is described by taking the first conductivity type as N-type and the second conductivity type as P-type as an example, then the substrate 100 and the epitaxial layer 200 are both film layers with the first conductivity type. The surface of the epitaxial layer 200 away from the side of the substrate 100 is taken as the first surface 201, and a gate trench is extended from the first surface 201 to the inside of the epitaxial layer 200, and the gate trench is filled with a gate structure 300. It should be noted that the gate trench is a process structure generated during the preparation of the semiconductor device, therefore, Figure 1 The gate trench is not marked. The gate structure 300 includes a gate oxide layer 301 covering the bottom and sidewalls of the gate trench and a gate 302 disposed on the side of the gate oxide layer 301 away from the gate trench, and the thickness of the gate oxide layer 301 at the bottom of the gate trench is greater than the thickness of the gate oxide layer 301 at the sidewall of the gate trench, thereby enhancing the breakdown resistance of the gate oxide layer 301 in the gate trench, which is beneficial to improving the reliability of the semiconductor device.

[0066] On at least one side of the gate structure 300, a first doped region 400 is provided extending from the first surface 201 to the inside of the epitaxial layer 200 to electrically contact the source of the semiconductor device. Figure 1 The case where the first doping region 400 is provided on both sides of the gate structure 300 is shown. The first doping region 400 has a second conductivity type. Exemplarily, in the embodiments of the present invention, the second conductivity type of the first doping region 400 is P-type as an example, and the first doping region 400 is a region with a higher concentration of P-type ion doping, and the structure of the semiconductor device is described. A buried layer structure 500 is also provided in the epitaxial layer 200, and the buried layer structure 500 is provided on the side of the bottom of the first doping region 400 close to the substrate 100, and the buried layer structure 500 is in contact with the bottom of the first doping region 400. The buried layer structure 500 includes at least two layers of buried layer portions 510 arranged in a stacked manner, and a first buried layer 511 and a second buried layer 512 are included in one buried layer portion 510, wherein the first buried layer 511 has a second conductivity type, and the second buried layer 512 has a first conductivity type, that is, the first buried layer 511 is P-type doped, and the second buried layer 512 is N-type doped.

[0067] At least two first buried layers 511 are stacked and arranged along the direction from the epitaxial layer 200 to the substrate 100, and the width of each first buried layer 511 is gradually reduced, so that the first doped region 400 and the first buried layer 511 form a step-shaped super junction structure extending deep into the epitaxial layer 200, and the first buried layer 511 and the epitaxial layer 200 form a depletion region, which is conducive to shielding the high electric field at the bottom and sidewall of the gate structure 300, thereby protecting the gate oxide layer 301 in the gate structure 300 from being easily broken down, and improving the reliability of the semiconductor device. In addition, a second buried layer 512 is arranged on the side of the first buried layer 511, and the ion concentration of the second buried layer 512 is greater than the ion concentration of the epitaxial layer 200, reducing the contact area between the first buried layer 511 and the epitaxial layer 200, thereby reducing the width of the depletion region, so that the second buried layer 512 and the first buried layer 511 form a depletion region with a smaller width, reducing the on-resistance, thereby providing a conduction current transmission channel for the semiconductor device, and effectively increasing the on-state current of the semiconductor device. At the same time, compared with extending the first doped region 400 in a direction close to the substrate 100 with the same and wider width, the embodiment of the present invention provides a shorter path for the current flowing out of the bottom of the buried structure 500 to flow upward by setting a stepped buried structure 500 from the bottom of the first doped region 400 in a direction close to the substrate 100, thereby ensuring the on-state current of the semiconductor device.

[0068] The semiconductor device provided by the embodiment of the present invention has an epitaxial layer with a first conductivity type, a first doping region is arranged on at least one side of the gate structure, and a buried layer structure is arranged on the side of the first doping region close to the substrate. The buried layer structure includes at least two buried layer parts arranged in layers, each buried layer part includes a first buried layer and a second buried layer, the first buried layer has the second conductivity type, the second buried layer has the first conductivity type, and the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer. Along the direction from the epitaxial layer to the substrate, the width of each first buried layer decreases successively, forming a stepped super junction structure with a deeper depth extending into the epitaxial layer, thereby effectively shielding the higher electric field at the bottom and sidewall of the gate structure, protecting the gate oxide layer from being easily broken down; and providing a shorter path for the current flowing upward from the bottom of the buried layer structure, thereby providing a current conduction channel, which is conducive to increasing the on-state current of the semiconductor device. At the same time, a second buried layer is arranged on the side of the first buried layer, and the doping concentration of the second buried layer is higher than that of the epitaxial layer, which can effectively reduce the width of the depletion region formed by the second buried layer and the first buried layer, which is conducive to reducing the on-resistance and increasing the on-state current of the semiconductor device.

[0069] The width setting of the first buried layer 511 may include various situations. The following embodiments will specifically describe the possible situations of the width of the first buried layer 511.

[0070] Optionally, Figure 2FIG. 1 is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention. Figure 1 and Figure 2 The side of the first buried layer 511 close to the first doping region 400 has a first preset width d1, and the side of the first buried layer 511 away from the first doping region 400 has a second preset width d2.

[0071] In two adjacent first buried layers 511 , the second preset width d2 close to the first doping region 400 is greater than the first preset width d1 far from the first doping region 400 .

[0072] Specifically, since the greater the width of the first buried layer 511 close to the first doping region 400, the better the shielding effect on the higher electric field at the bottom and sidewall of the gate structure 300, the width of the first buried layer 511 is set to gradually decrease along the direction from close to the first doping region 400 to far away from the first doping region 400, which is beneficial to improving the shielding effect of the buried layer structure 500 on the higher electric field around the gate structure 300. In the same buried layer portion 510, the width of the first buried layer 511 on the side close to the first doping region 400 can be set to the first preset width d1, and the width of the first buried layer 511 on the side away from the first doping region 400 can be set to the second preset width d2. Exemplarily, the first preset width d1 is greater than the second preset width d2; or, the first preset width d1 is equal to the second preset width d2. See Figure 2 , Figure 2 The figure shows that the first preset width d1 of the first buried layer 511 is greater than the second preset width d2, that is, the cross-sectional shape of the first buried layer 511 in each buried layer portion 510 is an inverted trapezoid, and in a first buried layer 511, its width gradually decreases from close to the first doping region 400 to far away from the first doping region 400. Figure 1 , Figure 1 It shows the case where the first preset width d1 of the first buried layer 511 is equal to the second preset width d2, that is, the cross-sectional shape of the first buried layer 511 in each buried layer portion 510 is rectangular, then in one layer of the first buried layer 511, the width is equal along the direction from close to the first doping region 400 to away from the first doping region 400.

[0073] For the first buried layer 511 in the two adjacent buried layer portions 510, the second preset width d2 of the first buried layer 511 close to the first doping region 400 is set to be greater than the first preset width d1 of the first buried layer 511 far from the first doping region 400, that is, along the direction from close to the first doping region 400 to far from the first doping region 400, each layer of the first buried layer 511 forms a step-like structure. In this way, the relationship between the shielding effect on the higher electric field around the gate structure 300 and the on-state current of the semiconductor device can be effectively balanced, so that the higher electric field around the gate structure 300 can be well shielded, and the gate oxide layer 301 can be protected from being easily broken down. At the same time, a shorter transmission path for the current flowing out of the bottom of the buried structure 500 can be provided, so as to ensure that the on-state current of the semiconductor device has less impact, so that the semiconductor device has good electrical performance.

[0074] Optionally, Figure 3 FIG. 1 is a cross-sectional structural diagram of another semiconductor device provided by an embodiment of the present invention. Figure 1 and Figure 3 The stacked first buried layers 511 are distributed axially symmetrically.

[0075] For example, see Figure 3 , each first buried layer 511 stacked in a step-like manner may form a step only on one side, while the other side of each first buried layer 511 is flush. Alternatively, see Figure 1 The first buried layers 511 stacked in a step-like arrangement may also form steps on both sides, that is, the first buried layers 511 are distributed in an axisymmetric manner. Figure 1 and Figure 3 The two arrangements of the first buried layers 511 shown can both achieve effective shielding of the higher electric field at the bottom and side walls of the gate structure 300. At the same time, by setting a second buried layer 512 on the side of each first buried layer 511, the width of the depletion region formed can also be effectively reduced, providing a current conduction channel for the semiconductor device and increasing the on-state current of the semiconductor device.

[0076] Optionally, based on the above embodiments, continue to refer to Figure 1 The number of the first buried layers 511 ranges from 2 to 4 layers, and the thickness of each first buried layer 511 ranges from 0.3 to 1 μm.

[0077] Specifically, according to the general thickness of the semiconductor device, the number of first buried layers 511 that can be provided is approximately 2 to 4 layers. Figure 1The buried layer structure 500 includes two buried layer portions 510. The number of first buried layers 511 can be set according to the actual needs of the semiconductor device and is not limited here. If only one first buried layer 511 is provided or the thickness of each first buried layer 511 is too small, the shielding effect of the higher electric field around the gate structure 300 may be insufficient; if too many first buried layers 511 are provided or the thickness of each first buried layer 511 is too large, the thickness of the semiconductor device may not be sufficient to arrange too many first buried layers 511.

[0078] Optionally, based on the above embodiments, continue to refer to Figure 1 , the thickness of the second buried layer 512 is equal to the thickness of the first buried layer 511 of the same layer; in two adjacent buried layer portions 510, the sum of the first preset width d1 away from the first doping region 400 and the width of the second buried layer 512 is equal to the second preset width d2 close to the first doping region 400.

[0079] For example, in each buried layer portion 510, the thickness of the second buried layer 512 is set equal to the thickness of the first buried layer 511, so that the second buried layer 512 completely surrounds the side of the first buried layer 511, increases the contact area between the second buried layer 512 and the first buried layer 511, reduces the depletion region, thereby increasing the on-current and improving the performance of the semiconductor device. The second preset width d2 close to the first doping region 400 is set to be equal to the sum of the first preset width d1 away from the first doping region 400 and the width of the second buried layer 512, which can simplify the preparation process to a certain extent.

[0080] Optionally, Figure 4 FIG. 1 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present invention. Figure 4 As shown, the semiconductor device further includes: a second doped region 600 , a body region 700 , a dielectric layer 800 , a source electrode 900 , a passivation layer 110 and a drain electrode 120 .

[0081] The second doped region 600 is located on the first surface 201 of the epitaxial layer 200; the body region 700 is located on the side of the second doped region 600 away from the first surface 201; the dielectric layer 800 is located on the side of the epitaxial layer 200 away from the substrate 100, and the orthographic projection of the dielectric layer 800 on the substrate 100 covers the orthographic projection of the gate structure 300 on the substrate 10; the source 900 is located on the side of the dielectric layer 800 away from the epitaxial layer 200, and the orthographic projection of the source 900 on the substrate 100 completely overlaps with the orthographic projection of the substrate 100; the passivation layer 110 is located on the side of the source 900 away from the epitaxial layer 200, and the orthographic projection of the passivation layer 110 on the substrate 100 covers the orthographic projection of the first doped region 400 on the substrate 100; the drain 120 is located on the side of the substrate 100 away from the epitaxial layer 200.

[0082] Specifically, a second doping region 600 and a body region 700 are provided on both sides of the gate structure 300, wherein the conductivity type of the body region 700 is the same as the conductivity type of the first doping region 400, and the conductivity type of the second doping region 600 is different from the conductivity type of the body region 700. Exemplarily, in this embodiment, the conductivity type of the body region 700 may be a P-type, and the second doping region 600 may be an N-type heavily doped region. The body region 700 contacts the first doping region 400 and is electrically connected to the source 900 through the first doping region 400. The second doping region 600, as an active region of the semiconductor device, contacts the body region 700 to transmit the conduction current. A dielectric layer 800 is provided on the surface of the gate structure 300, so that the dielectric layer 800 covers the gate structure 300 and insulates the gate structure 300 from the source 900. A drain 120 is formed on the side of the substrate 100 away from the epitaxial layer 200, that is, on the back side of the substrate 100, thereby obtaining a complete semiconductor device.

[0083] An embodiment of the present invention also provides a method for preparing a semiconductor device. Figure 5 is a schematic flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure corresponding to each step in the process. Figure 5 and Figure 6 The semiconductor device manufacturing method specifically comprises the following steps:

[0084] S110 , providing a substrate 100 ; the substrate 100 has a first conductivity type.

[0085] Exemplarily, the substrate may be an N-type heavily doped silicon carbide substrate.

[0086] S120 , forming an epitaxial layer 200 on the surface of the substrate 100 ; the epitaxial layer 200 has a first conductivity type, and the epitaxial layer 200 includes a first surface 201 .

[0087] Exemplarily, an N-type lightly doped silicon carbide epitaxial layer is formed by epitaxial growth on the surface of the substrate, and a surface of the epitaxial layer away from the substrate is the first surface.

[0088] S130 , forming a buried layer structure 500 in the epitaxial layer 200 ; the buried layer structure 500 includes at least two buried layer portions 510 arranged in a stacked manner, each buried layer portion 510 includes a first buried layer 511 and a second buried layer 512 , and the second buried layer 512 is located on the side of the first buried layer 511 .

[0089] Specifically, ion implantation is performed from the epitaxial layer to the inside using corresponding conductive ions, thereby forming at least two buried layer portions including a first buried layer and a second buried layer in a stacked arrangement in the epitaxial layer, thereby obtaining a buried layer structure. Exemplarily, ion implantation is performed on the epitaxial layer using P-type conductive ions to form the first buried layer in each buried layer portion; and ion implantation is performed on the epitaxial layer using N-type conductive ions to form the second buried layer in each buried layer portion. Each buried layer portion is prepared layer by layer from close to the substrate to far away from the substrate, thereby obtaining a buried layer structure.

[0090] S140, performing ion implantation on the first surface 201 to form a first doped region 400; the first doped region 400 is located on a side of the buried structure 500 away from the substrate 100; the first doped region 400 has a second conductivity type.

[0091] Exemplarily, ion implantation is performed using P-type conductive ions on the first surface of the epitaxial layer to form a first doped region with a certain implantation depth on at least one side of the semiconductor device, and the bottom of the first doped region contacts the buried layer structure.

[0092] S150 , forming a gate trench 202 on the first surface 201 .

[0093] Exemplarily, etching is performed from the first surface of the epitaxial layer toward the inside to form a gate trench.

[0094] S160 , forming a gate structure 300 inside the gate trench.

[0095] Exemplarily, a thermal oxidation method is used to deposit silicon oxide material inside the gate trench to form a gate oxide layer 301. The thickness of the gate oxide layer at the bottom of the gate trench is greater than the thickness of the gate oxide layer at the sidewall of the gate trench. Polysilicon material is deposited on the surface of the gate oxide layer, and back-etching is performed to fill the inside of the gate trench with polysilicon material to form a gate 302.

[0096] Among them, the first buried layer 511 has the second conductivity type, and the second buried layer 512 has the first conductivity type; the ion concentration of the second buried layer 512 is greater than the ion concentration of the epitaxial layer 200; the widths of at least two first buried layers 511 are different; along the direction from the epitaxial layer 200 to the substrate 100, the width of each first buried layer 511 decreases successively.

[0097] In the method for preparing a semiconductor device provided by an embodiment of the present invention, a buried layer structure is provided in the epitaxial layer, wherein the buried layer structure includes at least two buried layer parts arranged in a stacked manner, each buried layer part includes a first buried layer and a second buried layer, and the second buried layer is provided on the side of the first buried layer. The width of each first buried layer pointing to the substrate along the epitaxial layer gradually decreases to form a stepped superjunction structure. Since the first buried layer has the same conductivity type as the first doped region, the extension depth of the region of the conductivity type in the epitaxial layer can be increased, thereby effectively shielding the higher electric field at the bottom and sidewall of the gate structure, protecting the gate oxide layer from being easily broken down, and improving the reliability of the semiconductor device; and a shorter path can be provided for the current flowing upward from the bottom of the buried layer structure, thereby providing a current conduction channel, which is conducive to increasing the on-state current of the semiconductor device. In addition, a second buried layer is provided on the side of the first buried layer, and the doping concentration of the second buried layer is greater than the doping concentration of the epitaxial layer, thereby reducing the width of the depletion region, and providing a transmission channel for the on-state current, thereby increasing the on-state current.

[0098] Optionally, Figure 7 is a specific flow chart of step S130 in a method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 8 is a schematic diagram of the cross-sectional structure corresponding to each specific step in step S130. Figure 7 and Figure 8 The step S130 of forming a buried layer structure in the epitaxial layer specifically includes the following steps:

[0099] S131 , ion implantation is performed on the epitaxial layer 200 to form a buried layer 510 .

[0100] Exemplarily, P-type conductive ions are used to perform ion implantation on the surface of the epitaxial layer away from the substrate and near the side to form a first buried layer; and N-type conductive ions are used to perform ion implantation on both sides of the first buried layer to form a second buried layer, thereby obtaining a buried layer portion.

[0101] S132 , forming the epitaxial layer 200 again on the side of the buried layer 510 away from the substrate 100 .

[0102] Exemplarily, an epitaxial layer is further formed on the surface of the first buried layer portion, thereby obtaining a buried layer structure including only one buried layer portion.

[0103] S133 , repeatedly performing the steps of ion implantation and forming the epitaxial layer 200 until the buried layer structure 500 is formed.

[0104] Specifically, the steps of forming the first buried layer and the second buried layer and forming the epitaxial layer by ion implantation are repeated, and the number of times the steps are performed determines the number of buried layer portions formed, thereby forming a buried layer structure. Figure 6 and Figure 8 In the embodiment of the present invention, the steps of performing two ion implantations and forming an epitaxial layer are taken as an example, that is, two buried layers arranged in a stacked manner are formed. After the buried layer structure is prepared, another epitaxial layer is formed on the surface of the buried layer structure, and the surface of the epitaxial layer away from the substrate is the first surface, so as to perform subsequent process operations.

[0105] Optionally, Fig. 9 1 is a schematic diagram of a cross-sectional structure corresponding to the steps before forming the first doped region. Based on the above embodiments, before ion implantation is performed on the first surface to form the first doped region, the method further includes:

[0106] Ion implantation is performed on the first surface 201 to form a body region 700 and a second doping region 600 ; wherein the second doping region 600 is located on the first surface 201 of the epitaxial layer 200 , and the body region 700 is located on a side of the second doping region 600 away from the first surface 201 .

[0107] For example, see Fig. 9 , P-type conductive ions are implanted into the first surface at a relatively deep implantation depth to form a body region, and N-type conductive ions are implanted into the first surface at a relatively shallow implantation depth to form a second doped region.

[0108] Optionally, Fig.10 is a schematic flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Fig.11 is a schematic diagram of the cross-sectional structure corresponding to step S170 to step S200. Fig.10 and Fig.11 , the semiconductor device manufacturing method further includes the following steps:

[0109] S110 , providing a substrate 100 ; the substrate 100 has a first conductivity type.

[0110] S120 , forming an epitaxial layer 200 on the surface of the substrate 100 ; the epitaxial layer 200 has a first conductivity type, and the epitaxial layer 200 includes a first surface 201 .

[0111] S130 , forming a buried layer structure 500 in the epitaxial layer 200 ; the buried layer structure 500 includes at least two buried layer portions 510 arranged in a stacked manner, each buried layer portion 510 includes a first buried layer 511 and a second buried layer 512 , and the second buried layer 512 is located on the side of the first buried layer 511 .

[0112] S140, performing ion implantation on the first surface 201 to form a first doped region 400; the first doped region 400 is located on a side of the buried structure 500 away from the substrate 100; the first doped region 400 has a second conductivity type.

[0113] S150 , forming a gate trench 202 on the first surface 201 .

[0114] S160 , forming a gate structure 300 inside the gate trench.

[0115] S170 , forming a dielectric layer 800 on a side of the epitaxial layer 200 away from the substrate 100 ; the orthographic projection of the dielectric layer 800 on the substrate 100 covers the orthographic projection of the gate structure 300 on the substrate 100 .

[0116] Exemplarily, an insulating material is deposited on the first surface of the epitaxial layer to form a dielectric layer, so that the dielectric layer covers the gate structure and exposes the first doped region, so that the first doped region achieves ohmic contact with the source.

[0117] S180 , forming a source electrode 900 on a side of the dielectric layer 800 away from the epitaxial layer 200 ; the orthographic projection of the source electrode 900 on the substrate 100 completely overlaps with the orthographic projection of the substrate 100 .

[0118] Exemplarily, a metal material is deposited on the surface of the dielectric layer to form the source electrode.

[0119] S190 , forming a passivation layer 110 on a side of the source 900 away from the epitaxial layer 200 ; the orthographic projection of the passivation layer 110 on the substrate 100 covers at least a portion of the orthographic projection of the first doped region 400 on the substrate 100 .

[0120] Exemplarily, silicon nitride material is deposited on the surface of the source, the silicon nitride 111 at the position corresponding to the first doped region is etched to retain, and a polyimide layer 112 is formed on the surface of the silicon nitride to wrap the silicon nitride to form a passivation layer.

[0121] S200 , forming a drain 120 on a side of the substrate 100 away from the epitaxial layer 200 .

[0122] Exemplarily, a metal material is deposited on the back side of the substrate to form a drain.

[0123] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type and being located on a surface of the substrate, the epitaxial layer comprising a first surface, the first surface being provided with a gate trench; A gate structure, located inside the gate trench; A first doped region, located on at least one side of the gate structure, the first doped region having a second conductivity type; a buried layer structure, located on a side of the first doped region close to the substrate; the buried layer structure comprises at least two buried layer portions arranged in a stacked manner, each of the buried layer portions comprises a first buried layer and a second buried layer, the second buried layer being located on a side of the first buried layer; the first buried layer has the second conductivity type, the second buried layer has the first conductivity type, and the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer; Wherein, at least two layers of the first buried layers have different widths; Along the direction from the epitaxial layer to the substrate, the width of each of the first buried layers decreases successively.

2. The semiconductor device according to claim 1, wherein: A side of the first buried layer close to the first doped region has a first preset width, and a side of the first buried layer away from the first doped region has a second preset width; In two adjacent layers of the first buried layers, the second preset width close to the first doping region is greater than the first preset width far from the first doping region.

3. The semiconductor device according to claim 2, characterized in that In the first buried layer, the first preset width is greater than the second preset width; Alternatively, in the first buried layer, the first preset width is equal to the second preset width.

4. The semiconductor device according to claim 3, characterized in that The stacked first buried layers are distributed in an axisymmetric manner.

5. The semiconductor device according to claim 2, wherein: The number of the first buried layers ranges from 2 to 4 layers, and the thickness of each of the first buried layers ranges from 0.3 to 1 μm.

6. The semiconductor device according to claim 5, characterized in that The thickness of the second buried layer is equal to the thickness of the first buried layer in the same layer; In two adjacent buried layer portions, the sum of the first preset width away from the first doping region and the width of the second buried layer is equal to the second preset width close to the first doping region.

7. The semiconductor device according to claim 1, wherein: Also includes: a second doped region, located on the first surface of the epitaxial layer; a body region, located at a side of the second doped region away from the first surface; a dielectric layer, located on a side of the epitaxial layer away from the substrate, wherein an orthographic projection of the dielectric layer on the substrate covers an orthographic projection of the gate structure on the substrate; A source electrode is located on a side of the dielectric layer away from the epitaxial layer, and an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate; A passivation layer, located on a side of the source electrode away from the epitaxial layer, wherein an orthographic projection of the passivation layer on the substrate covers at least a portion of an orthographic projection of the first doped region on the substrate; The drain is located at a side of the substrate away from the epitaxial layer.

8. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate; the substrate has a first conductivity type; forming an epitaxial layer on a surface of the substrate; The epitaxial layer has the first conductivity type, and the epitaxial layer includes a first surface; A buried layer structure is formed in the epitaxial layer; the buried layer structure comprises at least two buried layer portions arranged in a stacked manner, each buried layer portion comprises a first buried layer and a second buried layer, and the second buried layer is located on a side of the first buried layer; Performing ion implantation on the first surface to form a first doped region; the first doped region is located on a side of the buried layer structure away from the substrate; the first doped region has a second conductivity type; forming a gate trench on the first surface; forming a gate structure inside the gate trench; The first buried layer has the second conductivity type, and the second buried layer has the first conductivity type; the ion concentration of the second buried layer is greater than the ion concentration of the epitaxial layer; and at least two layers of the first buried layer have different widths; Along the direction from the epitaxial layer to the substrate, the width of each of the first buried layers decreases successively.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The forming of a buried layer structure in the epitaxial layer comprises: Performing ion implantation on the epitaxial layer to form a buried layer; forming the epitaxial layer again on a side of the buried layer away from the substrate; The steps of ion implantation and forming the epitaxial layer are repeatedly performed until the buried layer structure is formed.

10. The method for preparing a semiconductor device according to claim 8, characterized in that: Before the ion implantation into the first surface to form the first doped region, the method further comprises: Performing ion implantation on the first surface to form a body region and a second doped region; wherein the second doped region is located on the first surface of the epitaxial layer, and the body region is located on a side of the second doped region away from the first surface; The semiconductor device manufacturing method further includes: forming a dielectric layer on a side of the epitaxial layer away from the substrate; the orthographic projection of the dielectric layer on the substrate covers the orthographic projection of the gate structure on the substrate; A source electrode is formed on a side of the dielectric layer away from the epitaxial layer; an orthographic projection of the source electrode on the substrate completely overlaps with an orthographic projection of the substrate; A passivation layer is formed on a side of the source electrode away from the epitaxial layer; the orthographic projection of the passivation layer on the substrate covers at least a portion of the orthographic projection of the first doped region on the substrate; A drain is formed on a side of the substrate away from the epitaxial layer.

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