Semiconductor structure and forming method thereof, inverter circuit

Abstract

A semiconductor structure and a method for forming the same, as well as an inverter circuit, wherein the method comprises: forming a drain-doped layer, the drain-doped layer comprising a first drain-doped region, an isolation structure, and a second drain-doped region, the isolation structure being located between the first drain-doped region and the second drain-doped region, the first drain-doped region and the second drain-doped region having different conductivity types; forming a first body region on the first drain-doped region, and forming a first source-doped region on the surface of the first body region; forming a second body region on the second drain-doped region, and forming a second source-doped region on the surface of the second body region; forming a first groove on the surface of the drain-doped layer, between the first body region and the second body region, and between the first source-doped region and the second source-doped region; and forming a gate structure within the first groove, the gate structure comprising a gate layer located between the first body region and the second body region, thereby facilitating reduction of on-resistance and power loss of a CMOS device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof, and an inverter circuit. Background Art

[0002] The planar metal-oxide semiconductor field-effect transistor (MOSFET) is a basic electronic component. It can be divided into NMOS and PMOS depending on the type of its conductive channel. The CMOS (Complementary Metal Oxide Semiconductor) gate circuit, composed of NMOS and PMOS, is the most basic circuit structure in digital integrated circuits.

[0003] In integrated circuits, to be compatible with current CMOS processes, inverters are usually constructed using a lateral CMOS structure.

[0004] However, the performance of existing lateral CMOS structures needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, and an inverter circuit, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a drain-doped layer, the drain-doped layer including a first drain-doped region, an isolation structure and a second drain-doped region, the isolation structure being located between the first drain-doped region and the second drain-doped region, and the first drain-doped region and the second drain-doped region having different conductivity types; a first body region located on the first drain-doped region, and a first source-doped region on the surface of the first body region; a second body region located on the second drain-doped region, and a second source-doped region on the surface of the second body region; a first groove located on the surface of the drain-doped layer, between the first body region and the second body region, and between the first source-doped region and the second source-doped region; a gate structure located in the first groove, the gate structure including a gate layer, and the gate layer being located between the first body region and the second body region.

[0007] Optionally, it also includes: a first drift region, the first drift region is located between the surface of the first drain-doped region and the first body region, the conductivity type of the first drift region is the same as the conductivity type of the first drain-doped region, and the doping concentration of the first drift region is lower than the doping concentration of the first drain-doped region; a second drift region, the second drift region is located between the surface of the second drain-doped region and the second body region, the conductivity type of the second drift region is the same as the conductivity type of the second drain-doped region, and the doping concentration of the second drift region is lower than the doping concentration of the second drain-doped region.

[0008] Optionally, the gate layer is further located between the first source doping region and the second source doping region; the gate layer is further located between a portion of the first drift region and a portion of the second drift region.

[0009] Optionally, the gate structure also includes: a shielding gate, which is located between part of the first drift region and part of the second drift region, and the gate layer is located above the shielding gate; a gate dielectric layer, which is located between the gate layer and the sidewall of the first groove and the shielding gate; and a shielding gate dielectric layer, which is located between the shielding gate and the first drift region, the second drift region, and the drain doping layer.

[0010] Optionally, the drain doped layer includes a first surface and a second surface relative to each other, and the first body region, the second body region and the first groove are all located on the first surface; the semiconductor structure also includes: a gate conductive layer located on a portion of the surface of the gate layer; a first source conductive layer located on a portion of the surface of the first source doped region; a second source conductive layer located on a portion of the surface of the second source doped region; a first dielectric layer located on the second surface; a second groove located in the first dielectric layer, the second groove exposing a portion of the first source doped region and a portion of the second drain doped region; and a drain conductive layer located in the second groove.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: forming a drain-doped layer, the drain-doped layer including a first drain-doped region, an isolation structure and a second drain-doped region, the isolation structure being located between the first drain-doped region and the second drain-doped region, the first drain-doped region and the second drain-doped region having different conductivity types; forming a first body region on the first drain-doped region, and forming a first source-doped region on the surface of the first body region; forming a second body region on the second drain-doped region, and forming a second source-doped region on the surface of the second body region; forming a first groove on the surface of the drain-doped layer, between the first body region and the second body region, and between the first source-doped region and the second source-doped region; forming a gate structure in the first groove, the gate structure including a gate layer, and the gate layer being located between the first body region and the second body region.

[0012] Optionally, the drain doped layer includes a first surface and a second surface relative to each other; the first body region, the second body region and the first groove are all formed on the first surface; the method further includes: forming a first dielectric layer on the second surface; forming a second groove in the first dielectric layer, the second groove exposing a portion of the first source doped region and a portion of the second drain doped region; and forming a drain conductive layer in the second groove.

[0013] Optionally, the method for forming the drain doped layer and the first dielectric layer includes: providing a substrate, the substrate including a first initial surface and a second initial surface; forming the first dielectric layer on the second initial surface; etching a portion of the substrate from the first initial surface until penetrating the substrate to form a third groove in the substrate; forming the isolation structure in the third groove; forming the drain doped layer using the substrate, with the first initial surface as the first surface and the second initial surface as the second surface.

[0014] Optionally, the substrate and the first source doping region have the same conductivity type and doping concentration; forming the drain doping layer with the substrate includes: using the substrate on one side of the isolation structure as the first drain doping region; and injecting second doping ions into the substrate on the other side of the isolation structure, wherein the conductivity type of the second doping ions is different from the conductivity type of the substrate, to form the second drain doping region.

[0015] Optionally, the substrate and the second source doping region have the same conductivity type and doping concentration; forming the drain doping layer with the substrate includes: using the substrate on one side of the isolation structure as the second drain doping region; and injecting first doping ions into the substrate on the other side of the isolation structure, wherein the conductivity type of the first doping ions is different from the conductivity type of the substrate, to form the first drain doping region.

[0016] Optionally, the substrate is an intrinsic semiconductor, or the conductivity type of the substrate is the same as the conductivity type of the first drain-doped region, but the doping concentration of the substrate is lower than the doping concentration of the first drain-doped region, or the conductivity type of the substrate is the same as the conductivity type of the second drain-doped region, but the doping concentration of the substrate is lower than the doping concentration of the second drain-doped region; forming the drain-doped layer with the substrate includes: injecting first doping ions into the substrate on one side of the isolation structure to form the first drain-doped region; and injecting second doping ions into the substrate on the other side of the isolation structure to form the second drain-doped region.

[0017] Optionally, the method for forming the first body region, the second body region, the first source doping region, the second source doping region and the first groove includes: forming a first epitaxial layer on the surface of the drain-doped layer; performing a first doping treatment on the first epitaxial layer to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain-doped region, and forming a second initial body region and a second initial source doping region located on the second initial body region on the second drain-doped region; etching part of the first initial source doping region, part of the second initial source doping region, part of the first initial body region and part of the second initial body region until the drain-doped layer is exposed to form the first groove and form the first body region with the first initial body region, form the first source doping region with the first initial source doping region, form the second body region with the second initial body region, and form the second source doping region with the second initial source doping region; the first groove has a first projection on the surface of the drain-doped layer, the isolation structure has a second projection on the surface of the drain-doped layer, and the second projection is located within the range of the first projection.

[0018] Optionally, the first epitaxial layer and the first drain-doped region have the same conductivity type, and the doping concentration of the first epitaxial layer is lower than the doping concentration of the first drain-doped region; the first doping treatment is performed on the first epitaxial layer to form a first initial body region on the first drain-doped region and a first initial source doping region located on the first initial body region, and to form a second initial body region on the second drain-doped region and a second initial source doping region located on the second initial body region, including: injecting third doping ions into the first epitaxial layer on the first drain-doped region, wherein the conductivity type of the third doping ions is different from the conductivity type of the first drain-doped region, so as to form the first initial body region in the first epitaxial layer. body region; injecting fourth doping ions into the first epitaxial layer on the first drain-doped region, the injection depth of the third doping ions being greater than the injection depth of the fourth doping ions, the conductivity type of the fourth doping ions being the same as the conductivity type of the first drain-doped region, so as to form a first source doping region on the first initial body region; injecting fifth doping ions into the first epitaxial layer on the second drain-doped region, the injection depth of the fifth doping ions being lower than the thickness of the first epitaxial layer, the conductivity type of the fifth doping ions being the same as the conductivity type of the second drain-doped region, so as to form a second initial body region on the second drain-doped region and a second initial source doping region located on the second body region.

[0019] Optionally, the first epitaxial layer and the second drain doping region have the same conductivity type and doping concentration; the first epitaxial layer is subjected to a first doping treatment to form a first initial body region on the first drain doping region and a first initial source doping region located on the first initial body region, and a second initial body region on the second drain doping region and a second initial source doping region located on the second initial body region, comprising: injecting a sixth doping ion into the first epitaxial layer on the second drain doping region, wherein the conductivity type of the sixth doping ion is different from the conductivity type of the second drain doping region, so as to form the second initial body region in the first epitaxial layer; and injecting a sixth doping ion into the second drain doping region. Fifth doping ions are implanted into the first epitaxial layer, the implantation depth of the sixth doping ions is greater than the implantation depth of the fifth doping ions, and the conductivity type of the fifth doping ions is the same as the conductivity type of the second drain doping region, so as to form a second initial source doping region on the second initial body region; fourth doping ions are implanted into the first epitaxial layer on the first drain doping region, the implantation depth of the fourth doping ions is lower than the thickness of the first epitaxial layer, and the conductivity type of the fourth doping ions is the same as the conductivity type of the first drain doping region, so as to form the first initial body region and the first initial source doping region located on the first initial body region on the first drain doping region.

[0020] Optionally, the first epitaxial layer is an intrinsic semiconductor; the first doping treatment of the first epitaxial layer to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain-doping region, and to form a second initial body region and a second initial source doping region located on the second initial body region on the second drain-doping region includes: injecting third doping ions into the first epitaxial layer on the first drain-doping region; injecting sixth doping ions into the first epitaxial layer on the second drain-doping region; injecting fourth doping ions into the first epitaxial layer on the first drain-doping region, the injection depth of the third doping ions being greater than the injection depth of the fourth doping ions, so as to form the first initial body region and the first initial source doping region located on the first initial body region on the first drain-doping region; injecting fifth doping ions into the first epitaxial layer on the second drain-doping region, the injection depth of the sixth doping ions being greater than the injection depth of the fifth doping ions, so as to form the second initial body region and the second initial source doping region located on the second drain-doping region.

[0021] Optionally, the method further includes: forming a first drift region between the surface of the first drain doping region and the first body region; forming a second drift region between the surface of the second drain doping region and the second body region; and the first groove is also formed between the first drift region and the second drift region.

[0022] Optionally, the method for forming the first drift region and the second drift region includes: before forming the first epitaxial layer, forming a second epitaxial layer on the surface of the drain doping layer; performing a second doping treatment on the second epitaxial layer to form a first initial drift region on the surface of the first drain doping region, and forming a second initial drift region on the surface of the second drain doping region, the conductivity type of the first initial drift region is the same as the conductivity type of the first drain doping region, and the doping concentration of the first initial drift region is lower than the doping concentration of the first drain doping region, the conductivity type of the second initial drift region is the same as the conductivity type of the second drain doping region, and the doping concentration of the second initial drift region is lower than the doping concentration of the second drain doping region; after etching the first initial body region and the second initial body region, also etching part of the first initial drift region and part of the second initial drift region, forming the first drift region with the initial first drift region, and forming the second drift region with the second initial drift region.

[0023] Optionally, the conductivity type of the second epitaxial layer is the same as the conductivity type of the first drain-doped region; the second doping treatment of the second epitaxial layer to form a first initial drift region on the surface of the first drain-doped region, and the formation of a second initial drift region on the surface of the second drain-doped region include: injecting eighth doping ions into the second epitaxial layer on the second drain-doped region, the conductivity type of the eighth doping ions is the same as the conductivity type of the second drain-doped region, the second epitaxial layer on the first drain-doped region is the first initial drift region, and the second epitaxial layer on the second drain-doped region is the second initial drift region.

[0024] Optionally, the conductivity type of the second epitaxial layer is the same as the conductivity type of the second drain-doped region; the second doping treatment of the second epitaxial layer to form a first initial drift region on the surface of the first drain-doped region, and the formation of the second initial drift region on the surface of the second drain-doped region include: injecting seventh doping ions into the second epitaxial layer on the first drain-doped region, the conductivity type of the seventh doping ions is the same as the conductivity type of the first drain-doped region, the second epitaxial layer on the first drain-doped region is the first initial drift region, and the second epitaxial layer on the second drain-doped region is the second initial drift region.

[0025] Optionally, the second epitaxial layer is an intrinsic semiconductor; the second doping treatment is performed on the second epitaxial layer to form a first initial drift region on the surface of the first drain-doped region, and the second initial drift region is formed on the surface of the second drain-doped region, including: injecting seventh doping ions into the second epitaxial layer on the first drain-doped region, the conductivity type of the seventh doping ions is the same as the conductivity type of the first drain-doped region, and the epitaxial layer on the first drain-doped region is the first initial drift region; injecting eighth doping ions into the second epitaxial layer on the second drain-doped region, the conductivity type of the eighth doping ions is the same as the conductivity type of the second drain-doped region, and the second epitaxial layer on the second drain-doped region is the second initial drift region.

[0026] Optionally, the gate layer is also located between part of the first drift region and part of the second drift region; the gate layer is also located between the first source doping region and the second source doping region; the gate structure also includes a shielding gate, the shielding gate is located between part of the first drift region and part of the second drift region, and the gate layer is located above the shielding gate; the method for forming the gate structure includes: forming the shielding gate in the first groove; forming the gate layer on the shielding gate.

[0027] Optionally, the gate structure also includes a shielding gate dielectric layer, which is located between the shielding gate and the first drift region, the second drift region, and the drain doping layer; the method for forming the shielding gate dielectric layer and the shielding gate includes: forming a second dielectric material layer on the surface of the first source doping region, the surface of the second source doping region and in the first groove; forming a first gate material layer on the surface of the second dielectric material layer; flattening the first gate material layer and the second dielectric material layer until the surface of the first source doping region and the surface of the second source doping region are exposed; etching back the first gate material layer so that the top surface of the first gate material layer is lower than the surface of the first drift region and lower than the surface of the second drift region to form the shielding gate, and forming a shielding gate dielectric layer with the second dielectric material layer between the shielding gate and the first drift region, the second drift region, and the drain doping layer.

[0028] Optionally, the gate structure further includes: a gate dielectric layer, wherein the gate dielectric layer is located between the gate layer and the sidewall of the first groove and the shielding gate; the method for forming the gate dielectric layer and the gate layer includes: after forming the shielding gate, forming a third dielectric material layer on the surface of the first source doping region, the surface of the second source doping region, and in the first groove; forming a second gate material layer on the surface of the third dielectric material layer; flattening the second gate material layer and the third dielectric material layer until the surface of the first source doping region and the surface of the second source doping region are exposed, using the second gate material layer in the first groove as the gate layer, and using the third dielectric material layer between the gate layer and the sidewall of the first groove and the shielding gate as the gate dielectric layer.

[0029] Optionally, the method further includes: forming a gate conductive layer on a portion of the surface of the gate layer; forming a first source conductive layer on a portion of the surface of the first source doping region; and forming a second source conductive layer on a portion of the surface of the second source doping region.

[0030] Correspondingly, the technical solution of the present invention also provides an inverter circuit, which includes the semiconductor structure described above, wherein one of the first source doping region and the second source doping region is connected to a power supply, and the other is grounded, the gate layer is connected to an input end, and the first drain doping region and the second drain doping region are connected to an output end.

[0031] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0032] In the semiconductor structure provided by the technical solution of the present invention, the semiconductor structure is a CMOS device, in which the first drain doping region, the first body region and the first source doping region of one MOS device, and the second drain doping region, the second body region and the second source doping region of the other MOS device are all distributed vertically. Compared with a lateral CMOS device, since there is no parasitic JFET region, it is beneficial to reduce the on-resistance of the device and reduce the power loss of the device.

[0033] Furthermore, the presence of the first drift region and the second drift region improves the voltage resistance of the CMOS device. The voltage resistance of the CMOS device depends on the longitudinal dimensions of the first drift region and the second drift region, rather than the lateral dimensions. Therefore, under the same voltage resistance requirements, the device size can be effectively reduced compared to the lateral CMOS device.

[0034] Furthermore, the gate structure also includes a shielding gate, which is located between part of the first drift region and part of the second drift region, and the gate layer is located above the shielding gate. The shielding gate is beneficial to reducing the parasitic capacitance and on-resistance of the CMOS device and improving the performance of the CMOS device.

[0035] In the method for forming a semiconductor structure provided by the technical solution of the present invention, in the formed CMOS device, the first drain doping region, the first body region and the first source doping region of one MOS device, and the second drain doping region, the second body region and the second source doping region of the other MOS device are all distributed vertically. Compared with a lateral CMOS device, since there is no parasitic JFET region, it is beneficial to reduce the on-resistance of the device and reduce the power loss of the device.

[0036] Furthermore, the presence of the first drift region and the second drift region improves the voltage resistance of the CMOS device. The voltage resistance of the CMOS device depends on the longitudinal dimensions of the first drift region and the second drift region, rather than the lateral dimensions. Therefore, under the same voltage resistance requirements, the device size can be effectively reduced compared to the lateral CMOS device.

[0037] Furthermore, the gate structure also includes a shielding gate, which is located between part of the first drift region and part of the second drift region, and the gate layer is located above the shielding gate. The shielding gate is beneficial to reducing the parasitic capacitance and on-resistance of the CMOS device and improving the performance of the CMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of CMOS structure and inverter circuit connection;

[0039] Figures 2 to 12 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0040] Figure 13 FIG. 1 is a schematic diagram of a semiconductor structure inverter circuit connection according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0042] As described in the background art, the performance of existing lateral CMOS structures needs to be further improved. An explanation and analysis will now be provided in conjunction with a CMOS structure.

[0043] Figure 1 It is a schematic diagram of CMOS structure and inverter circuit connection.

[0044] Please refer to Figure 1The CMOS structure includes: a substrate 100, the substrate 100 includes a first region I, a second region II and a third region III, the third region III is located between the first region I and the second region II, the conductivity type of the substrate 100 is P type, the substrate 100 further has a well region 101 located in the second region II, the conductivity type of the well region 101 is N type; an NMOS device, the NMOS device includes a first gate structure located on a surface of a portion of the first region I, a first source doping region 102 and a first drain doping region 103 located in the first region I on both sides of the first gate structure, the first source doping region 102 and the first drain doping region 103 The impurity regions 103 are all N-type, the first gate structure includes a first gate oxide layer 104 and a first gate layer 105 located on the surface of the first gate oxide layer 104; a PMOS device, the PMOS device includes a second gate structure located on the surface of a portion of the second region II, a second source doped region 106 and a second drain doped region 107 located in the well region 101 on both sides of the second gate structure, the conductivity type of the second source doped region 106 and the second drain doped region 107 are both P-type, the second gate structure includes a second gate oxide layer 108 and a second gate layer 109 located on the surface of the second gate oxide layer 108; and a field oxide layer 110 located on the surface of the third region III.

[0045] The above structure is a lateral CMOS structure. In the resulting inverter circuit, the first drain doping region 103 and the second drain doping region 107 are electrically connected, serving as the inverter output Vout. The first gate layer 105 and the second gate layer 109 are electrically connected, serving as the inverter input Vin. The first source doping region 102 and the second source doping region 106 are both grounded. Inverters formed using lateral CMOS are well compatible with current CMOS processes in integrated circuits.

[0046] However, as integrated circuits enter the deep submicron scale, lateral CMOS inevitably has parasitic junction field effect transistor (JFET) resistance, making it difficult to reduce the on-resistance and power loss of CMOS devices.

[0047] To address the above-mentioned problems, the present invention provides a semiconductor structure, a method for forming the same, and an inverter circuit, in which a CMOS device is formed, wherein the first drain-doped region, the first body region, and the first source-doped region of one MOS device, and the second drain-doped region, the second body region, and the second source-doped region of the other MOS device are all distributed vertically. Compared with lateral CMOS devices, the absence of a parasitic JFET region helps reduce the on-resistance of the device and lowers the power loss of the device.

[0048] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] Figures 2 to 12 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0050] Please refer to Figure 2 , forming a drain doping layer, the drain doping layer includes a first drain doping region 201, an isolation structure 202 and a second drain doping region 203, the isolation structure 202 is located between the first drain doping region 201 and the second drain doping region 203, and the first drain doping region 201 and the second drain doping region 203 have different conductivity types.

[0051] Subsequently, a first body region is formed on the first drain doping region 201 , and a first source doping region is formed on the surface of the first body region; a second body region is formed on the second drain doping region 203 , and a second source doping region is formed on the surface of the second body region.

[0052] The first drain doping region 201, the first body region and the first source doping region are arranged vertically to form one MOS device of the CMOS device, and the second drain doping region 203, the second body region and the second source doping region are also arranged vertically to form another MOS device of the CMOS device.

[0053] In this embodiment, the conductivity type of the first drain doping region 201 is N-type, which is used to form an NMOS device, and the conductivity type of the second drain doping region 203 is P-type, which is used to form a PMOS device.

[0054] In another embodiment, the conductivity type of the first drain doping region is P-type, for forming a PMOS device, and the conductivity type of the second drain doping region is N-type, for forming an NMOS device.

[0055] In this embodiment, the drain doped layer includes a first surface 100a and a second surface 100b opposite to each other. Subsequently, a first body region, a second body region and a first groove are formed on the first surface 200a.

[0056] In this embodiment, a first dielectric layer 204 is further formed on the second surface 200 b.

[0057] In this embodiment, the method for forming the drain doped layer 200 and the first dielectric layer 204 includes: providing a substrate (not shown in the figure), the substrate including a first initial surface (not shown in the figure) and a second initial surface (not shown in the figure); forming the first dielectric layer 204 on the second initial surface; etching a portion of the substrate from the first initial surface until it penetrates the substrate, forming a third groove (not shown in the figure) in the substrate; forming the isolation structure 202 in the third groove; and forming the drain doped layer 200 using the substrate, with the first initial surface serving as the first surface 200a and the second initial surface serving as the second surface 200b.

[0058] In this embodiment, the substrate is made of silicon. In another embodiment, the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of Group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0059] In this embodiment, the substrate and the first drain doping region 201 have the same conductivity type and doping concentration; the formation of the drain doping layer using the substrate includes: using the substrate on one side of the isolation structure 202 as the first drain doping region 201; and injecting second doping ions into the substrate on the other side of the isolation structure, wherein the conductivity type of the second doping ions is different from the conductivity type of the substrate, to form the second drain doping region 203.

[0060] Specifically, the method of injecting second doping ions into the substrate on the other side of the isolation structure includes: forming a first mask layer (not shown in the figure) on the surface of the substrate, the first mask layer exposing a portion of the substrate; using the first mask layer as a mask, injecting second doping ions into the substrate on the other side of the isolation structure; and removing the first mask layer.

[0061] In this embodiment, the material of the first mask layer includes photoresist.

[0062] In another embodiment, the substrate and the second drain doping region have the same conductivity type and doping concentration; forming the drain doping layer with the substrate includes: using the substrate on one side of the isolation structure as the second drain doping region; and injecting first doping ions into the substrate on the other side of the isolation structure, wherein the conductivity type of the first doping ions is different from the conductivity type of the substrate, to form the first drain doping region.

[0063] In another embodiment, the substrate is an intrinsic semiconductor, or the conductivity type of the substrate is the same as the conductivity type of the first drain-doped region, but the doping concentration of the substrate is lower than the doping concentration of the first drain-doped region, or the conductivity type of the substrate is the same as the conductivity type of the second drain-doped region, but the doping concentration of the substrate is lower than the doping concentration of the second drain-doped region; forming the drain-doped layer with the substrate includes: injecting first doping ions into the substrate on one side of the isolation structure to form the first drain-doped region; and injecting second doping ions into the substrate on the other side of the isolation structure to form the second drain-doped region.

[0064] Subsequently, a first groove is formed on the surface of the drain doping layer, between the first body region and the second body region, and between the first source doping region and the second source doping region.

[0065] In this embodiment, a first drift region is formed between the surface of the first drain doping region 201 and the first body region; a second drift region is formed between the surface of the second drain doping region 203 and the second body region; and the first groove is also formed between the first drift region and the second drift region.

[0066] In another embodiment, the first drift region and the second drift region may not be formed.

[0067] In this embodiment, the formation method of the first body region, the second body region, the first source doping region, the second source doping region, the first drift region and the second drift region can be referred to. Figures 3 to 9 .

[0068] Please refer to Figure 3 , forming a second epitaxial layer 205 on the surface of the drain doped layer.

[0069] The second epitaxial layer 205 is used to form a first drift region and a second drift region.

[0070] In this embodiment, the conductivity type of the second epitaxial layer 205 is the same as the conductivity type of the first drain doped region 201 .

[0071] In another embodiment, the conductivity type of the second epitaxial layer is the same as the conductivity type of the second drain doping region.

[0072] In yet another embodiment, the second epitaxial layer is an intrinsic semiconductor.

[0073] Please refer to Figure 4 , for the second epitaxial layer 205 (such as Figure 3As shown in the figure, a second doping treatment is performed to form a first initial drift region 206 on the surface of the first drain-doped region 201, and a second initial drift region 207 is formed on the surface of the second drain-doped region. The conductivity type of the first initial drift region 206 is the same as the conductivity type of the first drain-doped region 201, and the doping concentration of the first initial drift region 206 is lower than the doping concentration of the first drain-doped region 201. The conductivity type of the second initial drift region 207 is the same as the conductivity type of the second drain-doped region 203, and the doping concentration of the second initial drift region 207 is lower than the doping concentration of the second drain-doped region 203.

[0074] In this embodiment, the second doping treatment is performed on the second epitaxial layer 205 to form a first initial drift region 206 on the surface of the first drain doping region, and the second initial drift region 207 is formed on the surface of the second drain doping region, including: injecting eighth doping ions 208 into the second epitaxial layer 205 on the second drain doping region 203, the conductivity type of the eighth doping ions 208 is the same as the conductivity type of the second drain doping region 203, the second epitaxial layer 205 on the first drain doping region 201 is the first initial drift region 206, and the second epitaxial layer 205 on the second drain doping region 203 is the second initial drift region 207.

[0075] In this embodiment, the eighth doping ion 208 is a P-type conductive ion. In another embodiment, the eighth doping ion 208 can be an N-type conductive ion.

[0076] In this embodiment, the injection of the eighth doping ion 208 into the second epitaxial layer 205 on the second drain-doping region 203 includes: forming a second mask layer 209 on the surface of the second epitaxial layer 205, the second mask layer 209 exposing the second epitaxial layer 205 on the second drain-doping region 203; using the second mask layer 209 as a mask, the injection of the eighth doping ion 208 into the second epitaxial layer 205 on the second drain-doping region 203; and removing the second mask layer 209.

[0077] More specifically, the second mask layer 209 further exposes a portion of the surface of the second epitaxial layer 205 on the isolation structure 202 to improve the process window of ion implantation.

[0078] In this embodiment, the material of the second mask layer 209 includes a photoresist layer.

[0079] In another embodiment, the conductivity type of the second epitaxial layer is the same as the conductivity type of the second drain-doped region; the second doping treatment is performed on the second epitaxial layer to form a first initial drift region on the surface of the first drain-doped region, and the formation of the second initial drift region on the surface of the second drain-doped region includes: injecting seventh doping ions into the second epitaxial layer on the first drain-doped region, the conductivity type of the seventh doping ions is the same as the conductivity type of the first drain-doped region, the second epitaxial layer on the first drain-doped region is the first drift region, and the second epitaxial layer on the second drain-doped region is the second drift region.

[0080] In another embodiment, the second epitaxial layer is an intrinsic semiconductor; the second doping treatment is performed on the second epitaxial layer to form a first initial drift region on the surface of the first drain-doped region, and the second initial drift region is formed on the surface of the second drain-doped region, including: injecting seventh doping ions into the second epitaxial layer on the first drain-doped region, the conductivity type of the seventh doping ions is the same as the conductivity type of the first drain-doped region, and the epitaxial layer on the first drain-doped region is the first drift region; injecting eighth doping ions into the second epitaxial layer on the second drain-doped region, the conductivity type of the eighth doping ions is the same as the conductivity type of the second drain-doped region, and the second epitaxial layer on the second drain-doped region is the second drift region.

[0081] Please refer to Figure 5 , forming a first epitaxial layer 210 on the surface of the drain doped layer.

[0082] Specifically, after the first initial drift region 206 and the second initial drift region 207 are formed, the first epitaxial layer 210 is formed on the surface of the second epitaxial layer 205 .

[0083] In another embodiment, the first initial drift region and the second initial drift region may not be formed, and the first epitaxial layer and the drain doping layer surface may be in direct contact.

[0084] In this embodiment, the first epitaxial layer 210 and the first drain doping region have the same conductivity type, and the doping concentration of the first epitaxial layer 210 is lower than the doping concentration of the first drain doping region.

[0085] Subsequently, the first epitaxial layer 210 is subjected to a first doping treatment to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain doping region 201, and to form a second initial body region and a second initial source doping region located on the second initial body region on the second drain doping region.

[0086] In this embodiment, the first epitaxial layer 210 and the first drain-doped region 201 have the same conductivity type, and the doping concentration of the first epitaxial layer 210 is lower than the doping concentration of the first drain-doped region 201; the first epitaxial layer 210 is subjected to a first doping treatment to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain-doped region 201, and a second initial body region and a second initial source doping region located on the second initial body region on the second drain-doped region 203. Figures 6 and 7 .

[0087] Please refer to Figure 6 , third doping ions 211 are implanted into the first epitaxial layer 210 on the first drain doping region 201 , where the conductivity type of the third doping ions 211 is different from the conductivity type of the first drain doping region 201 , to form the first initial body region 213 in the first epitaxial layer 210 .

[0088] In this embodiment, the third doping ions 211 are P-type conductive ions. In another embodiment, the third doping ions may be N-type conductive ions.

[0089] The method for injecting third doping ions 211 into the first epitaxial layer 210 on the first drain-doping region 201 includes: forming a third mask layer 212 on the surface of the first epitaxial layer 210, the third mask layer 212 exposing the first epitaxial layer 210 on the first drain-doping region 201; using the third mask layer 212 as a mask, injecting third doping ions 211 into the first epitaxial layer 210 on the first drain-doping region 201; and removing the third mask layer 212.

[0090] In this embodiment, the material of the third mask layer 212 includes a photoresist layer.

[0091] Please refer to Figure 7 , fourth doping ions 214 are implanted into the first epitaxial layer 210 on the first drain doping region 201, the implantation depth of the third doping ions 211 is greater than the implantation depth of the fourth doping ions 214, and the conductivity type of the fourth doping ions 214 is the same as the conductivity type of the first drain doping region 201, so as to form a first source doping region 215 on the first initial body region 213.

[0092] Specifically, after the third doping ions 211 are implanted, fourth doping ions 214 are implanted into the first epitaxial layer 210 on the first drain doping region 201 .

[0093] In this embodiment, the fourth doping ions 214 are N-type conductive ions. In another embodiment, the fourth doping ions may be P-type conductive ions.

[0094] The process of injecting fourth doping ions 214 into the first epitaxial layer 210 on the first drain-doped region 201 includes: forming a fourth mask layer 216 on the surface of the first epitaxial layer 210, wherein the fourth mask layer 216 exposes the first epitaxial layer 210 on the first drain-doped region 201; using the fourth mask layer 216 as a mask, injecting fourth doping ions 214 into the first epitaxial layer 210 on the first drain-doped region 201; and removing the fourth mask layer 216.

[0095] In this embodiment, the material of the fourth mask layer 216 includes a photoresist layer.

[0096] Please refer to Figure 8 , fifth doping ions 217 are implanted into the first epitaxial layer 210 on the second drain doping region 203, the implantation depth of the fifth doping ions is lower than the thickness of the first epitaxial layer 210, and the conductivity type of the fifth doping ions 217 is the same as the conductivity type of the second drain doping region 204, so as to form the second initial body region 218 on the second drain doping region 204 and the second source doping region 219 located on the second initial body region 218.

[0097] In this embodiment, the fifth doping ion 217 is a P-type conductive ion. In another embodiment, the fifth doping ion can be an N-type conductive ion.

[0098] The process of injecting the fifth doping ion 217 into the first epitaxial layer 210 on the second drain-doping region 203 includes: forming a fifth mask layer 220 on the surface of the first epitaxial layer 210, wherein the fifth mask layer 220 exposes the first epitaxial layer 210 on the second drain-doping region 203; using the fifth mask layer 220 as a mask, injecting the fifth doping ion 217 into the first epitaxial layer 210 on the second drain-doping region 203; and removing the fifth mask layer 220.

[0099] In this embodiment, the material of the fifth mask layer 220 includes a photoresist layer.

[0100] In another embodiment, the first epitaxial layer and the second drain doping region have the same conductivity type and doping concentration; performing a first doping treatment on the first epitaxial layer to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain doping region, and forming a second initial body region and a second initial source doping region located on the second initial body region on the second drain doping region comprises: implanting a sixth doping ion into the first epitaxial layer on the second drain doping region, wherein the conductivity type of the sixth doping ion is different from the conductivity type of the second drain doping region, so as to form the second initial body region in the first epitaxial layer; implanting a sixth doping ion into the second drain doping region, wherein the sixth doping ion has a conductivity type different from that of the second drain doping region; and implanting a sixth doping ion into the second drain doping region. Fifth doping ions are implanted into the first epitaxial layer on the drain-doped region, the implantation depth of the sixth doping ions is greater than the implantation depth of the fifth doping ions, and the conductivity type of the fifth doping ions is the same as the conductivity type of the second drain-doped region, so as to form a second initial source doping region on the second initial body region; fourth doping ions are implanted into the first epitaxial layer on the first drain-doped region, the implantation depth of the fourth doping ions is lower than the thickness of the first epitaxial layer, and the conductivity type of the fourth doping ions is the same as the conductivity type of the first drain-doped region, so as to form the first initial body region and the first initial source doping region located on the first initial body region on the first drain-doped region.

[0101] In another embodiment, the first epitaxial layer is an intrinsic semiconductor; the first doping treatment of the first epitaxial layer to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain-doping region, and to form a second initial body region and a second initial source doping region located on the second initial body region on the second drain-doping region includes: injecting third doping ions into the first epitaxial layer on the first drain-doping region; injecting sixth doping ions into the first epitaxial layer on the second drain-doping region; injecting fourth doping ions into the first epitaxial layer on the first drain-doping region, the injection depth of the third doping ions being greater than the injection depth of the fourth doping ions, so as to form the first initial body region and the first initial source doping region located on the first initial body region on the first drain-doping region; injecting fifth doping ions into the first epitaxial layer on the second drain-doping region, the injection depth of the sixth doping ions being greater than the injection depth of the fifth doping ions, so as to form the second initial body region and the second initial source doping region located on the second drain-doping region.

[0102] Please refer to Figure 9, etching part of the first initial source doping region 215, part of the second initial source doping region 219, part of the first initial body region 213 and part of the second initial body region 218 until the drain doping layer is exposed to form the first groove 221, and forming the first body region 222 with the first initial body region 213, forming the first source doping region 223 with the first initial source doping region 215, forming the second body region 224 with the second initial body region 218, and forming the second source doping region 225 with the second initial source doping region 219.

[0103] In this embodiment, the first groove 221 has a first projection on the surface of the drain-doped layer, and the isolation structure 202 has a second projection on the surface of the drain-doped layer. The second projection is located within the range of the first projection.

[0104] In this embodiment, the first groove 221 is further formed between the first drift region and the second drift region.

[0105] Specifically, after etching the first initial body region 213 and the second initial body region 218 , part of the first initial drift region 206 and part of the second initial drift region 207 are also etched to form the first drift region 226 with the initial first drift region 206 and to form the second drift region 227 with the second initial drift region 207 .

[0106] Here, the presence of the first drift region 226 and the second drift region 227 improves the voltage resistance of the CMOS device. The voltage resistance of the CMOS device depends on the longitudinal dimensions of the first drift region 226 and the second drift region 227, rather than the lateral dimensions. Therefore, under the same voltage resistance requirements, the device size can be effectively reduced compared to the lateral CMOS device.

[0107] Subsequently, a gate structure is formed in the first groove 221 . The gate structure includes a gate layer. The gate layer is located between the first body region and the second body region.

[0108] In this embodiment, the gate structure further includes a shielding gate, the shielding gate is located between a portion of the first drift region and a portion of the second drift region, and the gate layer is located above the shielding gate.

[0109] In this embodiment, the method for forming the gate structure is described in detail. Figures 10 and 11 .

[0110] Please refer to Figure 10 , the shielding grid 228 is formed in the first groove 221 .

[0111] The shielding gate 228 is beneficial for reducing the parasitic capacitance and on-resistance of the CMOS device, thereby improving the performance of the CMOS device.

[0112] In this embodiment, the shielding gate 228 is made of polysilicon.

[0113] In this embodiment, the gate structure further includes a shielding gate dielectric layer 229 . The shielding gate dielectric layer 229 is located between the shielding gate 228 and the first drift region 226 , the second drift region 227 , and the drain doping layer.

[0114] In this embodiment, the method for forming the shielding gate dielectric layer 229 and the shielding gate 228 includes: forming a second dielectric material layer (not shown in the figure) on the surface of the first source doping region 223, the surface of the second source doping region 225 and in the first groove 221; forming a first gate material layer (not shown in the figure) on the surface of the second dielectric material layer; planarizing the first gate material layer and the second dielectric material layer until the surface of the first source doping region 223 and the surface of the second source doping region 225 are exposed; etching back the first gate material layer so that the top surface of the first gate material layer is lower than the surface of the first drift region 226 and lower than the surface of the second drift region 227 to form the shielding gate 228, and forming a shielding gate dielectric layer 229 with the second dielectric material layer between the shielding gate 228 and the first drift region 226, the second drift region 227, and the drain doping region.

[0115] In this embodiment, the second dielectric material layer is further etched back so that the top surface of the second dielectric material layer is flush with the top surface of the shielding grid 228 .

[0116] Please refer to Figure 11 , the gate layer 230 is formed on the shielding gate 228 .

[0117] At this point, in the formed CMOS device, the first drain doping region, the first body region and the first source doping region of one MOS device, and the second drain doping region, the second body region and the second source doping region of the other MOS device are all distributed vertically. Compared with the lateral CMOS device, the absence of the parasitic JFET region is conducive to reducing the on-resistance of the device and reducing the power loss of the device.

[0118] In this embodiment, the gate layer 230 is made of polysilicon.

[0119] In this embodiment, the gate layer 230 is further located between a portion of the first drift region 226 and a portion of the second drift region 227 ; the gate layer 230 is further located between the first source doping region 223 and the second source doping region 225 .

[0120] In this embodiment, the gate structure further includes: a gate dielectric layer 231, the gate dielectric layer 231 is located between the gate layer 230 and the first groove 221 (such as Figure 9 As shown) side wall and the shielding grid 228.

[0121] In this embodiment, the method for forming the gate dielectric layer 231 and the gate layer 230 includes: after forming the shielding gate 228, forming a third dielectric material layer (not shown in the figure) on the surface of the first source doping region 223, the surface of the second source doping region 225, and in the first groove 221; forming a second gate material layer (not shown in the figure) on the surface of the third dielectric material layer; planarizing the second gate material layer and the third dielectric material layer until the surface of the first source doping region 223 and the surface of the second source doping region 225 are exposed, using the second gate material layer in the first groove 221 as the gate layer 230, and using the third dielectric material layer between the gate layer 230 and the sidewall of the first groove 221 and the shielding gate 228 as the gate dielectric layer 231.

[0122] Please refer to Figure 12 A gate conductive layer 233 is formed on a portion of the surface of the gate layer 230; a first source conductive layer 234 is formed on a portion of the surface of the first source doping region 223; a second source conductive layer 235 is formed on a portion of the surface of the second source doping region 225; a second groove (not shown in the figure) is formed in the first dielectric layer 204, the second groove exposing a portion of the first source doping region 201 and a portion of the second drain doping region 203; and a drain conductive layer 232 is formed in the second groove.

[0123] In this embodiment, before forming the second groove, the first dielectric layer 204 is further thinned; the thinning process includes a mechanical chemical polishing process.

[0124] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 12, comprising: a drain doping layer, the drain doping layer comprising a first drain doping region 201, an isolation structure 202 and a second drain doping region 203, the isolation structure 202 being located between the first drain doping region 201 and the second drain doping region 203, the first drain doping region 202 and the second drain doping region 203 having different conductivity types; a first body region 222 located on the first drain doping region, and a first source doping region 223 on the surface of the first body region 222; a second body region 224 located on the second drain doping region 203, and a second source doping region 225 on the surface of the second body region 224; a first groove 221 (such as a groove 221) located on the surface of the drain doping layer and between the first body region 222 and the second body region 224 and between the first source doping region 223 and the second source doping region 225. Figure 9 a gate structure located in the first groove 221 , the gate structure comprising a gate layer 230 , the gate layer 230 being located between the first body region 222 and the second body region 224 .

[0125] At this point, the semiconductor structure is a CMOS device, in which the first drain doping region, the first body region and the first source doping region of one MOS device, and the second drain doping region, the second body region and the second source doping region of the other MOS device are all distributed vertically. Compared with the lateral CMOS device, since there is no parasitic JFET region, it is beneficial to reduce the on-resistance of the device and reduce the power loss of the device.

[0126] In this embodiment, the gate layer 230 is also located between the first source doping region 223 and the second source doping region 225 .

[0127] In this embodiment, the semiconductor structure further includes: a first drift region 226, the first drift region 226 is located between the surface of the first drain-doped region 201 and the first body region 222, the conductivity type of the first drift region 226 is the same as the conductivity type of the first drain-doped region 201, and the doping concentration of the first drift region 226 is lower than the doping concentration of the first drain-doped region 201; a second drift region 227, the second drift region 227 is located between the surface of the second drain-doped region 203 and the second body region 224, the conductivity type of the second drift region 227 is the same as the conductivity type of the second drain-doped region 203, and the doping concentration of the second drift region 227 is lower than the doping concentration of the second drain-doped region 203.

[0128] Here, the presence of the first drift region 226 and the second drift region 227 improves the voltage resistance of the CMOS device. The voltage resistance of the CMOS device depends on the longitudinal dimensions of the first drift region 226 and the second drift region 227, rather than the lateral dimensions. Therefore, under the same voltage resistance requirements, the device size can be effectively reduced compared to the lateral CMOS device.

[0129] In this embodiment, the gate layer 230 is also located between a portion of the first drift region 226 and a portion of the second drift region 227 .

[0130] In this embodiment, the gate structure further includes a shielding gate 228 . The shielding gate 228 is located between a portion of the first drift region 226 and a portion of the second drift region 227 , and the gate layer 230 is located above the shielding gate 228 .

[0131] Here, the shielding gate 228 is helpful to reduce the parasitic capacitance and on-resistance of the CMOS device, thereby improving the performance of the CMOS device.

[0132] In this embodiment, the gate structure further includes a shielding gate dielectric layer 229 . The shielding gate dielectric layer 229 is located between the shielding gate 228 and the first drift region 226 , the second drift region 227 , and the drain doping layer.

[0133] In this embodiment, the gate structure further includes: a gate dielectric layer 231, the gate dielectric layer 231 is located between the gate layer 230 and the first groove 221 (such as Figure 9 As shown) side wall and the shielding grid 228.

[0134] In this embodiment, the semiconductor structure further includes: a gate conductive layer 233 located on a surface of a portion of the gate layer 230 ; a first source conductive layer 234 located on a surface of a portion of the first source doping region 223 ; and a second source conductive layer 235 located on a surface of a portion of the second source doping region 225 .

[0135] In this embodiment, the drain doped layer includes a first surface 200 a and a second surface 200 b opposite to each other, and the first body region 222 , the second body region 224 and the first groove 221 are all located on the first surface 200 a .

[0136] In this embodiment, the semiconductor structure further includes: a first dielectric layer 204 located on the second surface 200b; a second groove (not shown in the figure) located in the first dielectric layer 204, the second groove exposing a portion of the first source doped region 201 and a portion of the second drain doped region 203; and a drain conductive layer 232 located in the second groove.

[0137] Figure 13 FIG. 1 is a schematic diagram of a semiconductor structure inverter circuit connection according to an embodiment of the present invention.

[0138] Accordingly, an embodiment of the present invention further provides an inverter circuit, wherein the inverter circuit includes the semiconductor structure described above. Figure 12 Based on the reference Figure 13, wherein one of the first source doping region 223 and the second source doping region 225 is connected to the power supply VDD, and the other is grounded GND, the gate layer is connected to the input terminal Vin, and the first drain doping region 201 and the second drain doping region 203 are connected to the output terminal Vout.

[0139] Specifically, one of the first source conductive layer 234 and the second source conductive layer 235 is connected to the power supply VDD, and the other is connected to the ground GND. The gate conductive layer 233 is connected to the input terminal Vin, and the drain conductive layer 232 is connected to the output terminal Vout.

[0140] In this embodiment, the first source doping region 223 is connected to the ground GND, and the second source doping region 225 is connected to the power supply VDD. In another embodiment, the first source doping region may be connected to the power supply VDD, and the second source doping region may be connected to the ground GND.

[0141] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a drain-doped layer, the drain-doped layer comprising a first drain-doped region, an isolation structure, and a second drain-doped region, the isolation structure being located between the first drain-doped region and the second drain-doped region, the first drain-doped region and the second drain-doped region having different conductivity types; a first body region located on the first drain doped region, and a first source doped region on the surface of the first body region; a second body region located on the second drain doped region, and a second source doped region on the surface of the second body region; a first groove located on the surface of the drain doped layer and between the first body region and the second body region and between the first source doped region and the second source doped region; A gate structure is located in the first groove, wherein the gate structure includes a gate layer, and the gate layer is located between the first body region and the second body region.

2. The semiconductor structure according to claim 1, wherein Also includes: a first drift region, wherein the first drift region is located between the surface of the first drain-doped region and the first body region, the conductivity type of the first drift region is the same as the conductivity type of the first drain-doped region, and the doping concentration of the first drift region is lower than the doping concentration of the first drain-doped region; and a second drift region, wherein the second drift region is located between the surface of the second drain-doped region and the second body region, the conductivity type of the second drift region is the same as the conductivity type of the second drain-doped region, and the doping concentration of the second drift region is lower than the doping concentration of the second drain-doped region.

3. The semiconductor structure according to claim 2, wherein: The gate layer is further located between the first source doping region and the second source doping region; the gate layer is further located between a portion of the first drift region and a portion of the second drift region.

4. The semiconductor structure according to claim 3, wherein: The gate structure also includes: a shielding gate, which is located between part of the first drift region and part of the second drift region, and the gate layer is located above the shielding gate; a gate dielectric layer, which is located between the gate layer and the sidewall of the first groove and the shielding gate; and a shielding gate dielectric layer, which is located between the shielding gate and the first drift region, the second drift region, and the drain doping layer.

5. The semiconductor structure according to claim 1, wherein The drain doped layer includes a first surface and a second surface opposite to each other, and the first body region, the second body region and the first groove are all located on the first surface; The semiconductor structure further includes: a gate conductive layer located on a portion of the surface of the gate layer; a first source conductive layer located on a portion of the surface of the first source doped region; a second source conductive layer located on a portion of the surface of the second source doped region; a first dielectric layer located on the second surface; a second groove located in the first dielectric layer, the second groove exposing a portion of the first source doped region and a portion of the second drain doped region; and a drain conductive layer located in the second groove.

6. A method for forming a semiconductor structure, characterized in that: include: forming a drain-doped layer, the drain-doped layer comprising a first drain-doped region, an isolation structure, and a second drain-doped region, the isolation structure being located between the first drain-doped region and the second drain-doped region, the first drain-doped region and the second drain-doped region having different conductivity types; forming a first body region on the first drain doped region, and forming a first source doped region on a surface of the first body region; forming a second body region on the second drain doped region, and forming a second source doped region on a surface of the second body region; forming a first groove on the surface of the drain doped layer, between the first body region and the second body region, and between the first source doped region and the second source doped region; A gate structure is formed in the first groove, wherein the gate structure includes a gate layer, and the gate layer is located between the first body region and the second body region.

7. The method for forming a semiconductor structure according to claim 6, wherein: The drain doped layer includes a first surface and a second surface opposite to each other; the first body region, the second body region and the first groove are all formed on the first surface; The method further includes: forming a first dielectric layer on the second surface; forming a second groove in the first dielectric layer, wherein the second groove exposes a portion of the first source doping region and a portion of the second drain doping region; and forming a drain conductive layer in the second groove.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the drain doped layer and the first dielectric layer includes: providing a substrate, the substrate including a first initial surface and a second initial surface; forming the first dielectric layer on the second initial surface; etching a portion of the substrate from the first initial surface until it penetrates the substrate to form a third groove in the substrate; forming the isolation structure in the third groove; and forming the drain doped layer using the substrate, with the first initial surface serving as the first surface and the second initial surface serving as the second surface.

9. The method for forming a semiconductor structure according to claim 8, wherein: The substrate and the first source doping region have the same conductivity type and doping concentration; forming the drain doping layer with the substrate includes: using the substrate on one side of the isolation structure as the first drain doping region; injecting second doping ions into the substrate on the other side of the isolation structure, the conductivity type of the second doping ions being different from the conductivity type of the substrate, to form the second drain doping region.

10. The method for forming a semiconductor structure according to claim 8, wherein: The substrate and the second source doping region have the same conductivity type and doping concentration; the formation of the drain doping layer using the substrate includes: using the substrate on one side of the isolation structure as the second drain doping region; injecting first doping ions into the substrate on the other side of the isolation structure, the conductivity type of the first doping ions being different from the conductivity type of the substrate, to form the first drain doping region.

11. The method for forming a semiconductor structure according to claim 8, wherein: The substrate is an intrinsic semiconductor, or the conductivity type of the substrate is the same as the conductivity type of the first drain-doped region, but the doping concentration of the substrate is lower than the doping concentration of the first drain-doped region, or the conductivity type of the substrate is the same as the conductivity type of the second drain-doped region, but the doping concentration of the substrate is lower than the doping concentration of the second drain-doped region; forming the drain-doped layer with the substrate includes: implanting first doping ions into the substrate on one side of the isolation structure to form the first drain-doped region; and implanting second doping ions into the substrate on the other side of the isolation structure to form the second drain-doped region.

12. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the first body region, the second body region, the first source doping region, the second source doping region and the first groove includes: forming a first epitaxial layer on the surface of the drain-doped layer; performing a first doping treatment on the first epitaxial layer to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain-doped region, and forming a second initial body region and a second initial source doping region located on the second initial body region on the second drain-doped region; etching part of the first initial source doping region, part of the second initial source doping region, part of the first initial body region and part of the second initial body region until the drain-doped layer is exposed to form the first groove and form the first body region with the first initial body region, form the first source doping region with the first initial source doping region, form the second body region with the second initial body region, and form the second source doping region with the second initial source doping region; the first groove has a first projection on the surface of the drain-doped layer, the isolation structure has a second projection on the surface of the drain-doped layer, and the second projection is located within the range of the first projection.

13. The method for forming a semiconductor structure according to claim 12, wherein: The first epitaxial layer and the first drain doping region have the same conductivity type, and the doping concentration of the first epitaxial layer is lower than the doping concentration of the first drain doping region; the first epitaxial layer is subjected to a first doping treatment to form a first initial body region on the first drain doping region and a first initial source doping region located on the first initial body region, and to form a second initial body region on the second drain doping region and a second initial source doping region located on the second initial body region, comprising: implanting third doping ions into the first epitaxial layer on the first drain doping region, wherein the conductivity type of the third doping ions is different from the conductivity type of the first drain doping region, so as to form the first initial body region in the first epitaxial layer ; Injecting fourth doping ions into the first epitaxial layer on the first drain-doping region, the injection depth of the third doping ions is greater than the injection depth of the fourth doping ions, and the conductivity type of the fourth doping ions is the same as the conductivity type of the first drain-doping region, so as to form a first source doping region on the first initial body region; Injecting fifth doping ions into the first epitaxial layer on the second drain-doping region, the injection depth of the fifth doping ions is lower than the thickness of the first epitaxial layer, and the conductivity type of the fifth doping ions is the same as the conductivity type of the second drain-doping region, so as to form the second initial body region on the second drain-doping region and a second initial source doping region located on the second body region.

14. The method for forming a semiconductor structure according to claim 12, wherein: The first epitaxial layer and the second drain doping region have the same conductivity type and doping concentration; the first epitaxial layer is subjected to a first doping treatment to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain doping region, and a second initial body region and a second initial source doping region located on the second initial body region on the second drain doping region, comprising: injecting a sixth doping ion into the first epitaxial layer on the second drain doping region, wherein the conductivity type of the sixth doping ion is different from the conductivity type of the second drain doping region, so as to form the second initial body region in the first epitaxial layer; and injecting a sixth doping ion into the first epitaxial layer on the second drain doping region. Fifth doping ions are implanted into the first epitaxial layer, the implantation depth of the sixth doping ions is greater than the implantation depth of the fifth doping ions, and the conductivity type of the fifth doping ions is the same as the conductivity type of the second drain doping region, so as to form a second initial source doping region on the second initial body region; fourth doping ions are implanted into the first epitaxial layer on the first drain doping region, the implantation depth of the fourth doping ions is lower than the thickness of the first epitaxial layer, and the conductivity type of the fourth doping ions is the same as the conductivity type of the first drain doping region, so as to form the first initial body region and the first initial source doping region located on the first initial body region on the first drain doping region.

15. The method for forming a semiconductor structure according to claim 12, wherein: The first epitaxial layer is an intrinsic semiconductor; the first doping treatment is performed on the first epitaxial layer to form a first initial body region and a first initial source doping region located on the first initial body region on the first drain-doping region, and to form a second initial body region and a second initial source doping region located on the second initial body region on the second drain-doping region, including: injecting third doping ions into the first epitaxial layer on the first drain-doping region; injecting sixth doping ions into the first epitaxial layer on the second drain-doping region; injecting fourth doping ions into the first epitaxial layer on the first drain-doping region, the injection depth of the third doping ions being greater than the injection depth of the fourth doping ions, so as to form the first initial body region and the first initial source doping region located on the first initial body region on the first drain-doping region; injecting fifth doping ions into the first epitaxial layer on the second drain-doping region, the injection depth of the sixth doping ions being greater than the injection depth of the fifth doping ions, so as to form the second initial body region and the second initial source doping region located on the second drain-doping region.

16. The method for forming a semiconductor structure according to claim 12, wherein: The method further includes: forming a first drift region between the surface of the first drain doping region and the first body region; forming a second drift region between the surface of the second drain doping region and the second body region; and the first groove is also formed between the first drift region and the second drift region.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the first drift region and the second drift region includes: before forming the first epitaxial layer, forming a second epitaxial layer on the surface of the drain doping layer; performing a second doping treatment on the second epitaxial layer to form a first initial drift region on the surface of the first drain doping region, and forming a second initial drift region on the surface of the second drain doping region, the conductivity type of the first initial drift region is the same as the conductivity type of the first drain doping region, and the doping concentration of the first initial drift region is lower than the doping concentration of the first drain doping region, the conductivity type of the second initial drift region is the same as the conductivity type of the second drain doping region, and the doping concentration of the second initial drift region is lower than the doping concentration of the second drain doping region; after etching the first initial body region and the second initial body region, further etching part of the first initial drift region and part of the second initial drift region, forming the first drift region with the first initial drift region, and forming the second drift region with the second initial drift region.

18. The method for forming a semiconductor structure according to claim 17, wherein: The conductivity type of the second epitaxial layer is the same as the conductivity type of the first drain-doped region; the second doping treatment is performed on the second epitaxial layer to form a first initial drift region on the surface of the first drain-doped region, and the second initial drift region is formed on the surface of the second drain-doped region, including: injecting eighth doping ions into the second epitaxial layer on the second drain-doped region, the conductivity type of the eighth doping ions is the same as the conductivity type of the second drain-doped region, the second epitaxial layer on the first drain-doped region is the first initial drift region, and the second epitaxial layer on the second drain-doped region is the second initial drift region.

19. The method for forming a semiconductor structure according to claim 17, wherein: The conductivity type of the second epitaxial layer is the same as the conductivity type of the second drain-doped region; the second doping treatment is performed on the second epitaxial layer to form a first initial drift region on the surface of the first drain-doped region, and the second initial drift region is formed on the surface of the second drain-doped region, including: injecting seventh doping ions into the second epitaxial layer on the first drain-doped region, the conductivity type of the seventh doping ions is the same as the conductivity type of the first drain-doped region, the second epitaxial layer on the first drain-doped region is the first initial drift region, and the second epitaxial layer on the second drain-doped region is the second initial drift region.

20. The method for forming a semiconductor structure according to claim 17, wherein: The second epitaxial layer is an intrinsic semiconductor; the second doping treatment is performed on the second epitaxial layer to form a first initial drift region on the surface of the first drain doping region, and the second initial drift region is formed on the surface of the second drain doping region, including: injecting seventh doping ions into the second epitaxial layer on the first drain doping region, the conductivity type of the seventh doping ions is the same as the conductivity type of the first drain doping region, and the epitaxial layer on the first drain doping region is the first initial drift region; injecting eighth doping ions into the second epitaxial layer on the second drain doping region, the conductivity type of the eighth doping ions is the same as the conductivity type of the second drain doping region, and the second epitaxial layer on the second drain doping region is the second initial drift region.

21. The method for forming a semiconductor structure according to claim 16, wherein: The gate layer is further located between a portion of the first drift region and a portion of the second drift region; the gate layer is further located between the first source doping region and the second source doping region; the gate structure further includes a shielding gate, the shielding gate is located between a portion of the first drift region and a portion of the second drift region, and the gate layer is located above the shielding gate; The method for forming the gate structure includes: forming the shielding gate in the first groove; The gate layer is formed on the shielding gate.

22. The method for forming a semiconductor structure according to claim 21, wherein: The gate structure further includes a shielding gate dielectric layer, wherein the shielding gate dielectric layer is located between the shielding gate and the first drift region, the second drift region, and the drain doping layer; The method for forming the shielding gate dielectric layer and the shielding gate includes: forming a second dielectric material layer on the surface of the first source doping region, the surface of the second source doping region and in the first groove; forming a first gate material layer on the surface of the second dielectric material layer; planarizing the first gate material layer and the second dielectric material layer until the surface of the first source doping region and the surface of the second source doping region are exposed; etching back the first gate material layer so that the top surface of the first gate material layer is lower than the surface of the first drift region and lower than the surface of the second drift region to form the shielding gate, and forming a shielding gate dielectric layer with the second dielectric material layer between the shielding gate and the first drift region, the second drift region, and the drain doping layer.

23. The method for forming a semiconductor structure according to claim 22, wherein: The gate structure further includes: a gate dielectric layer, wherein the gate dielectric layer is located between the gate layer and the sidewall of the first groove and the shield gate; a method for forming the gate dielectric layer and the gate layer includes: after forming the shield gate, forming a third dielectric material layer on the surface of the first source doping region, the surface of the second source doping region, and in the first groove; forming a second gate material layer on the surface of the third dielectric material layer; planarizing the second gate material layer and the third dielectric material layer until the surface of the first source doping region and the surface of the second source doping region are exposed, using the second gate material layer in the first groove as the gate layer, and using the third dielectric material layer between the gate layer and the sidewall of the first groove and the shield gate as the gate dielectric layer.

24. The method for forming a semiconductor structure according to claim 6, wherein: Also includes: forming a gate conductive layer on a portion of the surface of the gate layer; forming a first source conductive layer on a portion of the surface of the first source doped region; A second source conductive layer is formed on a portion of the surface of the second source doping region.

25. An inverter circuit, characterized in that: The inverter circuit comprises the semiconductor structure according to any one of claims 1 to 5, wherein one of the first source doping region and the second source doping region is connected to a power supply and the other is grounded, the gate layer is connected to an input end, and the first drain doping region and the second drain doping region are connected to an output end.

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