A hetero-channel ring-gate device and a preparation method thereof

Abstract

The application discloses a hetero-channel ring gate device and a preparation method thereof, which comprises: an NMOS device and a PMOS device arranged adjacently, wherein the NMOS device and the PMOS device are respectively provided with a gate structure enclosed on the side surface of the channel; the channel material of the NMOS device is different from the channel material of the PMOS device; and the composition and material of the work function layer in the gate structure of the NMOS device are the same as the composition and material of the work function layer in the gate structure of the PMOS device. The application is advantageous for improving the carrier mobility of the PMOS and improving the on-state current of the device by making the NMOS and the PMOS have a hetero-channel, and is advantageous for realizing the same set of work function gate materials for the NMOS and the PMOS by the combination of the hetero-channel, so as to simplify the gate stack process of the ring gate device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuit process, and in particular to a hetero-channel ring-gate device and a preparation method thereof. BACKGROUND

[0002] At present, the development of integrated circuit process has encountered some bottlenecks. With the transistor size gradually approaching the physical limit, the quantum effect and parasitic effect cause the power density to increase, resulting in the increasing difficulty and cost of research and development of transistor size proportional micro-etching. Therefore, in recent years, the improvement speed of integration has gradually fallen behind the prediction of "Moore's Law", and the industry has entered the "post-Moore era".

[0003] In the "post-Moore era", the related research on integrated circuits has changed from the original planar process to the vertical direction, including the research of advanced process nodes such as Nanosheet (nanosheet), Forksheet (fork plate) after FinFET, hoping to continue "Moore's Law" in the vertical direction of integrated devices or chips.

[0004] At present, in the 2 / 3nm node, the ring-gate device technology is entering. Different from the FinFET channel surrounded by the gate on three sides, the ring-gate device is surrounded by the gate on four sides, and is therefore called ring-gate device. However, the gate stack process of the traditional ring-gate device needs to process the work function layer of the NMOS gate and the work function layer of the PMOS gate respectively due to the use of the same Si material channel for NMOS and PMOS, which not only causes the complication of the process, but also makes the distance between NMOS and PMOS subject to the thickness of the work function layer of PMOS, thereby affecting the micro-etching of the device.

[0005] Therefore, it is necessary to provide a new type of ring-gate device and its gate stack technology to solve the above problems existing in the prior art. SUMMARY

[0006] The present application aims to overcome the above-mentioned defects existing in the prior art, and provides a hetero-channel ring-gate device and a preparation method thereof.

[0007] To achieve the above-mentioned purpose, the technical solution of the present application is as follows:

[0008] The application provides a hetero-channel ring-gate device, comprising: an NMOS device and a PMOS device arranged adjacently, the NMOS device and the PMOS device are respectively provided with a gate structure enclosed on the side of the respective channel, the channel material of the NMOS device is different from the channel material of the PMOS device, and the composition and material of the work function layer in the gate structure of the NMOS device are the same as the composition and material of the work function layer in the gate structure of the PMOS device.

[0009] Further, the NMOS device and the PMOS device are arranged adjacently on one side of a substrate, the NMOS device is provided with a first channel and a first gate structure enclosed on the side of the first channel, the first gate structure is provided with a first work function layer, the first work function layer comprises a plurality of first sub-work function layers, the PMOS device is provided with a second channel and a second gate structure enclosed on the side of the second channel, the second gate structure is provided with a second work function layer, the second work function layer comprises a plurality of second sub-work function layers, the material of the first channel is a first semiconductor, the material of the second channel is a second semiconductor different from the first semiconductor, each first sub-work function layer is arranged correspondingly to each second sub-work function layer, and the material of each first sub-work function layer is the same as the material of a corresponding second sub-work function layer.

[0010] Further, the first gate structure is further provided with a first gate metal layer enclosed on the outside of the first work function layer, the second gate structure is further provided with a second gate metal layer enclosed on the outside of the second work function layer, and the first gate metal layer and the second gate metal layer are connected between the NMOS device and the PMOS device.

[0011] Further, the NMOS device comprises a plurality of first channels arranged in parallel in sequence away from the substrate, the side of each first channel is sequentially enclosed with the first work function layer and the first gate metal layer, the PMOS device comprises a plurality of second channels arranged in parallel in sequence away from the substrate, the side of each second channel is sequentially enclosed with the second work function layer and the second gate metal layer, the first gate metal layer is further filled between any two adjacent first channels, the second gate metal layer is further filled between any two adjacent second channels, and the first gate metal layer and the second gate metal layer are further filled between the first channel and the second channel to be closely connected.

[0012] Further, the material of the first gate metal layer is the same as the material of the second gate metal layer, forming a gate metal layer shared by the first gate structure and the second gate structure.

[0013] Further, the first channel and the second channel have the same cross-sectional size, the first work function layer and the second work function layer have the same thickness, or the thickness of each first sub-work function layer is the same as the thickness of a corresponding second sub-work function layer; and / or, the first channel and the second channel are arranged in a staggered manner away from the substrate.

[0014] Further, the first semiconductor comprises Si, and the second semiconductor comprises SiGe; and / or, the first sub-work function layer and the second sub-work function layer are three layers, and sequentially comprise a TiN layer, a TiAl layer and a TiN layer from inside to outside; and / or, the first channel and the first work function layer, and the second channel and the second work function layer are respectively sequentially provided with a SiO2 layer and a HfO2 layer from inside to outside.

[0015] Further, the thickness of the TiN layer is 1-2 nm, the thickness of the TiAl layer is 3-4 nm, and the thickness of the TiN layer is 1-2 nm, or the thickness of the first work function layer and the second work function layer is 8-11 nm; the thickness of the SiO2 layer is less than 1 nm, and the thickness of the HfO2 layer is 1-2 nm.

[0016] Further, the hetero-channel ring gate device comprises an inverter.

[0017] The application further provides a preparation method of a hetero-channel ring gate device, comprising:

[0018] forming the adjacent NMOS device and PMOS device, so that the NMOS device and the PMOS device are respectively formed with a gate structure enclosed on the side of the respective channel, the channel material of the NMOS device is different from the channel material of the PMOS device, and the composition and material of the work function layer in the gate structure of the NMOS device are the same as the composition and material of the work function layer in the gate structure of the PMOS device.

[0019] Further, the forming method of the NMOS device and PMOS device specifically comprises:

[0020] providing a substrate;

[0021] forming the first channel of the NMOS device and the second channel of the PMOS device on one side of the substrate; the material of the first channel is a first semiconductor, and the material of the second channel is a second semiconductor different from the first semiconductor;

[0022] forming a first gate structure enclosing the first channel side and a second gate structure enclosing the second channel side; the first gate structure comprises a first work function layer, the first work function layer comprises a plurality of first sub work function layers, the second gate structure is provided with a second work function layer, the second work function layer comprises a plurality of second sub work function layers, each first sub work function layer is provided correspondingly to each second sub work function layer, and the material of each first sub work function layer is the same as the material of the corresponding second sub work function layer.

[0023] Further, the forming method of the first channel and the second channel specifically comprises:

[0024] alternately forming a plurality of second semiconductor layers and a plurality of first semiconductor layers on the surface of the substrate with the first semiconductor material;

[0025] performing patterning on the second semiconductor layers and the first semiconductor layers to form a plurality of fins on the surface of the substrate, including adjacent first fins and second fins, and forming isolation trenches downward on the surface of the substrate on both sides of the fins;

[0026] forming a first dielectric layer on the surface of the substrate to fill the isolation trenches;

[0027] forming a dummy gate across the first fins and the second fins, and an outer spacer layer covering the dummy gate, the first fins and the second fins, and then removing the first fins and the second fins exposed on both sides of the dummy gate;

[0028] at least partially removing the second semiconductor layer material exposed on both ends of the first fins and the first semiconductor layer material exposed on both ends of the second fins to form recesses, and then forming inner spacers in the recesses;

[0029] forming first source-drains on both ends of the first semiconductor layer exposed by the first fins and second source-drains on both ends of the second semiconductor layer exposed by the second fins;

[0030] forming an opening on the top of the outer spacer layer to expose the top of the dummy gate below, then removing the dummy gate to form a cavity, and removing the second semiconductor layer material remaining on the first fins and the first semiconductor layer material remaining on the second fins, so that a plurality of first channels are formed correspondingly by a plurality of the first semiconductor layers on the first fins, and a plurality of second channels are formed correspondingly by a plurality of the second semiconductor layers on the second fins.

[0031] Further, the forming method of the first gate structure and the second gate structure specifically comprises:

[0032] forming a work function layer comprising a plurality of sub work function layers on the side of the first channel and the second channel in the cavity, wherein the sub work function layer on the side of the first channel is the first sub work function layer, and the sub work function layer on the side of the second channel is the second sub work function layer;

[0033] and filling a gate metal layer in the cavity.

[0034] Further, the first semiconductor comprises Si, and the second semiconductor comprises SiGe; and / or, the number of the sub work function layers is three, and the sub work function layers comprise a TiN layer, a TiAl layer and a TiN layer from inside to outside.

[0035] Further, before forming the work function layer, the method further comprises: sequentially forming a SiO2 layer and a HfO2 layer on the side of the first channel and the second channel in the cavity, and then forming the work function layer on the HfO2 layer.

[0036] Further, after forming the gate metal layer, the method further comprises: forming a cover layer on the opening to close the gate metal layer.

[0037] As can be seen from the above technical solution, the present application uses different channel materials (for example, the first channel material of the NMOS device uses Si, and the second channel material of the PMOS device uses SiGe) to integrate the NMOS device and the PMOS device, so that the NMOS and the PMOS have a hetero channel, which is conducive to improving the carrier mobility of the PMOS, thereby improving the on-state current of the device, and is conducive to using the same set of work function gate material for the NMOS and the PMOS through the combination of the hetero channel, thereby simplifying the gate stack process of the ring gate device. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 FIG. 1 is a structure schematic diagram of a hetero channel ring gate device according to a preferred embodiment of the present application.

[0039] Figure 2 FIG. 3 is a flow chart of a preparation method of a hetero channel ring gate device according to a preferred embodiment of the present application.

[0040] Figures 3-24 FIG. 5 is a process step schematic diagram of a hetero channel ring gate device prepared according to the method of a preferred embodiment of the present application. Figure 2

[0041] Figure 25 FIG. 6 is a ring gate structure schematic diagram of a hetero channel ring gate device according to a preferred embodiment of the present application.

[0042] ​Figure 26 Fig. 1 is a schematic diagram of a ring gate structure of a conventional homogenous channel ring gate device. DETAILED DESCRIPTION

[0043] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall into the scope of the present application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as their common meanings to those of ordinary skill in the art to which the present application belongs. The words "comprise", "comprising", "include", "including" and the like used herein mean the elements or objects before the word "comprise", "comprising", "include", "including" and the like encompass the elements or objects listed after the word "comprise", "comprising", "include", "including" and the like and equivalents thereof, and do not exclude other elements or objects.

[0044] The specific embodiments of the present application will be described further in detail below with reference to the accompanying drawings.

[0045] Reference Figure 1 and Figure 25 , Figure 1 Fig. 1 is a schematic diagram of a ring gate structure of a conventional homogenous channel ring gate device. Figure 25 Fig. 1 is a schematic diagram of a ring gate structure of a conventional homogenous channel ring gate device. Figure 1 and Figure 25 As shown in Figs. 1 and 2, a heterogenous channel ring gate device of the present application comprises: an NMOS device and a PMOS device arranged adjacently. The NMOS device and the PMOS device are respectively provided with a channel and a gate structure enclosed on the side of the respective channel. The material of the channel of the NMOS device is different from the material of the channel of the PMOS device; and the composition and material of the work function layer in the gate structure of the NMOS device are the same as the composition and material of the work function layer in the gate structure of the PMOS device.

[0046] Reference Figure 1 and Figure 25 In some embodiments, the NMOS device and the PMOS device are arranged adjacently on one side of the substrate 10. Figure 1 Fig. 1 shows a structure in which the NMOS device and the PMOS device are arranged adjacently on the upper surface of the substrate 10.

[0047] The channel of the NMOS device is defined as the first channel 13, the gate structure of the NMOS device is defined as the first gate structure 14, and the first gate structure 14 is enclosed on the side of the first channel 13. That is, the four sides of the first channel 13 are surrounded by the first gate structure 14. The channel of the PMOS device is defined as the second channel 18, the gate structure of the PMOS device is defined as the second gate structure 17, and the second gate structure 17 is enclosed on the side of the second channel 18. That is, the four sides of the second channel 18 are surrounded by the second gate structure 17.

[0048] In some embodiments, the first gate structure 14 of the NMOS device is provided with a first work function layer 141 enclosed on the side of the first channel 13, and the first work function layer 141 includes a plurality of first sub-work function layers 1411 enclosed on the side of the first channel 13 in sequence. That is, the four sides of the first channel 13 are surrounded by the first work function layer 141 and the first sub-work function layers 1411 thereof. The second gate structure 17 of the PMOS device is provided with a second work function layer 172 enclosed on the side of the second channel 18, and the second work function layer 172 includes a plurality of second sub-work function layers 1721 enclosed on the side of the second channel 18 in sequence. That is, the four sides of the second channel 18 are surrounded by the second work function layer 172 and the second sub-work function layers 1721 thereof.

[0049] In some embodiments, the material of the first channel 13 is a first semiconductor, and the material of the second channel 18 is a second semiconductor different from the first semiconductor material. Therefore, the channel material of the NMOS device is different from the channel material of the PMOS device, forming a heterojunction channel ring gate device structure.

[0050] In some embodiments, each first sub-work function layer 1411 of the first gate structure 14 is provided in correspondence with each second sub-work function layer 1721 of the second gate structure 17, and the material of each first sub-work function layer 1411 is the same as the material of the corresponding second sub-work function layer 1721. In other words, the number of layers of the first sub-work function layers 1411 is the same as the number of layers of the second sub-work function layers 1721, and the material of the first sub-work function layer 1411 at the same layer is the same as the material of the second sub-work function layer 1721 at the same layer.

[0051] In some embodiments, the material of any two adjacent first sub-work function layers 1411 is different. The material of any two adjacent second sub-work function layers 1721 is different.

[0052] In some embodiments, the first gate structure 14 is further provided with a first gate metal layer 142 which encloses the first work function layer 141. That is, the four sides of the first channel 13 are surrounded by the first gate metal layer 142. The second gate structure 17 is further provided with a second gate metal layer 171 which encloses the second work function layer 172. That is, the four sides of the second channel 18 are surrounded by the second gate metal layer 171. Moreover, the first gate metal layer 142 and the second gate metal layer 171 are connected between the NMOS device and the PMOS device. In the present embodiment, the first gate metal layer 142 and the second gate metal layer 171 are closely connected and integrated between the NMOS device and the PMOS device.

[0053] Reference Figure 1 and Figure 25 In some embodiments, the NMOS device includes a plurality of first channels 13 which are arranged in parallel in sequence away from the upper surface of the substrate 10, and each of the first channels 13 has a first work function layer 141 and a first gate metal layer 142 which are enclosed in sequence on the side of the first channel 13. The PMOS device includes a plurality of second channels 18 which are arranged in parallel in sequence away from the upper surface of the substrate 10, and each of the second channels 18 has a second work function layer 172 and a second gate metal layer 171 which are enclosed in sequence on the side of the second channel 18. The first gate metal layer 142 further fills between any two adjacent first channels 13, the second gate metal layer 171 further fills between any two adjacent second channels 18, and the first gate metal layer 142 and the second gate metal layer 171 further fill between the first channels 13 and the second channels 18, so that the first gate metal layer 142 and the second gate metal layer 171 are closely connected and integrated.

[0054] In some embodiments, the material of the first gate metal layer 142 is the same as the material of the second gate metal layer 171. By the integrated and homogeneous first gate metal layer 142 and second gate metal layer 171, a gate metal layer 38 which is shared by the first gate structure 14 and the second gate structure 17 is formed, thereby forming a gate stack structure of the hetero-channel ring-gate device on the surface of the substrate 10. The present application can realize multi-threshold voltage through the ring-gate device. It is to be noted that the present application does not limit the number of the stack layers in the gate stack structure, i.e., the number of the first channel 13 / first gate structure 14 and the second channel 18 / second gate structure 17.

[0055] In some embodiments, the cross-sectional size of the first channel 13 is the same as the cross-sectional size of the second channel 18. For example, the first channel 13 has the same cross-sectional width and height as the second channel 18.

[0056] In some embodiments, the thickness of the first work function layer 141 is the same as the thickness of the second work function layer 172.

[0057] Further, the thickness of each first sub-work function layer 1411 of the first work function layer 141 is the same as the thickness of a corresponding one of the second sub-work function layers 1721 of the second work function layer 172.

[0058] In some other embodiments, the cross-sectional dimension of the first channel 13 and the cross-sectional dimension of the second channel 18 can be different. For example, the first channel 13 has a different cross-sectional width and height than the second channel 18.

[0059] In some embodiments, the first channel 13 and the second channel 18 are arranged staggered in a direction away from the upper surface of the substrate 10, as shown. Figure 1 For example, the spacing between two adjacent first channels 13 in the up-down direction can correspond to the height of the second channel 18, or the spacing between two adjacent second channels 18 in the up-down direction can correspond to the height of the first channel 13, then in the vertical projection plane, the first channel 13 and the second channel 18 will be arranged in the vertical direction in turn and alternately.

[0060] In some embodiments, the first semiconductor includes Si, and the second semiconductor includes SiGe. The substrate 10 includes a Si substrate 10 of the first semiconductor material.

[0061] Referring to Figure 1 and Figure 25 In some embodiments, the number of the first sub-work function layers 1411 and the second sub-work function layers 1721 is three, and the first sub-work function layers 1411 and the second sub-work function layers 1721 include a TiN layer, a TiAl layer and a TiN layer in turn from the inside to the outside. That is, in the gate stack structure, the three first sub-work function layers 1411 in the first work function layer 141 of the NMOS device and the three second sub-work function layers 1721 in the second work function layer 172 of the PMOS device are all TiN layer, TiAl layer and TiN layer arranged in turn from the inside to the outside, so that the composition and material of the work function layers of the NMOS device and the PMOS device are completely the same, forming a unified work function layer 37 and sub-work function layer 371 structure of the NMOS device and the PMOS device.

[0062] In some embodiments, between the first channel 13 and the first work function layer 141, and between the second channel 18 and the second work function layer 172, a SiO2 layer and a HfO2 layer are further arranged in turn from the inside to the outside, respectively. That is, the NMOS device and the PMOS device have unified SiO2 layer and HfO2 layer.

[0063] In some embodiments, the thickness of the SiO2 layer is less than 1 nm, and the thickness of the HfO2 layer is 1-2 nm.

[0064] The thickness of the TiN layer is 1-2 nm. The thickness of the TiAl layer is 3-4 nm. The thickness of the TiN layer is 1-2 nm.

[0065] In some embodiments, the first work function layer 141 and the second work function layer 172 have a thickness of about 8-11 nm.

[0066] In some embodiments, the Si substrate 10 has a trench isolation structure 12 on its surface. The trench isolation structure 12 is formed by filling the first dielectric layer 11 in the isolation trench.

[0067] In some embodiments, the NMOS device and the PMOS device have an outer sidewall 19 enclosing the gate structure on the side of the gate structure. In addition, the Si substrate 10 has a second dielectric layer 15 (ILD layer) on its surface, the second dielectric layer 15 enclosing the outer sidewall 19 on its side, and the second dielectric layer 15 being integral with the surface of the first dielectric layer 11 below.

[0068] In some embodiments, the NMOS device and the PMOS device have a cap layer 16 on the top of the gate structure, the cap layer 16 being connected to the top of the outer sidewall 19, so that the gate structure of the NMOS device and the PMOS device is isolated from the outside.

[0069] In some embodiments, the hetero-channel ring-gate device of the present application includes an inverter, but the present application is not limited thereto.

[0070] The preparation method of a hetero-channel ring-gate device of the present application is further described in detail below through specific embodiments and in conjunction with the accompanying drawings.

[0071] The preparation method of a hetero-channel ring-gate device of the present application comprises:

[0072] The NMOS device and the PMOS device are formed adjacent to each other, and the NMOS device and the PMOS device are respectively formed with a gate structure enclosing the channel side of each device. The channel material of the NMOS device is different from the channel material of the PMOS device, and the composition and material of the work function layer in the gate structure of the NMOS device are the same as the composition and material of the work function layer in the gate structure of the PMOS device.

[0073] Reference Figure 2 , Figure 2 The flow chart of the preparation method of a hetero-channel ring-gate device of a preferred embodiment of the present application. In some embodiments, the preparation method of a hetero-channel ring-gate device of the present application can be used to prepare, for example, a hetero-channel ring-gate device of the present application as shown in FIG. 1. Figure 1 The preparation method of a hetero-channel ring-gate device of the present application comprises the following steps:

[0074] Step S1: providing a substrate.

[0075] As shown in FIG. 1, the preparation method of a hetero-channel ring-gate device of the present application comprises the following steps: Figure 3As shown, a Si substrate 10 is used to fabricate the heterochannel gate-around device of the present invention on the substrate 10 through the gate stacking process of the heterochannel of the present invention.

[0076] Step S2: Fabricate the source and drain of the NMOS and PMOS devices.

[0077] like Figure 3 As shown, an epitaxial process is used to alternately form multiple SiGe layers and multiple Si layers on the surface of a Si substrate 10. The SiGe layers serve as the second semiconductor layer 181, and the Si layers serve as the first semiconductor layer 131. In this embodiment, an epitaxial process is used to alternately form three SiGe layers and two Si layers on the surface of the Si substrate 10, that is, to alternately form three second semiconductor layers 181 and two first semiconductor layers 131 on the surface of the Si substrate 10, with the topmost layer being a SiGe layer (second semiconductor layer 181), and its thickness being greater than the thickness of each of the underlying SiGe layers and each of the underlying Si layers.

[0078] Then, a patterning process is used to pattern the second semiconductor layer 181 and the first semiconductor layer 131, forming multiple fins on the surface of the Si substrate 10. Each fin includes adjacent first and second fins. Further patterning is then used to form isolation trenches downwards on the surface of the Si substrate 10 on both sides of the formed fins. In this embodiment, as... Figure 4 As shown, a first silicon oxide layer 201 and a first silicon nitride layer 202 are sequentially deposited on the surface of the topmost SiGe layer to serve as a first hard mask layer 20. Then, photoresist is spin-coated onto the surface of the first hard mask layer 20, and a first photoresist pattern 21 is formed on the surface of the first silicon nitride layer 202 using a photolithography process. Figure 5 As shown, an etching process is then used to form a first fin 22 and a second fin 23 on the surface of the Si substrate 10 through pattern transfer. Isolation trenches are then formed by etching downwards on the surface of the Si substrate 10 on both sides of the formed fins. In this embodiment, the first fin 22 and the second fin 23 consist of a five-layer patterned structure consisting of alternating layers of SiGe, Si, SiGe, SiGe, and SiGe from bottom to top. Afterwards, the remaining photoresist is removed, leaving a remaining patterned first hard mask layer 20 (including a patterned first silicon oxide layer 201 and a patterned first silicon nitride layer 202) on top of the fins.

[0079] like Figure 5As shown, next, a dielectric deposition process is used to deposit a first dielectric layer 11 on the surface of the Si substrate 10 to fill the isolation trench and to cover the pattern of the first hard mask layer 20 on top of the fin. Then, a planarization process, such as chemical mechanical polishing, is used to planarize the surface of the first dielectric layer 11 to expose the surface of the remaining first silicon nitride layer 202.

[0080] like Figure 6 As shown, the chemical mechanical polishing process is then used to thin the top of the first dielectric layer 11 until the surface of the uppermost SiGe layer on the first fin 22 and the second fin 23 is exposed on the surface of the thinned first dielectric layer 11, and the remaining thickness of the uppermost SiGe layer on the first fin 22 and the second fin 23 is consistent with (or substantially consistent with) the thickness of each SiGe layer below.

[0081] Next, the first dielectric layer 11 is selectively etched, for example, using a dielectric etch-back process to thin the first dielectric layer 11, reducing its surface to a height level flush with or substantially flush with the surface of the Si substrate 10, thereby forming a trench isolation structure 12 filled with the first dielectric layer 11. At this point, the first fin 22 and the second fin 23 are completely exposed on the surface of the Si substrate 10. Then, a dielectric protective layer 24 is deposited on the surface of the Si substrate 10 using a dielectric deposition process, covering the surface of the first dielectric layer 11 and the top and sides of the first fin 22 and the second fin 23, thus providing protection for the surfaces of the first fin 22 and the second fin 23.

[0082] like Figure 7 As shown, next, a deposition process is used to deposit, for example, a polysilicon layer 25 for forming a dummy gate, on the surface of the dielectric protective layer 24 (not shown, the same below), covering the top of the first fin 22 and the second fin 23, and a chemical mechanical polishing process is used to planarize the surface of the polysilicon layer 25. Then, a second silicon nitride layer 261 and a second silicon oxide layer 262 are sequentially deposited on the planar surface of the polysilicon layer 25 as a second hard mask layer 26. Afterwards, photoresist is spin-coated on the surface of the second hard mask layer 26, and a second photoresist pattern 27 is formed on the surface of the second silicon oxide layer 262 by a photolithography process.

[0083] like Figure 8 As shown, next, an etching process is used to pattern the polysilicon layer 25 through a pattern transfer method. After etching the polysilicon layer 25, a polysilicon dummy gate 251 is formed spanning the first fin 22 and the second fin 23. The two ends of the first fin 22 and the second fin 23 need to be exposed on both sides of the dummy gate 251. Afterward, the remaining photoresist is removed.

[0084] As shown in FIG. 2B, a second hard mask layer 26 is formed on the surface of the Si substrate 10. The second hard mask layer 26 is formed by depositing a second silicon nitride layer 261 on the surface of the Si substrate 10, and then patterning the second silicon nitride layer 261 by a photolithography process. The second silicon nitride layer 261 is then covered by a second silicon oxide layer 262. The second silicon oxide layer 262 is formed by depositing a second silicon oxide layer 262 on the surface of the second silicon nitride layer 261, and then patterning the second silicon oxide layer 262 by a photolithography process. Figure 9 As shown in FIG. 2C, a selective etching process is used to remove the remaining second silicon oxide layer 262 on top of the patterned second hard mask layer 26, leaving the second silicon nitride layer 261 in the pattern of the second hard mask layer 26. Then, a third silicon nitride layer is deposited on the surface of the Si substrate 10 to form an outer spacer layer 28 covering the dummy gate 251, the second silicon nitride layer 261, the first fin 22 and the second fin 23. The outer spacer layer 28 also covers the dielectric protection layer 24. The dielectric protection layer 24 needs to be made of a dielectric material that has a large etching selectivity with respect to silicon nitride.

[0085] As shown in FIG. 2D, an etching process, such as a back etching process, is then used to etch the outer spacer layer 28 to remove the outer spacer layer 28 covering the dielectric protection layer 24. The second silicon nitride layer 261 in the second hard mask layer 26 is used to prevent the top of the dummy gate 251 from being exposed and damaged during the etching of the outer spacer layer 28. Figure 10 As shown in FIG. 2E, the dielectric protection layer 24 is then removed to expose the surface of the first fin 22 and the second fin 23. An etching process is then used to further cut the first fin 22 and the second fin 23 exposed on both sides of the dummy gate 251, and to expose the end surface of the cut first fin 22 and the second fin 23 on both sides of the outer spacer layer 28. A chemical mechanical polishing process is then used to planarize the top of the outer spacer layer 28 to form an outer spacer 19 and to expose the planar top of the dummy gate 251.

[0086] As shown in FIG. 2F, a photoresist is then spin-coated on the structure formed in the above steps, and a third photoresist pattern 29 is formed by a photolithography process. The third photoresist pattern 29 is used to shield the PMOS device region and to expose the NMOS device region. A lateral etching process is then used to at least partially remove the SiGe second semiconductor layer 181 material exposed on both ends of the first fin 22 to form a lateral first recess 1811 in situ. The remaining photoresist in the PMOS device region is then removed. A same process is then used to form a fourth photoresist pattern 30 by spin-coating a photoresist and forming the fourth photoresist pattern 30 by a photolithography process. The fourth photoresist pattern 30 is used to shield the NMOS device region and to expose the PMOS device region. A lateral etching process is then used to at least partially remove the Si first semiconductor layer 131 material exposed on both ends of the second fin 23 to form a lateral second recess 1311 in situ.

[0087] Figure 11 As shown in FIG. 2G, a photoresist is then spin-coated on the structure formed in the above steps, and a fifth photoresist pattern 31 is formed by a photolithography process. The fifth photoresist pattern 31 is used to shield the PMOS device region and to expose the NMOS device region. A lateral etching process is then used to at least partially remove the SiGe second semiconductor layer 181 material exposed on both ends of the first fin 22 to form a lateral first recess 1811 in situ. The remaining photoresist in the PMOS device region is then removed. A same process is then used to form a sixth photoresist pattern 32 by spin-coating a photoresist and forming the sixth photoresist pattern 32 by a photolithography process. The sixth photoresist pattern 32 is used to shield the NMOS device region and to expose the PMOS device region. A lateral etching process is then used to at least partially remove the Si first semiconductor layer 131 material exposed on both ends of the second fin 23 to form a lateral second recess 1311 in situ. Figure 12 ​The photoresist remaining in the NMOS device region is then removed.

[0088] As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end). Figure 13 As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end).

[0089] As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end). Figure 14 As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end). Figure 15 As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end).

[0090] Step S3: Preparation of the channel of the NMOS device and the PMOS device.

[0091] As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end). Figure 16 As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end). Figure 17 As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end). Figure 16 As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end).

[0092] As shown in FIG. 3B, a photoresist is then spin-coated on the structure formed in the above step, and a fifth photoresist pattern 32 is formed by a photolithography process. The PMOS device region is shielded by the fifth photoresist pattern 32, and the NMOS device region is exposed. An N-type doped epitaxial source-drain process is then performed to form a first source-drain 132 on both ends of the Si first semiconductor layer 131 exposed by the first fin 22 (one end as a source end, and the other end as a drain end). Figure 18As shown, a wet etching process is then used to remove the dummy gate 251 through an opening formed at the top of the outer wall 19, forming a cavity 34 in situ within the outer wall 19, exposing the first fin 22 and the second fin 23 located within the cavity 34. Then, a wet etching process is used to remove the dielectric protective layer 24 covering the surfaces of the first fin 22 and the second fin 23 within the cavity 34. Figure 19 Showing the Figure 18 The device formed in the process has a half-section structure along the cross-sectional direction of the fin. The first fin 22 and the second fin 23 located in the cavity 34 after the dielectric protective layer 24 has been removed can be clearly seen.

[0093] like Figure 20 As shown, next, photoresist is spin-coated onto the structure formed after the above steps, and a seventh photoresist pattern 35 is formed through photolithography. The seventh photoresist pattern 35 is used to mask the PMOS device region, exposing the NMOS device region. Note that the second fin 23 located in the cavity 34 needs to be completely masked. Then, a wet etching process is used to remove the SiGe second semiconductor layer 181 material on the exposed first fin 22, while retaining the Si first semiconductor layer 131 material on the first fin 22. Thus, the Si first channels 13 of multiple NMOS devices are formed corresponding to the multiple mutually spaced Si first semiconductor layers 131 on the formed first fin 22. After the SiGe second semiconductor layer 181 material is removed, the inner sidewall 31 will be exposed.

[0094] like Figure 21 As shown, the remaining photoresist in the PMOS device area is removed. Next, photoresist is spin-coated again, and an eighth photoresist pattern 36 is formed using photolithography. This eighth photoresist pattern 36 is used to mask the NMOS device area, exposing the PMOS device area. Note that the first channel 13 already fabricated within the cavity 34 needs to be completely masked. Then, a wet etching process is used to remove the Si first semiconductor layer 131 material on the exposed second fin 23, while retaining the SiGe second semiconductor layer 181 material on the second fin 23. This forms multiple SiGe second channels 18 for the PMOS devices, corresponding to the multiple spaced-apart SiGe second semiconductor layers 181 on the formed second fin 23. After the Si first semiconductor layer 131 material is removed, the inner sidewall 31 is exposed. Then, the remaining photoresist in the NMOS device area is removed. This completes the fabrication of the channels for the NMOS and PMOS devices.

[0095] Step S4: Fabricate the gate structures of NMOS and PMOS devices.

[0096] like Figure 22 and Figure 25As shown, first, a SiO2 layer is grown as an interface layer on the side surface of the first channel 13 and the second channel 18 in the cavity 34 by a thermal oxidation process. Then, a HfO2 layer is deposited on the surface of the second dielectric layer 15 by, for example, an ALD process, and the deposited HfO2 layer covers the surface of the SiO2 layer on the side surface of the first channel 13 and the second channel 18. Then, a TiN layer, a TiAl layer and a TiN layer are sequentially deposited on the surface of the HfO2 layer by, for example, an ALD process, and the deposited TiN layer, TiAl layer and TiN layer sequentially covers the side surface of the first channel 13 and the second channel 18 in the cavity 34, i.e. covers the surface of the HfO2 layer, as the sub work function layer 371 of the three-layer structure of the first gate structure 14 and the second gate structure 17. Figure 1 As shown, the sub work function layer 371 of the three-layer structure of the first gate structure 14 and the second gate structure 17 is common, i.e. the material of each first sub work function layer 1411 of the first work function layer 141 and the second sub work function layer 1721 of the corresponding second work function layer 172 is the same. Thus, the side surface of the first channel 13 and the second channel 18 is prepared to form a work function layer 37 with three-layer same sub work function layer 371. Among them, the sub work function layer 371 on the side surface of the first channel 13 is the first sub work function layer 1411, and the sub work function layer 371 on the side surface of the second channel 18 is the second sub work function layer 1721. So that the NMOS device and the PMOS device have a unified structure of the work function layer 37, as shown. Figure 25

[0097] As shown, Figure 23 Then, the top of the tungsten gate metal layer 38 exposed in the cavity 34 is etched to form a groove at the opening of the top of the cavity 34. Finally, a fourth silicon nitride layer is deposited in the groove and planarized to form a cap layer 16 that seals the tungsten gate metal layer 38 on the opening of the cavity 34. Thus, the preparation of the heterojunction channel ring gate device of the present application is completed.

[0098] Step S5: preparing a cap layer 16.

[0099] As shown, Figure 24 Then, the top of the tungsten gate metal layer 38 exposed in the cavity 34 is etched to form a groove at the opening of the top of the cavity 34. Finally, a fourth silicon nitride layer is deposited in the groove and planarized to form a cap layer 16 that seals the tungsten gate metal layer 38 on the opening of the cavity 34. Thus, the preparation of the heterojunction channel ring gate device of the present application is completed. ​

[0100] Reference Figure 26 , Figure 26 is a schematic diagram of a ring gate structure of an existing homogenous channel ring gate device. The existing NMOS and PMOS ring gate devices are made of homogenous Si material channels, and are formed into ring gate structures through a gate stack process. The ring gate structure of the NMOS includes, in order from the inside out, a SiO2 layer, an HfO2 layer, a TiN layer, a TiAl layer, a TiN layer, and a W layer surrounding the Si channel of the NMOS, and the ring gate structure of the PMOS includes, in order from the inside out, a SiO2 layer, an HfO2 layer, a TiN layer, a TaN layer, a TiN layer, a TiAl layer, a TiN layer, and a W layer surrounding the Si channel of the PMOS.

[0101] The gate stack process of the existing NMOS and PMOS ring gate devices (AS-IS conventional ring gate devices) is generally as follows:

[0102] An ALD process is used to sequentially deposit a SiO2 layer (<1 nm), an HfO2 layer (1-2 nm), a TiN layer (1-2 nm), and a TaN layer (1-2 nm) on the side of the channel of the NMOS and the PMOS; then, the PMOS is covered (with BARC), and the TaN layer of the NMOS is etched away; the photoresist is removed, and the NMOS and the PMOS are then continuously deposited with a TiN layer (1-2 nm), a TiAl layer (3-4 nm), and a TiN layer (1-2 nm). The final thickness of the work function layer of the NMOS is about 8-11 nm, and the final thickness of the work function layer of the PMOS is about 12-15 nm. The process is complicated because the work function layers of the NMOS and the PMOS need to be processed separately. Moreover, because the composition of the work function layers of the NMOS and the PMOS is quite different, the spacing between the NMOS and the PMOS is subject to the thickness of the work function layer of the PMOS, which affects the miniaturization of the device.

[0103] Reference Figure 25 , Figure 25 is a schematic diagram of a ring gate structure of a heterogenous channel ring gate device according to a preferred embodiment of the present application. The NMOS and PMOS ring gate devices of the present application are made of a heterogenous Si channel (first channel 13) and a SiGe channel (second channel 18), and are formed into ring gate structures through a gate stack process. The ring gate structure of the NMOS and the PMOS both includes, in order from the inside out, a SiO2 layer, an HfO2 layer, a TiN layer, a TiAl layer, a TiN layer, and a W layer surrounding the Si channel of the NMOS and the SiGe channel of the PMOS, respectively, wherein the TiN layer, the TiAl layer, and the TiN layer form a work function layer 37, which unifies the work function layers of the NMOS and the PMOS.

[0104] The gate stack process of the NMOS and PMOS hetero-channel ring gate device of the present application comprises:

[0105] The SiO2 layer (1-2nm), HfO2 layer (1-2nm), TiN layer (1-2nm), TiAl layer (3-4nm) and TiN (1-2nm) are sequentially deposited on the Si channel side of the NMOS and the SiGe channel side of the PMOS by using the ALD process. The thickness of the first work function layer 141 of the NMOS and the second work function layer 172 of the PMOS is the same, about 8-11nm. Therefore, compared with the above-mentioned existing gate stack process, the process of the present application is greatly simplified.

[0106] In summary, by using the integration technology of different channel materials (for example, the first channel 13 material of the NMOS device uses Si, and the second channel 18 material of the PMOS device uses SiGe), the NMOS and PMOS have hetero-channels, which is beneficial to improve the carrier mobility of the PMOS, and further improve the on-state current of the device, and is beneficial to realize the use of the same set of work function gate materials for the NMOS and PMOS through the combination of the hetero-channels, thereby simplifying the gate stack process of the ring gate device.

[0107] Although the embodiments of the present application have been described in detail above, it is obvious for those skilled in the art that various modifications and changes can be made to the embodiments. However, it should be understood that such modifications and changes all belong to the scope and spirit of the present application in the claims. Moreover, the present application described herein can have other embodiments, and can be implemented or realized in various ways.

Claims

1. A heterogeneous channel ring gate device, characterized in that, include: An NMOS device and a PMOS device are horizontally adjacent on one side of a substrate; the NMOS device includes a plurality of first channels arranged in parallel in a direction away from the substrate, and a first work function layer and a first gate metal layer are sequentially enclosed on the side of each first channel; the PMOS device includes a plurality of second channels arranged in parallel in a direction away from the substrate, and a second work function layer and a second gate metal layer are sequentially enclosed on the side of each second channel; the first gate metal layer further fills between any two adjacent first channels, the second gate metal layer further fills between any two adjacent second channels, and the first gate metal layer and the second gate metal layer further fill between the first channel and the second channel to be tightly connected; the materials of the first channel and the second channel are different, and the composition and material of the first work function layer are the same as those of the second work function layer.

2. The heterogeneous channel annular gate device according to claim 1, characterized in that, The first work function layer includes multiple first sub-work function layers, and the second work function layer includes multiple second sub-work function layers. The material of the first channel is a first semiconductor, and the material of the second channel is a second semiconductor different from the first semiconductor. Each first sub-work function layer is correspondingly set with each second sub-work function layer, and the material of each first sub-work function layer is the same as the material of the corresponding second sub-work function layer.

3. The heterochannel annular gate device according to claim 1, characterized in that, The material of the first gate metal layer is the same as that of the second gate metal layer, forming a gate metal layer shared by the first gate structure and the second gate structure.

4. The heterogeneous channel annular gate device according to claim 1, characterized in that, The cross-sectional dimensions of the first channel and the second channel are the same, the thickness of the first work function layer and the thickness of the second work function layer are the same, or the thickness of each first sub-work function layer is the same as the thickness of a corresponding second sub-work function layer; and / or, the first channel and the second channel are offset in a direction away from the substrate.

5. The heterochannel annular gate device according to claim 2, characterized in that, The first semiconductor includes Si, and the second semiconductor includes SiGe; and / or, the number of the first sub-work function layer and the second sub-work function layer is three, including a TiN layer, a TiAl layer and a TiN layer from the inside out; and / or, a SiO2 layer and a HfO2 layer are respectively provided from the inside out between the first channel and the first work function layer, and between the second channel and the second work function layer.

6. The heterochannel annular gate device according to claim 5, characterized in that, The thickness of the TiN layer is 1~2nm, the thickness of the TiAl layer is 3~4nm, or the thickness of the first work function layer and the second work function layer is 8~11nm; the thickness of the SiO2 layer is less than 1nm, and the thickness of the HfO2 layer is 1~2nm.

7. The heterochannel annular gate device according to claim 1, characterized in that, The heterochannel ring gate device includes an inverter.

8. A method for fabricating a heterochannel gate-around device, used to form the heterochannel gate-around device as described in any one of claims 1 to 7, characterized in that, The preparation method includes: An adjacent NMOS device and a PMOS device are formed on one side of the substrate. The NMOS device includes a plurality of first channels arranged in parallel in a direction away from the substrate, and a first work function layer and a first gate metal layer are sequentially surrounded on the side of each first channel. The PMOS device includes a plurality of second channels arranged in parallel in a direction away from the substrate, and a second work function layer and a second gate metal layer are sequentially surrounded on the side of each second channel. The first gate metal layer is filled between any two adjacent first channels, and the second gate metal layer is filled between any two adjacent second channels. The first gate metal layer and the second gate metal layer are also filled between the first channel and the second channel to be tightly connected. The materials of the first channel and the second channel are different, while the composition and material of the first work function layer are the same as those of the second work function layer.

9. The method for fabricating a heterochannel annular gate device according to claim 8, characterized in that, The method for forming the NMOS and PMOS devices specifically includes: Provide substrate; A first channel of the NMOS device and a second channel of the PMOS device are formed on one side of the substrate; the first channel is made of a first semiconductor, and the second channel is made of a second semiconductor different from the first semiconductor. A first gate structure is formed surrounding the side of the first channel and a second gate structure is formed surrounding the side of the second channel; the first gate structure includes a first work function layer, the first work function layer includes a plurality of first sub-work function layers, the second gate structure is provided with a second work function layer, the second work function layer includes a plurality of second sub-work function layers, each first sub-work function layer is correspondingly disposed with each second sub-work function layer, and the material of each first sub-work function layer is the same as the material of the corresponding second sub-work function layer.

10. The method for fabricating a heterochannel annular gate device according to claim 9, characterized in that, The method for forming the first channel and the second channel specifically includes: A plurality of second semiconductor layers and a plurality of first semiconductor layers are alternately formed on the surface of the substrate, which is made of a first semiconductor material; The second semiconductor layer and the first semiconductor layer are patterned, and a plurality of fins are formed on the surface of the substrate, including adjacent first fins and second fins, and isolation trenches are formed downward on the surface of the substrate on both sides of the fins. A first dielectric layer is formed on the surface of the substrate to fill the isolation trench; A dummy gate is formed across the first fin and the second fin, and an outer wall layer is formed covering the dummy gate, the first fin and the second fin. Then, the first fin and the second fin exposed on both sides of the dummy gate are removed. At least partially remove the second semiconductor layer material exposed at both ends of the first fin and the first semiconductor layer material exposed at both ends of the second fin to form a recess, and then form an inner wall in the recess; A first source / drain is formed at both ends of the first semiconductor layer exposed at the first fin, and a second source / drain is formed at both ends of the second semiconductor layer exposed at the second fin; An opening is formed at the top of the outer wall layer to expose the top of the dummy gate below. Then, the dummy gate is removed to form a cavity, and the remaining second semiconductor layer material on the first fin and the remaining first semiconductor layer material on the second fin are removed, thereby forming a plurality of first channels corresponding to the plurality of first semiconductor layers on the first fin and a plurality of second channels corresponding to the plurality of second semiconductor layers on the second fin.

11. The method for fabricating a heterochannel annular gate device according to claim 10, characterized in that, The method for forming the first gate structure and the second gate structure specifically includes: A work function layer comprising multiple sub-work function layers is formed on the sides of the first channel and the second channel in the cavity, wherein the sub-work function layer on the side of the first channel serves as the first sub-work function layer, and the sub-work function layer on the side of the second channel serves as the second work function layer; and A gate metal layer is filled into the cavity.

12. The method for fabricating a heterochannel annular gate device according to claim 11, characterized in that, The first semiconductor includes Si, the second semiconductor includes SiGe; and / or, the number of sub-work function layers is three, which include a TiN layer, a TiAl layer and a TiN layer from the inside out.

13. The method for fabricating a heterochannel annular gate device according to claim 11, characterized in that, Before forming the work function layer, the method further includes: firstly forming a SiO2 layer and a HfO2 layer sequentially on the sides of the first channel and the second channel in the cavity, and then forming the work function layer on the HfO2 layer.

14. The method for fabricating a heterochannel annular gate device according to claim 11, characterized in that, After forming the gate metal layer, the method further includes forming a capping layer on the opening to close the gate metal layer.

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