Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module. The method comprises the following steps: (1) providing a substrate, wherein the substrate comprises a base, a tunneling oxide layer and an intrinsic amorphous silicon layer which are stacked in sequence; (2) according to a preset pattern, covering one side surface, far away from the tunneling oxide layer, of the intrinsic amorphous silicon layer with phosphorus-containing slurry, and drying the phosphorus-containing slurry; (3) carrying out phosphorus diffusion on the dried product; and (4) annealing a product subjected to phosphorus diffusion to obtain a phosphorus-doped polycrystalline silicon layer with phosphorus heavily doped regions and phosphorus lightly doped regions arranged at intervals. The method provided by the embodiment of the invention is simple in process and easy to implement; the prepared solar cell has a good passivation effect and high photoelectric efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] Tunnel Oxide and Passivated Contact (TOPCon) solar cells are a new type of high-efficiency solar cells. This type of solar cell achieves the selective passage of photogenerated carriers by tunneling silicon oxide and doped polysilicon passivated crystalline silicon solar cells (hereinafter referred to as solar cells or cells). That is, the majority carriers can pass through the tunneling silicon oxide layer without obstacles into the doped polysilicon film and then be collected. At the same time, the recombination rate of minority carriers at the interface of tunneling silicon oxide and silicon is very low and cannot pass through the tunneling silicon oxide to reach the doped polysilicon film. TOPCon cells can achieve one-dimensional collection of photogenerated carriers, reducing the recombination probability of minority carriers; at the same time, it also increases the collection probability of majority carriers.

[0003] TOPCon (tunneling oxide passivation contact) cells currently use a tunneling oxide layer with uniform thickness on the entire surface superimposed on a doped amorphous silicon layer. In order to avoid burn-through of the metallization paste, the doped amorphous silicon layer on the back needs to have a certain thickness (mainstream is about 110nm). However, a thicker doped polysilicon layer will bring greater parasitic absorption, limiting the improvement of the photovoltaic performance of solar cells.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] The embodiments of the present application provide a solar cell and a method for preparing the same, and a photovoltaic module to solve or alleviate one or more of the technical problems mentioned above.

[0006] According to a first aspect of an embodiment of the present application, a method for preparing a solar cell is provided, comprising: (1) providing a substrate, wherein the substrate comprises a base, a tunneling oxide layer and an intrinsic amorphous silicon layer which are stacked in sequence; (2) covering a phosphorus-containing slurry on a side of the intrinsic amorphous silicon layer away from the tunneling oxide layer according to a predetermined pattern and drying the slurry; (3) diffusing phosphorus on the dried product; and (4) annealing the phosphorus-diffused product to obtain a phosphorus-doped polysilicon layer in which phosphorus-heavy doped regions and phosphorus-lightly doped regions are spaced apart.

[0007] The method of the embodiment of the present application is simple and easy to implement. The prepared solar cell improves the passivation effect and reduces the parasitic absorption of carriers, so that the solar cell exhibits a higher photoelectric efficiency.

[0008] Specifically, according to a predetermined pattern, a phosphorus-containing slurry is covered on the intrinsic amorphous silicon layer and dried to provide the phosphorus source required for the heavily doped area. The dried product is subjected to phosphorus diffusion so that the area covered by the phosphorus-containing slurry forms a phosphorus-heavy doped area, which is used to form a metal electrode on its surface, and other areas form a non-metallized area (phosphorus-lightly doped area) structure. Annealing can make the transformation of amorphous silicon to polycrystalline silicon more sufficient and uniform while making the grain crystallization, and make the area covered with the phosphorus-containing slurry a phosphorus-heavy doped area in the phosphorus-doped polycrystalline silicon layer. In addition, the method of the present application can form a selective doping structure by adding a step of covering the phosphorus-containing slurry, forming a doped polycrystalline silicon layer with a lower concentration in the non-metallic area (the area not covered with the phosphorus-containing slurry), and the lower phosphorus doping concentration can significantly reduce parasitic absorption and reduce recombination; the metallized area (phosphorus-heavy doped area) can significantly improve the contact performance between the electrode and the phosphorus-doped polycrystalline silicon layer, that is, a high concentration of phosphorus is conducive to reducing the contact resistance and forming a good contact with the metal electrode. In summary, the selectively doped passivated contact structure obtained by the method of the present application is beneficial to reducing the contact resistance between the electrode slurry and the heavily phosphorus-doped area, thereby reducing the parasitic absorption of carriers while ensuring passivation, thereby improving efficiency.

[0009] According to an embodiment of the present application, the drying temperature is 100-400°C.

[0010] According to an embodiment of the present application, the phosphorus diffusion is performed by gradient temperature increase within 14-40 minutes.

[0011] According to an embodiment of the present application, the gradient heating process includes the following steps performed in sequence: (3-1) Heating at a heating rate of V1 to a temperature of T1; (3-2) Heating at a heating rate V2 to a temperature T2; (3-3) Heating at a heating rate of V3 to a temperature of T3; (3-4) heating to temperature T4 at a heating rate V4; Among them, 20℃≤T2-T1≤70℃, 10℃≤T3-T2≤30℃, and 5℃≤T4-T3≤25℃.

[0012] According to an embodiment of the present application, in step (3-1), T1 is 800-860°C, and V1 is 0.4-0.8°C / s.

[0013] According to an embodiment of the present application, T2 in step (3-2) is 860-900°C, and V2 is 0.4-0.8°C / s.

[0014] According to an embodiment of the present application, T3 in step (3-3) is 880-920° C., and V3 is 0.4-0.8° C. / s.

[0015] According to an embodiment of the present application, T4 in step (3-4) is 900-945° C., and V4 is 0.4-0.8° C. / s.

[0016] According to an embodiment of the present application, in step (4), the annealing process includes a heat preservation process and a gradient cooling process performed sequentially.

[0017] According to an embodiment of the present application, the insulation process (4-1) is to keep the temperature at 900-945° C. for 1300-1800 seconds.

[0018] According to an embodiment of the present application, the gradient cooling process includes the following steps performed in sequence: (4-2) Cooling down to temperature T5 at a cooling rate V5; (4-3) cooling down to temperature T6 at a cooling rate V6; (4-4) cooling down to temperature T7 at a cooling rate V7; Among them, 10℃≤T5-T6≤50℃, 10℃≤T7-T6≤50℃.

[0019] According to an embodiment of the present application, T5 in step (4-2) is 870-900°C, and V5 is 0.3-0.9°C / s.

[0020] According to an embodiment of the present application, T6 in step (4-3) is 850-890° C., and V6 is 0.3-0.9° C. / s.

[0021] According to an embodiment of the present application, T7 in step (4-4) is 800-850° C., and V7 is 0.3-0.9° C. / s.

[0022] According to an embodiment of the present application, the phosphorus concentration of the heavily phosphorus doped region is 3×E 20 -1×E 21 atoms / cm -3 .

[0023] The second aspect of the embodiment of the present application is a solar cell, comprising: a substrate; a tunneling oxide layer, the tunneling oxide layer being located on one side surface of the substrate; a phosphorus-doped polysilicon layer, the phosphorus-doped polysilicon layer being located on one side surface of the tunneling oxide layer away from the substrate, the phosphorus-doped polysilicon layer comprising phosphorus-heavy doped regions and phosphorus-lightly doped regions arranged at intervals, wherein the phosphorus-doped polysilicon layer is formed by coating a phosphorus-containing slurry on an intrinsic amorphous silicon layer according to a predetermined pattern and diffusing phosphorus.

[0024] According to an embodiment of the present application, the phosphorus concentration of the heavily phosphorus doped region is 3×E 20 -1×E 21 atoms / cm -3; The phosphorus concentration of the lightly phosphorus-doped region is 3×E 19 -2×E 20 atoms / cm -3 .

[0025] According to a third aspect of the embodiments of the present application, a photovoltaic module is provided, wherein the photovoltaic module comprises a solar cell obtained by the preparation method described in the first aspect or the solar cell described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0027] Figure 1 is a schematic diagram of the structure of a solar cell in some embodiments; Figure 2 It is a schematic diagram of the printing pattern of the phosphorus-containing paste.

[0028] Reference numerals: 1: substrate; 2: boron-doped layer; 3: tunneling oxide layer; 4: phosphorus-doped polysilicon layer; 5: phosphorus-heavy doped region; 6: passivation layer; 7: first electrode; 8: phosphorus-lightly doped region. DETAILED DESCRIPTION

[0029] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0031] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0034] At present, mass production uses a tunneling oxide layer with uniform thickness on the entire surface superimposed on a doped amorphous silicon layer. In order to avoid burn-through of the metallization slurry, the doped amorphous silicon layer on the back needs to ensure a certain thickness (the mainstream is about 110nm). However, the thicker doped polysilicon layer brings greater parasitic absorption, which limits the increase in current. Selectively doped passivation contact structure came into being, that is, heavy doping is formed in the corresponding area of ​​the back metallization, and light doping is formed in the non-metallized area, which ensures passivation while reducing parasitic absorption. However, the current selective doping method is complicated to operate, the steps are cumbersome, and mass production is difficult.

[0035] Accordingly, in a first aspect of an embodiment of the present application, a method for preparing a solar cell is provided, the method comprising: (1) providing a substrate, the substrate comprising a base, a tunneling oxide layer and an intrinsic amorphous silicon layer stacked in sequence; (2) covering a phosphorus-containing slurry on a side of the intrinsic amorphous silicon layer away from the tunneling oxide layer according to a predetermined pattern and drying the slurry; (3) diffusing phosphorus on the dried product; and (4) annealing the phosphorus-diffused product to obtain a phosphorus-doped polysilicon layer with phosphorus-heavy doped regions and phosphorus-lightly doped regions spaced apart.

[0036] The method of the embodiment of the present application is simple and easy to implement. The prepared solar cell improves the passivation effect and reduces the parasitic absorption of carriers, so that the solar cell exhibits a higher photoelectric efficiency.

[0037] Specifically, according to a predetermined pattern, a phosphorus-containing slurry is covered on the intrinsic amorphous silicon layer and dried to provide the phosphorus source required for the heavily doped area. The dried product is subjected to phosphorus diffusion so that the area covered by the phosphorus-containing slurry forms a phosphorus-heavy doped area, which is used to form a metal electrode on its surface, and other areas form a non-metallized area (phosphorus-lightly doped area) structure. Annealing can make the transformation of amorphous silicon to polycrystalline silicon more sufficient and uniform while making the grain crystallization, and make the area covered with the phosphorus-containing slurry a phosphorus-heavy doped area in the phosphorus-doped polycrystalline silicon layer. In addition, the method of the present application can form a selective doping structure by adding a step of covering the phosphorus-containing slurry, forming a doped polycrystalline silicon layer with a lower concentration in the non-metallic area (the area not covered with the phosphorus-containing slurry), and the lower phosphorus doping concentration can significantly reduce parasitic absorption and reduce recombination; the metallized area (phosphorus-heavy doped area) can significantly improve the contact performance between the electrode and the phosphorus-doped polycrystalline silicon layer, that is, a high concentration of phosphorus is conducive to reducing the contact resistance and forming a good contact with the metal electrode. In summary, the selectively doped passivated contact structure obtained by the method of the present application is beneficial to reducing the contact resistance between the electrode slurry and the heavily phosphorus-doped area, thereby reducing the parasitic absorption of carriers while ensuring passivation, thereby improving efficiency.

[0038] According to the method of the embodiment of the present application, step (1) provides a substrate. In this step, the substrate includes a base, a tunneling oxide layer and an intrinsic amorphous silicon layer stacked in sequence.

[0039] In some embodiments, the method of forming the substrate includes: providing a base; forming a tunneling oxide layer on a surface of one side of the base, and forming an intrinsic amorphous silicon layer on a side of the tunneling oxide layer away from the base.

[0040] Furthermore, it also includes texturing and cleaning the substrate to remove dirt and metal impurities on the surface of the substrate, and to remove the mechanical damage layer of the substrate generated during the cutting process, thereby reducing the recombination center and forming an uneven velvet surface to enhance the silicon wafer's absorption of sunlight and reduce reflectivity.

[0041] Optionally, a uniform “positive pyramid” velvet surface is formed on two opposite surfaces of the substrate, and the velvet surface height is 0.5-3 μm.

[0042] Optionally, the substrate includes an N-type silicon wafer, a P-type silicon wafer, etc.

[0043] Optionally, the substrate has a thickness of 100-200 μm.

[0044] In some embodiments, the solar cell is a TOPcon cell.

[0045] Optionally, before providing the substrate, after forming a tunnel oxide layer on one side surface of the substrate, the method further includes: performing boron doping on a side of the substrate away from the tunnel oxide layer to form a boron doped layer and a borosilicate glass layer on the surface of the substrate. P-type impurities are diffused on the substrate to achieve a suitable doping concentration and square resistance, and to obtain a depth suitable for the PN junction of the solar cell.

[0046] Optionally, the temperature during the boron doping diffusion is 600-1000° C., and the time is 60-120 seconds. After the boron is diffused, the P-type impurities are diffused on the N-type substrate to form a PN junction, and a suitable doping concentration ρ / square resistance R is achieved.

[0047] Optionally, the boron source in the boron doping diffusion process includes at least one of BCl3 and BBr3.

[0048] Optionally, the boron doped layer has a thickness of 70-1200 nm, for example, 70 nm, 160 nm, 260 nm, 380 nm, 500 nm, 600 nm, 800 nm, 900 nm, 1100 nm, 1200 nm, etc.

[0049] Optionally, the substrate after the boron doping layer is formed is etched at a first angle to remove the borosilicate glass layer and etch and polish the back surface to increase the back reflectivity, thereby improving the long-wave absorption of the substrate and reducing the recombination of surface dangling bonds.

[0050] Optionally, the removal of the borosilicate glass layer is performed by chain pickling of the substrate using an HF solution.

[0051] Optionally, the concentration of HF is 0.5-10wt%, for example, 0.5wt%, 1wt%, 2wt%, 5wt%, 10wt%, etc.

[0052] In some embodiments, the etching is performed in an alkaline solution, and the alkaline solution includes a sodium hydroxide solution or a potassium hydroxide solution.

[0053] Optionally, the concentration of the sodium hydroxide solution is 0.5-5wt%, for example, 0.5wt%, 1wt%, 2wt%, 3wt%, 4wt%, 5wt%, etc.

[0054] In some embodiments, a tunneling oxide layer is formed on one side surface of the substrate, which can provide a tunneling channel, selectively pass electrons, and form an interface chemical passivation to block excessive phosphorus in the N-type doping layer from entering the silicon wafer.

[0055] In some embodiments, the surface where the tunnel oxide layer is formed is the back side of the substrate.

[0056] In some embodiments, the method of forming a tunnel oxide layer includes growing the tunnel oxide layer on a substrate using an LPCVD device at a temperature of 400-650° C.

[0057] Optionally, the thickness of the tunnel oxide layer is 1-2 nm.

[0058] In some embodiments, an intrinsic amorphous silicon layer is formed on a side of the tunnel oxide layer away from the substrate, so as to be used for subsequently forming a phosphorus-doped polysilicon layer.

[0059] In some embodiments, an intrinsic amorphous silicon layer (a-Si) is formed on a side of the tunnel oxide layer away from the substrate at a temperature of 400-650° C. using LPCVD (low pressure chemical vapor deposition) equipment.

[0060] Optionally, the thickness of the intrinsic amorphous silicon layer is 80-130 nm.

[0061] According to an embodiment of the present application, in step (2), a phosphorus-containing slurry is covered on a side of the intrinsic amorphous silicon layer away from the tunnel oxide layer according to a predetermined pattern and then dried.

[0062] In some embodiments, the covering comprises coating.

[0063] Optionally, refer to Figure 1 The coating method is slit coating to form a coating pattern of the phosphorus-containing slurry on the surface of the intrinsic amorphous silicon layer. The slit width H1 is 60-160 μm, which is used to match the width of the metal electrode.

[0064] Optionally, during slit coating, the width of the slit is greater than the width of the phosphorus-containing slurry coating.

[0065] Optionally, the phosphorus-containing slurry is coated with a width of 70-150 μm.

[0066] In some embodiments, the drying temperature is 100-400°C, such as 100°C, 250°C, 280°C, 300°C, 400°C, etc.

[0067] According to the present application, step (3) diffuses phosphorus on the dried product.

[0068] In some embodiments, the phosphorus diffusion is performed by gradient temperature increase within 14-40 minutes.

[0069] In some embodiments, the flow rate of phosphine is 500-2000 sccm, such as 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm, etc.

[0070] In some embodiments, the gradient heating process includes (3-1) heating to temperature T1 at a heating rate V1; (3-2) heating to temperature T2 at a heating rate V2; (3-3) heating to temperature T3 at a heating rate V3; (3-4) heating to temperature T4 at a heating rate V4; wherein 20°C≤T2-T1≤70°C, 10°C≤T3-T2≤30°C, and 5°C≤T4-T3≤25°C. The aforementioned gradient heating process is beneficial to reducing the defect generation rate caused by the heating process and making the phosphorus doping more uniform.

[0071] Furthermore, in step (3-1), T1 is 800-860°C, such as 800°C, 810°C, 830°C, 860°C, etc.; V1 is 0.4-0.8°C / s, such as 0.4°C / s, 0.6°C / s, 0.8°C / s, etc. Controlling T1 within the aforementioned range is beneficial to reducing the defect generation rate caused by the temperature increase process; controlling V1 within the aforementioned range is beneficial to making the phosphorus doping uniform.

[0072] Furthermore, T2 in step (3-2) is 860-900°C, for example, 860°C, 880°C, 890°C, 900°C, etc.; V2 is 0.4-0.8°C / s, for example, 0.4°C / s, 0.6°C / s, 0.8°C / s, etc.

[0073] Furthermore, T3 in step (3-3) is 880-920°C, such as 880°C, 890°C, 900°C, 920°C, etc.; V3 is 0.4-0.8°C / s, such as 0.4°C / s, 0.6°C / s, 0.8°C / s, etc.

[0074] Furthermore, T4 in step (3-4) is 900-945°C, such as 900°C, 910°C, 930°C, 945°C, etc.; V4 is 0.4-0.8°C / s, such as 0.4°C / s, 0.6°C / s, 0.8°C / s, etc.

[0075] According to the present application, step (4) anneals the product after the phosphorus diffusion to obtain a phosphorus-doped polysilicon layer in which phosphorus-heavy doped regions and phosphorus-lightly doped regions are alternately arranged.

[0076] In some embodiments, the annealing process includes a heat preservation process and a gradient cooling process performed sequentially.

[0077] In some embodiments, (4-1) the temperature is maintained at 900-945° C. for 1300-1800 seconds. This can improve the sufficiency and stability of the crystallization process of amorphous silicon, thereby forming a uniform and stable phosphorus-doped polysilicon layer.

[0078] In some embodiments, the gradient cooling process includes the following steps: (4-2) cooling to temperature T5 at a cooling rate V5; (4-3) cooling to temperature T6 at a cooling rate V6; (4-4) cooling to temperature T7 at a cooling rate V7; wherein 10°C≤T5-T6≤50°C, 10°C≤T7-T6≤50°C. The gradient cooling can reduce the defect generation rate caused by rapid cooling during the annealing process and improve the crystal form of polysilicon.

[0079] Furthermore, T5 in step (4-2) is 870-925°C, such as 870°C, 890°C, and 925°C; V5 is 0.3-0.9°C / s, such as 0.3°C / s, 0.6°C / s, and 0.9°C / s. This can further reduce the defect generation rate caused by rapid cooling during the annealing process and improve the crystal form of polysilicon.

[0080] Furthermore, T6 in step (4-3) is 850-890°C, such as 850°C, 860°C, 870°C; V6 is 0.3-0.9°C / s, such as 0.3°C / s, 0.6°C / s, 0.9°C / s, etc. This can further reduce the defect generation rate caused by rapid cooling during annealing and improve the crystal form of polysilicon.

[0081] Furthermore, T7 in step (4-4) is 800-850°C, such as 800°C, 830°C, 850°C; V7 is 0.3-0.9°C / s, such as 0.3°C / s, 0.6°C / s, 0.9°C / s, etc. This can further reduce the defect generation rate caused by rapid cooling during the annealing process and improve the crystal form of polysilicon.

[0082] In some embodiments, the method for preparing a solar cell further comprises (5): removing the phosphorus silicon glass layer on the front, edge and back sides, and the oxide layer on the front side comprises sequentially performing acid pickling, water washing, pre-dehydration and drying steps, wherein the acid pickling adopts hydrofluoric acid for 200-300 seconds; the water washing adopts deionized water for 100-200 seconds; the pre-dehydration time is 5-20 seconds, and the acid pickling, water washing and pre-dehydration can be performed at room temperature (20-30°C). Drying adopts hot air drying for 400-700 seconds at a temperature of 80-100°C.

[0083] In some embodiments, the phosphorus concentration of the heavily phosphorus doped region is 3×E 20 -1×E 21 atoms / cm -3 In this way, the heavily phosphorus-doped region has a higher phosphorus concentration, which is beneficial to improving its contact effect with the metal electrode.

[0084] In some embodiments, the method for preparing a solar cell further includes: (6) depositing a passivation layer on a side of the phosphorus-doped polycrystalline silicon away from the substrate to obtain the solar cell.

[0085] Furthermore, a PEVCD device is used to deposit a passivation layer.

[0086] Optionally, the thickness of the passivation layer is 1-5 nm.

[0087] In some embodiments, the method for preparing a solar cell further includes: (7) depositing an anti-reflection layer on both the front and back sides of the cell.

[0088] Furthermore, the thickness of the anti-reflection layer is 70-85 nm.

[0089] Furthermore, the thickness of the front anti-reflection layer is 70-80 nm, and the thickness of the back anti-reflection layer is 75-85 nm.

[0090] In some embodiments, the method for preparing a solar cell further includes: (8) forming a first electrode and a second electrode by screen printing. The first electrode is formed in contact with the phosphorus heavily doped region of the phosphorus doped polysilicon layer. In this way, the electrode paste has better contact with the first region, which can improve the passivation effect of the solar cell.

[0091] According to a second aspect of the present application, a solar cell is provided. Figure 2 The solar cell includes a substrate 1; a tunneling oxide layer 3, the tunneling oxide layer 3 is located on one side surface of the substrate 1; a phosphorus-doped polysilicon layer 4, the phosphorus-doped polysilicon layer 4 is located on the side surface of the tunneling oxide layer 3 away from the substrate 1, the phosphorus-doped polysilicon layer 4 includes a phosphorus-heavy doped area 5 and a phosphorus-lightly doped area 8 arranged at intervals, wherein the phosphorus-doped polysilicon layer is formed by coating a phosphorus-containing slurry on an intrinsic amorphous silicon layer according to a predetermined pattern and diffusing phosphorus.

[0092] The solar cell of the embodiment of the present application improves the passivation effect while reducing the parasitic absorption of carriers, so that the solar cell exhibits higher photoelectric efficiency.

[0093] The solar cell has a selectively doped passivated contact structure. The non-metallic area (area not covered by the phosphorus-containing slurry) forms a doped polysilicon layer with a thinner thickness and lower concentration. The thinner thickness can significantly reduce parasitic absorption and reduce recombination; the metallized area (phosphorus-heavy doped area) can significantly improve the contact performance between the electrode and the phosphorus-doped polysilicon layer, that is, a high concentration of phosphorus is conducive to reducing contact resistance and forming good contact with the metal electrode.

[0094] In some embodiments, there is a lightly phosphorus-doped region between adjacent heavily phosphorus-doped regions.

[0095] Optionally, the phosphorus concentration of the heavily phosphorus doped region is 3×E 20 -1×E 21 atoms / cm -3 ; The phosphorus concentration of the lightly phosphorus-doped region is 3×E 19 -2×E 20 atoms / cm -3 .

[0096] In some embodiments, reference Figure 2 , further comprising a boron doped layer 2. The boron doped layer is located on a side of the substrate away from the tunnel oxide layer.

[0097] In some embodiments, reference Figure 1 , the solar cell further comprises a passivation layer 6. The passivation layer is located on a side of the phosphorus-doped polysilicon layer away from the tunnel oxide layer.

[0098] In some embodiments, the solar cell further includes an anti-reflection layer, and the anti-reflection layer is located on the back side of the passivation layer and the substrate.

[0099] In some embodiments, a first electrode 7 is further included. The first electrode is in contact with the phosphorus doped region, and the second electrode is in contact with the boron doped layer.

[0100] According to a third aspect of the embodiments of the present application, a photovoltaic module may be provided, wherein the photovoltaic module comprises a solar cell obtained by the preparation method according to the first aspect or a solar cell according to the second aspect.

[0101] In some embodiments, the photovoltaic module includes a plurality of solar cells connected in series and / or in parallel; wherein at least one solar cell is a solar cell obtained by the preparation method described in the first aspect or a solar cell described in the second aspect. A plurality of solar cells in series form a cell string, and adjacent solar cells can be connected together by string welding.

[0102] In a fourth aspect of the embodiments of the present application, a photovoltaic system is provided, comprising the photovoltaic module in any of the above embodiments. The photovoltaic system also has the advantages of the above photovoltaic modules, which will not be described in detail here.

[0103] In some embodiments, the above-mentioned photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to a junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0104] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0105] Example 1 S1: Texturing and cleaning The N-type silicon wafer with a thickness of 120 μm was textured and cleaned to form a uniform "positive pyramid" texture surface on the two opposite surfaces of the silicon wafer, and the texture surface height was 3 μm.

[0106] S2: Boron doping on the front side of N-type silicon wafer A boron-doped layer with a thickness of 300 nm is diffused on the front side of the silicon wafer after texturing and cleaning.

[0107] S3: First winding etching The boron-doped substrate was chain-picked using a 5wt% HF solution.

[0108] The back side of the substrate is etched using a sodium hydroxide solution with a concentration of 5 wt %.

[0109] S4: Tunneling oxide layer and intrinsic amorphous silicon layer Using LPCVD equipment, at a temperature of 650°C, a tunneling oxide layer and an intrinsic amorphous silicon layer (a-Si) are grown on the back of the silicon wafer, where the thickness of the first tunneling oxide layer is 1.5nm and the thickness of the intrinsic amorphous silicon layer is 100nm.

[0110] S4: Applying phosphorus-containing slurry on a local area of ​​the intrinsic amorphous silicon.

[0111] The phosphorus-containing slurry was coated by slit coating, the drying temperature was 200° C., and the width between the slits was 100 μm (the width of the first region).

[0112] S5: Phosphorus Diffusion Phosphorus diffusion is to load the silicon wafer after depositing amorphous silicon into a tubular phosphorus diffusion furnace, use phosphine as the process gas, and diffuse phosphorus on the back of the battery. The temperature of the phosphorus diffusion process is a gradient heating.

[0113] Gradient heating process: first heat the S4 product to 800°C; then heat it from 800°C to 840°C in 600 seconds; then heat it from 840°C to 880°C in 600 seconds; then heat it from 880°C to 900°C in 300 seconds; and then heat it from 900°C to 913°C in 200 seconds. The process control time is 25 minutes, and the phosphorus concentration in the phosphorus heavily doped area is 6×E 20 cm -3 , the phosphorus concentration in the lightly doped region is 2×E 20 atoms / cm -3 .

[0114] S6: Annealing The phosphorus-diffused product is annealed to obtain a phosphorus-doped polysilicon layer, wherein the phosphorus-containing slurry-covered region in the phosphorus-doped polysilicon layer is a phosphorus-heavy doped region. The annealing process includes a heat preservation process and a gradient cooling process.

[0115] The heat preservation process is to keep the temperature at 910°C for 1380 seconds.

[0116] Gradient cooling process: cooling from 910°C to 870°C in 600 seconds; cooling from 870°C to 850°C in 600 seconds; cooling from 850°C to 800°C in 600 seconds.

[0117] S7: Second winding etching on the front side The product obtained in step S6 is subjected to acid washing, water washing, pre-dehydration and drying steps in sequence, wherein the acid washing adopts hydrofluoric acid for 300 seconds; the water washing adopts deionized water for 200 seconds; the pre-dehydration time is 20 seconds, and the acid washing, water washing and pre-dehydration can all be carried out at room temperature. The drying adopts hot air drying for 700 seconds at a temperature of 100°C.

[0118] S8: Deposition of passivation layer A 5 nm passivation layer was deposited on the front side of the product after front side etch.

[0119] S9: Deposition of reflective film A 30nm reflective film is deposited on the front and back sides of the cell after the passivation film is deposited.

[0120] S10: Forming metal electrodes The light-receiving surface and the backlight surface of the solar cell are respectively made of a first metal silver electrode and a second metal silver electrode.

[0121] S11: Light injection The cell obtained in S10 is subjected to light injection treatment to form a solar cell, wherein the light injection temperature is 220° C. and the time is 120 s, so as to obtain a solar cell (tunneling passivated contact solar cell).

[0122] Embodiment 2-4 The solar cell was prepared in the manner of Example 1, except that in S4: the drying temperatures were 100° C., 300° C. and 400° C. respectively.

[0123] Example 5 A solar cell was prepared in the same manner as in Example 1, except that in S5: the phosphorus concentration in the phosphorus heavily doped region was 3×E 20 cm -3 , the phosphorus concentration in the lightly doped region is 2×E 20 atoms / cm -3 .

[0124] Example 6 A solar cell was prepared in the same manner as in Example 1, except that in S5: the phosphorus concentration in the heavily phosphorus doped region was 1×E 21 cm -3 , the phosphorus concentration in the lightly doped region is 2×E 20 atoms / cm -3 .

[0125] Example 7 A solar cell was prepared in the same manner as in Example 1, except that S6: gradient annealing Gradient heating process: first heat the S5 product to 800°C; then heat it from 800°C to 830°C in 600 seconds; then heat it from 830°C to 860°C in 600 seconds; then heat it from 860°C to 920°C in 300 seconds; and then heat it from 920°C to 945°C in 200 seconds.

[0126] The crystallization process was carried out at 945°C for 1380 seconds.

[0127] Gradient cooling process: cooling from 945°C to 900°C in 600 seconds; cooling from 900°C to 850°C in 600 seconds; cooling from 850°C to 830°C in 600 seconds.

[0128] Comparative Example 1 A solar cell was prepared in the same manner as in Example 1, except that S6 was not performed.

[0129] Comparative Example 2: The solar cell was prepared in the manner of Example 1, except that S6 only had a heat preservation process: specifically, heat preservation at 910° C. for 4880 seconds.

[0130] Comparative Example 3 The solar cell was prepared in the manner of Example 1, except that the gradient cooling process in S6 was to directly cool the temperature from 945° C. to 830° C. within 1800 seconds.

[0131] Comparative Example 4 A solar cell is prepared in the manner of Example 1, except that S4: the phosphorus-containing slurry is completely coated on the side of the intrinsic amorphous silicon away from the substrate, and then dried.

[0132] The photovoltaic performance of the solar cells of the above-mentioned embodiments and comparative examples was tested, and the test results are shown in Table 1. It should be noted that the values ​​in the following table are relative values ​​compared with comparative example 1.

[0133] Table 1

[0134] It can be seen from Table 1 that, by comparing Examples 1-7 with Comparative Examples 1-4, the photoelectric performance of the solar cell of the embodiment is better than that of the solar cell of the comparative example. This is because the method of the present application can form a selective doping structure by only adding a step of covering the phosphorus-containing slurry, the metallized area is a phosphorus heavily doped area, and a phosphorus lightly doped area with a lower concentration is formed in the non-metallic area. This doped polysilicon layer formed by the phosphorus heavily doped area and the phosphorus lightly doped area can reduce parasitic absorption and improve the contact performance between the electrode and the phosphorus-doped polysilicon layer, thereby obtaining a solar cell with better photoelectric efficiency.

[0135] It should also be noted that the "some embodiments", "other embodiments", "embodiments", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure or characteristic is described in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0136] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0137] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: include: (1) Providing a substrate, wherein the substrate comprises a base, a tunneling oxide layer, and an intrinsic amorphous silicon layer stacked in sequence; (2) covering a phosphorus-containing slurry on a side of the intrinsic amorphous silicon layer away from the tunnel oxide layer according to a predetermined pattern and drying the slurry; (3) diffusing phosphorus on the dried product; (4) Annealing the phosphorus-diffused product to obtain a phosphorus-doped polysilicon layer in which phosphorus-heavy doped regions and phosphorus-lightly doped regions are alternately arranged.

2. The preparation method according to claim 1, characterized in that: The drying temperature is 100-400°C.

3. The preparation method according to claim 1, characterized in that: In step (3), the phosphorus diffusion is carried out by gradient heating within 14-40 minutes.

4. The preparation method according to claim 3, characterized in that: The process of gradient heating includes the following steps: (3-1) Heating at a heating rate of V1 to a temperature of T1; (3-2) Heating at a heating rate V2 to a temperature T2; (3-3) Heating at a heating rate of V3 to a temperature of T3; (3-4) heating to temperature T4 at a heating rate V4; Among them, 20℃≤T2-T1≤70℃, 10℃≤T3-T2≤30℃, and 5℃≤T4-T3≤25℃.

5. The preparation method according to claim 4, characterized in that: In step (3-1), T1 is 800-860°C, and V1 is 0.4-0.8°C / s; and / or, in step (3-2), T2 is 860-900°C, and V2 is 0.4-0.8°C / s; and / or, in step (3-3), T3 is 880-920°C, and V3 is 0.4-0.8°C / s; And / or, in step (3-4), T4 is 900-945°C, and V4 is 0.4-0.8°C / s.

6. The preparation method according to claim 1, characterized in that: In step (4), the annealing process includes a heat preservation process and a gradient cooling process performed sequentially.

7. The preparation method according to claim 6, characterized in that: (4-1) The heat preservation process is to keep the temperature at 900-945°C for 1300-1800s.

8. The preparation method according to claim 6, characterized in that: The gradient cooling process includes the following steps performed in sequence: (4-2) Cooling down to temperature T5 at a cooling rate V5; (4-3) cooling down to temperature T6 at a cooling rate V6; (4-4) cooling down to temperature T7 at a cooling rate V7; Among them, 10℃≤T5-T6≤50℃, 10℃≤T7-T6≤50℃.

9. The preparation method according to claim 8, characterized in that: In step (4-2), T5 is 870-900°C, and V5 is 0.3-0.9°C / s; and / or, in step (4-3), T6 is 850-890°C, and V6 is 0.3-0.9°C / s; And / or, in step (4-4), T7 is 800-850°C, and V7 is 0.3-0.9°C / s.

10. The preparation method according to claim 1, characterized in that: The phosphorus concentration of the heavily phosphorus doped region is 3×E 20 -1×E 21 atoms / cm -3 .

11. A solar cell, characterized in that: include: substrate; A tunneling oxide layer, wherein the tunneling oxide layer is located on a side surface of the substrate; a phosphorus-doped polysilicon layer, the phosphorus-doped polysilicon layer being located on a surface of the tunnel oxide layer away from the substrate, the phosphorus-doped polysilicon layer comprising a phosphorus-heavy doped region and a phosphorus-lightly doped region arranged at intervals, The phosphorus-doped polysilicon layer is formed by coating a phosphorus-containing slurry on the intrinsic amorphous silicon layer according to a predetermined pattern and diffusing phosphorus.

12. The solar cell according to claim 11, characterized in that: The phosphorus concentration of the heavily phosphorus doped region is 3×E 20 -1×E 21 atoms / cm -3 ; The phosphorus concentration of the lightly phosphorus doped region is 3×E 19 -2×E 20 atoms / cm -3 .

13. A photovoltaic module, characterized in that: The photovoltaic module comprises a solar cell obtained by the preparation method according to any one of claims 1 to 10 or a solar cell according to any one of claims 11 or 12.

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