Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module. The solar cell comprises a semiconductor substrate; the electrode structure is formed on the first surface of the semiconductor substrate and comprises a first metal layer and a second metal layer, and the first metal layer is close to the semiconductor substrate relative to the second metal layer; the side surface of the first metal layer comprises a plurality of curved surfaces which are sequentially connected along the extension direction of the electrode structure, and at least one curved surface comprises a first sub-side surface and a second sub-side surface which are connected along the thickness direction of the semiconductor substrate; the width of the first metal layer at the connection position of the first sub-side surface and the second sub-side surface is greater than the width of other positions. Part of light irradiated to the second sub-side surface can be reflected to the first surface of the semiconductor substrate, and in addition, light reflected to the second sub-side surface from the surface of the semiconductor substrate can be reflected to the first surface again, so that the surface of the semiconductor substrate can receive more reflected light, and the utilization rate of the light is improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] However, in the existing solar cell manufacturing process, the main raw material of the electrode is silver, resulting in a high cost of the electrode structure. In addition, when the existing solar cell is in operation, part of the light will be reflected back to the environment by the side of the electrode structure, reducing the utilization rate of the light, which is not conducive to improving the photoelectric conversion efficiency of the solar cell. Summary of the invention

[0004] The purpose of the present application is to provide a solar cell and a photovoltaic module to reduce the reflection from the side of the electrode structure and improve the utilization rate of light.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell comprising:

[0007] A semiconductor substrate having a first surface and a second surface opposite to each other;

[0008] An electrode structure is formed on the first surface of the semiconductor substrate, the electrode structure comprising a first metal layer and a second metal layer stacked in sequence along the thickness direction of the semiconductor substrate, the first metal layer being closer to the semiconductor substrate than the second metal layer;

[0009] The side surface of the first metal layer includes multiple curved surfaces connected in sequence along the extension direction of the electrode structure, and at least one curved surface includes a first sub-side surface and a second sub-side surface connected along the thickness direction of the semiconductor substrate; the width of the first metal layer at the position where the first sub-side surface and the second sub-side surface are connected is greater than the width at other positions.

[0010] In the case of adopting the above technical solution, the position where the first sub-side surface and the second sub-side surface meet protrudes outward, so that part of the light irradiated on the first sub-side surface and the second sub-side surface can be reflected to the first surface of the semiconductor substrate, and the light reflected from the semiconductor substrate surface to the second sub-side surface can be reflected to the first surface again, which is beneficial for the semiconductor substrate surface to receive more reflected light, thereby improving the utilization rate of light. In addition, the side surface of the first metal layer includes a plurality of curved surfaces that are sequentially connected along the extension direction of the electrode structure, and the edge where the side surface of the first metal layer meets the semiconductor substrate includes a plurality of first arc edges, and the plurality of first arc edges can increase the length of the bottom side edge of the side surface of the first metal layer, and can increase the transmission path and area of ​​the carrier at the bottom side edge of the first metal layer, thereby helping to reduce the contact resistance. In addition, since the electrode structure provided in the embodiment of the present application includes two metal layers, namely the first metal layer and the second metal layer, it is possible to select a lower-priced material according to the functions required by the first metal layer and the second metal layer, thereby reducing costs. Further, since there is no conductive waste at the edge of the electrode structure provided in the embodiment of the present application, waste is avoided, and the cost of making the electrode structure is reduced.

[0011] In one implementation, a portion of the side surface of the first metal layer along the extension direction of the electrode structure facing the first surface of the semiconductor substrate is a polished surface, and the polished surface is conducive to improving the passivation effect;

[0012] Alternatively, a portion of the side surface of the first metal layer along the extension direction of the electrode structure facing the first surface of the semiconductor substrate is velvet to improve the adhesion between the electrode structure and the first surface of the semiconductor substrate.

[0013] In one implementation, the angle between the first sub-side surface and the second sub-side surface is an obtuse angle, so that the angle between the first sub-side surface and the first surface is larger, which is more conducive to the reflection of light irradiated on the first sub-side surface and the second sub-side surface to the semiconductor substrate, and is conducive to the semiconductor substrate surface receiving more reflected light.

[0014] In one implementation, the angle between the first sub-side surface and the first surface of the semiconductor substrate is greater than 45°; and / or the angle between the second sub-side surface and the first surface of the semiconductor substrate is greater than 45°. In this configuration, the angle between the first sub-side surface and / or the second sub-side surface and the first surface is larger, which is more conducive to the reflection of light incident on the first sub-side surface to the surface of the semiconductor substrate, and when the angle between the second sub-side surface and the first surface is larger, a part of the light can be directly irradiated onto the second sub-side surface, and then reflected by the second sub-side surface to the semiconductor substrate, thereby improving the utilization rate of light.

[0015] In one implementation, the boundary of the projection of the surface of the first metal layer close to the semiconductor substrate and the surface of the first metal layer away from the semiconductor substrate on the semiconductor substrate extends along a wavy line. By adopting this technical solution, the overall extension length of the first metal layer can be increased, thereby increasing the transmission path and area of ​​the carriers in the first metal layer, which is beneficial to reducing the contact resistance; or, the boundary of the projection of the surface of the first metal layer close to the semiconductor substrate and the surface of the first metal layer away from the semiconductor substrate on the semiconductor substrate extends along a straight line, which simplifies the processing technology of the electrode structure and facilitates improving the processing efficiency.

[0016] And / or, along the extension direction of the electrode structure, the arc length of at least one curved surface away from the semiconductor substrate is smaller than the arc length of the curved surface close to the semiconductor substrate. In this way, the edge lengths of both sides of the lower surface of the first metal layer can be increased, thereby increasing the transmission path and area of ​​carriers in the first metal layer, which is conducive to reducing contact resistance.

[0017] In one implementation, along the width direction of the electrode structure, the width of the second metal layer is greater than the width of the first metal layer away from the surface of the semiconductor substrate, which can ensure that there is a larger contact area between the second metal layer of the electrode structure and the welding strip or the interconnection part during the welding process, thereby improving the welding efficiency; or the width of the second metal layer is equal to the width of the first metal layer away from the surface of the semiconductor substrate, which can prevent the second metal layer from blocking the first metal layer and avoiding affecting the first metal layer from reflecting light toward the semiconductor substrate.

[0018] In one implementation, along the width direction of the electrode structure, the width of the second metal layer is greater than the width of the first metal layer away from the surface of the semiconductor substrate;

[0019] The second metal layer does not cover the side of the first metal layer, so that more light can be irradiated to the side of the first metal layer, and then more light can be reflected to the semiconductor substrate, thereby improving the utilization rate of light;

[0020] Alternatively, the second metal layer covers at least part of the side surface of the first metal layer. The part of the second metal layer covering the first metal layer can protect the first metal layer. When the first metal layer is a metal that is easily oxidized, surface oxidation of the first metal layer can be avoided before the solar cells are assembled into photovoltaic modules.

[0021] In one implementation, the second metal layer covers at least a portion of a side surface of the first metal layer;

[0022] At least a portion of the second metal layer extends continuously from the surface of the first metal layer away from the semiconductor substrate to the side of the first metal layer; in this way, the second metal layer covers the upper surface and side surfaces of the first metal layer as an integrated structure, so that the second metal layer covers the upper surface and side surfaces of the first metal layer as a whole and the adhesion between the surface of the first metal layer is stronger and it is not easy to separate from the first metal layer.

[0023] Alternatively, at least a portion of the second metal layer covering the surface of the first metal layer away from the semiconductor substrate is disconnected from a portion covering the side surface of the first metal layer.

[0024] In one implementation, the second metal layer covers at least a portion of a side surface of the first metal layer;

[0025] The second metal layer covers the surface of the first metal layer away from the semiconductor substrate and extends to cover the first surface of the semiconductor substrate. The second metal layer extends to cover the first surface of the semiconductor substrate so that the second metal layer can cover other film layers on the semiconductor substrate, such as partially doped semiconductor layers and / or transparent conductive layers, to play a protective role and prevent impurities in the air from contaminating the doped semiconductor layers and / or transparent conductive layers and affecting performance.

[0026] In one implementation, there is a gap between the second metal layer and the side of the first metal layer. With this technical solution, light emitted from the first metal layer will be reflected by the second metal layer toward the silicon substrate, which is beneficial to improving light absorption.

[0027] In one implementation, along the width of the electrode structure, the width of the second metal layer is greater than the width of the first metal layer away from the surface of the semiconductor substrate; the portion of the second metal layer that extends beyond the edge of the first metal layer away from the surface of the semiconductor substrate includes at least one element of the first metal layer.

[0028] In one implementation, the width W1 of the first metal layer away from the semiconductor substrate is 80% to 110% of the width W2 of the second metal layer, so as to avoid the side of the first metal layer being blocked by the second metal layer, so that more light is irradiated to the side of the first metal layer, and then more light is reflected to the semiconductor substrate, thereby improving the utilization rate of light and ensuring that the second metal layer of the electrode structure has a larger contact area with the welding strip or interconnection member during the welding process, thereby improving the welding efficiency.

[0029] In one implementation, the width of the second metal layer beyond the edge of the first metal layer away from the surface of the semiconductor substrate is 1μm to 30μm; using this technical solution, the edge of the second metal layer beyond the upper surface of the first metal layer is within a reasonable range, which not only ensures that there is a larger contact area between the second metal layer of the electrode structure and the welding strip or interconnection component during the welding process, but also avoids the side of the first metal layer being blocked by the second metal layer, so that more light can be irradiated to the side of the first metal layer.

[0030] And / or, the thickness of the first metal layer is 0.5μm to 20μm, so as to ensure strong adhesion between the first metal layer and the semiconductor substrate while reducing processing costs; and / or, the thickness of the second metal layer is 5nm to 300nm, so as to ensure strong welding between the second metal layer and the welding strip or the interconnection component while reducing processing costs; and / or, the thickness of the second metal layer is less than or equal to 10% of the thickness of the first metal layer, so as to ensure strong welding between the second metal layer and the welding strip or the interconnection component while facilitating patterning of the second metal layer, for example, making the laser used for laser patterning of the second metal layer more selective.

[0031] In one implementation, the first metal layer includes multiple first sub-metal layers stacked along the thickness direction of the semiconductor substrate. With this technical solution, the multiple first sub-metal layers can achieve different functions through the selection of materials for the multiple first sub-metal layers, for example, the metal in the second metal layer can be prevented from diffusing into the semiconductor substrate, resulting in a reduction in the short-circuit current density (Jsc); at the same time, the multiple first sub-metal layers can reduce the stress of the entire electrode structure and reduce the warpage.

[0032] In one implementation, the side surface of each first sub-metal layer is an inclined surface that is gradually inclined along the thickness direction of the semiconductor substrate, and the side surfaces of the multiple first sub-metal layers are sequentially connected to form a first sub-side surface and a second sub-side surface, and the side surfaces of the multiple first sub-metal layers that form the first sub-side surface have the same inclination angle as the first sub-side surface, and the side surfaces of the multiple first sub-metal layers that form the second sub-side surface have the same inclination angle as the second sub-side surface, so that the cross-section of the side surface of the first metal layer is similar to Thus, the overall structure of the side surface of the first metal layer is simple and easy to process and manufacture.

[0033] In one implementation, the side surface of the at least one first sub-metal layer includes a first sub-side surface and a second sub-side surface connected along the thickness direction of the semiconductor substrate; thus, the cross section of the side surface of the at least one first sub-metal layer is similar to shape, and the other side surfaces of the first sub-metal layer can be of any shape, which ensures that part of the light irradiated to the first sub-side surface and the second sub-side surface can be reflected to the first surface of the semiconductor substrate, while reducing the difficulty of processing the side surfaces of the first metal layer.

[0034] In one implementation, the side surface of each first sub-metal layer includes a first sub-side surface and a second sub-side surface connected along the thickness direction of the semiconductor substrate; or, the side surface of a first sub-metal layer or a plurality of adjacent first sub-metal layers includes a first sub-side surface and a second sub-side surface connected along the thickness direction of the semiconductor substrate. While reducing the processing difficulty of the side surface of the first metal layer, it can also ensure that part of the light irradiated onto the first sub-side surface and the second sub-side surface can be reflected to the first surface of the semiconductor substrate.

[0035] In one implementation, the edge region of the second metal layer is porous, and the porous structure can increase more diffuse reflection area, allowing more light to be incident on the semiconductor substrate; and / or,

[0036] The side surface of the first metal layer has a pit; and / or,

[0037] The side surface of the first metal layer has a texture pattern. The pit structure and the texture pattern can increase the roughness of the side surface of the first metal layer, thereby increasing the adhesion between the first metal layer and the packaging film during the packaging process.

[0038] In one implementation, the difference between the standard electrode potential of the first metal layer and the standard electrode potential of the second metal layer is 0.1V to 3.5V and the standard electrode potential of the first metal layer is less than the standard electrode potential of the second metal layer. In this way, during the wet etching process, the etching solution preferentially corrodes the first metal layer, forming the shape of the side of the first metal layer while ensuring that the second metal layer is not severely corroded.

[0039] In one implementation, the first metal layer includes one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and alloys thereof; and / or the second metal layer includes one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn and alloys thereof.

[0040] In one implementation, the solar cell further includes a buffer layer located between the electrode structure and the semiconductor substrate, the buffer layer facilitates the deposition of the first metal layer and improves the adhesion between the electrode structure and the semiconductor substrate;

[0041] Alternatively, the solar cell further includes a transparent conductive layer between the semiconductor substrate and the electrode structure. The transparent conductive layer has a high electrical conductivity, can reduce the contact resistance, can timely conduct the collected carriers, and reduce the carrier recombination rate.

[0042] Alternatively, the solar cell also includes a buffer layer and a transparent conductive layer stacked between the semiconductor substrate and the electrode structure, and the transparent conductive layer is closer to the semiconductor substrate relative to the buffer layer, so that the buffer layer can be used to improve the adhesion between the electrode structure and the semiconductor substrate, while the transparent conductive layer can be used to timely guide the collected carriers to reduce the carrier recombination rate.

[0043] In one implementation, the width of the transparent conductive layer is greater than or equal to the width of the electrode structure, so that the transparent conductive layer can be in full contact with the bottom surface of the electrode structure, further improving the carrier extraction rate.

[0044] In one implementation, the width of the transparent conductive layer is greater than the width of the electrode structure;

[0045] The difference between the width of the transparent conductive layer and the width of the electrode structure is greater than 0 and less than 30 μm, so as to ensure that the transparent conductive layer can be in full contact with the bottom surface of the electrode structure, while preventing the transparent conductive layer from being too large to block light or extending to another doped semiconductor layer of opposite conductivity type when the electrode structure is applied to a back contact battery, resulting in leakage.

[0046] In one implementation, the width of the transparent conductive layer is greater than the width of the electrode structure; and the difference between the width of the transparent conductive layer and the width of the electrode structure is greater than 0 and less than 10 μm.

[0047] In one implementation, the thickness of the buffer layer is 5 nm to 300 nm; the thickness of the buffer layer is less than or equal to 10% of the thickness of the first metal layer to ensure the transmission efficiency of carriers.

[0048] In one implementation, the solar cell further includes a doped semiconductor layer and a passivation layer stacked between the semiconductor substrate and the electrode structure; an opening is provided on the passivation layer, the electrode structure passes through the opening and contacts the doped semiconductor layer, and the electrode structure is recessed at the opening;

[0049] The roughness of the electrode structure at the opening is greater than the roughness of the electrode structure at other positions. In this technical solution, the roughness of the electrode structure at the opening is greater. During the packaging process, the contact area between the electrode structure at the opening and the packaging material can be increased, and the adhesion between the electrode structure at the opening and the packaging material can be improved, thereby improving the firmness of the electrode structure packaging;

[0050] And / or, at the opening, the first metal layer includes holes. In this technical solution, the holes included in the first metal layer can release stress, thereby preventing problems such as loose welding and warping of the battery cell caused by the release of stress from the electrode structure when the electrode structure is welded to the interconnection part, while saving raw materials for forming the first metal layer.

[0051] In one implementation, the solar cell is a back-contact cell, which also includes a first semiconductor region, a second semiconductor region, and an isolation region between the first semiconductor region and the second semiconductor region, which are arranged on the first surface of the semiconductor substrate; the electrode structure includes a first electrode arranged in the first semiconductor region and a second electrode arranged in the second semiconductor region.

[0052] A photovoltaic assembly comprises: a solar cell as described in any one of the above items.

[0053] Compared with the prior art, the beneficial effects of the photovoltaic module provided in the present application are the same as the beneficial effects of the above-mentioned solar cells, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0055] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0056] Figure 1 It is a top view SEM image of the electrode structure in the prior art;

[0057] Figure 2 It is a cross-sectional SEM image of an electrode structure in the prior art;

[0058] Figure 3 A schematic diagram of a photovoltaic module provided in an embodiment of the present application;

[0059] Figure 4 A cross-sectional view of a semiconductor substrate and an electrode structure provided in an embodiment of the present application;

[0060] Figure 5 A cross-sectional view of a semiconductor substrate and an electrode structure provided in another embodiment of the present application;

[0061] Figure 6 A SEM image of the side surface of the first metal layer provided in an embodiment of the present application;

[0062] Figure 7 for Figure 6 A partial enlarged view of the middle A area;

[0063] Figure 8 A partial top view of a solar cell provided in an embodiment of the present application;

[0064] Fig. 9A partial cross-sectional view of a solar cell provided in one embodiment of the present application;

[0065] Fig.10 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0066] Fig.11 A SEM image of a semiconductor substrate and an electrode structure provided in one embodiment of the present application;

[0067] Fig.12 for Fig.11 Enlarged schematic diagram;

[0068] Fig.13 A SEM image of the edge area of ​​the second metal layer provided in an embodiment of the present application;

[0069] Fig.14 A schematic diagram of an opening in a passivation layer of a solar cell provided in an embodiment of the present application;

[0070] Fig.15 A schematic diagram of an electrode structure of a solar cell provided by an embodiment of the present application passing through an opening of a passivation layer;

[0071] Fig.16 A top view SEM image of a solar cell provided in an embodiment of the present application;

[0072] Fig.17 This is a local cross-sectional SEM image of the solar cell provided in an embodiment of the present application.

[0073] Reference numerals:

[0074] 01-electrode structure, 02-conductive waste, 03-gentle slope;

[0075] 1-semiconductor substrate, 2-first metal layer, 2a-first sub-side, 2b-second sub-side, 2c-curved surface, 2d-hole, 3-second metal layer, 4-passivation layer, 4a-opening, 5-doped semiconductor layer. DETAILED DESCRIPTION

[0076] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0077] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0078] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0079] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0080] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0081] The present application embodiment provides a photovoltaic module, which includes a plurality of solar cells, and the plurality of solar cells are electrically connected in series and / or in parallel. For example, Figure 3 A schematic diagram of a plurality of solar cells electrically connected together is provided. Figure 3 As shown, multiple solar cells are arranged in sequence along direction A to form a battery string, and multiple solar cells in the battery string are connected in series in sequence. Two or more battery strings are arranged in sequence along direction A to form a group of battery strings, and multiple groups of battery strings are arranged in sequence along direction B.

[0082] In the existing solar cell manufacturing process, the main raw material of the electrode is silver, which leads to a high cost of the electrode structure 01. Figure 1 As shown, there are a lot of conductive wastes 02 near the edge of the electrode structure 01 formed by the prior art. Figure 2 As shown, the edge of the electrode structure 01 formed by the prior art is generally in a gentle slope shape 03, such as Figure 2The position shown by 03 in the figure results in a smaller angle between the edge of the electrode structure 01 and the surface of the semiconductor substrate. As a result, light incident on the edge of the electrode structure 01 will be basically reflected back into the environment, reducing the utilization rate of light.

[0083] In view of the above situation, in order to reduce the cost of the electrode structure, reduce the reflection on the side of the electrode structure and improve the utilization rate of light, the present application also provides a solar cell, which can be applied to the above photovoltaic module.

[0084] The present application provides a solar cell, which includes: a semiconductor substrate 1, the semiconductor substrate 1 having a first surface and a second surface relative to each other; an electrode structure formed on the first surface of the semiconductor substrate 1, the electrode structure including a first metal layer 2 and a second metal layer 3 arranged in sequence along the thickness direction of the semiconductor substrate 1, the first metal layer 2 being closer to the semiconductor substrate 1 relative to the second metal layer 3; a side surface of the first metal layer 2 including a plurality of curved surfaces 2c connected in sequence along an extension direction of the electrode structure, at least one curved surface 2c including a first sub-side surface 2a and a second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1; the width of the first metal layer 2 at a position where the first sub-side surface 2a and the second sub-side surface 2b are connected is greater than the width at other positions.

[0085] In some embodiments, the solar cell includes a semiconductor substrate 1, a first doped semiconductor layer, a second doped semiconductor layer and an electrode structure, wherein the first doped semiconductor layer and the second doped semiconductor layer are arranged between the semiconductor substrate 1 and the electrode structure. The semiconductor substrate 1 has a first surface and a second surface opposite to each other. The first doped semiconductor layer and the second doped semiconductor layer can both be arranged on the first surface of the semiconductor substrate 1, or the first doped semiconductor layer and the second doped semiconductor layer can be arranged on the first surface and the second surface, respectively. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types, so as to collect and extract electrons and holes, respectively, so as to facilitate the formation of photocurrent.

[0086] It can be understood that the first surface of the semiconductor substrate 1 corresponds to the backlight side of the solar cell, and the second surface of the semiconductor substrate 1 corresponds to the light-facing side of the solar cell; or, the first surface of the semiconductor substrate 1 corresponds to the light-facing side of the solar cell, and the second surface of the semiconductor substrate 1 corresponds to the backlight side of the solar cell. Based on this, the light-facing side of the semiconductor substrate 1 can be a plane, or the light-facing side of the semiconductor substrate 1 can have a texture structure, and the texture structure has a light-trapping effect. Therefore, when the light-facing side of the semiconductor substrate 1 has a texture structure, the reflectivity of the light-facing side can be reduced, which is conducive to more light being refracted from the light-facing side into the semiconductor substrate 1 and absorbed and utilized by the semiconductor substrate 1, which is conducive to improving the photoelectric conversion efficiency of the solar cell. The texture structure can be an inverted pyramid velvet structure, or a positive pyramid velvet structure, and of course, a wormhole velvet structure.

[0087] The material of the semiconductor substrate 1 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0088] Exemplarily, the semiconductor substrate 1 may be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0089] In addition, the materials of the first doped semiconductor layer and the second doped semiconductor layer can be silicon (Si), germanium (Ge), silicon carbide (SiCx) or gallium arsenide (GaAs), etc. The first doped semiconductor layer can be additionally formed on the semiconductor substrate 1 by deposition technology, and can also be formed in the semiconductor substrate 1 by diffusion, ion implantation, etc.

[0090] In terms of conductivity type, the first doped semiconductor layer may be an n-type doped layer, and the second doped semiconductor layer may be a p-type doped layer; or, the first doped semiconductor layer may be a p-type doped layer, and the second doped semiconductor layer may be an n-type doped layer.

[0091] The solar cell provided in the present application may include a first electrode and a second electrode, the first electrode being electrically connected to the first doped semiconductor layer, and the second electrode being electrically connected to the second doped semiconductor layer, so as to utilize the first electrode and the second electrode to extract carriers. In the case where the solar cell is a back-contact cell, the first doped semiconductor layer and the second doped semiconductor layer are both located on the first surface of the semiconductor substrate 1, and the electrode structure is also formed on the first surface of the semiconductor substrate 1, that is, the first electrode and the second electrode are both formed on the first surface. In the case where the solar cell is a bifacial cell, the first doped semiconductor layer and the second doped semiconductor layer are respectively located on the first surface and the second surface of the semiconductor substrate 1, and the electrode structure is formed on the first surface and the second surface of the semiconductor substrate 1, that is, the first electrode is formed on the first surface, and the second electrode is formed on the second surface.

[0092] It should be noted that the solar cell provided in the embodiment of the present application may be a double-sided solar cell or a back-contact solar cell.

[0093] In the case where the solar cell is a bifacial solar cell, the bifacial solar cell may be a PREC (Passivated Emitter Rear Cell) solar cell, a TOPCon (Tunnel Oxide Passivated Contact) solar cell or a HIT (Heterojunction with Intrinsic Thin-layer) solar cell.

[0094] The structure of a PREC solar cell may be, for example, that a first passivation layer and a first electrode are disposed on the backlight side of a semiconductor substrate, the first electrode is electrically connected to the semiconductor substrate through a through hole on the first passivation layer, an emitter is disposed on the light-facing side of the semiconductor substrate, a second passivation layer disposed on a side of the emitter away from the semiconductor substrate, and a second electrode, the second electrode is electrically connected to the emitter through a through hole on the second passivation layer. In the PREC solar cell, the materials of the first passivation layer and the second passivation layer may include one or more of SiNx and Al2O3.

[0095] The structure of a TOPCon solar cell may be, for example, that a tunnel oxide layer, a doped polysilicon layer, a first passivation layer and a first electrode are sequentially arranged on the backlight side of a semiconductor substrate, and the first electrode is electrically connected to the doped polysilicon layer through a through hole on the first passivation layer. An emitter, a second passivation layer and a second electrode are sequentially arranged on the light-facing side of the semiconductor substrate, and the second electrode is electrically connected to the emitter through a through hole on the second passivation layer. The materials of the first passivation layer and the second passivation layer may include one or more of SiNx and Al2O3.

[0096] The structure of a HIT solar cell can be, for example, as follows: a first intrinsic semiconductor layer, a first doped amorphous silicon layer, a first transparent conductive layer and a first electrode are sequentially arranged on the backlight side of the semiconductor substrate, and a second intrinsic semiconductor layer, a second doped amorphous silicon layer, a second transparent conductive layer and a second electrode are sequentially arranged on the light-facing side of the semiconductor substrate.

[0097] When the solar cell is a back contact solar cell, the back contact solar cell may be a HTBC (Heterojunction Tunnel Oxide Passivated Contact Back Contact) solar cell, an HBC (Heterojunction Back Contact) solar cell, a TBC (Tunnel Oxide Passivated Contact Back Contact) or a HPBC (Hybrid Passivated Back Contact) solar cell.

[0098] The structure of the HBC solar cell can be, for example, that the backlight surface of the semiconductor substrate includes alternating first semiconductor regions and second semiconductor regions, the first semiconductor region includes a first intrinsic amorphous silicon layer, a first doped amorphous silicon layer, a first transparent electrode layer and a first electrode sequentially arranged on the semiconductor substrate, and the second semiconductor region includes a second intrinsic amorphous silicon layer, a second doped amorphous silicon layer, a second transparent conductive layer and a second electrode sequentially arranged on the semiconductor substrate. Among them, one of the first semiconductor region and the second semiconductor region is a P-type region, and the other is an N-type region. The light-facing surface of the semiconductor substrate includes a passivation anti-reflection layer.

[0099] The structure of a TBC solar cell may be, for example, as follows: the backlight surface of the semiconductor substrate includes an alternating first semiconductor region and a second semiconductor region, the first semiconductor region includes a first tunneling oxide layer and a first doped polysilicon layer sequentially disposed on the semiconductor substrate, and the second semiconductor region includes a second tunneling oxide layer and a second doped polysilicon layer sequentially disposed on the semiconductor substrate; the structure of the TBC solar cell also includes a passivation layer disposed on the first doped polysilicon layer and the second doped polysilicon layer away from the semiconductor substrate, the first semiconductor region also includes a first electrode, the first electrode is electrically connected to the first doped polysilicon layer through a through hole on the passivation layer, and the second semiconductor region also includes a second electrode, the second electrode is electrically connected to the second doped polysilicon layer through a through hole on the passivation layer. Among them, one of the first semiconductor region and the second semiconductor region is a P-type region, and the other is an N-type region. The light-facing surface of the semiconductor substrate includes a passivation anti-reflection layer.

[0100] The structure of the HPBC solar cell may be, for example, that the backlight surface of the semiconductor substrate includes an alternating first semiconductor region and a second semiconductor region, the first semiconductor region includes a first tunneling oxide layer and a first doped polysilicon layer sequentially disposed on the semiconductor substrate, the structure of the HPBC solar cell also includes a passivation layer disposed on the side of the first doped polysilicon layer away from the semiconductor substrate, the first semiconductor region also includes a first electrode, the first electrode is electrically connected to the first doped polysilicon layer through a through hole in the passivation layer, and the second semiconductor region also includes a second electrode, the second electrode is electrically connected to the semiconductor substrate through a through hole in the passivation layer. Among them, one of the first semiconductor region and the second semiconductor region is a P-type region, and the other is an N-type region. The light-facing surface of the semiconductor substrate includes a passivation anti-reflection layer.

[0101] The structure of the HTBC solar cell may be, for example, that the backlight surface of the semiconductor substrate includes alternating first and second semiconductor regions, the first semiconductor region includes a tunneling oxide layer, a doped polysilicon layer, a transparent conductive layer, and a first electrode sequentially disposed on the semiconductor substrate, and the second semiconductor region includes an intrinsic amorphous silicon layer, a doped amorphous silicon layer, a transparent conductive layer, and a second electrode sequentially disposed on the semiconductor substrate. Among them, one of the first semiconductor region and the second semiconductor region is a P-type region, and the other is an N-type region. The light-facing surface of the semiconductor substrate includes a passivation anti-reflection layer.

[0102] In the above-mentioned various solar cell structures, when a passivation layer is provided on the side of the doped semiconductor layer facing away from the semiconductor substrate, at least one opening 4a is provided on the passivation layer, and the electrode structure contacts the doped semiconductor layer through the opening 4a; when a transparent conductive layer is provided on the side of the doped semiconductor layer facing away from the semiconductor substrate, the bottom of the electrode structure is in direct contact with the side of the transparent conductive layer facing away from the doped semiconductor layer; when neither a passivation layer nor a transparent conductive layer is provided on the side of the doped semiconductor layer facing away from the semiconductor substrate, the bottom of the electrode structure is in direct contact with the side of the doped semiconductor layer facing away from the semiconductor substrate.

[0103] The electrode structure in the present application may include the above-mentioned first electrode and / or second electrode. In addition, the first electrode and the second electrode may only include bus electrodes or only include collector electrodes; of course, they may also include collector electrodes and bus electrodes.

[0104] like Figure 4 As shown, the electrode structure includes a first metal layer 2 and a second metal layer 3, and the first metal layer 2 and the second metal layer 3 are sequentially stacked along the thickness direction of the semiconductor substrate 1, and the first metal layer 2 is closer to the semiconductor substrate 1 than the second metal layer 3, that is, the first metal layer 2 is located between the second metal layer 3 and the semiconductor substrate 1. Figure 6 and Figure 7As shown, the side surface of the first metal layer 2 includes multiple curved surfaces 2c connected in sequence along the extension direction of the electrode structure. In some examples, along the extension direction of the electrode structure, the side surfaces of both sides of the first metal layer 2 include multiple curved surfaces 2c connected in sequence, and the sizes and depths of the multiple curved surfaces 2c along the extension direction of the electrode structure can be the same or different. The above-mentioned curved surface 2c can be a concave curved surface.

[0105] It can be understood that the first metal layer 2 includes a lower surface close to the semiconductor substrate 1 and an upper surface away from the semiconductor substrate 1 which are arranged relatively along the thickness direction, and side surfaces except the upper and lower surfaces.

[0106] like Figure 4 and Figure 7 As shown, at least one curved surface 2c includes a first sub-side surface 2a and a second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1, and the first sub-side surface 2a is located on the side of the second sub-side surface 2b away from the semiconductor substrate 1, that is, the second sub-side surface 2b is located between the first sub-side surface 2a and the semiconductor substrate 1. The width of the first metal layer 2 at the junction of the first sub-side surface 2a and the second sub-side surface 2b is greater than the width at other locations. Specifically, as Fig. 9 As shown, the surface that separates the first metal layer 2 into two parts along the width direction and is perpendicular to the first surface of the semiconductor substrate 1 is the separation plane, the first sub-side surface 2a gradually moves away from the above-mentioned separation plane along the direction approaching the semiconductor substrate 1, and the second sub-side surface 2b gradually moves away from the above-mentioned separation plane along the direction away from the semiconductor substrate 1, so that the position where the first sub-side surface 2a and the second sub-side surface 2b are connected is farthest from the separation plane, so that the width of the first metal layer 2 is the largest at the position where the first sub-side surface 2a and the second sub-side surface 2b are connected.

[0107] It should be noted that, for the multiple curved surfaces 2c included in the first metal layer 2, one curved surface 2c may include a first sub-side surface 2a and a second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1, or multiple curved surfaces 2c may include a first sub-side surface 2a and a second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1. In the case where multiple curved surfaces 2c include a first sub-side surface 2a and a second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1, the ridgeline between the first sub-side surface 2a and the second sub-side surface 2b in the multiple curved surfaces 2c may be at the same distance from the semiconductor substrate or at different distances.

[0108] In the case of adopting the above technical solution, the position where the first sub-side surface 2a and the second sub-side surface 2b meet protrudes outward, so that part of the light irradiated on the first sub-side surface 2a and the second sub-side surface 2b can be reflected to the first surface of the semiconductor substrate 1, and the light reflected from the first surface of the semiconductor substrate 1 to the second sub-side surface 2b can be reflected to the first surface again, which is beneficial for the surface of the semiconductor substrate 1 to receive more reflected light, thereby improving the utilization rate of light. In addition, the side of the first metal layer 2 includes a plurality of curved surfaces 2c that are sequentially connected along the extension direction of the electrode structure, and the edge where the side of the first metal layer 2 meets the semiconductor substrate 1 includes a plurality of first arc edges, and the plurality of first arc edges can increase the length of the bottom edge of the side of the first metal layer 2, and can increase the transmission path and area of ​​the carrier at the bottom edge of the first metal layer 2, thereby helping to reduce the contact resistance. In addition, since the electrode structure provided in the embodiment of the present application includes two metal layers, namely the first metal layer 2 and the second metal layer 3, it is possible to select a lower-priced material according to the functions required by the first metal layer 2 and the second metal layer 3, thereby reducing costs. Further, since there is no conductive waste at the edge of the electrode structure provided in the embodiment of the present application, waste is avoided, and the cost of making the electrode structure is reduced.

[0109] In the above technical solution, if Figure 4 As shown, the first sub-side surface 2a may be a plane, and the second sub-side surface 2b may also be a plane; or Figure 5 As shown, the first sub-side surface 2a may also be a curved surface 2c, and the second sub-side surface 2b may also be a curved surface 2c.

[0110] In some embodiments, Figure 6-Figure 7 As shown, the side of the first metal layer 2 along the extension direction of the electrode structure facing the first surface of the semiconductor substrate 1 is a polished surface. The setting of the polished surface can improve the passivation effect. In this technical solution, the electrode structure can be set as a whole on the polished surface to improve the passivation effect; or, the two side surfaces of the electrode structure facing the first surface of the semiconductor substrate 1 are polished surfaces, and the part between the two side surfaces of the electrode structure facing the first surface of the semiconductor substrate 1 is a velvet surface, so as to increase the contact area between the electrode structure and the first surface of the semiconductor substrate 1, and improve the adhesion between the electrode structure and the first surface of the semiconductor substrate 1. The velvet surface may include a tower base structure, a pyramid structure and / or an inverted pyramid structure.

[0111] In other embodiments, the side surface of the first metal layer 2 along the extension direction of the electrode structure facing the first surface of the semiconductor substrate 1 is a velvet surface, so as to increase the contact area between the two side edges of the first metal layer 2 and the first surface of the semiconductor substrate 1, and to increase the adhesion between the two side edges of the first metal layer 2 and the first surface of the semiconductor substrate 1. In this technical solution, the electrode structure can be arranged as a whole on the velvet surface to increase the adhesion between the electrode structure and the first surface of the semiconductor substrate 1; or, the two side surfaces of the electrode structure facing the first surface of the semiconductor substrate 1 are velvet surfaces, and the part between the two side surfaces of the electrode structure facing the first surface of the semiconductor substrate 1 is a polished surface, so as to improve the passivation effect. The velvet surface can include a tower base structure, a pyramid structure and / or an inverted pyramid structure.

[0112] In some embodiments, Figure 14-16 As shown, the solar cell further includes a doped semiconductor layer 5 and a passivation layer 4 stacked between the semiconductor substrate 1 and the electrode structure, and the passivation layer 4 is located on the side of the doped semiconductor layer 5 away from the semiconductor substrate. The passivation layer 4 can be one or more layers, and the passivation layer 4 can be some film layers that can play a passivation, anti-reflection or insulation role. The passivation layer 4 is provided with an opening 4a, and the opening 4a can be any shape such as circular, elliptical, square, etc. Fig.16 As shown, the electrode structure passes through the opening 4a and contacts the doped semiconductor layer 5, and the electrode structure is recessed at the opening 4a. In this technical solution, the solar cell can be a TOPCon solar cell or a TBC solar cell.

[0113] Further, such as Fig.16 and Fig.17 As shown, the roughness of the electrode structure at the opening is greater than the roughness of the electrode structure at other locations, such as Fig.16 and Fig.17 The roughness of the middle electrode structure in the C region is greater than the roughness in the surrounding region. In this technical solution, the roughness of the electrode structure at the opening is greater, and during the packaging process, the contact area between the electrode structure at the opening and the packaging material can be increased, and the adhesion between the electrode structure at the opening and the packaging material can be improved, thereby improving the firmness of the electrode structure packaging.

[0114] like Fig.17 As shown, at the opening, the first metal layer 2 includes a hole 2d, and the hole 2d can be located near the boundary of the opening or inside the opening. The first metal layer 2 is missing at the hole 2d. In this technical solution, the hole 2d included in the first metal layer 2 can release stress, preventing problems such as loose welding and warping of the battery cell caused by the release of stress from the electrode structure when welding the electrode structure to the interconnection part, while saving the raw materials for forming the first metal layer 2.

[0115] In a specific embodiment, the angle between the first sub-side surface 2a and the second sub-side surface 2b is an obtuse angle, that is, the angle between the first sub-side surface 2a and the second sub-side surface 2b toward the separation surface is an obtuse angle, that is, the angle between the first sub-side surface 2a and the second sub-side surface 2b is greater than 90° and less than 180°. In this way, the angle between the first sub-side surface 2a and the first surface is larger, which is more conducive to the reflection of the light irradiated on the first sub-side surface 2a to the semiconductor substrate 1, and the surface of the semiconductor substrate 1 is conducive to receiving more reflected light.

[0116] Further, the angle between the first sub-side surface 2a and the first surface of the semiconductor substrate 1 is greater than 45°, and / or the angle between the second sub-side surface 2b and the first surface of the semiconductor substrate 1 is greater than 45°. Among them, the angle between the first sub-side surface 2a and the first surface of the semiconductor substrate 1 refers to the smaller angle of the two angles where the first sub-side surface 2a intersects with the first surface; the angle between the second sub-side surface 2b and the first surface of the semiconductor substrate 1 refers to the smaller angle of the two angles where the second sub-side surface 2b intersects with the first surface. In this way, the angle between the first sub-side surface 2a and the first surface is larger, which is more conducive to the reflection of the light incident on the first sub-side surface 2a to the surface of the semiconductor substrate 1, further improving the utilization rate of the light. In addition, after the light incident on the surface of the semiconductor substrate is reflected to the second sub-side surface 2b, it is reflected to the semiconductor substrate by the second sub-side surface 2b to improve the utilization rate of light. When the angle between the second sub-side surface 2b and the first surface is larger, a part of the light can be directly irradiated to the second sub-side surface 2b, and then reflected to the semiconductor substrate by the second sub-side surface 2b, which also improves the utilization rate of light.

[0117] Exemplarily, the angle between the first sub-side surface 2a and the first surface of the semiconductor substrate 1 can be 46°, 48°, 50°, 55°, 60° or 65°; the angle between the second sub-side surface 2b and the first surface of the semiconductor substrate 1 can be 46°, 48°, 50°, 55°, 60° or 65°.

[0118] In addition, the electrode structure of the solar cell includes a first metal layer 2 and a second metal layer 3, wherein the second metal layer 3 can be used as a welding layer, the second metal layer 3 can be made of a weldable metal material, and the first metal layer 2 can be made of a metal material with low cost and good conductivity. Compared with the electrode structure in the prior art as an integrated structure, since the first metal layer 2 and the second metal layer 3 can be made of different materials as needed, different functions can be achieved.

[0119] Since at least part of the surface of the first metal layer 2 is covered by the second metal layer 3, the second metal layer 3 protects the first metal layer 2 and prevents the first metal layer 2 from being corroded by oxidation. Therefore, the first metal layer 2 can be formed by a metal that is not resistant to acid and alkali corrosion, and the second metal layer 3 can be formed by a metal that is resistant to acid and alkali corrosion. Compared with the prior art in which the electrode structure is an integrated structure and all of the metals resistant to acid and alkali corrosion are selected, the selectivity of the first metal layer 2 is increased, which is conducive to patterning the first metal layer 2 and the second metal layer 3.

[0120] In the process of preparing the electrode structure, the first metal layer 2 and the second metal layer 3 can be formed by LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), etc., so that the first metal layer 2 and the second metal layer 3 have a high density, and when the second metal layer 3 is used as a welding layer, it is beneficial to improve the welding effect of the second metal layer 3. Compared with the electrode formed by printing in the prior art, the electrode structure provided by the present application, for example, the first metal layer 2 and the second metal layer 3 in the electrode structure formed by the above method have clear edges of the electrode structure 01 and less conductive waste 02, which avoids the conductive waste 02 blocking the light and affecting the collection of carriers. The above-mentioned various methods can be used to first form a first metal layer 2 and a second metal layer 3 that are set as a whole layer, and then a wet etching process can be used to etch to form a patterned first metal layer 2 and a second metal layer 3, and the side of the first metal layer 2 can be processed to form a first sub-side surface 2a and a second sub-side surface 2b.

[0121] It can be understood that the first metal layer 2 and the second metal layer 3 can be formed by the same process. For example, the first metal layer 2 and the second metal layer 3 can be both formed by magnetron sputtering or both formed by evaporation; alternatively, the first metal layer 2 and the second metal layer 3 can be formed by different processes. For example, the first metal layer 2 is formed by magnetron sputtering and the second metal layer 3 is formed by evaporation, or the first metal layer 2 is formed by evaporation and the second metal layer 3 is formed by magnetron sputtering.

[0122] From a microscopic perspective, the edge where the side of the first metal layer 2 meets the semiconductor substrate 1 includes a plurality of first arc edges, that is, the boundary of the orthographic projection of the lower surface of the first metal layer 2 on the semiconductor substrate 1 is formed by the connection of a plurality of first arc edges. The upper side boundary of the side of the first metal layer 2 includes a plurality of second arc edges, and the boundary of the orthographic projection of the upper surface of the first metal layer 2 on the semiconductor substrate 1 is formed by the connection of a plurality of second arc edges. In this way, the transmission path and area of ​​carriers at the bottom edge and the top edge of the first metal layer 2 can be increased, which is conducive to reducing the contact resistance. Among them, the arc length, chord length or chord height of the plurality of first arc edges can be the same or different, the arc length, chord length or chord height of the plurality of second arc edges can be the same or different, and the arc length, chord length or chord height of the first arc edge and the second arc edge can be the same or different.

[0123] From a macro perspective, Figure 8 As shown, the boundary of the orthographic projection of the surface of the first metal layer 2 close to the semiconductor substrate 1 and the surface of the first metal layer 2 far from the semiconductor substrate 1 on the semiconductor substrate 1 extends along the wavy line. In other words, the boundary of the orthographic projection of the upper surface and the lower surface of the first metal layer 2 on the semiconductor substrate 1 extends along the wavy line. It can be understood that the boundary of the orthographic projection of the surface of the first metal layer 2 close to the semiconductor substrate 1 and the surface of the first metal layer 2 far from the semiconductor substrate 1 on the semiconductor substrate 1 is as shown in FIG. Figure 8 As shown, the overall appearance is that it extends along the wavy line. By adopting this technical solution, the overall extension length of the first metal layer 2 can be increased, thereby increasing the transmission path and area of ​​the carriers in the first metal layer 2, which is beneficial to reduce the contact resistance.

[0124] Alternatively, the boundaries of the orthographic projections of the surface of the first metal layer 2 close to the semiconductor substrate 1 and the surface of the first metal layer 2 away from the semiconductor substrate 1 on the semiconductor substrate 1 extend along a straight line. In other words, the boundaries of the orthographic projections of the upper surface and the lower surface of the first metal layer 2 on the semiconductor substrate 1 extend along a straight line. It can be understood that the boundaries of the orthographic projections of the surface of the first metal layer 2 close to the semiconductor substrate 1 and the surface of the first metal layer 2 away from the semiconductor substrate 1 on the semiconductor substrate 1 appear to extend along a straight line as a whole. The use of this technical solution simplifies the processing technology of the electrode structure, which is convenient for improving processing efficiency.

[0125] Along the extension direction of the electrode structure, the arc length of at least one curved surface 2c away from the semiconductor substrate is smaller than the arc length of the curved surface 2c close to the semiconductor substrate. That is, along the extension direction of the electrode structure, the extension length of the upper edge of the curved surface 2c is smaller than the extension length of the lower edge of the curved surface 2c, and the curved surface 2c included in the side surface of the first metal layer 2 is narrow at the top and wide at the bottom. In this way, the length of the two side edges of the lower surface of the first metal layer 2 can be increased, thereby increasing the transmission path and area of ​​the carriers in the first metal layer 2, which is conducive to reducing the contact resistance.

[0126] like Figure 4 As shown, along the width direction of the electrode structure, the width W2 of the second metal layer 3 is greater than the width W1 of the surface of the first metal layer 2 away from the semiconductor substrate 1, that is, the width W2 of the second metal layer 3 is greater than the width W1 of the upper surface of the first metal layer 2. This arrangement can ensure that there is a larger contact area between the second metal layer 3 of the electrode structure and the welding strip or interconnection during the welding process, thereby improving the welding efficiency. Alternatively, the width W2 of the second metal layer 3 is equal to the width W1 of the surface of the first metal layer 2 away from the semiconductor substrate 1, that is, the width of the second metal layer 3 is equal to the width W1 of the upper surface of the first metal layer 2. This arrangement can prevent the second metal layer 3 from blocking the first metal layer 2, avoid affecting the absorption of light by the first metal layer 2, and prevent the first metal layer 2 from reflecting light to the semiconductor substrate 1. Of course, the width of the second metal layer 3 can also be less than the width of the surface of the first metal layer 2 away from the semiconductor substrate 1, that is, the width of the second metal layer 3 is less than the width of the upper surface of the first metal layer 2, which is not limited here.

[0127] In which, when the width W2 of the second metal layer 3 is greater than the width W1 of the first metal layer 2 away from the surface of the semiconductor substrate 1, the portion of the second metal layer 3 that extends beyond the first metal layer 2 may extend in a direction parallel to the first surface of the semiconductor substrate 1, may extend in a direction close to the first surface of the semiconductor substrate 1, or may extend in a direction away from the first surface of the semiconductor substrate 1.

[0128] It should be noted that in the embodiment of the present application, the relationship between the width W2 of the second metal layer 3 in the electrode structure and the width W1 of the first metal layer 2 away from the surface of the semiconductor substrate 1, as well as the position setting relationship between the second metal layer 3 and the first metal layer 2, can be any position of the electrode structure that satisfies the relationship described in the specification of the present application, or all positions of the electrode structure can satisfy the relationship described in the specification of the present application. In addition, for different positions of the electrode structure, the size relationship and position setting relationship of the second metal layer 3 and the first metal layer 2 can be the same or different.

[0129] like Figure 4 As shown, along the width direction of the electrode structure, the width W2 of the second metal layer 3 is greater than the width W1 of the first metal layer 2 away from the surface of the semiconductor substrate 1, and the second metal layer 3 does not cover the side of the first metal layer 2, so that more light can be irradiated to the side of the first metal layer 2, and then more light can be reflected to the semiconductor substrate 1, thereby improving the utilization rate of light.

[0130] Or, if Fig. 9 and Fig.10 As shown, the second metal layer 3 covers at least part of the side surface of the first metal layer 2. Specifically, as Fig.10As shown, the second metal layer 3 covers all sides of the first metal layer 2; or Fig. 9 As shown, the second metal layer 3 may also cover part of the side surface of the first metal layer 2. The part of the first metal layer 2 covered by the second metal layer 3 can protect the first metal layer 2, for example, to prevent oxidation or scratches. When the first metal layer 2 is a metal that is easily oxidized, the surface oxidation of the first metal layer 2 can be avoided before the solar cell is assembled into a photovoltaic module.

[0131] like Fig. 9 As shown, at least part of the second metal layer 3 extends continuously from the surface of the first metal layer 2 away from the semiconductor substrate 1 to the side of the first metal layer 2, that is, the second metal layer 3 extends continuously from the upper surface of the first metal layer 2 to the two side surfaces of the first metal layer 2. In this solution, the entire second metal layer 3 can be continuously extended from the upper surface of the first metal layer 2 to the two side surfaces of the first metal layer 2, or part of the second metal layer 3 can be continuously extended from the upper surface of the first metal layer 2 to the two side surfaces of the first metal layer 2. In this way, the second metal layer 3 covering the upper surface and side surfaces of the first metal layer 2 is an integrated structure, so that the second metal layer 3 covering the upper surface and side surfaces of the first metal layer 2 is more firmly bonded to the surface of the first metal layer 2 as a whole, and is not easy to separate from the first metal layer 2.

[0132] Alternatively, at least part of the second metal layer 3 covering the surface of the first metal layer 2 away from the semiconductor substrate 1 is disconnected from the part covering the side of the first metal layer 2, that is, part of the second metal layer 3 covers the upper surface of the first metal layer 2, and part of the second metal layer 3 covers the side of the first metal layer 2, and the part of the second metal layer 3 covering the upper surface of the first metal layer 2 is disconnected and discontinuous from the part covering the side of the first metal layer 2.

[0133] like Figure 10-12 As shown, the second metal layer 3 covers the surface of the first metal layer 2 away from the semiconductor substrate 1, and extends to cover the first surface of the semiconductor substrate 1. Specifically, the second metal layer 3 covers the upper surface of the first metal layer 2, and the second metal layer 3 extends to cover the first surface of the semiconductor substrate 1, so that the second metal layer 3 can not only protect the first metal layer 2, but also cover other film layers on the semiconductor substrate 1, such as part of the semiconductor layer and / or the transparent conductive layer, to play a protective role, and prevent impurities in the air from contaminating the semiconductor layer and / or the transparent conductive layer, etc., and affecting the performance.

[0134] Furthermore, there is a gap between the second metal layer 3 and the side of the first metal layer 2, that is, the second metal layer 3 does not contact the side of the first metal layer 2, and the second metal layer 3 extends from the side of the first metal layer 2 to the first surface of the semiconductor substrate 1. With this technical solution, light emitted from the first metal layer 2 will be reflected by the second metal layer 3 toward the silicon substrate, which is conducive to improving light absorption.

[0135] In another specific embodiment, the first metal layer 2 includes multiple first sub-metal layers stacked along the thickness direction of the semiconductor substrate 1. With such a configuration, multiple first sub-metal layers can be processed in sequence to form multiple layers. The materials of the multiple first sub-metal layers can be different, and the thicknesses of the multiple first sub-metal layers can be the same or different. The number of layers, thickness and material of the first sub-metal layer can be set according to actual conditions. Specifically, the first sub-metal layer can be 2 layers, 3 layers, 4 layers or more layers. With this technical solution, different purposes can be achieved by reasonably selecting the materials of each first sub-metal layer in the first metal layer 2. For example, by selecting the first sub-metal layer, the metal in the second metal layer 3 is prevented from diffusing into the semiconductor substrate, resulting in a decrease in the short-circuit current density (Jsc); at the same time, multiple first sub-metal layers can reduce the stress of the entire electrode structure and reduce the warpage.

[0136] In the above embodiment, the side surface of each first sub-metal layer is an inclined surface that is gradually inclined along the thickness direction of the semiconductor substrate 1, and the side surfaces of the multiple first sub-metal layers are sequentially connected to form a first sub-side surface 2a and a second sub-side surface 2b. Specifically, the side surfaces of the multiple first sub-metal layers that form the first sub-side surface 2a have the same inclination angle as the first sub-side surface 2a, and the side surfaces of the multiple first sub-metal layers that form the second sub-side surface 2b have the same inclination angle as the second sub-side surface 2b, so that the cross-section of the side surface of the first metal layer 2 as a whole forms a cross-section similar to Thus, the overall structure of the side surface of the first metal layer 2 is simple and easy to process and manufacture.

[0137] In another embodiment, the side surface of at least one first sub-metal layer includes a first sub-side surface 2a and a second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1. Thus, the cross section of the side surface of at least one first sub-metal layer is similar to The shape of the other side surfaces of the first sub-metal layer can be of any shape, which ensures that part of the light irradiated to the first sub-side surface 2a and the second sub-side surface 2b can be reflected to the first surface of the semiconductor substrate 1, while reducing the difficulty of processing the side surfaces of the first metal layer 2.

[0138] Furthermore, the side surface of each first sub-metal layer may include a first sub-side surface 2a and a second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1, that is, the cross section of the side surface of each first sub-metal layer is similar to The technical solution is more conducive to reflecting the light irradiated to the side of the first metal layer 2 from various angles to the semiconductor substrate 1. Alternatively, the side of only one first sub-metal layer may include the first sub-side surface 2a and the second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1, or the side of multiple adjacent first sub-metal layers may include the first sub-side surface 2a and the second sub-side surface 2b connected along the thickness direction of the semiconductor substrate 1, which reduces the processing difficulty of the side of the first metal layer 2 and ensures that part of the light irradiated to the first sub-side surface 2a and the second sub-side surface 2b can be reflected to the first surface of the semiconductor substrate 1.

[0139] In addition, if Fig.13 As shown, the edge region of the second metal layer 3 may be a porous structure, and the porous structure may increase more diffuse reflection area, allowing more light to be incident on the semiconductor substrate 1. The width of the edge region of the second metal layer 3 may be 1 μm to 10 μm, for example, the width of the edge region of the second metal layer 3 is 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm.

[0140] As a possible implementation, the side of the first metal layer 2 has a pit, and the pit structure can increase the roughness of the side of the first metal layer 2, thereby increasing the adhesion between the first metal layer 2 and the packaging film during the packaging process. It can be understood that in some embodiments, the side 2a of the first metal layer 2 has a pit; in other embodiments, the side of the first metal layer 2 has no pit.

[0141] Alternatively, the side surface of the first metal layer 2 has a textured pattern, and the textured pattern can also increase the roughness of the side surface of the first metal layer 2, thereby increasing the adhesion between the first metal layer 2 and the packaging film during the packaging process.

[0142] Considering that the width W1 of the surface of the first metal layer 2 away from the semiconductor substrate 1 is much smaller than the width W2 of the second metal layer 3, the side of the first metal layer 2 will be blocked by the second metal layer 3, affecting the utilization rate of light; if the width W1 of the surface of the first metal layer 2 away from the semiconductor substrate 1 is much larger than the width W2 of the second metal layer 3, then when the overall width of the electrode structure remains unchanged, the width of the second metal layer 3 will be limited, reducing the contact area between the second metal layer 3 and the welding strip or the interconnection component. Therefore, when designing the width of the first metal layer 2 and the second metal layer 3, the width W1 of the surface of the first metal layer 2 facing away from the semiconductor substrate 1 can be 80% to 110% of the width W2 of the second metal layer 3, that is, the width W1 of the upper surface of the first metal layer 2 is 80% to 110% of the width W2 of the second metal layer 3, so as to avoid the side of the first metal layer 2 being blocked by the second metal layer 3, so that more light is irradiated to the side of the first metal layer 2, and then more light is reflected to the semiconductor substrate 1, thereby improving the utilization rate of light and ensuring that there is a larger contact area between the second metal layer 3 in the electrode structure and the welding strip or interconnection part during the welding process, thereby improving the welding efficiency.

[0143] Exemplarily, the width W1 of the surface of the first metal layer 2 facing away from the semiconductor substrate 1 is 80%, 85%, 90%, 95%, 100%, 105% or 110% of the width W2 of the second metal layer 3 .

[0144] like Figure 4 As shown, the width L1 of the portion of the second metal layer 3 that exceeds the edge of the surface of the first metal layer 2 away from the semiconductor substrate 1 is 1μm to 30μm. Specifically, the second metal layer 3 may exceed the edge of the upper surface of the first metal layer 2 on only one side, or both sides of the second metal layer 3 may exceed the edge of the upper surface of the first metal layer 2. On this basis, for any side of the electrode structure along its width direction, the second metal layer 2 may exceed the edge of the upper surface of the first metal layer 2 in the extension direction of the electrode structure in whole or in part. The width L1 of the portion of the second metal layer 3 that exceeds the edge of the upper surface of the first metal layer 2 is 1μm to 30μm, for example, 1μm, 5μm, 10μm, 15μm, 20μm, 25μm or 30μm. With this technical solution, the edge of the second metal layer 3 that exceeds the upper surface of the first metal layer 2 is within a reasonable range, which not only ensures that there is a large contact area between the second metal layer 3 of the electrode structure and the welding strip or interconnection during welding, but also avoids the side of the first metal layer 2 being blocked by the second metal layer 3, so that more light can be irradiated to the side of the first metal layer 2.

[0145] Considering that if the thickness of the first metal layer 2 is too small, the resistance of the electrode structure may be large, and the bonding between the first metal layer 2 and the semiconductor substrate 1 may not be strong, and if the thickness of the second metal layer 3 is too large, the cost may be high, so the thickness of the first metal layer 2 can be set within a reasonable range of 0.5 μm to 20 μm to ensure that the resistance of the electrode structure is small, the bonding between the first metal layer 2 and the semiconductor substrate 1 is strong, and the processing cost is reduced. For example, the thickness of the first metal layer 2 is 0.5 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm, etc.

[0146] Considering that if the thickness of the second metal layer 3 is too small, the welding between the second metal layer 3 and the welding strip or the interconnection part may not be firm, and if the thickness of the second metal layer 3 is too large, the selectivity of the laser is less during the laser patterning process, the thickness of the second metal layer 3 is set within a reasonable range of 5nm to 300nm to ensure that the welding between the second metal layer 3 and the welding strip or the interconnection part is firm, while the selectivity of the laser during the laser patterning process is not limited. For example, the thickness of the second metal layer 3 is 5nm, 25nm, 50nm, 75nm, 100nm, 125nm, 150nm, 175nm, 200nm, 225nm, 250nm, 275nm or 300nm, etc.

[0147] The thickness of the second metal layer 3 is less than or equal to 10% of the thickness of the first metal layer 2 to ensure that the second metal layer is firmly welded to the welding strip or the interconnection component while facilitating the patterning of the second metal layer. For example, the laser used for laser patterning of the second metal layer has more selectivity. For example, the thickness of the second metal layer 3 is 10%, 9%, 8%, 7%, 6% or 5% of the thickness of the first metal layer 2.

[0148] In another embodiment, the difference between the standard electrode potential of the first metal layer 2 and the standard electrode potential of the second metal layer 3 is 0.1V to 3.5V, and the standard electrode potential of the first metal layer 2 is less than the standard electrode potential of the second metal layer 3. In this way, during the wet etching process, the etching solution preferentially corrodes the first metal layer 2, forming the shape of the side of the first metal layer 2 while ensuring that the second metal layer 3 is not severely corroded. In the case where the first metal layer 2 includes multiple first sub-metal layers, the difference between the standard electrode potential of any first sub-metal layer and the standard electrode potential of the second metal layer 3 is 0.1V to 3.5V. Exemplarily, the difference between the standard electrode potential of the first metal layer 2 and the standard electrode potential of the second metal layer 3 is 0.1V, 0.5V, 1V, 1.5V, 2V, 2.5V, 3V or 3.5V, etc.

[0149] Optionally, the standard electrode potential of the first metal layer 2 is less than the standard electrode potential of the second metal layer 3. This arrangement ensures that the transmission resistance between the first metal layer 2 and the semiconductor substrate 1 is low, thereby reducing current loss.

[0150] From the material point of view, the first metal layer 2 may include one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and their alloys. The second metal layer 3 may include one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn and their alloys. It can be understood that the materials of the first metal layer 2 and the second metal layer 3 are different, and the materials of the first metal layer 2 and the second metal layer 3 cannot be Cu or Ag at the same time.

[0151] As a possible implementation, the solar cell further includes a buffer layer located between the electrode structure and the semiconductor substrate 1 , and the buffer layer facilitates the deposition of the first metal layer 2 and improves the adhesion between the electrode structure and the semiconductor substrate 1 .

[0152] In terms of materials, the buffer layer may include one or more of metal oxides, metal nitrides, metal fluorides, metal silicides and metals. Among them, metal oxides include AZO, TiO X 、Cu2O、MgO X 、TaO X , VO X CrO X , SnO2, B:ZnO (boron-doped zinc oxide), CdO X and MoO X One or more of. Metal nitrides include TiN X and TiO X The metal fluoride includes one or more of MgF2, LiF, YF3 and CeF3. The metal silicide includes one or more of TiSi2, TaSi2, MOSi2, CoSi2, Ni2Si and WSi2. The metal includes one or more of Ni, Ti, Cr, Cu, W, Mo and Ag. The material of the buffer layer can be selected according to actual needs.

[0153] The buffer layer may be a single-layer structure, or the buffer layer may include multiple sub-buffer layers stacked along the thickness direction of the semiconductor substrate 1. Multiple sub-buffer layers can reduce the stress of the entire electrode structure and reduce the warpage. The materials of the multiple sub-buffer layers may be different, and the thickness, refractive index or conductivity of the sub-buffer layers may be the same or different.

[0154] If the thickness of the buffer layer is too thick, the carrier transmission efficiency may be reduced, so the thickness of the buffer layer is 5nm to 300nm; and / or, the thickness of the buffer layer is less than or equal to 10% of the thickness of the first metal layer 2 to ensure the carrier transmission efficiency. Exemplarily, the thickness of the buffer layer is 5nm, 50nm, 100nm, 150nm, 200nm, 250nm or 300nm. Alternatively, the thickness of the buffer layer is 10%, 9%, 8%, 7% or 6% of the thickness of the first metal layer 2, etc.

[0155] It can be understood that, in the case where at least one side of the second metal layer 3 exceeds the edge of the surface of the first metal layer 2 away from the semiconductor substrate 1, the portion of the second metal layer 3 that exceeds the edge of the surface of the first metal layer 2 away from the semiconductor substrate 1 includes at least one element of the first metal layer 2; in the case where the solar cell also includes a buffer layer, the portion of the second metal layer 3 that exceeds the edge of the surface of the first metal layer 2 away from the semiconductor substrate 1 includes at least one element of the buffer layer. The surface of the first metal layer 2 away from the semiconductor substrate 1 is the upper surface of the first metal layer 2.

[0156] As another possible implementation, the solar cell further includes a transparent conductive layer between the semiconductor substrate 1 and the electrode structure. The transparent conductive layer has a high electrical conductivity and can timely conduct the collected carriers to reduce the carrier recombination rate. It can be selected as needed whether to set the transparent conductive layer on the side of the first doped semiconductor layer and the second doped semiconductor layer away from the semiconductor substrate 1.

[0157] It can be understood that the current transmission capacity of doped polycrystalline silicon is relatively high. When the first doped semiconductor layer and / or the second doped semiconductor layer is doped polycrystalline silicon, the side of the first doped semiconductor layer and / or the second doped semiconductor layer away from the semiconductor substrate 1 may not be provided with a transparent conductive layer, and the first doped semiconductor layer and / or the second doped semiconductor layer may be directly in ohmic contact with the electrode. When the first doped semiconductor layer and / or the second doped semiconductor layer is one or more of doped microcrystalline silicon and doped nanocrystalline silicon, the side of the first doped semiconductor layer and / or the second doped semiconductor layer away from the semiconductor substrate 1 may be provided with a transparent conductive layer, or may not be provided with a transparent conductive layer. When the first doped semiconductor layer and / or the second doped semiconductor layer is doped amorphous silicon, the side of the first doped semiconductor layer and / or the second doped semiconductor layer away from the semiconductor substrate 1 may be provided with a transparent conductive layer, and the electrode is in ohmic contact with the transparent conductive layer to improve the current transmission efficiency. In addition, when the first doped semiconductor layer and the second doped semiconductor layer are both provided with a transparent conductive layer on the side away from the semiconductor substrate 1, an opening may also be provided on the transparent conductive layer, and the opening passes through the transparent conductive layer along the thickness direction of the semiconductor substrate 1.

[0158] For the above-mentioned transparent conductive layer, the embodiment of the present invention does not specifically limit the material and thickness of the transparent conductive layer. Exemplarily, the material of the transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, indium hydroxide, titanium nitride, cadmium oxide, cuprous oxide, and fluorine-doped zinc oxide.

[0159] Exemplarily, the thickness of the transparent conductive layer may be greater than or equal to 10 nm and less than or equal to 100 nm.

[0160] As another possible implementation, the solar cell further includes a buffer layer and a transparent conductive layer stacked between the semiconductor substrate 1 and the electrode structure, and the transparent conductive layer is closer to the semiconductor substrate 1 than the buffer layer. While the buffer layer is used to improve the adhesion between the electrode structure and the semiconductor substrate 1, the transparent conductive layer is used to timely guide the collected carriers to reduce the carrier recombination rate.

[0161] In the above technical solution, the width of the transparent conductive layer is greater than or equal to the width of the electrode structure. In this way, the transparent conductive layer can be completely in contact with the bottom surface of the electrode structure, further improving the carrier extraction rate. In this solution, when the solar cell also includes a buffer layer, the width of the transparent conductive layer can be greater than or equal to the width of the buffer layer.

[0162] In the case where the width of the transparent conductive layer is greater than the width of the electrode structure, the difference between the width of the transparent conductive layer and the width of the electrode structure is greater than 0 and less than 30 μm. This ensures that the transparent conductive layer can be in full contact with the bottom surface of the electrode structure while preventing the transparent conductive layer from being too large to block light or, when the electrode structure is applied to a back contact battery, the transparent conductive layer extends to another doped semiconductor layer of the opposite conductivity type, causing leakage. Furthermore, the difference between the width of the transparent conductive layer and the width of the lower surface of the first metal layer 2 is greater than 0 and less than 10 μm.

[0163] In the present application, in view of the fact that the widths of the first metal layer 2, the second metal layer 3, the buffer layer, and the transparent conductive layer at different positions along the extension direction of the electrode structure may be different. Therefore, in this application, the width W1 of the upper surface of the first metal layer 2 may refer to the average width of the upper surface of the first metal layer 2, or the maximum width of the upper surface of the first metal layer 2. The width of the lower surface of the first metal layer 2 may refer to the average width of the lower surface of the first metal layer 2, or the maximum width of the lower surface of the first metal layer 2. The width W2 of the second metal layer 3 may refer to the average width of the second metal layer 3, or the maximum width of the second metal layer 3. The width of the buffer layer may refer to the average width of the buffer layer, or the maximum width of the buffer layer. The width of the transparent conductive layer may refer to the average width of the buffer layer, or the maximum width of the transparent conductive layer.

[0164] In addition, the portion of the first surface of the semiconductor substrate 1 opposite to the electrode structure is a polished surface to simplify the processing of the solar cell. Of course, the portion of the first surface of the semiconductor substrate 1 opposite to the electrode structure may also be a velvet surface to increase the contact area between the electrode structure and the first surface of the semiconductor substrate 1 and to increase the adhesion between the electrode structure and the first surface of the semiconductor substrate 1.

[0165] In this application, the solar cell can be a back-contact cell, which also includes a first semiconductor region, a second semiconductor region and an isolation region between the first semiconductor region and the second semiconductor region, which are arranged on the first surface of the semiconductor substrate 1; the electrode structure includes a first electrode and a second electrode, wherein the first electrode is arranged in the first semiconductor region and the second electrode is arranged in the second semiconductor region.

[0166] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0167] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; An electrode structure formed on the first surface of the semiconductor substrate, the electrode structure comprising a first metal layer and a second metal layer stacked in sequence along a thickness direction of the semiconductor substrate, the first metal layer being closer to the semiconductor substrate than the second metal layer; The side surface of the first metal layer includes a plurality of curved surfaces connected in sequence along the extension direction of the electrode structure, and at least one of the curved surfaces includes a first sub-side surface and a second sub-side surface connected along the thickness direction of the semiconductor substrate; the width of the first metal layer at the position where the first sub-side surface and the second sub-side surface are connected is greater than the width at other positions.

2. The solar cell according to claim 1, characterized in that The portion of the side surface of the first metal layer along the extension direction of the electrode structure facing the first surface of the semiconductor substrate is a polished surface; Alternatively, a portion of the side surface of the first metal layer along the extending direction of the electrode structure facing the first surface of the semiconductor substrate is a velvet surface.

3. The solar cell according to claim 1, characterized in that The angle between the first sub-side surface and the second sub-side surface is an obtuse angle.

4. The solar cell according to claim 1, characterized in that An angle between the first sub-side surface and the first surface of the semiconductor substrate is greater than 45°; and / or an angle between the second sub-side surface and the first surface of the semiconductor substrate is greater than 45°.

5. The solar cell according to claim 1, characterized in that: The boundary between the surface of the first metal layer close to the semiconductor substrate and the surface of the first metal layer far from the semiconductor substrate projected on the semiconductor substrate extends along a wavy line or a straight line; And / or, along the extension direction of the electrode structure, an arc length of at least one of the curved surfaces away from the semiconductor substrate is smaller than an arc length of the curved surface close to the semiconductor substrate.

6. The solar cell according to claim 1, characterized in that Along the width direction of the electrode structure, the width of the second metal layer is greater than or equal to the width of the first metal layer away from the surface of the semiconductor substrate.

7. The solar cell according to claim 6, characterized in that: Along the width direction of the electrode structure, the width of the second metal layer is greater than the width of the first metal layer away from the surface of the semiconductor substrate; The second metal layer does not cover the side of the first metal layer; Alternatively, the second metal layer covers at least a portion of a side surface of the first metal layer.

8. The solar cell according to claim 7, characterized in that: The second metal layer covers at least a portion of a side surface of the first metal layer; At least a portion of the second metal layer continuously extends from a surface of the first metal layer away from the semiconductor substrate to a side surface of the first metal layer; Alternatively, at least a portion of the second metal layer covering a surface of the first metal layer away from the semiconductor substrate is disconnected from a portion covering a side surface of the first metal layer.

9. The solar cell according to claim 8, characterized in that The second metal layer covers at least a portion of a side surface of the first metal layer; The second metal layer covers a surface of the first metal layer away from the semiconductor substrate and extends to cover the first surface of the semiconductor substrate.

10. The solar cell according to claim 9, characterized in that: There is a gap between the second metal layer and the side surfaces of the first metal layer.

11. The solar cell according to claim 6, characterized in that: Along the width direction of the electrode structure, the width of the second metal layer is greater than the width of the first metal layer away from the surface of the semiconductor substrate; A portion of the second metal layer beyond an edge of the first metal layer away from a surface of the semiconductor substrate includes at least one element of the first metal layer.

12. The solar cell according to claim 1, characterized in that The width W1 of the first metal layer away from the surface of the semiconductor substrate is 80% to 110% of the width W2 of the second metal layer; and / or, the width of the second metal layer beyond the edge of the first metal layer away from the surface of the semiconductor substrate is 1 μm to 30 μm; and / or, the thickness of the first metal layer is 0.5 μm to 20 μm; and / or, the thickness of the second metal layer is 5 nm to 300 nm; And / or, the thickness of the second metal layer is less than or equal to 10% of the thickness of the first metal layer.

13. The solar cell according to claim 1, characterized in that The first metal layer includes a plurality of first sub-metal layers stacked along the thickness direction of the semiconductor substrate; The side surface of each layer of the first sub-metal layer is an inclined surface that is gradually inclined along the thickness direction of the semiconductor substrate, and the side surfaces of multiple layers of the first sub-metal layers are sequentially connected to form the first sub-side surface and the second sub-side surface; or The side surface of at least one layer of the first sub-metal layer includes the first sub-side surface and the second sub-side surface connected to each other along the thickness direction of the semiconductor substrate.

14. The solar cell according to claim 1, characterized in that The edge region of the second metal layer has a porous structure; and / or, The side surface of the first metal layer has a pit; and / or, The side surface of the first metal layer has a textured pattern.

15. The solar cell according to claim 1, characterized in that The difference between the standard electrode potential of the first metal layer and the standard electrode potential of the second metal layer is 0.1V to 3.5V, and the standard electrode potential of the first metal layer is lower than the standard electrode potential of the second metal layer.

16. The solar cell according to claim 1, characterized in that The first metal layer includes one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and their alloys; and / or the second metal layer includes one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn and their alloys.

17. The solar cell according to claim 1, characterized in that The solar cell further comprises a buffer layer between the electrode structure and the semiconductor substrate; Alternatively, the solar cell further comprises a transparent conductive layer located between the semiconductor substrate and the electrode structure; Alternatively, the solar cell further comprises a buffer layer and a transparent conductive layer stacked between the semiconductor substrate and the electrode structure, and the transparent conductive layer is closer to the semiconductor substrate than the buffer layer.

18. The solar cell according to claim 17, characterized in that: The width of the transparent conductive layer is greater than or equal to the width of the electrode structure.

19. The solar cell according to claim 18, characterized in that The width of the transparent conductive layer is greater than the width of the electrode structure; The difference between the width of the transparent conductive layer and the width of the electrode structure is greater than 0 and less than 30 μm.

20. The solar cell according to claim 17, characterized in that: The thickness of the buffer layer is 5 nm to 300 nm; the thickness of the buffer layer is less than or equal to 10% of the thickness of the first metal layer.

21. The solar cell according to claim 1, characterized in that The solar cell further comprises a doped semiconductor layer and a passivation layer stacked between the semiconductor substrate and the electrode structure; an opening is provided on the passivation layer, the electrode structure passes through the opening and contacts the doped semiconductor layer, and the electrode structure is recessed at the opening; The roughness of the electrode structure at the opening is greater than the roughness of the electrode structure at other positions; And / or, at the opening, the first metal layer includes a hole.

22. The solar cell according to any one of claims 1 to 21, characterized in that The solar cell is a back-contact cell, which also includes a first semiconductor region, a second semiconductor region and an isolation region between the first semiconductor region and the second semiconductor region, which are arranged on the first surface of the semiconductor substrate; the electrode structure includes a first electrode arranged in the first semiconductor region and a second electrode arranged in the second semiconductor region.

23. A photovoltaic module, characterized in that: include: A solar cell as claimed in any one of claims 1 to 22.

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