Array substrate, display panel, driving method of display panel, and display device

Abstract

An array substrate, a display panel, a driving method for the display panel, and a display device are disclosed. The array substrate includes a substrate, a plurality of sub-pixels, a plurality of gate lines, and a plurality of data lines disposed on the substrate. The plurality of sub-pixels are arranged in an array on the substrate, forming a plurality of pixel groups. Each pixel group includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first electrode group connected together, and the second sub-pixel includes a second transistor and a second electrode group connected together. The first transistor and the second transistor are both located between the first electrode group and the second electrode group, and are respectively located at both ends of the pixel group along the column direction. The first electrode group includes a first pixel electrode and a first common electrode, and the second electrode group includes a second pixel electrode and a second common electrode. The overlap area of ​​the first pixel electrode and the first common electrode is equal to the overlap area of ​​the second pixel electrode and the second common electrode.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a driving method for the display panel, and a display device. Background Technology

[0002] In the field of display technology, display panels and display devices typically use thin-film transistors (TFTs) for driving. With the development of display technology, to reduce costs, dual-gate driving is commonly used to drive pixel arrays. Dual-gate driving halves the number of data lines compared to traditional driving methods, thereby reducing the number of source driver circuits, and consequently reducing the number of driver chips and lowering costs. Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of sub-pixels, a plurality of gate lines, and a plurality of data lines disposed on the substrate. The plurality of sub-pixels are arranged in an array on the substrate in an E-row, F-column configuration. The plurality of sub-pixels form a plurality of pixel groups, each pixel group including a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first electrode group connected together, and the second sub-pixel includes a second transistor and a second electrode group connected together. The first electrode group and the second electrode group are arranged sequentially along the row direction. The first transistor and the second transistor are both located between the first electrode group and the second electrode group, and are respectively located at both ends of the pixel group along the column direction. The first electrode group includes a first pixel electrode and a first common electrode, and the second electrode group includes a second pixel electrode and a second common electrode. The plurality of gate lines form a plurality of gate line groups, each of the plurality of gate line groups including a first gate line and a second gate line. The first sub-pixel and the second sub-pixel of each pixel group are respectively connected to the first gate line and the second gate line of a gate line group. Multiple data lines are disposed on the substrate, and the first sub-pixel and the second sub-pixel of each pixel group are connected to one of the data lines; at least a portion of the multiple data lines include a third data segment extending along the row direction, a first data segment and a second data segment extending along the column direction, the third data segment connecting the first data segment and the second data segment, the first data segment being disposed between the i-th column sub-pixel and the (i+1)-th column sub-pixel, the second data segment being disposed between the (ij)-th column sub-pixel and the (ij-1)-th column sub-pixel, j being greater than or equal to 1; i+1 ≤ F; wherein, the overlap area of ​​the first pixel electrode and the first common electrode is equal to the overlap area of ​​the second pixel electrode and the second common electrode.

[0004] In some embodiments, j=1; the two outermost data lines in the row direction are a first data line and a second data line. The first data line has a first data segment located between the first column sub-pixels and the second column sub-pixels, and a second data segment located on the side of the first column sub-pixels away from the multiple columns of sub-pixels. The second data line has a first data segment located on the side of the Fth column sub-pixels away from the multiple columns of sub-pixels, and a second data segment located between the (F-1)th column sub-pixels and the Fth column sub-pixels.

[0005] In some embodiments, at least a portion of the data line connected to the pixel group is located between the first electrode group and the second electrode group of the pixel group; at least a portion of the data line is the first data segment or the second data segment; the first electrode of the first transistor and the first electrode of the second transistor are both connected to the data line, the second electrode of the first transistor is connected to the first pixel electrode, and the second electrode of the second transistor is connected to the second pixel electrode; the direction in which the first electrode of the first transistor points to the second electrode and is parallel to the row direction is a first direction, and the direction in which the first electrode of the second transistor points to the second electrode and is parallel to the row direction is a second direction, wherein the first direction is opposite to the second direction.

[0006] In some embodiments, both the first transistor and the second transistor include a gate, an active layer, and source / drain electrodes stacked sequentially. The source / drain electrodes include a first electrode and a second electrode. The orthographic projection of the active layer on the substrate falls within the orthographic projection of the gate on the substrate. At least a portion of the orthographic projections of the first electrode and the second electrode on the substrate fall within the orthographic projection of the active layer on the substrate. The orthographic projection of the first electrode is U-shaped, and the opening of the first electrode faces the second electrode.

[0007] In some embodiments, the first pixel electrode and the second pixel electrode are block electrodes, the first common electrode and the second common electrode are strip electrodes, and both the first common electrode and the second common electrode include a plurality of slits; the aperture ratio of the first sub-pixel is equal to the aperture ratio of the second sub-pixel; the first electrode group includes a first domain region and a second domain region disposed along the column direction, and the second electrode group includes a third domain region and a fourth domain region disposed along the column direction, and the aperture ratios of the first domain region, the second domain region, the third domain region and the fourth domain region are equal.

[0008] In some embodiments, the array substrate further includes: a first spacer disposed on the side of the first transistor away from the substrate, and a second spacer disposed on the side of the second transistor away from the substrate; the center of the orthographic projection of the first spacer on the substrate is offset by a first distance in a third direction relative to the center of the orthographic projection of the first transistor on the substrate, the third direction being the direction in which the first transistor points to the second transistor; the center of the orthographic projection of the second spacer on the substrate is offset by a second distance in a fourth direction relative to the center of the orthographic projection of the second transistor on the substrate, the fourth direction being the direction in which the second transistor points to the first transistor.

[0009] In some embodiments, the first distance is equal to the second distance.

[0010] In some embodiments, the orthographic projection of the first spacer on the substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the substrate; the orthographic projection of the second spacer on the substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the substrate.

[0011] On the other hand, a display panel is provided, including a display area and a peripheral area. The display panel includes: an array substrate as described in any of the above embodiments; the plurality of pixel groups located in the display area; at least one gate driving circuit disposed on the substrate, the gate driving circuit being located in the peripheral area; the gate driving circuit including N cascaded shift registers; wherein the output terminal of the i-th stage shift register is connected to the input terminal of the (i+n)-th stage shift register; the output terminal of the (i+n+2j)-th stage shift register is connected to the reset terminal of the i-th stage shift register; j is greater than or equal to 1; the plurality of gate lines are arranged sequentially along the column direction, and the plurality of first gate lines and the plurality of second gate lines are alternately arranged; in the N cascaded shift registers, each shift register is electrically connected to one gate line.

[0012] In some embodiments, the plurality of shift registers are arranged along a column direction; the display panel further includes: a first voltage signal line disposed on one side of the gate driving circuit along a row direction; each shift register includes a plurality of transistors, at least one of the plurality of transistors being electrically connected to the first voltage signal line; the plurality of transistors includes a reset transistor and a plurality of noise reduction transistors, the shift register further includes an input transistor, the input transistor and the reset transistor being located away from the first voltage signal line relative to the noise reduction transistor; the display panel further includes an auxiliary first voltage signal line located on the other side of the gate driving circuit, the first voltage signal line and the auxiliary first voltage signal line being connected; the input transistor and the reset transistor being located close to the auxiliary first voltage signal line relative to the noise reduction transistor; at least a portion of the reset transistors of the shift registers are connected to the auxiliary first voltage signal line via a first lead.

[0013] In some embodiments, the display panel further includes: a connection voltage signal line disposed on the side of the last stage shift register of the gate driving circuit away from other shift registers, wherein the first voltage signal line and the auxiliary first voltage signal line are connected through the connection voltage signal line, and the connection voltage signal line extends along the row direction; the connection voltage signal line includes multiple electrically connected sub-signal lines.

[0014] In some embodiments, the noise reduction transistor of the shift register is connected to the first voltage signal line via a second lead.

[0015] In some embodiments, the plurality of noise-reducing transistors include multiple groups of transistors, each group of transistors including two transistors; the second lead is located between the two transistors in each group of transistors; the two transistors in at least one group of transistors are staggered in the column direction.

[0016] In some embodiments, the size of the region where each shift register is located in the column direction is 60μm to 100μm.

[0017] In some embodiments, the display panel further includes: M clock signal lines disposed on the side of the gate driving circuit away from the display area, the clock signal lines being electrically connected to the gate driving circuit, wherein the i-th clock signal line is connected to the (Mm+i)-th stage shift register, where 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N; the starting position of the effective clock signal transmitted by the i-th clock signal line is earlier than the starting position of the effective clock signal transmitted by the (i+1)-th clock signal line, i+1≤M.

[0018] In some embodiments, starting from the first clock signal line, each pair of adjacent clock signal lines forms a group, and the starting position of the effective clock signal output by the second clock signal line in each group of clock signal lines is earlier than the starting position of the effective clock signal output by the first clock signal line; the starting position of the effective clock signal transmitted by the i-th clock signal line is earlier than the starting position of the effective clock signal transmitted by the (i+2)-th clock signal line; i+2≤M.

[0019] In another aspect, a driving method for a display panel is provided. The driving method is applied to a display panel as described in any of the above embodiments, wherein the plurality of pixel groups include a plurality of row pixel groups arranged along a column direction, each row pixel group including at least two pixel groups arranged along a row direction; each row pixel group is disposed between a first gate line and a second gate line of a gate line group, and is electrically connected to the gate line group; the driving method includes: when the display panel displays a first set image, the gate driving circuit outputs a first set of gate driving signals, the plurality of row pixel groups are activated row by row under the scanning of the plurality of gate line groups, and in each row pixel group, a first sub-pixel electrically connected to the first gate line is activated before a second sub-pixel electrically connected to the second gate line.

[0020] In some embodiments, when the display panel displays a second setting screen, the gate driving circuit outputs a second gate driving signal, and the plurality of row pixel groups are activated row by row under the scanning of the plurality of gate line groups, and in each row pixel, the second sub-pixel electrically connected to the second gate line is activated before the first sub-pixel electrically connected to the first gate line.

[0021] In another aspect, a display device is provided. The display device includes a display panel as described in any of the above embodiments.

[0022] In some embodiments, the display device further includes M clock signal lines, the i-th clock signal line being connected to the (Mm+i)-th shift register, where 1≤i≤M and i is a positive integer, 0≤m and m is a positive integer; (Mm+i)≤N; the display device further includes a control chip, the control chip being connected to the M clock signal lines and outputting clock signals to the M clock signal lines; the control chip is configured to, when detecting that the display panel displays a first set screen, output valid clock signals sequentially to the M clock signal lines in a first order, wherein the first order is 1, 2, 3, 4...M-1, M; when detecting that the display panel displays a second set screen, output valid clock signals sequentially to the M clock signal lines in a second order, wherein the second order is 2, 1, 4, 3...M, M-1. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 This is a structural diagram of an array substrate according to some embodiments;

[0025] Figure 2A This is another structural diagram of an array substrate according to some embodiments;

[0026] Figure 2B This is a structural diagram of the gate lines of an array substrate according to some embodiments;

[0027] Figure 2C This is a structural diagram of the active layer of an array substrate according to some embodiments;

[0028] Figure 2D This is a structural diagram of the pixel electrode of an array substrate according to some embodiments;

[0029] Figure 2E This is a structural diagram of the data lines of an array substrate according to some embodiments;

[0030] Figure 2F This is a structural diagram of the common electrode of the array substrate according to some embodiments;

[0031] Figure 3A This is a structural diagram showing the overlapping of pixel electrodes and common electrodes on an array substrate according to some embodiments;

[0032] Figure 3B According to Figure 3A A magnified view of a portion at point A;

[0033] Figure 4 This is a structural diagram of a pixel group on an array substrate according to some embodiments;

[0034] Figure 5 for Figure 4 Cross-sectional structure diagram obtained by drawing a section along the section line CC;

[0035] Figure 6 This is yet another structural diagram of a pixel group on an array substrate according to some embodiments;

[0036] Figure 7 This is a pixel aperture structure diagram of a pixel group of an array substrate according to some embodiments;

[0037] Figure 8 This is a domain region structure diagram of a pixel group on an array substrate according to some embodiments;

[0038] Figure 9A This is yet another structural diagram of a pixel group on an array substrate according to some embodiments;

[0039] Figure 9B According to Figure 9A A magnified view of the structure at point B;

[0040] Figure 9C According to Figure 9B The cross-sectional structure diagram obtained by taking a section along the cross-section line EE of the first diaphragm in the middle;

[0041] Figure 10 This is a structural diagram of a display panel according to some embodiments;

[0042] Figure 11A This is another structural diagram of a display panel according to some embodiments;

[0043] Figure 11B According to Figure 11A The resulting enlarged image;

[0044] Figure 11C for Figure 11A Timing diagrams based on some embodiments;

[0045] Figure 11D for Figure 11A Timing diagrams based on some embodiments;

[0046] Figure 11E Here is a circuit diagram of a shift register according to some embodiments;

[0047] Figure 11F This is a timing diagram and reset relationship diagram corresponding to the gate drive circuit according to some embodiments;

[0048] Figure 12A This is yet another structural diagram of an array substrate according to some embodiments;

[0049] Figure 12B This is yet another structural diagram of an array substrate according to some embodiments;

[0050] Figure 13 This is a connection structure diagram of a gate drive circuit according to some embodiments;

[0051] Figure 14A This is a connection diagram of a shift register according to some embodiments;

[0052] Figure 14B According to Figure 14AThe resulting magnified structural diagram;

[0053] Figure 14C According to Figure 14A The resulting magnified structural diagram;

[0054] Figure 15A According to Figure 14A A magnified view of the local structure obtained at point D;

[0055] Figure 15B According to Figure 14A A magnified view of the structure obtained at point E;

[0056] Figure 16 This is a structural diagram of a display device according to some embodiments;

[0057] Figure 17 This is a connection structure diagram of the control chip of a display device according to some embodiments. Detailed Implementation

[0058] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0059] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0060] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0061] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0062] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0063] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0064] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0065] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0066] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0067] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0068] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0069] Currently, low-cost display products typically employ a dual-gate line drive (DLR) method to drive the pixel array. This DLR method reduces the number of data lines, thereby reducing the number of driver chips and lowering costs. However, in existing display panels using the DLR method, variations in the thin-film transistor layout can lead to misalignment between different film layers during the manufacturing process, resulting in differences in parasitic capacitance. This, in turn, results in poor display performance, manifesting as vertical lines, flickering, and image retention.

[0070] Based on this, some embodiments of this disclosure provide an array substrate, a display panel, a driving method for the display panel, and a display device to solve the problem of poor image display (e.g., flickering, afterimages, vertical lines, etc.) while ensuring uniform light effect, thereby improving product yield and quality.

[0071] The array substrate, display panel, driving method of display panel and display device provided in this disclosure will be described below.

[0072] Some embodiments of the present invention provide an array substrate 10, such as Figure 1 and Figure 2A As shown, the array substrate 10 includes a substrate 1 and a plurality of sub-pixels 2', a plurality of gate lines 3', and a plurality of data lines 4 disposed on the substrate 1. The plurality of sub-pixels 2' are arranged in an array on the substrate 1, and the plurality of sub-pixels are arranged in E rows and F columns; the plurality of sub-pixels form a plurality of pixel groups 2.

[0073] Reference Figure 2A and Figure 4 As shown, multiple sub-pixels 2' are divided into multiple pixel groups. Each pixel group 2 includes two adjacent sub-pixels 2', which are arranged along the row direction X. Each sub-pixel 2' includes a transistor and an electrode group, which consists of overlapping pixel electrodes and a common electrode. Each pixel group 2 includes a first sub-pixel 21 and a second sub-pixel 22. The first sub-pixel 21 includes a first transistor 211 and a first electrode group 212 connected together. The second sub-pixel 22 includes a second transistor 221 and a second electrode group 222 connected together. The first electrode group 212 and the second electrode group 222 are arranged sequentially along the row direction X. The first transistor 211 and the second transistor 221 are both located between the first electrode group 212 and the second electrode group 222, and are located at opposite ends of the pixel group 2 along the column direction Y. The first electrode group 212 includes a first pixel electrode 2121 and a first common electrode 2122, and the second electrode group 222 includes a second pixel electrode 2221 and a second common electrode 2222.

[0074] The multiple gate lines 3' form multiple gate line groups 3. Each gate line group 3 includes a first gate line 31 and a second gate line 32. The first sub-pixel 21 and the second sub-pixel 22 of each pixel group 2 are respectively connected to the first gate line 31 and the second gate line 32 of a gate line group 3. That is, the gate of the first transistor 211 included in the first sub-pixel 21 is electrically connected to the first gate line 31, and the gate of the second transistor 221 included in the second sub-pixel 22 is electrically connected to the second gate line 32.

[0075] For example, multiple gate lines 3' extend along the row direction X and are arranged along the column direction Y. Each pair of adjacent gate lines 3' forms a gate line group 3. The gate line group 3 is electrically connected to a row of sub-pixels 2'. The two gate lines of each gate line group 3 are located on both sides of a row of sub-pixels 2'. The first gate line 31 is electrically connected to the first sub-pixel 21 of each pixel group 2 in the row of sub-pixels 2', and the second gate line 32 is electrically connected to the second sub-pixel of each pixel group 2 in the row of sub-pixels 2'.

[0076] It should be noted that in each pixel group 2, the relative positions of the first sub-pixel 21 and the second sub-pixel 22 are not fixed. In a row of sub-pixels 2' and the corresponding gate group 3, the sub-pixels electrically connected to the first gate line 31 are all the first sub-pixel 21, and the sub-pixels electrically connected to the second gate line 32 are all the second sub-pixels 22. For example, as... Figure 2A As shown, in the pixel group 2 in the upper left corner, the first sub-pixel 21 is located to the left of the second sub-pixel 22. The first sub-pixel 21 is the odd-numbered sub-pixel in this row. In the pixel group 2 in the upper right corner, the first sub-pixel 21 is located to the right of the second sub-pixel 22. The first sub-pixel 21 is the even-numbered sub-pixel in this row.

[0077] like Figure 1 As shown, the first sub-pixel 21 and the second sub-pixel 22 of each pixel group 2 are connected to a data line 4, meaning that two sub-pixels in a pixel group 2 are controlled by the same data line. Multiple data lines 4 are arranged along the row direction X. At least a portion of the multiple data lines 4 include a third data segment 43 extending along the row direction X, a first data segment 41 extending along the column direction Y, and a second data segment 42. The third data segment 43 connects the first data segment 41 and the second data segment 42. The first data segment 41 is located between the i-th column sub-pixel and the (i+1)-th column sub-pixel, and the second data segment 42 is located between the (ij)-th column sub-pixel and the (ij-1)-th column sub-pixel, where j is greater than or equal to 1; i+1 ≤ F.

[0078] It should be noted that "at least some of the data lines" here refers to all data lines except for the two data lines located on the outermost side of the X direction along the row.

[0079] For example, refer to Figure 1 As shown in the figure, the arrangement of at least some of the data lines 4 is illustrated when j equals 1. These at least some data lines include a third data segment 43 extending along the row direction X, a first data segment 41 extending along the column direction Y, and a second data segment 42 extending from... Figure 1 As can be seen from the data, the first data segment 41 is located between the i-th column sub-pixel and the (i+1)-th column sub-pixel, and the first data segment 41 is electrically connected to the sub-pixels on both sides of it. The second data segment 42 is located between the (i-1)-th column sub-pixel and the (i-2)-th column sub-pixel, and the second data segment 42 is electrically connected to the sub-pixels on both sides of it. In other words, there are two columns of sub-pixels between the first data segment 41 and the second data segment 42 on the same data line 4. Figure 1 The arrangement of data line 4 shown is only an example, that is, the arrangement of data lines when j equals 1; when j is greater than 1, the first data segment 41 and the second data segment 42 of the same data line 4 are separated by three columns of sub-pixels, four columns of sub-pixels, etc.

[0080] It is understandable that in the above configuration, the same data line 4 can be electrically connected to two adjacent pixel groups 2, wherein each first data segment 41 of the data line is electrically connected to each odd-numbered pixel group 2 (or even-numbered pixel group 2) of one of the pixel groups, and each second data segment 42 of the data line 4 is electrically connected to each even-numbered pixel group 2 (or odd-numbered pixel group 2) of the other pixel group.

[0081] In some embodiments, continue to refer to Figure 1 Where j=1; the two outermost data lines 4 located in the row direction X are the first data line 401 and the second data line 402. The first data segment 41 of the first data line 401 is located between the first column sub-pixels and the second column sub-pixels, and the second data segment 42 of the first data line 401 is located on the side of the first column sub-pixels away from the multi-column sub-pixels; the first data segment 41 of the second data line 402 is located on the side of the F-th column sub-pixels away from the multi-column sub-pixels, and the second data segment 42 of the second data line 402 is located between the (F-1)-th column sub-pixels and the F-th column sub-pixels.

[0082] For example, such as Figure 1 As shown, Figure 1 The sub-pixel columns arranged from left to right are the first column of sub-pixels, the second column of sub-pixels, ..., the Fth column of sub-pixels. The first data line 401 and the second data line 402 are located at the leftmost and rightmost sides of the multiple data lines 4, respectively. The second data segment 42 of the first data line 401 is located on the side of the first column of sub-pixels that is far away from the multiple columns of sub-pixels, that is, the second data segment 42 is located to the left of the first column of sub-pixels. The first data segment 41 of the second data line 402 is located on the side of the Fth column of sub-pixels that is far away from the multiple columns of sub-pixels, that is, the first data segment 41 is located to the right of the Fth column of sub-pixels.

[0083] For example, the substrate 1 has a supporting and protective function and can be a rigid substrate, such as a glass substrate or a silicon substrate; or it can be a flexible substrate, such as a polyimide substrate, etc., which is not limited here.

[0084] In some embodiments, refer to Figure 2AAs shown, multiple pixel groups 2 are arranged in multiple rows and columns, with each row of pixel groups 2 positioned between the first gate line 31 and the second gate line 32 of a gate line group 3; multiple data lines 4 are arranged along the row direction, each data line 4 including multiple alternating first data segments 41 and multiple second data segments 42. Except for the two data lines 4 located on the outermost side in the row direction, the multiple first data segments 41 of the data lines 4 are respectively located between the first electrode group 212 and the second electrode group 222 of the odd-numbered row pixel groups in the first column pixel group, and the multiple second data segments 42 of the data lines 4 are respectively located between the first electrode group 212 and the second electrode group 222 of the even-numbered row pixel groups in the second column pixel group. The first column pixel group and the second column pixel group are adjacent; the data lines 4 also include multiple third data segments 43, which connect adjacent first data segments 41 and second data segments 42.

[0085] For example, refer to Figure 2A The diagram shows multiple pixel groups 2 arranged in four rows and six columns. Each row of pixel groups 2 is positioned between the first gate line 31 and the second gate line 32 of a gate line group 3. That is, within the same row of pixel groups 2, the first sub-pixel 21 and the second sub-pixel 22 of each pixel group 2 are electrically connected to the same gate line group 3. Multiple data lines 4 are arranged along the row direction X. The multiple data lines 4 include multiple first data segments 41 and multiple second data segments 42 extending along the column direction Y. The first data segments 41 are located between the first electrode group 212 and the second electrode group 222 of the odd-numbered rows of pixel groups in the first column of pixel group 2a. The second data segments 42 are located between the first electrode group 212 and the second electrode group 222 of the even-numbered rows of pixel groups in the second column of pixel group 2b. It should be noted that the first column of pixel groups and the second column of pixel groups are adjacent, but their specific positional relationship is not limited. Figure 2A The multiple pixel groups 2 shown are merely an example, wherein the first column of pixel groups is located to the right of the second column of pixel groups and the two are adjacent. The third data segment 43 of the multiple data lines 4 extends along the row direction X and connects the first data segment 41 and the second data segment 42. As can be seen from the above, each data line 4 is distributed in an arc shape.

[0086] like Figure 1 The aforementioned dual-gate + bow-shaped pixel architecture employs a dual-gate + bow-shaped pixel structure. In this structure, each sub-pixel in each row is electrically connected to two gate lines in alternating odd and even configurations. Multiple data lines are arranged in a bow shape. The first data segment 41 of each data line 4 is located between two adjacent columns of sub-pixels, and the second data segment is located between another two adjacent columns of sub-pixels. This arrangement reduces the number of data lines 4 and the number of source drive channels for transmitting data signals. Furthermore, due to the bow-shaped data line design, two sub-pixels in each pixel group are electrically connected to the same data line, while adjacent pixel groups are connected to different data lines. Figure 1The "+" and "-" in the text represent opposite polarities. When the polarities of multiple data lines alternate between odd and even along the row direction, the polarities of multiple sub-pixels can be flipped by 2 dot (pixel points) in units of pixel groups. That is, the polarities of two sub-pixels in each pixel group are the same, and the polarities of adjacent pixel groups are opposite. This can, to a certain extent, shield most of the vertical lines and improve undesirable display phenomena such as vertical lines.

[0087] like Figures 2B-2F As shown, Figures 2B-2F This diagram illustrates the layers of multiple pixel groups. The array substrate includes a substrate, on which a gate layer 101, a semiconductor layer 103, a pixel electrode layer 104, a source / drain metal layer 105, and a common electrode layer 107 (collectively referred to as functional layers) are sequentially disposed. Exemplarily, the semiconductor layer 103 and the pixel electrode layer 104 are located on the same layer. Optionally, the same layer can be sequentially disposed on the substrate. The array substrate also includes an insulating layer disposed between adjacent functional layers. Figure 2B The diagram shows the layout structure of multiple gate lines. The multiple gate lines 3' are arranged in multiple gate line groups 3. Each gate line group 3 includes a first gate line 31 and a second gate line 32, and multiple transistor gates are uniformly connected on each gate line 3'. Figure 2C This is a structural diagram of semiconductor layer 103, which includes active layers 12 of multiple transistors. The material of the semiconductor layer can be, for example, amorphous silicon, low-temperature polycrystalline silicon, metal oxide semiconductor, etc., and is not limited here. Figure 2D The diagram shows the structure of the pixel electrode layer 104, which includes multiple pixel electrodes arranged in an array. The first pixel electrode 2121 and the second pixel electrode 2221 in each pixel group 2 extend in the same direction. Along the row direction X, a spare data line (as indicated by the arrow) is provided between two adjacent pixel electrodes. The spare data line is electrically connected to the data line and is configured to assist in transmitting data signals, or to serve as a spare data line to transmit data signals when the data line fails. Optionally, the lengths of the spare data lines can be set differently, for example, adjacent spare data lines have different lengths along the X direction. Figure 2EThe diagram shows the structure of the source / drain metal layer, which includes multiple data lines. As can be seen from the diagram, each data line 4 is arranged in a bow shape. Each data line 4 includes a first data segment 41 and a second data segment 42 extending along the column direction Y, and a third data segment 43 extending along the row direction X. The third data segment 43 electrically connects the first data segment 41 and the second data segment 42. In addition, the source / drain metal layer also includes the first and second electrodes of multiple transistors, wherein the first electrodes of the transistors are connected to the data lines. Figure 2F This is a structural diagram of the common electrode layer. The common electrodes are arranged in a mesh structure, and the common electrodes of each sub-pixel are electrically connected to form a whole. It can be understood that the common electrode in a sub-pixel is the part of the common electrode layer that overlaps with the pixel electrode of that sub-pixel.

[0088] In some embodiments, refer to Figure 3A The overlapping area of ​​the first pixel electrode 2121 and the first common electrode 2122 is equal to the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222.

[0089] For example, such as Figure 4 As shown, in a pixel group 2, the first transistor 211 and the second transistor 221 are located between two first electrode groups and two second electrode groups. The shape, arrangement, and placement of the first transistor 211 and the second transistor 221 are not completely consistent. Therefore, the shapes of the first pixel electrode 2121 and the second pixel electrode 2221 near the boundaries of the two transistors are different, resulting in a difference in the area of ​​the first pixel electrode 2121 and the second pixel electrode 2221. Consequently, the overlapping area of ​​the first pixel electrode 2121 and the first common electrode 2122, and the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222 are different. That is, the capacitance generated by the first sub-pixel 21 and the second sub-pixel 22 is different, which will cause a deviation in the sub-pixel display and affect the display effect.

[0090] Reference Figure 3A By setting the overlap area of ​​the first pixel electrode 2121 and the first common electrode 2122 to be equal to the overlap area of ​​the second pixel electrode 2221 and the second common electrode 2222, it can be ensured that the capacitance generated between the first pixel electrode 2121 and the first common electrode 2122 is consistent with the capacitance generated between the second pixel electrode 2221 and the second common electrode 2222. In this way, the electric field intensity generated by the first electrode group and the second electrode group is consistent, the deflection of the liquid crystal layer is consistent, and the transmitted light is consistent, thereby avoiding poor image display phenomena such as flickering and vertical lines.

[0091] Since the common electrode layer is a single-layer structure laid across the display area, with the common electrodes of multiple sub-pixels connected together, the main way to adjust the overlap area between the pixel electrodes and the common electrodes is to adjust the shape of the pixel electrodes, such as... Figure 3A As shown, the dashed box represents the outline of the pixel electrode. Pixel group 2 includes a first electrode group 212 and a second electrode group 222. The second electrode group 222' on the right is a structural diagram before adjustment. For example, before adjustment, the area of ​​the second pixel electrode 2221' is larger than the area of ​​the first pixel electrode 2121, causing the capacitance formed by the first electrode group 212 to differ from the capacitance formed by the second electrode group 222' by 1.6%, and the ΔVp difference to be 1.2%, which can easily lead to flickering. (Refer to...) Figure 3B , Figure 3B for Figure 3A In the enlarged view at point A, the area of ​​the dashed box region S is s. Figure 3A The region S of the second pixel electrode 2221' is partially removed, thus obtaining... Figure 3A The second pixel electrode 2221 on the left side of the image, for example, has a size of 5.24um in the row direction X of region S. The overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222 is also reduced. By adjusting the overlapping area of ​​the second pixel electrode and the second common electrode in the second electrode group, without adjusting the first electrode group, the overlapping area of ​​the first pixel electrode 2121 and the first common electrode 2122 is equal to the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222. The capacitance generated by the second electrode group is consistent with the capacitance generated by the first electrode group, avoiding poor image display phenomena such as flickering and vertical lines.

[0092] In some embodiments, refer to Figure 4 As shown, at least a portion of the data line 4 connected to the pixel group 2 is located between the first electrode group 212 and the second electrode group 222 of the pixel group 2; at least a portion of the data line 4 is either the first data segment 41 or the second data segment 42; the first electrode 211a of the first transistor 211 and the first electrode 221a of the second transistor 221 are both connected to the data line 4, the second electrode 211b of the first transistor 211 is connected to the first pixel electrode 2121, and the second electrode 221b of the second transistor 221 is connected to the second pixel electrode 2221; the direction in which the first electrode 211a of the first transistor 211 points to the second electrode 211b and is parallel to the row direction X is the first direction F1, and the direction in which the first electrode 221a of the second transistor 221 points to the second electrode 221b and is parallel to the row direction X is the second direction F2, and the first direction F1 and the second direction F2 are opposite.

[0093] For example, refer to Figure 4The first direction F1 and the second direction F2 described above are both for a single pixel group 2, where the first electrode of the transistor points to the second electrode. Figure 4 The pixel group shown is only one example. The specific direction needs to be determined based on the position of the first and second electrodes of the transistor. The first direction F1 and the second direction F2 are not fixed. However, it can be understood that the first direction F1, in which the first electrode 211a of the first transistor 211 points to the second electrode 211b and is parallel to the row direction X, is opposite to the second direction F2, in which the first electrode 221a of the second transistor 221 points to the second electrode 221b and is parallel to the row direction X. This is beneficial for the spatial arrangement of other structures in the pixel group 2, and makes it easier to make the overlap area of ​​the first pixel electrode 2121 and the first common electrode 2122 equal to the overlap area of ​​the second pixel electrode 2221 and the second common electrode 2222.

[0094] It should be noted that at least a portion of the data line 4 connected to pixel group 2 is located between the first electrode group 212 and the second electrode group 222 of pixel group 2, such as... Figure 4 As shown, at least a portion of the data line 4 extends along the column direction Y and is located between the first electrode group 212 and the second electrode group 222. At least a portion of the data line 4 is configured to provide data signals to the first pixel electrode 2121 and the second pixel electrode 2221 respectively through the first transistor 211 and the second transistor 221. The data signal can be a voltage signal, the magnitude of which corresponds to the brightness of the sub-pixel.

[0095] In some embodiments, the first transistor 211 and the second transistor 221 are arranged in a centrally symmetrical manner.

[0096] It should be noted that, continue to refer to Figure 4 In the region where pixel group 2 is located, the central symmetry point is O. The first transistor 211 and the second transistor 221 are symmetrical about the central symmetry point O. The line segment formed by connecting the center of the first transistor 211 and the center of the second transistor 221 passes through the central symmetry point O.

[0097] In some embodiments, refer to Figure 4 and Figure 5The first transistor 211 and the second transistor 221 are bottom-gate transistors. Both the first transistor 211 and the second transistor 221 include a gate 11, an active layer 12, and source / drain electrodes 13 stacked sequentially. The source / drain electrodes 13 include a first electrode 131 and a second electrode 132. The orthographic projection of the active layer 12 on the substrate 1 falls within the orthographic projection of the gate 11 on the substrate 1. At least a portion of the orthographic projections of the first electrode 131 and the second electrode 132 on the substrate 1 fall within the orthographic projection of the active layer 12 on the substrate 1. The orthographic projection shape of the first electrode 131 (e.g., the first electrode 221a of the second transistor 221) is U-shaped, and the opening of the first electrode 131 faces the second electrode 132.

[0098] For example, the orthographic projection of the active layer 12 of the first transistor 211 and the second transistor 221 onto the substrate 1 falls into the orthographic projection of the gate 11 onto the substrate 1. That is, the area of ​​the active layer 12 of the first transistor 211 and the active layer 12 of the second transistor 221 is smaller than the area of ​​the gate 11 of the corresponding first transistor 211 and the gate 11 of the corresponding second transistor 221. At least a portion of the orthographic projection of the first electrode 131 and the second electrode 132 onto the substrate 1 falls into the orthographic projection of the active layer 12 onto the substrate 1.

[0099] It should be noted that, as Figure 5 As shown, combined with Figures 2B-2F A gate layer 101, a gate insulating layer 102, a semiconductor layer 103, a pixel electrode layer 104, a source / drain metal layer 105, a passivation layer 106, and a common electrode layer 107 are sequentially disposed on a substrate 1. The semiconductor layer 103 and the pixel electrode layer 104 are located on the same layer, and the source / drain metal layer 105 is disposed on the side of the semiconductor layer 103 and the pixel electrode layer 104 away from the substrate 1. The gate layer 101 includes a transistor gate 11, the semiconductor layer 103 includes a transistor active layer 12, and the pixel electrode layer 104 is provided with multiple pixel electrodes (e.g., a second pixel electrode 2221). Figure 2C and Figure 2D As shown, the shapes of the two pixel electrodes in a pixel group 2, respectively, near the boundaries of the two transistors, correspond to the shape of the active layer 12, thereby achieving a reasonable spatial arrangement of multiple pixel electrodes and multiple active layers located on the same layer. The source / drain metal layer 105 includes a first electrode 131 and a second electrode 132 of the transistor. The second electrode 132 of the transistor contacts the pixel electrode to achieve electrical connection, and the first electrode 131 and the second electrode 132 of the transistor respectively contact the two ends of the active layer 12 of the transistor to achieve electrical connection. The common electrode layer 107 includes multiple common electrodes.

[0100] The following uses the second transistor as an example to illustrate the relationship between the gate, active layer, and source / drain of a transistor.

[0101] like Figure 5 As shown, Figure 5 for Figure 4 A cross-sectional view of the second transistor 221 obtained by taking a section along the cross-section line CC, wherein, from Figure 5 As can be seen, the orthographic projection of the active layer 12 of the second transistor 221 onto the substrate 1 falls into the orthographic projection of the gate 11 onto the substrate 1, and at least a portion of the orthographic projections of the first electrode 131 and the second electrode 132 of the second transistor 221 onto the substrate 1 falls into the orthographic projection of the active layer 12 onto the substrate 1. The first electrode 131 and the second electrode 132 of the second transistor 221 are electrically connected to their active layer. At least a portion of the orthographic projection of the second electrode 132 of the second transistor 221 onto the substrate 1 falls into the orthographic projection of the pixel electrode layer 104 onto the substrate 1. The second electrode 132 of the second transistor 221 is electrically connected to the pixel electrode on the pixel electrode layer 104.

[0102] In some embodiments, refer to Figure 2D , Figure 2F , Figure 6 and Figure 7 The first pixel electrode 2121 and the second pixel electrode 2221 are block electrodes, and the first common electrode 2122 and the second common electrode 2222 are strip electrodes, such as... Figure 3A As shown, both the first common electrode 2122 and the second common electrode 2222 include multiple slits f; the aperture ratio of the first sub-pixel 21 is equal to the aperture ratio of the second sub-pixel 22.

[0103] For example, refer to Figure 6 As shown, the first pixel electrode 2121 and the second pixel electrode 2221 are arranged side by side. The first common electrode 2122 and the second common electrode 2222 include multiple slits f, wherein each slit f extends along the column direction. A black matrix layer 110 is disposed above the pixel group 2. The black matrix layer 110 is used for light blocking. The actual light-transmitting area in the sub-pixel is the area not blocked by the black matrix layer 110. The aperture ratio of the first sub-pixel 21 is equal to that of the second sub-pixel 22. That is, the ratio of the actual light-transmitting area of ​​the first sub-pixel 21 to the total area is equal to that of the second sub-pixel 22, thereby ensuring light extraction efficiency. (Refer to...) Figure 7 , Figure 7 Here is a pixel opening structure diagram of the first sub-pixel and the second sub-pixel, where the pixel opening of the first sub-pixel is called the first pixel opening K1 and the pixel opening of the second sub-pixel is called the second pixel opening K2. Then the area of ​​the first pixel opening K1 is equal to the area of ​​the second pixel opening K2.

[0104] In some embodiments, refer to Figure 8The first electrode group 212 includes a first domain region 212m and a second domain region 212n arranged along the column direction Y. The second electrode group 222 includes a third domain region 222m and a fourth domain region 222n arranged along the column direction. The aperture ratios of the first domain region 212m, the second domain region 212n, the third domain region 222m and the fourth domain region 222n are equal.

[0105] For example, the first domain region 212m and the second domain region 212n are connected, and the third domain region 222m and the fourth domain region 222n are connected. The areas of the first domain region 212m, the second domain region 212n, the third domain region 222m and the fourth domain region 222n are equal, that is, the aperture ratios of the domain regions where the first electrode group 212 and the second electrode group 222 are located are equal, which can ensure that the light output efficiency of each domain region of the first electrode group 212 and the second electrode group 222 is the same and the light is uniform.

[0106] In some embodiments, refer to Figures 9A-9C As shown, the array substrate 10 further includes: a first spacer 51 disposed on the side of the first transistor 211 away from the substrate 1, and a second spacer 52 disposed on the side of the second transistor 221 away from the substrate 1; the first spacer 51 and the second spacer 52 serve as supports to form a space for placing the liquid crystal layer of the display panel.

[0107] In some examples, due to the placement of transistors, the black matrix layer 110 may experience insufficient light shading near the transistors, resulting in abnormal light effects. The first spacer 51 and the second spacer 52 can play a role in light shading and affect the aperture ratio of the sub-pixels. By adjusting the positions of the first spacer 51 and the second spacer 52, the light shading ability can be ensured while keeping their influence on the aperture ratio of the two sub-pixels consistent.

[0108] like Figure 9C As shown, taking the first spacer 51 as an example, the first spacer 51 includes a first part 511, a second part 512, and a third part 513 stacked sequentially. The first part 511 is closer to the substrate than the second part 512, and the orthographic projection of the first part 511 onto the substrate falls within the orthographic projection of the second part 512 onto the substrate. The orthographic projection of the second part 512 onto the substrate falls within the orthographic projection of the third part 513 onto the substrate. Figure 9B As shown, the boundary 51c of the orthographic projection of the third part 513 onto the substrate surrounds the boundary 51b of the orthographic projection of the second part 512 onto the substrate, and the boundary 51b of the orthographic projection of the second part 512 onto the substrate surrounds the boundary 51a of the orthographic projection of the first part 511 onto the substrate. The third part 513 is located in the same layer as the black matrix layer 110, and it can be considered that the third part of the first spacer and the second spacer belongs to the black matrix layer.

[0109] The center G1 of the orthogonal projection of the first spacer 51 on the substrate 1 is offset by a first distance H1 relative to the center J1 of the orthogonal projection of the first transistor 211 on the substrate 1 in a third direction F3, wherein the third direction F3 is the direction in which the first transistor 211 points to the second transistor 221; the center G2 of the orthogonal projection of the second spacer 52 on the substrate 1 is offset by a second distance H2 relative to the center J2 of the orthogonal projection of the second transistor 221 on the substrate 1 in a fourth direction F4, wherein the fourth direction F4 is the direction in which the second transistor 221 points to the first transistor 211.

[0110] It should be noted that the first transistor 211 and the second transistor 221 here are transistors in the same pixel group, and the aforementioned third direction F3 and fourth direction F4 are also directions determined based on two transistors in the same pixel group.

[0111] like Figure 9A As shown, the black matrix layer 110 may leak light on the side near the first transistor and the side near the second transistor. Here, the first spacer is shifted a first distance H1 towards the third direction F3 to block the position of the black matrix layer 110 near the first transistor 211. The second spacer 52 is shifted a second distance H2 towards the fourth direction F4 to block the position of the black matrix layer 110 near the second transistor 221. This compensates for the insufficient light blocking of the black matrix layer and ensures that there will be no display abnormalities caused by light leakage. In addition, the spacer shifting design can also prevent the problem of two spacers that are close to each other from sticking together.

[0112] In some embodiments, refer to Figure 9B As shown, the first distance H1 is equal to the second distance H2.

[0113] It should be noted that, in order to clearly illustrate the offset distance, Figure 9B The first and second transistors in the above description are taken as examples of the first and second transistors in adjacent pixel groups. The first spacer 51 and the second spacer 52 are offset by equal distances. This is primarily to ensure that the aperture ratios of the first domain region 212m, the second domain region 212n, the third domain region 222m, and the fourth domain region 222n are equal, thereby ensuring light extraction efficiency. On the other hand, referring to... Figure 9B and Figure 9C Since the first spacer 51 and the second spacer 52 are columnar structures, the surrounding liquid crystal deflection is disordered, which easily causes light leakage. Setting an offset distance can prevent light leakage.

[0114] In some embodiments, continue to refer to Figure 9BThe orthographic projection of the first spacer 51 on the substrate 1 overlaps with the orthographic projections of the first pixel electrode 2121 and the second pixel electrode 2221 on the substrate 1; the orthographic projection of the second spacer 52 on the substrate 1 overlaps with the orthographic projections of the first pixel electrode 2121 and the second pixel electrode 2221 on the substrate 1.

[0115] It should be noted that the aforementioned overlap refers to at least a portion of the orthogonal projection of the first spacer 51 onto the substrate 1 covering the orthogonal projection of the first pixel electrode 2121 onto the substrate 1, while at least a portion of the orthogonal projection of the first spacer 51 onto the substrate 1 also covers the orthogonal projection of the second pixel electrode 2221 onto the substrate 1. Figure 9B As shown, the outermost boundary 51c of the orthographic projection of the first spacer 51 onto the substrate 1 intersects with the boundaries of the orthographic projections of the first pixel electrode 2121 and the second pixel electrode 2221. Similarly, at least a portion of the orthographic projection of the second spacer 52 onto the substrate 1 covers the orthographic projection of the first pixel electrode 2121 onto the substrate 1, and at least a portion of the orthographic projection of the second spacer 52 onto the substrate 1 also covers the orthographic projection of the second pixel electrode 2221 onto the substrate 1. Figure 9B As shown, the outermost boundary 52c of the second spacer 52 projected onto the substrate 1 intersects with the boundaries of the first pixel electrode 2121 and the second pixel electrode 2221. This overlapping design ensures that the area between the transistor and the pixel electrode is blocked, effectively preventing light leakage.

[0116] For example, the first spacer 51 and the second spacer 52 can be disposed on the color filter substrate (CF) or on the array substrate. The color filter substrate, also known as the opposing substrate, has a liquid crystal layer disposed between it and the array substrate. The color filter substrate may have a black matrix layer and a color filter layer. The color filter layer includes multiple filter units of different colors, such as red, green, and blue filter units formed using red, green, and blue photosensitive resins. Each filter unit corresponds to a sub-pixel. The black matrix layer is used to define the boundaries between the filter units, preventing light leakage between adjacent filter units.

[0117] like Figure 10As shown, some embodiments of this disclosure also provide a display panel 100, including a display area AA and a peripheral area BB disposed around the display area AA; the display panel includes an array substrate 10 provided in any of the above embodiments and at least one gate driving circuit 20 disposed on the substrate 1; the plurality of pixel groups 2 are located in the display area AA; the gate driving circuit 20 is disposed in the peripheral area BB, and the gate driving circuit 20 includes N cascaded shift registers 30.

[0118] The gate driving circuit 20 is used to output gate signals to the display area to control each sub-pixel to turn on and input data signals. The multiple gate lines 3' are arranged sequentially along the column direction, and multiple first gate lines 31 and multiple second gate lines 32 are arranged alternately; among the N cascaded shift registers 30, the shift registers 30 are electrically connected to the gate lines 3' and output gate scan signals to the gate lines 3'.

[0119] For example, see Figure 10 The display panel includes two gate driving circuits 20, located on opposite sides of the display area. In both gate driving circuits 20, the same-stage shift register is electrically connected to the same gate line. For example, the first-stage shift registers of both gate driving circuits are electrically connected to the first gate line, simultaneously outputting gate scan signals to the gate line. This approach improves driving efficiency, saves scanning time, allows multiple sub-pixels to open faster for data signal writing, and improves display quality. Optionally, this design can also support single-sided driving, i.e., setting the gate driving circuit on one side of the non-display area; this is not limited to this design.

[0120] Shift register 30 includes input, output, and reset terminals. In some examples, the cascaded relationship of N shift registers 30 is as follows: the output of the i-th stage shift register is connected to the input of the (i+n)-th stage shift register; the output of the (i+n)-th stage shift register is connected to the reset terminal of the i-th stage shift register. This cascaded arrangement is called the conventional reset cascaded arrangement, where a shift register carries over to the n-th stage shift register and is then reset by that shift register.

[0121] It should be noted that the output of a shift register can be either the output terminal responsible for outputting the gate scan signal, electrically connected to the gate line, and outputting the gate scan signal to the gate line, or it can be the output terminal responsible for cascading. The output terminal responsible for cascading serves the functions of cascading carry and reset, and is not electrically connected to the gate line of the display area. In other words, the shift register has two output terminals with different functions. In some examples, the shift register has a single output terminal, which is both connected to the gate line and responsible for cascading.

[0122] In some other embodiments of this application, the cascade relationship of the N shift registers 30 is as follows: the output of the i-th shift register is connected to the input of the (i+n)-th shift register; the output of the (i+n+2j)-th shift register is connected to the reset terminal of the i-th shift register; j is greater than or equal to 1. This cascade method is called the delayed reset cascade method, that is, one shift register outputs a carry signal to the n-th shift register (called the carry shift register) arranged after it, and is then reset by the 2j-th shift register arranged after the carry shift register, which is equivalent to delaying the reset by 2j rows.

[0123] For example, such as Figure 11A As shown, Figure 11A The diagram shows the first eight cascaded shift registers 30 included in the gate drive circuit 20. When i=1, n=4, j=1 and i, n, and j are all positive integers greater than 0, i+n=5, i+n+2j=7, that is, the output of the first-stage shift register is connected to the input of the fifth-stage shift register, and the output of the seventh-stage shift register is connected to the reset terminal of the first-stage shift register. When i=2, the output of the second-stage shift register is connected to the input of the sixth-stage shift register; the output of the eighth-stage shift register is connected to the reset terminal of the second-stage shift register, and so on. Further details are omitted.

[0124] In some examples, the inputs of the first n stages of the N shift registers are connected to the initialization signal line STV, and the reset input of the last (n+2j)th stage shift register is connected to the initialization signal line. The last (n+2j)th stage shift register is, for example, a dummy shift register. For example, continuing to refer to... Figure 11A It can be seen that the input terminals of the first four shift registers of the N shift registers are connected to the initialization signal line STV, and the reset terminals of the last six shift registers are connected to the initialization signal line.

[0125] It should be noted that the above cascading relationship uses a 2j-row delay for reset. For example, a two-row delay reset using an even-numbered row delay can support the implementation of parity swapping of timing signals, which will be described in detail below.

[0126] In some embodiments, such as Figure 11EAs shown, the shift register includes multiple transistors, including an input transistor M1, a reset transistor M2, an output transistor M3, a storage capacitor C1, and multiple noise reduction transistors M, including a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. Specifically, the gate and first terminal of input transistor M1 are electrically connected to the input terminal Input, and the second terminal is electrically connected to the pull-up node PU; the gate of reset transistor M2 is electrically connected to the reset terminal Reset, the first terminal of reset transistor is electrically connected to the pull-up node PU, and the second terminal is electrically connected to the first voltage signal line VGL; the gate of output transistor M3 is electrically connected to the pull-up node PU, the first terminal of output transistor M3 is electrically connected to the clock signal line CLK, and the second terminal is electrically connected to the output terminal Output; the storage capacitor C1 is electrically connected between the pull-up node PU and the output terminal Output.

[0127] The fourth transistor M4, sixth transistor M6, seventh transistor M7, eighth transistor M8, tenth transistor M10, eleventh transistor M11, thirteenth transistor M13, fourteenth transistor M14, sixteenth transistor M16, and seventeenth transistor M17 of the multiple noise reduction transistors M are all electrically connected to the first voltage signal line VGL. The fifth transistor M5, sixth transistor M6, eighth transistor M8, and ninth transistor M9 form the first pull-down node control sub-circuit. The first pull-down node control sub-circuit is electrically connected to the second voltage signal line VDDO and the first pull-down node PD1. The first pull-down node PD1 controls the gates of the tenth transistor M10 and the eleventh transistor M11 to reduce noise at the pull-up node and the output. The twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 form the second pull-down node control sub-circuit. The second pull-down node control sub-circuit is electrically connected to the third voltage signal line VDDE and the second pull-down node PD2. The second pull-down node PD2 controls the gates of the sixteenth transistor M16 and the seventeenth transistor M17 to reduce noise at the pull-up node and the output. The average voltage levels of the signals transmitted on the second voltage signal line VDDO and the third voltage signal line VDDE are higher than the level of the signal transmitted on the first voltage signal line VGL. The first pull-down node control sub-circuit and the second pull-down node control sub-circuit can operate alternately, improving the lifespan of the shift register. The initialization signal bus STV0 controls the gates of the seventh transistor M7 and the fourth transistor M4, used to perform a general reset of the pull-up nodes and outputs of all shift registers in the gate drive circuit before the start of a frame. Optionally, each shift register stage is connected to the initialization signal bus STV0 signal. The specific transistor connection relationships in this case are referenced [reference needed]. Figure 11E For example, the gate and first terminal of input transistor M1 are electrically connected (optionally, the gate and first terminal of input transistor M1 can also be given signals separately, which is not limited here), the second terminal of input transistor M1 is electrically connected to the pull-up node PU, the gate of output transistor M3 is electrically connected to the pull-up node, the first terminal of output transistor M3 is electrically connected to the clock signal line CLK, and the second terminal of output transistor M3 is electrically connected to the output terminal Output. For other transistor connection methods, see [link to documentation]. Figure 11E I will not go into details here.

[0128] When the voltage of the pull-up node PU is at the turn-on voltage, the output transistor M3 is turned on, transmitting the valid clock signal from the clock signal line to the output terminal Output. This valid clock signal serves as the gate scan signal and is output from the output terminal Output to the connected gate line. The gate scan signal is transmitted through the gate line to the connected sub-pixel, controlling the transistor in the sub-pixel to turn on. Simultaneously, this valid clock signal serves as the cascaded output signal, outputting to the input or output terminal of the cascaded shift register. The cascaded output signal is transmitted to the input terminal of the shift register, controlling the input transistor M1 to turn on and charging the pull-up node PU. Alternatively, the cascaded output signal is transmitted to the reset terminal of the shift register, controlling the reset transistor M2 to turn on and resetting the pull-up node PU. The effective clock signal is a signal that enables the transistor it controls to turn on. For example, if the transistor in the sub-pixel, or the input transistor M1 and the reset transistor M2 are N-type transistors, the level of the effective clock signal is high. If the transistor in the sub-pixel, or the input transistor M1 and the reset transistor M2 are P-type transistors, the level of the effective clock signal is low.

[0129] In some embodiments, refer to Figure 11A The display panel 100 further includes: M clock signal lines CLK disposed on the side of the gate driving circuit 20 away from the display area, the clock signal lines CLK being electrically connected to the gate driving circuit 20, wherein the i-th clock signal line is connected to the (Mm+i)-th shift register, wherein 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N.

[0130] For example, refer to Figure 11B , Figure 11B The diagram shows eight clock signal lines CLK, namely the first clock signal line CLK1 to the eighth clock signal line CLK8, i.e., M equals 8. When m = 0 and i = 1~8, the first clock signal line CLK1 is connected to the first-stage shift register, the second clock signal line CLK2 is connected to the second-stage shift register, and the eighth clock signal line CLK8 is connected to the eighth-stage shift register. When m = 1 and i = 1~8, the first clock signal line CLK1 is connected to the ninth-stage shift register, and so on. Multiple shift registers are grouped into groups of eight adjacent ones, and each shift register in each group is connected to a corresponding clock signal line.

[0131] In some examples, the signal transmission method of multiple clock signal lines CLK is such that the start position of the effective clock signal transmitted by the i-th clock signal line is earlier than the start position of the effective clock signal transmitted by the (i+1)-th clock signal line, where i+1≤M. Taking a high-level effective clock signal as an example (when the effective level is high, output transistor M3 is an N-type transistor; when the effective level is low, output transistor M3 is a P-type transistor; this example uses an N-type transistor), the rising edge of the i-th clock signal line is earlier than the rising edge of the effective clock signal transmitted by the (i+1)-th clock signal line.

[0132] Reference Figure 11C As shown, the start position of the effective clock signal transmitted by the first clock signal line CLK1 is earlier than the start position of the effective clock signal transmitted by the second clock signal line CLK2. The start position of the effective clock signal transmitted by the second clock signal line CLK2 is earlier than the start position of the effective clock signal transmitted by the third clock signal line CLK3. The start positions of the effective clock signals transmitted by the first clock signal line CLK1 to the eighth clock signal line CLK8 are sequentially delayed. The effective clock signals transmitted by the eight clock signal lines are output in the first order, i.e., CLK1→CLK2→CLK3→CLK4→CLK5→CLK6→CLK7→CLK8. Thus, the first-stage shift register to the Nth-stage shift register sequentially outputs the gate scan signal to the connected gate line.

[0133] In some embodiments, another transmission method for the signals of multiple clock signal lines CLK is as follows: starting from the first clock signal line, each pair of adjacent clock signal lines forms a group, and the starting position of the effective clock signal transmitted by the second clock signal line in each group is earlier than the starting position of the effective clock signal transmitted by the first clock signal line; the starting position of the effective clock signal output by the i-th clock signal line is earlier than the starting position of the effective clock signal output by the (i+2)-th clock signal line; i+2≤M.

[0134] For example, refer to Figure 11D , Figure 11DThe diagram shows eight clock signal lines CLK. Starting from the first clock signal line, each pair of adjacent clock signal lines forms a group: the first clock signal line CLK1 and the second clock signal line CLK2 form a group; the third clock signal line CLK3 and the fourth clock signal line CLK4 form a group; the fifth clock signal line CLK5 and the sixth clock signal line CLK6 form a group; and the seventh clock signal line CLK7 and the eighth clock signal line CLK8 form a group. In each group of clock signal lines, the starting position of the effective clock signal transmitted by the second clock signal line CLK2 is earlier than the starting position of the effective clock signal transmitted by the first clock signal line CLK1. That is, the starting positions of the effective clock signals transmitted by the eighth clock signal line CLK8, the sixth clock signal line CLK6, the fourth clock signal line CLK4, and the second clock signal line CLK2 are earlier than the starting positions of the effective clock signals transmitted by the seventh clock signal line CLK7, the fifth clock signal line CLK5, the third clock signal line CLK3, and the first clock signal line CLK1, respectively. The effective clock signals of the eight clock signal lines are output in a second sequence, namely CLK2→CLK1→CLK4→CLK3→CLK6→CLK5→CLK8→CLK7. Thus, the order of the gate scan signals output by the first-stage shift register to the Nth-stage shift register is reversed relative to the first sequence output method, i.e., the second-stage shift register outputs the gate scan signal before the first-stage shift register.

[0135] In the gate drive circuit provided by the above embodiments of this application, the cascaded relationship of each shift register is to use a 2j-row delay for reset, and to use an even-row delay reset method, which can support the implementation of odd-even interchange of timing signals, as described in detail below. Figure 11F As shown, exemplarily, taking eight clock signal lines and eight shift registers, with a two-row reset delay as an example, the cascaded shift registers are configured such that the first shift register RS1 carries to the fifth shift register RS5, the second shift register RS2 carries to the sixth shift register RS6, the seventh shift register RS7 resets to the first shift register RS1, and the eighth shift register RS8 resets to the second shift register RS2. Figure 11F In the diagram above, the effective clock signals of the eight clock signal lines are output in the first order, namely CLK1→CLK2→CLK3→CLK4→CLK5→CLK6→CLK7→CLK8. According to the cascading method of even-numbered row reset, CLK1 corresponds to CLK5 and CLK2 corresponds to CLK6 during carry, and CLK7 corresponds to CLK1 and CLK8 corresponds to CLK2 during reset. Figure 11FIn the diagram below, the effective clock signals of the eight clock signal lines are output in the second sequence: CLK2→CLK1→CLK4→CLK3→CLK6→CLK5→CLK8→CLK7. According to the cascading method of delayed even-numbered row reset, CLK1 corresponds to CLK5 and CLK2 corresponds to CLK6 during carry, and CLK7 corresponds to CLK1 and CLK8 corresponds to CLK2 during reset. It can be seen that the correspondence of the effective clock signals of the clock signal lines is consistent during carry and reset of the shift registers, regardless of which output method is used. Therefore, the timing of the clock signal lines can be changed between the two methods, and the carry and reset of each shift register of the gate drive circuit can be performed normally. Each shift register can output the gate scan signal / cascade signal normally without clock signal disorder causing malfunction.

[0136] In some embodiments, based on Figure 1 and Figure 2A The dual-grid + bow-shaped pixel architecture shown connects two columns of sub-pixels with the same data line, meaning the same data signal drives both odd and even columns of sub-pixels. Given pre-charging of the sub-pixels, the charging process differs between odd and even columns. Insufficient pixel charging rate leads to vertical stripes. This is especially true for images with mixed blue colors, which are more prone to vertical stripe defects.

[0137] In some embodiments, refer to Figure 12A , Figure 12A The diagram shows the arrangement of subpixels, where multiple subpixels 2' include red subpixels r, green subpixels g, and blue subpixels b. For example, along the row direction X, multiple subpixels are arranged in a column of red subpixels r, a column of green subpixels g, and a column of blue subpixels b. Subpixels arranged along the column direction Y are subpixels of the same color. A grid line group 3 is electrically connected to a row of subpixels.

[0138] In a sky-blue background, this pixel architecture exhibits inconsistencies in grayscale voltage between the blue and red / green subpixels. The blue subpixels have a higher grayscale voltage, causing voltage fluctuations on the data lines. This leads to insufficient charging when data signals are transmitted from blue subpixel b to red subpixel r, from blue subpixel b to green subpixels, from red subpixels to blue subpixels, and from green subpixels to blue subpixels. As a result of this insufficient charging, some red, green, and blue subpixels appear either too bright or too dark. Since the human eye is most sensitive to green subpixels, their brightness distribution has the greatest impact on visual effects. Consequently, green subpixels periodically appear too bright, ultimately resulting in the undesirable vertical stripe display.

[0139] Figure 12B Indicate Figure 12A The data lines sequentially write the color of each sub-pixel. Taking data line D4 as an example, data line D4 is electrically connected to each pixel group enclosed by frame Q, and the order in which the data signals are written to each sub-pixel is: red, green, red, blue, red, green, red, blue. Figure 12B As shown, exemplarily, under a sky-blue background, the grayscale voltage of the blue sub-pixel is greater than that of the red and green sub-pixels. The grayscale voltages of the red and green sub-pixels are the same. When the grayscale voltage changes abruptly, insufficient pixel charging is likely to occur. At position ① and position ②, there is no pre-charging process, resulting in a short charging time; at position ③, there is a pre-charging process, resulting in a longer charging time. Consequently, the blue sub-pixel at position ① appears darker (from a sudden change from low to high grayscale voltage), while the red sub-pixel at position ② appears brighter (from a sudden change from high to low grayscale voltage). Other sub-pixels have normal brightness. Throughout the display area, sub-pixels at various positions will exhibit either a darker or brighter display. Since the human eye is most sensitive to green sub-pixels, the brightness distribution of green sub-pixels has the greatest impact on the visual effect. Therefore, green sub-pixels will periodically appear brighter, ultimately leading to the undesirable display problem of vertical lines.

[0140] It is understandable that in the above gate drive circuit, the input signal of the shift register's reset signal terminal is delayed, thereby enabling timing signals to be output in both a first-order and a second-order output mode during timing control. For example... Figure 12A As shown in the diagram, red and blue subpixels connect to odd-numbered raster rows, while green and blue subpixels connect to even-numbered raster rows. After adjustment to... Figure 11C After the clock signal generated by the clock signal line shown, the starting position of the effective clock signal transmitted by the second clock signal line in each group of clock signal lines is earlier than the starting position of the effective clock signal transmitted by the first clock signal line. In other words, the signals received by the green and blue sub-pixels connected to the even-numbered rows are received before the signals received by the red and blue sub-pixels connected to the odd-numbered rows of grid lines. This changes the opening order of each sub-pixel, reduces the sudden change in grayscale voltage of sub-pixels that are opened one after the other, improves the dark or bright display caused by insufficient or sufficient charging of sub-pixels, and avoids the vertical stripe problem caused by charging differences. In particular, it solves the vertical stripe problem that appears when the display panel displays a sky blue image.

[0141] In some embodiments, the duty cycle of the effective clock signal on each clock signal line is 50%, enabling charge sharing of the clock signal and thus reducing the power consumption of the gate drive circuit. (Refer to...) Figure 11C and Figure 11D , Figure 11C and Figure 11D for Figure 11AThe timing diagram corresponding to the gate drive circuit in the diagram. Figure 11C and Figure 11D The falling edge of the timing signal received by the first clock signal line is at the same time as the rising edge of the timing signal received by the fifth clock signal line, and the falling edge of the timing signal received by the second clock signal line is at the same time as the rising edge of the timing signal received by the sixth clock signal line. In other words, the CLK duty (clock control signal duty cycle) can be set to 50% to achieve charge sharing and reduce power consumption.

[0142] In some embodiments, refer to Figure 13 Multiple shift registers 30 are arranged along the column direction Y; the display panel further includes a first voltage signal line 61 (VGL) disposed on one side of the gate drive circuit 20 along the row direction X; each stage of the shift register 30 includes multiple transistors 40, at least one of the multiple transistors 40 being electrically connected to the voltage signal line 61; the transistors 40 include multiple reset transistors M2 and multiple noise reduction transistors M, and the shift register 30 also includes an input transistor M1, such as... Figure 11E As shown above, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, the fourteenth transistor M14, the sixteenth transistor M16, and the seventeenth transistor M17 among the multiple noise reduction transistors M are all electrically connected to the first voltage signal line VGL, and the reset transistor M2 is electrically connected to the first voltage signal line 61.

[0143] like Figure 13 and Figure 14A As shown, the peripheral area of ​​the display panel is also provided with a second voltage signal line VDDO and a third voltage signal line VDDE. The first voltage signal line 61 (VGL), the second voltage signal line VDDO and the third voltage signal line VDDE all extend along the column direction Y and are all located on the side of the gate drive circuit 20 away from the display area AA.

[0144] The input transistor M1 and the reset transistor M2 are located further away from the first voltage signal line 61 (VGL) relative to the noise reduction transistor M; that is, the input transistor M1 and the reset transistor M2 are closer to the display area AA. Since the reset transistor M2 is connected to the reset terminal Reset and the input transistor M1 is connected to the input terminal Input, the reset terminal Reset and the input terminal Input need to be cascaded. The reset terminal Reset and the input terminal Input of a certain stage shift register are connected to the output terminal Output of other stages shift registers. The output terminal Output of the shift register is connected to the gate line and is located close to the display area. Therefore, the input transistor M1 and the reset transistor M2 are located close to the display area AA to facilitate connection. This results in the input transistor M1 and the reset transistor M2 being far from the first voltage signal line 61, causing a problem in the connection between the reset transistor M2 and the first voltage signal line 61. If a lead is added to each shift register to connect the first voltage signal line 61 and the reset transistor M2, the lead will be relatively long. Considering the spacing between each stage, as well as the via and transistor design, this will make the shift register layout design difficult, increase the space occupied, indirectly increase the area of ​​the surrounding area, and increase the bezel of the display panel.

[0145] Based on this, the display panel 100 also includes an auxiliary first voltage signal line 62 located on the other side of the gate driving circuit 20, the first voltage signal line 61 and the auxiliary first voltage signal line 62 being electrically connected; the input transistor M1 and the reset transistor M2 are close to the auxiliary first voltage signal line 62 relative to the noise reduction transistor M; at least a portion of the reset transistor M2 of the shift register 30 is electrically connected to the auxiliary first voltage signal line 62 through a first lead 71.

[0146] For example, such as Figure 13 and Figure 14A As shown, the first voltage signal line 61 and the auxiliary first voltage signal line 62 are respectively disposed on both sides of the gate driving circuit 20 along the row direction X. Both the first voltage signal line 61 and the auxiliary first voltage signal line 62 extend along the column direction Y. That is, the auxiliary first voltage signal line 62 is close to the display area AA and is relatively close to the reset transistor M2. At least part of the shift register 30 can electrically connect the reset transistor M2 and the auxiliary first voltage signal line 62 through their respective first leads 71. The first voltage signal line 61 and the auxiliary first voltage signal line 62 are electrically connected, thereby realizing the electrical connection between the reset transistor M2 and the first voltage signal line 61.

[0147] By setting an auxiliary first voltage signal line 62 and connecting the reset transistor M2 and the auxiliary first voltage signal line 62 with a first lead-out line 71, the length of the first lead-out line 71 is shortened compared to connecting the reset transistor M2 with a lead-out line from the first voltage signal line 61. This reduces the connection difficulty, improves the connection reliability, optimizes the spatial layout of the gate drive circuit, achieves a narrow bezel for the display panel, and improves the signal transmission efficiency.

[0148] In some embodiments, the display panel further includes: a connection voltage signal line 63 disposed on the side of the last stage shift register of the gate drive circuit 20 away from other shift registers 30, wherein the voltage signal line 61 and the auxiliary voltage signal line 62 are connected through the connection voltage signal line 63; the connection voltage signal line 63 extends along the row direction X; the connection voltage signal line 63 includes multiple electrically connected sub-signal lines 631.

[0149] For example, continue to refer to Figure 13 and Figure 14A The voltage signal line 63 extends along the X direction and includes multiple electrically connected sub-signal lines 631. These sub-signal lines 631 are connected in parallel, which can reduce the resistance of the voltage signal line 63 and reduce signal transmission loss. By setting the voltage signal line 63, the transmission of ultraviolet light and the occurrence of electrostatic breakdown can be reduced.

[0150] In some embodiments, the noise reduction transistor of the shift register 30 is connected to the voltage signal line 61 via a second lead 72.

[0151] For example, refer to Figure 13 and Figure 14A , Figure 14B As shown, the second lead 72 is electrically connected to the first voltage signal line 61. The second lead 72 is inserted between multiple noise reduction transistors M, and the second lead 72 is electrically connected to the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, the fourteenth transistor M14, the sixteenth transistor M16, and the seventeenth transistor M17 among the multiple noise reduction transistors M. The second lead 72 is configured to transmit the first voltage signal to some transistors in the shift register 30 of this stage.

[0152] The following describes the location of the membrane layer of each signal line in the surrounding area.

[0153] It should be noted that, referring to Figures 14A-14COptionally, the first voltage signal line 61 can be set in the same layer and material as the gate of the transistor, and the first voltage signal line 62 and the second lead 72 can be set in the same layer and material as the source and drain of the transistor. The second lead 72 is electrically connected to the first voltage signal line 61 through a via (the via is filled with a transition electrode, which is optionally in the same layer as the common electrode layer of the display area AA). Multiple transistors are electrically connected to other signal lines through vias.

[0154] The connecting voltage signal line 63 and the auxiliary first voltage signal line 62 are set in the same layer and with the same material. Optionally, they are set in the same layer and with the same material as the source and drain of the transistor. One end of the connecting voltage signal line 63 is electrically connected to the first voltage signal line 61 through a via (the via is filled with a transition electrode, which is optionally in the same layer as the common electrode layer of the display area AA), and the other end is electrically connected to the auxiliary first voltage signal line 62.

[0155] Optionally, the auxiliary first voltage signal line 62, the connecting voltage signal line 63, and the first lead-out line 71 are integrated into a single structure of the same layer and material, and are also disposed in the same layer and material as the source and drain of the transistor. One of the source and drain terminals of the reset transistor M2 is electrically connected to the first voltage signal line 61 through the first lead-out line 71.

[0156] For example, refer to Figure 14A and Figure 14B , combined Figure 5 The first voltage signal line 61 is located on the gate layer 101. The auxiliary first voltage signal line 62, the connecting voltage signal line 63, the first lead-out line 71, and the second lead-out line 72 are located on the source / drain metal layer 105. A transition electrode layer 108 is stacked on the source / drain metal layer. For example, the transition electrode layer 108 and the common electrode layer 107 are of the same layer and the same material. The transition electrode layer 108 includes multiple transition electrodes. Through-holes are provided between the transition electrodes and the gate layer and the source / drain metal layer. The transition electrodes are used to electrically connect the signal lines located on the gate layer 101 and the signal lines located on the source / drain metal layer 105. The first voltage signal line 61 is connected to the second lead-out line 72 through the corresponding transition electrode. The first voltage signal line 61 is connected to the connecting voltage signal line 63 through the corresponding transition electrode.

[0157] In some examples, the second voltage signal line VDDO and the third voltage signal line VDDE are both disposed on the same layer and material as the gate of the transistor. The second voltage signal line VDDO and the third voltage signal line VDDE are located in the gate layer 101. The second voltage signal line VDDO is connected to the lead in the shift register through a corresponding transfer electrode, and the third voltage signal line VDDE is connected to the lead in the shift register through a corresponding transfer electrode.

[0158] In some embodiments, the plurality of noise reduction transistors M include multiple groups of transistors, each group of transistors including two transistors; the second lead 72 is located between the two transistors in each group of transistors, the two transistors being staggered in the column direction.

[0159] For example, refer to Figure 15A A group of transistors includes two transistors, T and T', for example, the ninth transistor M9 and the fifteenth transistor M15. The two transistors are staggered in the column direction Y, wherein, combined with Figure 11E and Figure 14B The gate of the ninth transistor M9 is electrically connected to the third lead 73. One of the source and drain terminals of the ninth transistor M9 is electrically connected to the third lead 73 through the first transition electrode 1081 and the corresponding via. The third lead 73 is electrically connected to the second voltage signal line VDDO through the transition electrode and the corresponding via. The gate of the fifteenth transistor M15 is electrically connected to the fourth lead 74. One of the source and drain terminals of the fifteenth transistor M15 is electrically connected to the fourth lead 74 through the first transition electrode 1082 and the corresponding via. The fourth lead 74 is electrically connected to the third voltage signal line VDDE through the transition electrode and the corresponding via. It can be seen that the ninth transistor M9 and the fifteenth transistor M15 are located on both sides of the second lead 72, and are staggered in the column direction Y, that is, they are not arranged in a straight line in the column direction. The first transition electrode 1081 and its via, and the first transition electrode 1082 and its via corresponding to the ninth transistor M9 and the fifteenth transistor M15 are also staggered in the column direction. Correspondingly, the shape of the second lead 72 is such that it has a certain curvature along the row direction X to match the spatial position of the transistors arranged on both sides of it.

[0160] For example, refer to Figure 15B The third adapter electrode 1083 and the fourth adapter electrode 1084 are located on both sides of the second lead, and the third adapter electrode 1083 and the fourth adapter electrode 1084 are staggered in the column direction.

[0161] The aforementioned set of transistors and set of transition electrodes are all arranged in a staggered manner in the column direction. On the one hand, this can compress space in the column direction Y and reduce the height of each shift register (i.e., the size of the area where each shift register 30 is located in the column direction). In high-resolution products, this is beneficial for the arrangement of shift registers. On the other hand, it can increase the lifespan of the gate drive circuit.

[0162] In some embodiments, refer to Figure 14A As shown, the dimension L of the region where each shift register 30 is located in the column direction is 60μm~100μm.

[0163] For example, the dimension L in the column direction of the region where each shift register 30 is located is 60μm, 80μm, or 100μm.

[0164] like Figure 2A and 10 As shown, some embodiments of this disclosure also provide a driving method for a display panel, including the display panel provided in any of the above embodiments, wherein the plurality of pixel groups 2 include a plurality of row pixel groups arranged along the column direction Y, and each row pixel group includes at least two pixel groups 2 arranged along the row direction; each row pixel group is disposed between a first gate line 31 and a second gate line 32 of a gate line group 3, and is electrically connected to the gate line group 3; the driving method includes: when the display panel 100 displays a first set image, the gate driving circuit 20 outputs a first set of gate driving signals, the plurality of row pixel groups 2 are activated row by row under the scanning of the plurality of gate line groups 3, and in each row pixel, the first sub-pixel electrically connected to the first gate line 31 is activated before the second sub-pixel electrically connected to the second gate line 32.

[0165] For example, the first set screen mentioned above is a screen other than sky blue; it could be a pink screen, a yellow screen, or a less frequently used screen, or a normal screen. In this case, the grayscale voltage difference between each sub-pixel is small, so it will not affect the fluctuation of the voltage transmission signal, thus ensuring that the difference in brightness between sub-pixels is not obvious, and the display panel can display normally. The first set of gate driving signals output by the gate driving circuit 20 can drive each row of pixels to turn on row by row. At the same time, the first sub-pixel electrically connected to the first gate line 31 turns on before the second sub-pixel electrically connected to the second gate line 32. (Refer to...) Figure 12A , Figure 12A The first sub-pixel consists of a blue sub-pixel and a red sub-pixel, and the second sub-pixel consists of a blue sub-pixel and a green sub-pixel. Under the control of the first set of gate drive signals, the first sub-pixel is turned on before the second sub-pixel.

[0166] In some embodiments, refer to Figure 10 When the display panel 100 displays the second setting screen, the gate driving circuit 20 outputs the second gate driving signal, and the plurality of row pixel groups are activated row by row under the scanning of the plurality of gate line groups 3. In each row pixel, the second sub-pixel electrically connected to the second gate line is activated before the first sub-pixel electrically connected to the first gate line.

[0167] For example, in the second preset screen, which is a sky blue screen, the grayscale voltage difference between each sub-pixel is large, which will affect the fluctuation of the voltage transmission signal. The difference in brightness between sub-pixels is obvious, which can easily lead to vertical stripe defects and cause the display panel to fail to display the image normally. The second set of gate driving signals output by the gate driving circuit 20 can drive each row of pixels to turn on one by one. At the same time, the first sub-pixel electrically connected to the second gate line 32 turns on before the second sub-pixel electrically connected to the first gate line 31. In this way, changing the turning order of the driven sub-pixels can improve the phenomenon of insufficient charging between sub-pixels, thereby reducing the voltage difference and improving the problem of vertical stripe defects in the image display. (Refer to...) Figure 12A , Figure 12A The first sub-pixel consists of a blue sub-pixel and a red sub-pixel, and the second sub-pixel consists of a blue sub-pixel and a green sub-pixel. Under the control of the second set of gate drive signals, the second sub-pixel is turned on before the first sub-pixel, that is, the second sub-pixel, which is electrically connected to the even-numbered row gate lines, is electrically connected before the odd-numbered row gate lines.

[0168] like Figure 16 As shown, some embodiments of this disclosure also provide a display device 1000, including the display panel 100 provided in any of the above embodiments.

[0169] For example, the display device 1000 may be a Mini LED (Mini Light Emitting Diode) display device or a Micro LED (Micro Light-Emitting Diode) display device.

[0170] In some examples, miniature LEDs or micro LEDs are used as light-emitting devices. Compared with traditional LEDs, they occupy a smaller volume and have smaller particles. Within the same screen size, the light source density per unit area is higher and the light source unit size is smaller. Therefore, more precise local control of the light-emitting device can be achieved, which can ensure the uniformity of display brightness and thus ensure the display quality of the display device 1000.

[0171] Some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or stationary (e.g., still images), and whether text or images. More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0172] This disclosure does not impose any special restrictions on the specific form of the display device described above. The display device 1000 adopts the display panel 100 provided in the above embodiments. Therefore, the display device 1000 provided in this disclosure has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be elaborated here.

[0173] For example, such as Figure 16 As shown, the display device 1000 is, for example, rectangular.

[0174] In some embodiments, refer to Figure 17 and Figure 11A The display device 1000 further includes M clock signal lines, the i-th clock signal line being connected to the (Mm+i)-th shift register, where 1≤i≤M and i is a positive integer, 0≤m and m is a positive integer; (Mm+i)≤N; the display device 1000 further includes a control chip 50, which is connected to the M clock signal lines and outputs clock signals to the M clock signal lines; the control chip 50 is configured to, when detecting that the display panel displays a first set screen, output valid clock signals to the M clock signal lines in a first order, wherein the first order is 1, 2, 3, 4...M-1, M; when detecting that the display panel displays a second set screen, output valid clock signals to the M clock signal lines in a second order, wherein the second order is 2, 1, 4, 3...M,M-1.

[0175] For example, Figure 17The clock signal lines shown are eight, meaning M equals eight. When m equals 0, the first clock signal line is connected to the first-stage shift register. The display device 1000 includes a control chip 50, which is connected to the eight clock signal lines and outputs timing signals to them. When the control chip 50 detects that the display panel displays a first set screen, it outputs valid clock signals to the eight clock signal lines in a first order, where the first order is 1, 2, 3, 4, 5, 6, 7, 8. When the control chip 50 detects that the display panel displays a second set screen, it outputs valid clock signals to the eight clock signal lines in a second order, where the second order is 2, 1, 4, 3, 6, 5, 8, 7. Figure 17 The example shown is just one example. The order of the clock signals output by other numbers of clock signal lines under the corresponding settings screen can be calculated by referring to the above formula, and will not be elaborated here.

[0176] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized by, include: Display area and surrounding area; The display panel includes an array substrate; The array substrate includes: Substrate; Multiple sub-pixels are arrayed on the substrate in an E-row, F-column configuration. These sub-pixels form multiple pixel groups located in the display area. Each pixel group includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first electrode group connected together, and the second sub-pixel includes a second transistor and a second electrode group. The first and second electrode groups are sequentially arranged along the row direction. The first and second transistors are both located between the first and second electrode groups, and are respectively located at both ends of the pixel group along the column direction. The first electrode group includes a first pixel electrode and a first common electrode, and the second electrode group includes a second pixel electrode and a second common electrode. Multiple gate lines are disposed on the substrate, the multiple gate lines form multiple gate line groups, each gate line group includes a first gate line and a second gate line, and the first sub-pixel and the second sub-pixel of each pixel group are respectively connected to the first gate line and the second gate line of a gate line group. Multiple data lines are disposed on the substrate, and the first sub-pixel and the second sub-pixel of each pixel group are connected to one of the data lines; at least a portion of the multiple data lines include a third data segment extending along the row direction, a first data segment and a second data segment extending along the column direction, the third data segment connecting the first data segment and the second data segment, the first data segment being disposed between the i-th column sub-pixel and the (i+1)-th column sub-pixel, the second data segment being disposed between the (ij)-th column sub-pixel and the (ij-1)-th column sub-pixel, where j is greater than or equal to 1; i+1≤F; Wherein, the overlap area between the first pixel electrode and the first common electrode is equal to the overlap area between the second pixel electrode and the second common electrode; The display panel also includes: At least one gate driving circuit is disposed on the substrate, the gate driving circuit being located in the peripheral region; the gate driving circuit includes N cascaded shift registers; wherein, the output terminal of the i-th stage shift register is connected to the input terminal of the (i+n)-th stage shift register; the output terminal of the (i+n+2j)-th stage shift register is connected to the reset terminal of the i-th stage shift register; j is greater than or equal to 1; the plurality of gate lines are arranged sequentially along the column direction, and the plurality of first gate lines and the plurality of second gate lines are alternately arranged; among the N cascaded shift registers, the shift registers are electrically connected to the gate lines; the plurality of shift registers are arranged along the column direction; A first voltage signal line is disposed on one side of the gate driving circuit along the row direction; each shift register includes a plurality of transistors, at least one of which is electrically connected to the first voltage signal line; the plurality of transistors includes a reset transistor and a plurality of noise reduction transistors, and the shift register also includes an input transistor, the input transistor and the reset transistor being located away from the first voltage signal line relative to the noise reduction transistor; the display panel also includes an auxiliary first voltage signal line located on the other side of the gate driving circuit, the first voltage signal line and the auxiliary first voltage signal line being connected; the input transistor and the reset transistor are located closer to the auxiliary first voltage signal line relative to the noise reduction transistor; at least a portion of the reset transistors of the shift registers are connected to the auxiliary first voltage signal line via a first lead; The connection voltage signal line is located on the side of the last stage shift register of the gate drive circuit away from other shift registers. The first voltage signal line and the auxiliary first voltage signal line are connected through the connection voltage signal line, which extends along the row direction. The connection voltage signal line includes multiple electrically connected sub-signal lines.

2. The display panel of claim 1, wherein, The noise reduction transistor of the shift register is connected to the first voltage signal line via a second lead.

3. The display panel of claim 2, wherein, The plurality of noise reduction transistors include multiple groups of transistors, each group of transistors including two transistors; the second lead is located between the two transistors in each group of transistors. Two transistors in at least one group of transistors are staggered in the column direction.

4. The display panel of any one of claims 1-3, wherein, The area containing each shift register has a column dimension of 60μm to 100μm.

5. The display panel according to any one of claims 1 to 3, characterized in that, The display panel also includes: M clock signal lines are disposed on the side of the gate driving circuit away from the display area. The clock signal lines are electrically connected to the gate driving circuit. The i-th clock signal line is connected to the (Mm+i)-th shift register, where 1≤i≤M and i is a positive integer, 0≤m and m is a positive integer; (Mm+i)≤N. The starting position of the effective clock signal output by the i-th clock signal line is earlier than the starting position of the effective clock signal of the (i+1)-th clock signal line, where i+1≤M.

6. The display panel according to claim 5, characterized in that, Starting from the first clock signal line, each pair of adjacent clock signal lines forms a group. In each group of clock signal lines, the starting position of the effective clock signal transmitted by the second clock signal line is earlier than the starting position of the effective clock signal transmitted by the first clock signal line. The start position of the valid clock signal transmitted on the i-th clock signal line is earlier than the start position of the valid clock signal transmitted on the (i+2)-th clock signal line; i+2≤M.

7. The display panel according to claim 1, characterized in that, j=1； The two outermost data lines located in the row direction are the first data line and the second data line. The first data segment of the first data line is set between the first column sub-pixels and the second column sub-pixels, and the second data segment of the first data line is set on the side of the first column sub-pixels that is away from the multi-column sub-pixels. The first data segment of the second data line is located on the side of the F column sub-pixel that is far away from the multi-column sub-pixel, and the second data segment of the second data line is located between the (F-1) column sub-pixel and the F column sub-pixel.

8. The display panel according to claim 7, characterized in that, At least a portion of the data line connected to the pixel group is located between the first electrode group and the second electrode group of the pixel group; at least a portion of the data line is either the first data segment or the second data segment; The first electrode of the first transistor and the first electrode of the second transistor are both connected to the data line, the second electrode of the first transistor is connected to the first pixel electrode, and the second electrode of the second transistor is connected to the second pixel electrode; The first transistor has its first electrode pointing to its second electrode, and the direction parallel to the row direction is the first direction. The second transistor has its first electrode pointing to its second electrode, and the direction parallel to the row direction is the second direction. The first direction is opposite to the second direction.

9. The display panel according to claim 8, characterized in that, Both the first transistor and the second transistor include a gate, an active layer, and source and drain electrodes stacked sequentially. The source and drain electrodes include a first electrode and a second electrode. The orthographic projection of the active layer on the substrate falls within the orthographic projection of the gate on the substrate. At least a portion of the orthographic projections of the first electrode and the second electrode on the substrate fall within the orthographic projection of the active layer on the substrate. The orthographic projection of the first pole is U-shaped, and the opening of the first pole faces the second pole.

10. The display panel according to any one of claims 7 to 9, characterized in that, The first pixel electrode and the second pixel electrode are block electrodes, and the first common electrode and the second common electrode are strip electrodes. Both the first common electrode and the second common electrode include multiple slits. The aperture ratio of the first sub-pixel is equal to the aperture ratio of the second sub-pixel; The first electrode group includes a first domain region and a second domain region arranged along the column direction, and the second electrode group includes a third domain region and a fourth domain region arranged along the column direction. The aperture ratios of the first domain region, the second domain region, the third domain region and the fourth domain region are equal.

11. The display panel according to any one of claims 7 to 9, characterized in that, The display panel further includes: a first spacer disposed on the side of the first transistor away from the substrate, and a second spacer disposed on the side of the second transistor away from the substrate; The center of the orthographic projection of the first spacer on the substrate is offset by a first distance in a third direction relative to the center of the orthographic projection of the first transistor on the substrate, wherein the third direction is the direction in which the first transistor points to the second transistor; The center of the orthogonal projection of the second spacer on the substrate is offset by a second distance in a fourth direction relative to the center of the orthogonal projection of the second transistor on the substrate, the fourth direction being the direction in which the second transistor points to the first transistor.

12. The display panel according to claim 11, characterized in that, The first distance is equal to the second distance.

13. The display panel according to claim 12, characterized in that, The orthographic projection of the first spacer on the substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the substrate. The orthographic projection of the second spacer on the substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the substrate.

14. A driving method for a display panel, applied to the display panel as described in any one of claims 1 to 13, characterized in that, The display panel includes a plurality of sub-pixels arranged in an array on the substrate. The plurality of sub-pixels form a plurality of pixel groups. The plurality of pixel groups include a plurality of row pixel groups arranged along the column direction. Each row pixel group includes at least two pixel groups arranged along the row direction. Each row of pixels is positioned between the first and second gate lines of a gate line group and is electrically connected to the gate line group; the driving method includes: When the display panel displays the first set screen, the gate driving circuit outputs the first set of gate driving signals, and the plurality of row pixel groups are activated row by row under the scanning of the plurality of gate line groups. In each row pixel, the first sub-pixel electrically connected to the first gate line is activated before the second sub-pixel electrically connected to the second gate line.

15. The driving method for a display panel according to claim 14, characterized in that, Also includes: When the display panel displays the second setting screen, the gate driving circuit outputs the second gate driving signal, and the plurality of row pixel groups are activated row by row under the scanning of the plurality of gate line groups. In each row pixel, the second sub-pixel electrically connected to the second gate line is activated before the first sub-pixel electrically connected to the first gate line.

16. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 13.

17. The display device according to claim 16, characterized in that, The display device further includes M clock signal lines, the i-th clock signal line being connected to the (Mm+i)-th stage shift register, where 1≤i≤M and i is a positive integer, 0≤m and m is a positive integer; (Mm+i)≤N; The display device further includes a control chip, which is connected to the M clock signal lines and outputs clock signals to the M clock signal lines; The control chip is configured to, when detecting that the display panel displays a first set screen, output valid clock signals sequentially to the M clock signal lines in a first order, wherein the first order is 1, 2, 3, 4...M-1, M; and when detecting that the display panel displays a second set screen, output valid clock signals sequentially to the M clock signal lines in a second order, wherein the second order is 2, 1, 4, 3...M, M-1.

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