Memory controller with dummy channel support

Abstract

A data processor accesses a memory having a first dummy channel and a second dummy channel. The data processor includes: at least one memory access agent to generate a memory access request; a memory controller to selectively provide a memory command to the memory using the first dummy channel pipeline circuit and the second dummy channel pipeline circuit in response to the normalization request; and a data texture to selectively convert the memory access request to the normalized request for the first dummy channel and the second dummy channel.

Description

Background Art

[0001] Modern dynamic random access memory (DRAM) provides high memory bandwidth by increasing the data transfer speed on the bus connecting DRAM and one or more data processors such as graphics processing unit (GPU), central processing unit (CPU). DRAM is usually cheap and high-density, so that each device can integrate a large amount of DRAM. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards issued by the Joint Electron Device Engineering Council (JEDEC). Typically, several DDR DRAM chips are combined on a single printed circuit board substrate to form a memory module that can provide not only relatively high speed but also scalability.

[0002] Recently, a new type of memory called high bandwidth memory (HBM) has emerged. HBM promises to increase memory speed and bandwidth by integrating vertically stacked memory dies that allow a larger number of data signal lines and shorter signal traces to allow higher speed operation. An important feature of the newer HBM memory is the pseudo-channel mode. The pseudo-channel mode divides the channel into two separate sub-channels that operate semi-independently. The pseudo-channels share the command bus, but execute commands separately. Although the pseudo-channel mode will allow further flexibility, it poses a challenge for the memory controller to effectively schedule access within each pseudo-channel at a high command rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 illustrates, in block diagram form, a data processing system according to some embodiments;

[0004] Figure 2 A memory controller known in the prior art is illustrated in block diagram form according to some embodiments;

[0005] Figure 3 A block diagram is provided to illustrate a method that can be used according to some embodiments. Figure 1 a memory controller of a memory controller of a memory controller; and

[0006] Figure 4 A block diagram is provided to illustrate a method that can be used according to some embodiments. Figure 1 another memory controller of a memory controller.

[0007] In the following description, the same reference numerals are used in different drawings to indicate similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0008] A data processor for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes: at least one memory access agent for generating a memory access request; a memory controller for selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit to provide a memory command to the memory in response to a normalized request; and a data texture for selectively converting the memory access request into the normalized request for the first pseudo channel and the second pseudo channel.

[0009] The memory controller provides memory commands to a physical interface circuit of a memory having a first pseudo channel and a second pseudo channel. The memory controller includes a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, each of which includes: a front-end interface circuit for converting a normalized address into a decoded address of a decoded memory access request; a command queue coupled to the front-end interface circuit for storing the decoded memory access request; and an arbiter for selecting from the decoded memory access request from the command queue according to a predetermined criterion and providing the selected memory access request to its output.

[0010] A method for a data processor to provide a command to a memory having a first pseudo channel and a second pseudo channel, the method comprising generating a memory access request and a memory access response. The memory access request is selectively routed between an upstream port and a downstream port of a data texture. The memory access response is selectively routed between a downstream port and an upstream port of the data texture. The memory access request in the data texture is decoded according to one of a plurality of pseudo channels including the first pseudo channel and the second pseudo channel. A first memory access request of the first pseudo channel is decoded in a first decoding and command arbitration circuit, and a second memory access request of the second pseudo channel is decoded in a second decoding and command arbitration circuit independent of the first decoding and command arbitration circuit.

[0011] Figure 1 A data processing system 100 according to some embodiments is illustrated in block diagram form. The data processing system 100 includes a data processor in the form of a system on a chip (SOC) 110 and a memory 180 in the form of a low-power high-bandwidth memory version 3 (HBM3). In other embodiments, the memory 180 may be HBM, version four (HBM4) memory, or other memory types that implement pseudo channels. Many other components of an actual data processing system are typically present but are not relevant to understanding the present disclosure and are not shown for ease of illustration. Figure 1 Shown in.

[0012] SOC 110 typically includes a system management unit (SMU) 111, a system management network (SMN) 112, a central processing unit (CPU) core complex 120 labeled "CCX," a graphics controller 130 labeled "GFX," a real-time client subsystem 140, a memory / client subsystem 150, a data fabric 160, a memory channel 170, and a peripheral component interface express (PCIe) subsystem 190. As will be appreciated by one of ordinary skill in the art, SOC 110 may not have all of these elements present in every implementation, and may also have additional elements included therein.

[0013] The SMU 111 is bidirectionally connected to the major components in the SOC 110 through the SMN 112. The SMN 112 forms the control fabric of the SOC 110. The SMU 111 is a local controller that controls the operation of resources on the SOC 110 and synchronizes the communication between these resources. The SMU 111 manages the power-up sequencing of the various processors on the SOC 110, and controls a number of off-chip devices via reset, enable, and other signals. The SMU 111 includes one or more clock sources (not shown), such as a phase-locked loop (PLL), to provide clock signals to each of the components of the SOC 110. The SMU 111 also manages the power of the various processors and other functional blocks, and may receive measured power consumption values ​​from the CPU cores in the CPU core complex 120 and the graphics controller 130 to determine the appropriate P-state.

[0014] CPU core complex 120 includes a set of CPU cores, each of which is bidirectionally connected to SMU 111 via SMN 112. Each CPU core may be a single core that shares only a last level cache with other CPU cores, or may be combined with some but not all other cores in the cluster.

[0015] Graphics controller 130 is bidirectionally connected to SMU 111 via SMN 112. Graphics controller 130 is a high-performance graphics processing unit that can perform graphics operations such as vertex processing, fragment processing, shading, texture blending, etc. in a highly integrated and parallel manner. In order to perform its operations, graphics controller 130 needs to periodically access external memory. Figure 1 In the embodiment shown in , graphics controller 130 shares a common memory subsystem with the CPU cores in CPU core complex 120, an architecture known as a unified memory architecture. Because SOC 110 includes both a CPU and a GPU, it is also referred to as an accelerated processing unit (APU).

[0016] The real-time client subsystem 140 includes a set of real-time clients, such as representative real-time clients 142 and 143, and a memory management hub 141 labeled "MM Hub." Each real-time client is bidirectionally connected to the SMU 111 through the SMN 112, and is bidirectionally connected to the memory management hub 141. The real-time client can be any type of peripheral controller that requires periodic data movement, such as an image signal processor (ISP), an audio coder-decoder (codec), a display controller that renders and rasterizes objects generated by the graphics controller 130 for display on a monitor, etc.

[0017] The memory / client subsystem 150 includes a set of memory elements or peripheral controllers, such as representative memory / client devices 152 and 153, and a system and input / output hub 151 labeled "SYSHUB / IOHUB." Each memory / client device is bidirectionally connected to the SMU 111 through the SMN 112, and bidirectionally connected to the system and input / output hub 151. The memory / client device is a circuit that stores data or requires access to data in a non-cyclic manner, such as non-volatile memory, static random access memory (SRAM), external disk controllers such as a Serial Advanced Technology Attachment (SATA) interface controller, a Universal Serial Bus (USB) controller, a system management hub, etc.

[0018] The data fabric 160 is an interconnect that controls the flow of traffic in the SOC 110. The data fabric 160 is bidirectionally connected to the SMU 111 through the SMN 112, and is bidirectionally connected to the CPU core complex 120, the graphics controller 130, the memory management hub 141, and the system and input / output hub 151. The data fabric 160 includes a crossbar switch for routing memory-mapped access requests and responses between any of the various devices of the SOC 110. The data fabric includes a system memory map defined by the basic input / output system (BIOS) for determining the destination of memory access based on the system configuration, and a buffer for each virtual connection. In addition, it has a pseudo channel decoder circuit 161 for providing memory access requests to two downstream ports. The pseudo channel decoder circuit 161 has an input for receiving a memory access request including a multi-bit address labeled "address", a first output connected to the first downstream port and a second output connected to the second downstream port, and a control input for receiving an address bit labeled "PC".

[0019] The memory channel 170 is a circuit that controls data transfer to and from the memory 180. The memory channel 170 includes a last level cache 171 labeled “LLC0”, a last level cache 172 labeled “LLC1”, a memory controller 173, and a physical interface circuit 173 labeled “PHY” connected to the memory 180. The last level cache 171 is bidirectionally connected to the SMU 111 through the SMN 112, and has an upstream port and a downstream port connected to a first downstream port of the data fabric 160. The last level cache 172 is bidirectionally connected to the SMU 111 through the SMN 112, and has an upstream port and a downstream port connected to a second downstream port of the data fabric 160. The memory controller 173 has a first upstream port connected to the downstream port of the last level cache 171, a second upstream port connected to the downstream port of the last level cache 172, a first downstream port, and a second downstream port. The physical interface circuit 174 has a first upstream port bidirectionally connected to a first downstream port of the memory controller 173 , a second upstream port bidirectionally connected to a second downstream port of the memory controller 173 , and a downstream port bidirectionally connected to the memory 181 . The downstream port of the physical interface circuit 174 complies with the HBM3 standard and includes a set of differential pairs of command clock signals for each channel and / or pseudo channel, collectively labeled as "CK"; a set of differential pairs of write data select signals for each channel and / or pseudo channel, collectively labeled as "WDQS"; a set of differential pairs of read data select signals for each channel and / or pseudo channel, collectively labeled as "RDQS"; a set of row command signals for each channel and / or pseudo channel, collectively labeled as "ROW COM"; a set of column command signals for each channel and / or pseudo channel, collectively labeled as "COL COM"; a set of data signals for pseudo channel 0 of each channel, labeled as "DQ[31:0]"; and a set of data signals for pseudo channel 1 of each channel, labeled as "DQ[63:32]".

[0020] The peripheral component interface express (PCIe) subsystem 190 includes a PCIe controller 191 and a PCIe physical interface circuit 192. The PCIe controller 191 is bidirectionally connected to the SMU 111 through the SMN 112, and has an upstream port bidirectionally connected to the system and the input / output hub 151 and a downstream port. The PCIe physical interface circuit 192 has an upstream port bidirectionally connected to the PCIe controller 191 and a downstream port bidirectionally connected to the PCIe fabric ( Figure 1 The PCIe controller 191 can form a PCIe root complex of a PCIe system for connecting to a PCIe network including a PCIe switch, a router, and a device.

[0021] In operation, SOC 110 integrates a complex variety of computing and storage devices on a single chip, including CPU core complex 120 and graphics controller 130. Most of these controllers are well known and will not be discussed further. SOC 110 includes multiple internal buses for conducting data at high speed between these circuits. For example, CPU core complex 120 accesses data on a high-speed 32-bit bus through the upstream port of data texture 160. Data texture 160 multiplexes access between any memory access agent in a plurality of memory access agents connected to its upstream port and a memory access responder connected to its downstream port. Due to the large number of memory access agents and memory access responders, the number of internal bus lines is also quite large, and the crossbar switch in data texture 160 multiplexes these wide buses to form a virtual connection between a memory access requester and a memory access responder.

[0022] The various processing nodes also maintain their own cache hierarchies. In a typical configuration, the CPU core complex 120 includes four CPU cores, each with its own private level 1 (L1) and level 2 (L2) caches, and with a level 3 (L3) cache shared between the four CPU cores in the cluster. In this example, the last level caches 171 and 172 will form a level 4 (L4) cache, but regardless of the internal organization of the cache hierarchy in the CPU core complex 120, the level 4 cache operates as the last level cache in the cache hierarchy. In one example, the last level caches 171 and 172 implement inclusive caches, where any cache line stored in any higher level cache in the SOC 110 will also be stored in the last level caches 171 and 172. In another example, last level caches 171 and 172 are victim caches and include cache lines, each of which contained data requested by a data processor at an earlier point in time but eventually became the least recently used cache lines and were evicted from all upper level caches.

[0023] The data processing system 100 uses HBM3, which is currently a new and emerging memory type that provides an opportunity to increase memory bandwidth over other types of DDR SDRAM. HBM uses vertically stacked memory dies that communicate using short through-silicon via (TSV) technology, which shortens the physical distance between the processor and the memory and enables faster operating speeds through a larger bus width. In particular, HBM3 supports "pseudo-channels", allowing different parts of the memory die to be accessed independently using independent data paths with common command and address paths. Since command signals and address signals are provided at a lower frequency than data signals, command and address information can be sent from a memory controller to an HBM3 memory stack between two pseudo-channels in an interleaved manner. In other embodiments, the data processing system 100 can use HBM, version four (HBM4) memory, or other memory types that implement pseudo-channels.

[0024] As will be further explained below, the SOC 110 uses an architecture in which the data texture 160 is pseudo-channel aware. For example, in one embodiment, the physical address provided by a memory access agent such as the CPU core complex 120 or the graphics controller 130 is mapped to different pseudo-channels based on a single address bit. Due to this feature, the data texture 160 can separate accesses based on the pseudo-channel accessed by examining a single bit of the physical address and routing (demultiplexing) it to a specific downstream port based on the pseudo-channel accessed. The memory controller 173 receives the normalized address that does not include the PC bit on the corresponding port of its upstream port.

[0025] This pseudo-channel awareness allows the memory controller 173 to select accesses for each pseudo-channel independently, thereby reordering and prioritizing accesses based on the specific access patterns in each pseudo-channel. Prioritization can be achieved by using an arbiter for each pseudo-channel using the same arbitration rules, and thus arbitration and other circuits associated with each pseudo-channel can be easily replicated without requiring redesign.

[0026] The physical interface circuit 174 then receives the access on the upstream port corresponding to the different timing time slots and provides it to the HBM3 die in a deserialized manner using the pseudo channel interleaving of HBM3. As will be explained below, deserialization can occur in Figure 1 The PHY 174 is shown, or may occur in the memory controller 173.

[0027] Figure 2A memory controller 200 known in the art is illustrated in block diagram form. The memory controller 200 includes a memory channel controller 210 and a power controller 250. The memory channel controller 210 includes an interface 212, a queue 214, a command queue 220, an address generator 222, a content addressable memory (CAM) 224, a replay queue 230, a refresh logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check block 242, an ECC generation block 244, and a data buffer (DB) 246.

[0028] Interface 212 has a first bidirectional connection to the data fabric through an external bus and has an output. In memory controller 200, the external bus is compatible with Advanced eXtensible Interface version four (referred to as AXI4) specified by ARM Holdings, PLC of Cambridge, England, but may be other types of interfaces in other embodiments. Interface 212 converts memory access requests from a first clock domain referred to as the FCLK (or MEMCLK) domain to a second clock domain referred to as the UCLK domain internal to memory controller 200. Similarly, queue 214 provides memory access from the UCLK domain to the DFICLK domain associated with the DFI interface.

[0029] The address generator 222 decodes the address of the memory access request received from the data texture via the AXI4 bus. The memory access request includes an access address represented as a normalized address in the physical address space. The address generator 222 converts the normalized address into a format that can be used to address the actual memory device in the memory system and efficiently schedule the related access. The format includes a region identifier that associates the memory access request with a specific storage column, row address, column address, storage body address, and storage body group. At startup, the system BIOS queries the memory devices in the memory system to determine their size and configuration, and programs a set of configuration registers associated with the address generator 222. The address generator 222 uses the configuration stored in the configuration register to convert the normalized address into an appropriate format. The command queue 220 is a queue of memory access requests received from a memory access agent in the data processing system 100, such as a CPU core in the CPU core complex 120 and a graphics controller 130. Command queue 220 stores address fields decoded by address generator 222 and other address information, including access type and quality of service (QoS) identification, that allows arbiter 238 to efficiently select memory accesses. CAM 224 includes information that implements ordering rules such as write-before-write (WAW) and read-before-write (RAW) ordering rules.

[0030] The replay queue 230 is a temporary queue for storing memory accesses selected by the arbiter 238 that are waiting for responses, such as address and command parity responses, write cyclic redundancy check (CRC) responses for DDR4 DRAM, or write and read CRC responses for GDDR5 DRAM. The replay queue 230 accesses the ECC check block 242 to determine whether the returned ECC is correct or indicates an error. The replay queue 230 allows the access to be replayed in the event of a parity or CRC error in one of these cycles.

[0031] The refresh logic block 232 includes state machines for various power-down, refresh, and terminal resistance (ZQ) calibration cycles that are generated separately from normal read and write memory access requests received from the memory access agent. For example, if a memory storage column is in a pre-charge power-down, the memory storage column must be periodically awakened to run a refresh cycle. The refresh logic block 232 periodically generates automatic refresh commands to prevent data errors caused by charge leakage from the storage capacitors of the memory cells in the DRAM chip. In addition, the refresh logic block 232 periodically calibrates the ZQ to prevent mismatches in on-chip terminal resistances due to thermal variations in the system. The refresh logic block 232 also decides when to place the DRAM devices in different power-down modes.

[0032] The arbiter 238 is bidirectionally connected to the command queue 220 and is the core of the memory channel controller 210. The arbiter improves efficiency by intelligently scheduling accesses to improve the utilization of the memory bus. The arbiter 238 uses the timing block 234 to enforce the correct timing relationship by determining whether certain accesses in the command queue 220 are eligible to be issued based on the DRAM timing parameters. For example, each DRAM has a minimum specified time between activation commands to the same memory bank, called "t RC ". The timing block 234 maintains a set of counters that determine eligibility based on the timing parameters and other timing parameters specified in the JEDEC specification, and the timing block is bidirectionally connected to the replay queue 230. The page table 236 maintains status information about the active pages in each memory bank and memory column of the memory channel of the arbiter 238, and is bidirectionally connected to the replay queue 230.

[0033] In response to receiving a write memory access request from interface 212, ECC generation block 244 calculates ECC based on the write data. DB 246 stores the write data and ECC of the received memory access request. When arbiter 238 selects the corresponding write access for dispatching to the memory channel, the data buffer outputs the combined write data / ECC to queue 214.

[0034] The power controller 250 includes an interface 252 to the Advanced eXtensible Interface version one (AXI), an APB interface 254, and a power engine 260. The interface 252 has a first bidirectional connection to the SMN, which includes an input for receiving an event signal labeled "EVENT_n" shown separately in Figure 5, and an output. The APB interface 554 has an input connected to the output of the interface 252, and an output for connecting to the PHY via the APB. The power engine 260 has an input connected to the output of the interface 252, and an output connected to the input of the queue 214. The power engine 260 includes a set of configuration registers 262, a microcontroller (μC) 264, a self-refresh controller (SLFREF / PE) 266, and a reliable read / write training engine (RRW / TE) 268. The configuration registers 262 are programmed via the AXI bus and store configuration information to control the operation of various blocks in the memory controller 200. Therefore, the configuration registers 262 have outputs connected to these blocks, which are in Figure 2 The self-refresh controller 266 is an engine that allows refreshes to be manually generated in addition to the refreshes automatically generated by the refresh logic block 232. The reliable read / write training engine 268 provides a continuous memory access stream to the memory or I / O device for purposes such as DDR interface read latency training and loopback testing.

[0035] The memory channel controller 210 includes circuits that allow it to select memory accesses for scheduling to the associated memory channel. In order to make the desired arbitration decision, the address generator 222 decodes the address information into pre-decoding information, which includes the storage column, row address, column address, memory bank address and memory bank group in the memory system, and the command queue 220 stores the pre-decoding information. The configuration register 262 stores the configuration information to determine the manner in which the address generator 222 decodes the received address information. The arbitrator 238 uses the decoded address information, the timing condition information indicated by the timing block 234, and the active page information indicated by the page table 236 to efficiently schedule memory accesses while complying with other criteria such as QoS requirements. For example, the arbitrator 238 implements priority access to open pages to avoid the overhead of precharging and activating commands required to change memory pages, and hides the overhead access to one memory bank by interleaving the overhead access to one memory bank with the read and write access to another memory bank. In particular, during normal operation, the arbitrator 238 may decide to keep pages open in different memory banks until the pages need to be precharged, and then select different pages.

[0036] Figure 3 A block diagram is provided to illustrate a method that can be used according to some embodiments. Figure 1The memory controller 300 is a memory controller of the memory controller 173. The memory controller 300 generally includes a front-end interface stage 310, a DRAM command queue stage 320, an arbiter stage 330, a back-end queue stage 340, and a refresh logic circuit 350. The memory controller 300 includes a similar Figure 2 Other elements are shown in FIG. 1 , but those circuit blocks are not important to understanding the disclosed embodiments and will not be described further.

[0037] Front-end interface stage 310 is a circuit including front-end interface circuits 311 and 312, each labeled "FEI". Front-end interface circuit 311 has an upstream port connected to the first downstream port of data fabric 160 and a downstream port. Figure 3 In an embodiment of the present invention, the upstream port uses an interface called a scalable data port (SDP), and therefore the upstream port is labeled "SDP PC0", and the downstream port makes memory access requests for pseudo channel 0, and therefore is labeled "PC0". The front-end interface circuit 312 has an upstream port connected to a second downstream port of the data fabric 160 labeled "SDP PC1", and a downstream port labeled "PC1".

[0038] DRAM command queue stage 320 is a circuit that includes DRAM command queues 321 and 322, each labeled “DCQ.” DRAM command queue 321 has an upstream port connected to a downstream port of front-end interface circuit 311, and a downstream port similarly labeled “PC0.” DRAM command queue 322 has an upstream port connected to a downstream port of front-end interface circuit 312, and a downstream port similarly labeled “PC1.”

[0039] Arbiter stage 330 is a circuit including arbiters 331 and 332, each labeled “ARB”, and a pseudo channel arbiter 333 labeled “PCARB”. Arbiter 331 has a first upstream port connected to the downstream port of DRAM command queue 321, a second upstream port, and a downstream port similarly labeled “PC0”. Arbiter 332 has a first upstream port connected to the downstream port of DRAM command queue 322, a second upstream port, and a downstream port similarly labeled “PC1”. Pseudo channel arbiter 333 has a first upstream port connected to the downstream port of arbiter 331, a second upstream port connected to the downstream port of arbiter 332, a first downstream port labeled “Time Slot 0”, and a second downstream port labeled “Time Slot 1”.

[0040] The back-end queue stage 340 is a circuit including back-end queues 341 and 342, each labeled "BEQ", and command replay queues 343 and 344, each labeled "REC". The back-end queue 341 has a first upstream port connected to the first downstream port of the pseudo channel arbiter 333, a second upstream port, and a downstream port connected to the physical interface circuit 174, for providing a signal for the first phase labeled "Phase 0". The back-end queue 342 has a first upstream port connected to the second downstream port of the pseudo channel arbiter 333, a second upstream port, and a downstream port connected to the physical interface circuit 174, for providing a signal for the second phase labeled "Phase 1". The command replay queue 343 has a downstream port bidirectionally connected to the second upstream port of the back-end queue 341. The command replay queue 344 has a downstream port bidirectionally connected to the second upstream port of the back-end queue 342.

[0041] The refresh logic circuit 350 has a first output connected to the second upstream port of the arbiter 331, and a second output connected to the second upstream port of the arbiter 332. Figure 3 In the embodiment shown in , the refresh logic circuit 350 generates refresh access to each of the arbiters 331 and 332 based on the requirements of the memory 180. The refresh logic circuit 350 includes state machines for various power-down, refresh and terminal resistance (ZQ) calibration cycles, which are generated separately from the normal read and write memory access requests received from the memory access agent. For example, if the memory is in pre-charge power-down, the memory must be periodically awakened to run the refresh cycle. The refresh logic circuit 350 periodically generates automatic refresh commands to prevent data errors caused by charge leakage from the storage capacitors of the memory cells in the DRAM chip. In addition, the refresh logic circuit 350 periodically calibrates the ZQ to prevent mismatches of on-chip terminal resistances due to thermal changes in the system. The refresh logic circuit 350 also determines when to place the DRAM device in different power-down modes. In other embodiments, the memory controller 300 may include a separate refresh logic block for each pseudo channel.

[0042] The memory controller 300 utilizes the capability of the data texture 160 to identify the pseudo-channels accessed and separate the requests. The memory controller 300 implements a parallel pseudo-channel pipeline that receives normalized requests from the data texture 160. Each normalized request includes a normalized address of a physical address space associated with a particular pseudo-channel. Each of the parallel pseudo-channel pipelines decodes its corresponding normalized address to map the normalized request to its own physical address space without considering the pseudo-channel bits of the memory access request. Therefore, the front-end interface circuit 311, the command queue 321, and the arbiter 331 form a pseudo-channel pipeline circuit for PC0, and the front-end interface circuit 312, the command queue 322, and the arbiter 332 form a pseudo-channel pipeline circuit for PC1.

[0043] The memory controller 300 operates according to the UCLK signal. In some embodiments, the UCLK signal is half the frequency of the MEMCLK signal. For example, in some embodiments, the UCLK signal is 1 gigahertz (1 GHz), while the MEMCLK signal is 2 GHz. This slower UCLK speed allows the arbiters 331 and 332 to resolve timing dependencies and eligibility during a single UCLK cycle. The arbiters 331 and 332 reorder accesses for efficiency using normal standards during each UCLK cycle so that the back-end queues 341 and 342 can send commands for both PC0 and PC1 in the same UCLK cycle, respectively. In the case of an activation (ACT) command, the corresponding back-end queues extend the commands of the two phases. Therefore, if the ACT command is issued from phase 1, phase 0 of the next command cycle cannot be filled with any command.

[0044] The memory controller 300 adds a special pseudo-channel arbiter 333 that arbitrates between requests for pseudo-channels to identify the best access pattern based on the minimum timing required by the memory. The pseudo-channel arbiter 333 takes into account the timing constraints in each pseudo-channel and prioritizes access into one of the two command timing slots. Arbiters 331 and 332 indicate which phase of the MEMCLK signal the command will be on. For example, if the activate to read command (ACT to RD) time is met on an odd number of clocks and the ACT command starts in phase 0, the pseudo-channel arbiter 333 issues RD from phase 1. If a conflict occurs, a different pseudo-channel than the previous winner of the pseudo-channel arbitration will be adopted. The back-end queues 341 and 342 then send commands to the physical interface circuit 174 to multiplex them on the HBM3 command bus based on the selected phase of the UCLK signal based on its time slot.

[0045] The memory controller 300 implements shared circuit blocks for special operations. For example, the refresh logic 350 that controls the power-down, refresh, and ZQ calibration cycles is shared between the two pseudo-channel pipelines for efficiency. Similarly, the register file and other blocks ( Figure 3 343 and 344 are shared between pseudo channels. However, each of the command replay queues 343 and 344 is dedicated to a specific pseudo channel and sends replays in dedicated command time slots. The command replay queues 343 and 344 only support dependent replays, and in response to the replays, the command replay queues stop read and write operations in the two pseudo channels and in the power controller shared between the channels.

[0046] The physical interface circuit 174 serializes the two inputs received in one UCLK cycle to the higher MEMCLK rate.

[0047] By running parallel pipelines, the memory controller 300 operates at the slower speed required to resolve arbitration decisions and uses a lower supply voltage to reduce power consumption, but adds an acceptable die area increase.

[0048] Figure 4 A block diagram is provided to illustrate a method that can be used according to some embodiments. Figure 1 Another memory controller 400 of the memory controller 173. The memory controller 400 and Figure 3 The memory controller 300 is constructed in the same manner except that it additionally has a serializer 410 based on Figure 1 The pseudo channel arbiter 333 of the memory controller 400 provides memory commands to the physical interface circuit 174 based on serialized access to the first command phase (referred to as phase 0) and the second command phase (referred to as phase 1) based on the reordering of pseudo channel requests. The memory controller 400 will be useful if the interface between the memory controller 173 and the physical interface circuit 174 is standardized to include a serialized pseudo channel access mode. For example, a specification called the DDR-PHY Interface (DFI) specification has been published by Cadence Design Systems, Inc. and allows memory controller and PHY designs to be reused between different integrated circuit manufacturers. If a future DFI standard assumes that pseudo channel interleaving is already performed by the memory controller, the memory controller 400 will accommodate interoperability with the future DFI standard.

[0049] The data processors, SOCs, memory controllers, and portions thereof described herein may be embodied as one or more integrated circuits, any of which may be described or represented by a computer-accessible data structure in the form of a database or other data structure that may be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to produce a data set describing a geometric shape to be applied to a mask. The mask may then be used in various semiconductor manufacturing steps to produce an integrated circuit. Alternatively, the database on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set (as required) or a Graphic Data System (GDS) II data.

[0050] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, pseudo-channel aware data textures can decode a single address bit to divide accesses into different pseudo-channels, or decode more complex memory mapping functions. The memory controller can use the same arbitration rules for each pseudo-channel to simplify the design, or allow different access processing for two pseudo-channels. The memory controller can perform separate arbitration in each pseudo-channel, but then reorder the output of each pseudo-channel based on timing eligibility criteria to improve the utilization of the pseudo-channel bus. Refresh logic and associated non-memory access functions can be merged into a single refresh logic block for all pseudo-channels, or separated into similar blocks for each pseudo-channel. In addition, serialization of access can occur in the PHY or the memory controller.

[0051] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A data processor for accessing a memory having a first pseudo channel and a second pseudo channel, the data processor comprising: at least one memory access agent, the at least one memory access agent being configured to generate a memory access request; a memory controller for selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit to provide a memory command to the memory in response to a normalization request; and A data texture is used to selectively convert the memory access request into the normalized request for the first pseudo channel and the second pseudo channel.

2. A data processor according to claim 1, wherein: The data fabric converts the memory access request into the normalized request by decoding the memory access request into pseudo channel bits and a normalized address, and provides the normalized address to a selected one of the first pseudo channel pipeline circuit and the second pseudo channel pipeline circuit.

3. The data processor according to claim 2, wherein the data texture comprises: a pseudo channel decoder circuit that routes a memory access request to the first pseudo channel pipeline circuit in response to predetermined bits of an access address being in a first logic state, and routes the memory access request to the second pseudo channel pipeline circuit in response to the predetermined bits of the access address being in a second logic state.

4. The data processor according to claim 1, wherein: The second pseudo channel pipeline circuit operates independently of the first pseudo channel pipeline circuit.

5. The data processor of claim 4 , wherein each of the first pseudo channel pipeline circuit and the second pseudo channel pipeline circuit comprises: a front-end interface circuit coupled to the data texture for converting a normalized address into a decoded address of a decoded memory access request; a command queue, the command queue being coupled to the front-end interface circuit and configured to store the decoded memory access request; and An arbiter is configured to select from the decoded memory access requests from the command queue according to predetermined criteria and provide the selected memory access request to an output thereof.

6. The data processor of claim 5, wherein the arbiter of the first pseudo channel pipeline circuit uses substantially the same criteria as the arbiter of the second pseudo channel pipeline circuit.

7. The data processor according to claim 5, wherein the memory controller further comprises: A pseudo channel arbiter for selecting between outputs of the arbiter of each of the first pseudo channel pipeline circuit and the second pseudo channel pipeline circuit and providing a memory access command to a first phase output of a first phase and a second phase output of a second phase based on memory access timing eligibility.

8. The data processor of claim 7 , further comprising a physical interface circuit having a first phase input coupled to the first phase output of the pseudo channel arbiter and a second phase input coupled to the second phase output of the pseudo channel arbiter, and an output coupled to the memory, wherein the physical interface circuit serializes a first memory access command of the first phase and a second memory access command of the second phase on a common command bus for two pseudo channels.

9. The data processor according to claim 7, further comprising: a first backend queue for the first phase, the first backend queue having a first input coupled to the first phase output of the pseudo channel arbiter, a second input for receiving a replay command for the first pseudo channel, and an output; and A second backend queue for the second phase has a first input coupled to the second phase output of the pseudo channel arbiter, a second input for receiving a replay command for the second pseudo channel, and an output.

10. The data processor according to claim 5, wherein: the front end interface circuit, the command queue, and the arbiter of each of the first decode and command arbitration circuit and the second decode and command arbitration circuit operate according to a memory controller clock signal; and A physical interface circuit provides the memory command to the memory using a memory clock signal, wherein the memory clock signal has a higher frequency than the memory controller clock signal.

11. A memory controller for providing a memory command to a physical interface circuit of a memory having a first pseudo channel and a second pseudo channel, the memory controller comprising: A first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, wherein the first pseudo channel pipeline circuit and the second pseudo channel pipeline circuit each include: A front-end interface circuit for converting a normalized address into a decoded address of a decoded memory access request; a command queue, coupled to the front-end interface circuit, for storing the decoded memory access requests; and An arbiter is configured to select from the decoded memory access requests from the command queue according to predetermined criteria and provide the selected memory access request to an output thereof.

12. The memory controller according to claim 11, further comprising: A back-end queue stage has a first back-end queue for a first phase of a command bus to the memory and a second back-end queue for a second phase of the command bus to the memory.

13. The memory controller of claim 12, wherein: Each of the first backend queue and the second backend queue has a first input for receiving a playback command of a corresponding one of the first pseudo channel and the second pseudo channel.

14. The memory controller of claim 12, wherein: The front-end interface circuit, the command queue, and the arbitrator of each of the first pseudo channel and the second pseudo channel operate according to a memory controller clock signal, and wherein the back-end queue receives a memory access command from the arbitrator using the memory controller clock signal, and provides the memory access command to the first phase input and the second phase input of the physical interface circuit using a memory clock signal, wherein the memory clock signal has a higher frequency than the memory controller clock signal.

15. The memory controller according to claim 12, further comprising: A serializer having a first input coupled to the output of the first back-end queue, a second input coupled to the output of the second back-end queue, and an output coupled to the first input of the physical interface circuit.

16. The memory controller of claim 12, wherein: The first backend queue has an output coupled to a first input of the physical interface circuit; and The second back-end queue has an output coupled to a second input of the physical interface circuit, wherein the physical interface circuit serializes the output of the first back-end queue and the output of the second back-end queue before providing the memory access commands for the first pseudo channel and the second pseudo channel to the memory.

17. A method for a data processor to provide a command to a memory having a first pseudo channel and a second pseudo channel, the method comprising: generating a memory access request; selectively routing the memory access request between an upstream port and a downstream port of a data fabric, and selectively routing a memory access response between the downstream port and the upstream port of the data fabric; decoding the memory access request in the data fabric according to one of a plurality of pseudo channels including a first pseudo channel and a second pseudo channel; processing a first memory access request of the first pseudo channel in a first decoding and command arbitration circuit; as well as A second memory access request of the second pseudo channel is processed in a second decode and command arbitration circuit independent of the first decode and command arbitration circuit.

18. The method according to claim 17, further comprising: The outputs of the first decode and command arbitration circuit and the second decode and command arbitration circuit are selectively arbitrated onto a first phase port and a second phase port based on a memory timing standard.

19. The method according to claim 18, comprising: The commands from the first phase port and the second phase port are combined onto a physical interface of the memory using a physical interface circuit.

20. The method according to claim 19, comprising: The first memory access request of the first pseudo channel and the second memory access request of the second pseudo channel are processed at a memory controller clock rate, and the physical interface circuit is operated at a memory clock rate, wherein the memory clock rate is higher than the memory controller clock rate.

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