Vector decimation and merge instructions

Abstract

An apparatus, method and medium are provided. The apparatus includes decoder circuitry to generate a control signal in response to a vector decimation and merge instruction specifying a control parameter, a first vector register, a second vector register, and a destination vector register. The apparatus includes processing circuitry to perform a plurality of processing beats in response to the control signals, each beat including processing corresponding to at least portions of the first vector register and the destination vector register. For a Kth beat, the processing includes extracting bits specified by the control parameter from a Kth portion of the first vector register, cascading the bits with further bits, and storing a result in a Kth portion of the destination register. For a first portion, the further bits are extracted from a first portion of the second vector register, otherwise from a (K-1)-th portion of the first vector register.

Description

[0001] The present technology relates to an apparatus, a method of operating the apparatus, and a computer-readable medium for storing a computer-readable code for manufacturing the apparatus.

[0002] Some data processing systems support processing of vector instructions, where the source operand or result value of the instruction is a vector comprising multiple parts. By supporting the processing of several distinct parts of a vector in response to a single instruction, code density can be improved and the burden of fetching and decoding instructions can be reduced. Sometimes, it is desirable that a vector instruction be executed where the parts of the vector are dependent on each other.

[0003] According to some configurations, there is provided an apparatus comprising:

[0004] Multiple vector registers;

[0005] a decoder circuit that generates a control signal in response to a vector extract and merge instruction that specifies a control parameter and specifies the first source vector register, the second source vector register, and the destination vector register as designated registers of the plurality of vector registers; and

[0006] a processing circuit that executes a plurality of processing beats in response to the control signals, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, wherein the processing circuit is configured to set beat status information indicating which beats of the vector extract and merge instruction have been completed, and suppress the completed beats of the vector extract and merge instruction indicated as completed by the beat status information,

[0007] The combined processing of the Kth beat of the Kth part corresponding to each of the designated registers includes:

[0008] extracting bits as specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more further bits, and storing the result of the concatenation in the Kth portion of the destination register;

[0009] When the Kth portion is not the last portion of the designated registers, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register for processing in a (K+1)th beat of the plurality of beats;

[0010] For the first portion of the specified registers, the one or more additional bits are extracted from the first portion of the second source vector register; and

[0011] For each portion other than the first portion of the specified registers, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

[0012] According to some configurations, there is provided a method of operating an apparatus including a plurality of vector registers, a decoder circuit, and a processing circuit, the method comprising:

[0013] generating control signals using the decoder circuit and in response to a vector extract and merge instruction that specifies control parameters and specifies a first source vector register, a second source vector register, and a destination vector register as designated registers of the plurality of vector registers; and

[0014] executing a plurality of processing beats using the processing circuit and in response to the control signals, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, setting beat status information indicating which beats of the vector extract and merge instruction have been completed, and suppressing the completed beats of the vector extract and merge instruction indicated as completed by the beat status information,

[0015] The combined processing of the Kth beat of the Kth part corresponding to each of the designated registers includes:

[0016] extracting bits specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more further bits, and storing the result of the concatenation in the Kth portion of the destination register;

[0017] When the Kth portion is not the last portion of the designated registers, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register for processing in a (K+1)th beat of the plurality of beats;

[0018] For the first portion of the specified registers, the one or more additional bits are extracted from the first portion of the second source vector register; and

[0019] For each portion other than the first portion of the specified registers, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

[0020] According to some configurations, there is provided a computer readable medium for storing a computer readable code for manufacturing an apparatus, the apparatus comprising:

[0021] Multiple vector registers;

[0022] a decoder circuit that generates a control signal in response to a vector extract and merge instruction that specifies a control parameter and specifies the first source vector register, the second source vector register, and the destination vector register as designated registers of the plurality of vector registers; and

[0023] a processing circuit that executes a plurality of processing beats in response to the control signals, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, wherein the processing circuit is configured to set beat status information indicating which beats of the vector extract and merge instruction have been completed, and suppress the completed beats of the vector extract and merge instruction indicated as completed by the beat status information,

[0024] The combined processing of the Kth beat of the Kth part corresponding to each of the designated registers includes:

[0025] extracting bits specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more further bits, and storing the result of the concatenation in the Kth portion of the destination register;

[0026] When the Kth portion is not the last portion of the designated registers, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register for processing in a (K+1)th beat of the plurality of beats;

[0027] For the first portion of the specified registers, the one or more additional bits are extracted from the first portion of the second source vector register; and

[0028] For each portion other than the first portion of the specified registers, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

[0029] In some configurations, the computer readable medium is a non-transitory computer readable medium.

[0030] According to some configurations, there is provided a computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising:

[0031] a register logic unit, the register logic unit comprising a plurality of vector registers;

[0032] a decoder logic unit that generates a control signal in response to a vector extract and merge instruction that specifies a control parameter and specifies the first source vector register, the second source vector register, and the destination vector register as designated registers of the plurality of vector registers; and

[0033] a processing logic unit that executes a plurality of processing beats in response to the control signals, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, wherein the processing logic unit is configured to set beat status information indicating which beats of the vector extract and merge instruction have been completed, and to suppress the completed beats of the vector extract and merge instruction indicated as completed by the beat status information,

[0034] The combined processing of the Kth beat of the Kth part corresponding to each of the designated registers includes:

[0035] extracting bits specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more further bits, and storing the result of the concatenation in the Kth portion of the destination register;

[0036] When the Kth portion is not the last portion of the designated registers, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register for processing in a (K+1)th beat of the plurality of beats;

[0037] For the first portion of the specified registers, the one or more additional bits are extracted from the first portion of the second source vector register; and

[0038] For each portion other than the first portion of the specified registers, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

[0039] In some configurations, the computer program is recorded on a non-transitory computer readable medium.

[0040] The present technology will be further described, by way of example only, with reference to the configuration thereof as shown in the accompanying drawings, in which:

[0041] Figure 1 Schematically illustrating a data processing device supporting processing of vector instructions according to various configurations of the present technology;

[0042] Figure 2 schematically illustrates examples of overlapping execution of vector instructions according to various configurations of the present technology;

[0043] Figure 3schematically illustrates three examples of scaling the amount of overlap between consecutive vector instructions at runtime between different processor implementations or between different instruction execution scenarios according to various configurations of the present technology;

[0044] Figure 4 Schematically illustrating example encoding of beat status information for indicating which beats of a block of multiple vector instructions have been completed according to various configurations of the present technology;

[0045] Figure 5 Schematically illustrating two examples of recording beat status information when a debug event or exception occurs according to various configurations of the present technology;

[0046] Figure 6 schematically illustrates an example of using beat status information to resume processing after returning from a debug event or exception according to various configurations of the present technology;

[0047] Figure 7 Schematically illustrating a data processing device according to various configurations of the present technology;

[0048] Figure 8 Schematically illustrating a data processing device according to various configurations of the present technology;

[0049] Fig. 9 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0050] Fig.10 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0051] Fig.11 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0052] Fig.12 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0053] Fig.13 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0054] Fig.14 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0055] Fig.15 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0056] Fig.16 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0057] Fig.17 schematically illustrates examples of vector extract and merge instructions according to various configurations of the present technology;

[0058] Fig.18 schematically illustrates a series of steps performed by an apparatus according to various configurations of the present technology;

[0059] Fig.19 schematically illustrates apparatus according to various configurations of the present technology; and

[0060] Fig. 20 A simulator that may be used according to some example configurations is schematically shown.

[0061] Software written according to a given instruction set architecture can be executed on a series of different data processing devices with different hardware implementations. As long as a given instruction set gives the expected results of the architecture when executed, a specific implementation is free to use any method that can achieve compliance with this architecture to change its micro-architecture design. For example, for some applications, energy efficiency may be more important than performance, and therefore the micro-architecture design of the processing circuit provided for executing instructions from the instruction set architecture can be designed to consume as little energy as possible even at the expense of performance. Other applications may regard performance as a more important criterion than energy efficiency, and therefore may include more complex hardware structures, which realize larger instruction throughput, but it may consume more power. Therefore, it may be desirable to design an instruction set architecture so that it supports scaling across a series of different energy or performance points.

[0062] In some configurations, a device is provided, the device comprising: a plurality of vector registers; and a decoder circuit that generates a control signal in response to a vector extract and merge instruction. The vector extract and merge instruction specifies a control parameter and specifies a first source vector register, a second source vector register, and a destination vector register as designated registers of the plurality of vector registers. The device also includes a processing circuit that performs a plurality of processing beats in response to the control signals. Each beat includes a combined process corresponding to a portion of at least the first source vector register and the destination vector register. The processing circuit is configured to set a beat status information indicating which beats of the vector extract and merge instruction have been completed, and suppress the completed beats of the vector extract and merge instruction indicated as completed by the beat status information. The combined process of the Kth beat corresponding to the Kth portion of each of the designated registers includes: extracting bits as specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more additional bits, and storing the result of the concatenation in the Kth portion of the destination register. The combined processing of the Kth portion includes: when the Kth portion is not the last portion of the designated registers, carrying at least one bit in the Kth portion of the first source vector register that is not stored in the destination register for processing in the (K+1)th beat of the plurality of beats. For the first portion of the designated registers, the one or more additional bits are extracted from the first portion of the second source vector register, and for each portion other than the first portion of the designated registers, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

[0063] This arrangement implements a micro-architecture that supports vector instructions to more efficiently scale to different performance and energy points. By providing beat status information that tracks the completed beats of two or more vector instructions, this gives the freedom of a specific micro-architecture implementation to vary the amount by which the execution of different vector instructions overlaps, making it feasible that the corresponding beats of different vector instructions are executed in parallel with each other while still tracking the progress of each partially executed instruction. Some micro-architecture implementations may choose to not overlap the execution of corresponding vector instructions at all, so that all beats of a vector instruction are completed before the next instruction begins. Other micro-architectures may interleave the execution of consecutive vector instructions so that a first subset of the beats of a second vector instruction is executed in parallel with a second subset of the beats from a first vector instruction.

[0064] Vector extraction and merging instructions are instructions of an instruction set architecture interpreted by a decoder circuit. The instruction set architecture forms a complete instruction set that can be used by a programmer or compiler to instruct the processing circuit to perform an operation. As discussed, as long as the processing circuit conforms to the instruction set architecture, the actual implementation of the micro-architecture (i.e., the physical arrangement of the circuits and logic blocks constituting the processing circuit) can vary with the specific implementation. Some micro-architecture implementations can process all of the parts of the vector in parallel, while other specific implementations can process one or more parts of the vector at a time. Some vector instructions can be fully applicable to this flexibility by themselves. For example, a vector instruction that supports the element-by-element addition of multiple elements of two source vectors can be divided into multiple scalar additions corresponding to the elements of the vectors respectively. However, instructions (which may include multiple elements of the vector) (i.e., instructions that different parts are dependent on each other) that data is propagated between different elements or between different parts may not be easily adapted to this flexibility of the micro-architecture implementation.

[0065] The vector extraction and merging instruction is one such instruction. In the vector extraction and merging instruction, one or more bits from the first source vector register are cascaded with one or more bits from the second source vector register. The inventor has understood that the vector extraction and merging instruction providing this micro-architecture flexibility can be implemented by providing a processing circuit, which is arranged to use a parallel or interlaced manner to process one or more beats (which correspond to one or more parts of each specified vector register) and carry at least one bit between processing beats (that is, from one part to another part). Therefore, the processing circuit does not regard each beat as truly independent of each other beat. Alternatively, specific information can be propagated from one processed beat to another processed beat. Specifically, the vector extraction and merging instruction specifies a control parameter and a plurality of vector registers as inputs. The plurality of vector registers include a first source vector register, a second source vector register and a destination vector register. The control parameter indicates the number of bits to be extracted from the first source vector register during each processing beat, and can be explicitly specified in the instruction as a parameter passed to the decoder circuit, or can be implicitly indicated in the instruction as having a fixed value. For example, an instruction set architecture may define one or more vector extract and merge instructions, each of which implicitly defines a fixed control parameter. The control parameter may be an indication value, and thus may indirectly specify the number of bits to be extracted.

[0066] Combinatorial processing defined in this manner results in the propagation of bits from the first beat (first portion), wherein one or more additional bits of the second source vector register are cascaded with one or more bits extracted from the first source vector register (as specified by the control parameters). The bits of the first source vector register from the first beat (K=1) are then carried (propagated) to the second beat (K=2), and in the subsequent beats are cascaded with one or more bits of the first source vector register at the time of processing the subsequent beat. Then, the process is repeated by carrying one or more bits of the Kth beat to the (K+1)th beat. The carry is generated when the Kth portion is not the last portion of the specified register. In some configurations, the last portion of the specified vector register does not generate a carry. In some alternative configurations, a carry of at least one bit of the last portion of the first source vector register is generated. It will be understood that the ordering of the beats may be independent of the ordering of the bits within the vector register. In one configuration, the first beat (K=1) may correspond to the least significant bit set of the vector register, and the last beat may correspond to the most significant bit set of the vector register. However, in some alternative configurations, the first beat (K=1) may correspond to the most significant bit set of the vector register, and the last beat may correspond to the least significant bit set of the vector register.

[0067] In this way, the apparatus provides processing circuitry that implements vector extract and merge instructions to which microarchitectural implementations may vary while still allowing compliance with the instruction set architecture, resulting in a flexible implementation that can adapt based on power constraints and circuit size requirements.

[0068] In some configurations, the decoder circuit is responsive to the vector extract and merge instruction specifying a scalar register; the plurality of beats includes a subset of the one or more beats currently being executed, wherein the subset of the beats currently being executed excludes completed beats; and the processing circuit is responsive to the control signals to store at least one carry data item in the scalar register, the at least one carry data item including one or more bits to be carried between the subset of the one or more beats currently being executed and another subset of one or more beats in the plurality of beats. The subset of the beats currently being executed includes one or more beats in the plurality of beats and excludes another subset of at least one beat in the plurality of beats. In such configurations, the scalar register is used to carry the at least one carry data item between the subset of the beats currently being executed and one or more other subsets of the one or more beats. The scalar register may be explicitly specified as one of the plurality of scalar registers, for example, as a parameter in the vector extract and merge instruction. Alternatively, the processing circuitry may include a specific carry register that is implicitly defined in the vector extract and merge instructions.

[0069] The carry register can be used to propagate the carry data to a subset of the currently executed beats, or propagate away from a subset of the currently executed beats. In some configurations, for the first beat of the set of one or more beats currently executed, and before executing the vector extract and merge instruction, the beat status information indicates that at least one beat is to be suppressed, the processing circuit retrieves the one or more additional bits from the scalar register in response to the control signals. The subsets of the one or more processing beats are executed in the order of propagating one or more information bits from the first subset of the beats to the next subset of the beats. During execution, the processing circuit reads the control information to determine which beats include the first beat of the subset of the one or more beats currently executed. When one or more processing beats have been previously executed, the control information indicates that the one or more beats are to be suppressed. Therefore, the processing circuit can infer that the carry data is available in the scalar register and extract the one or more additional bits from the carry data in the vector register.

[0070] The data included in the carry data may take various forms. In some configurations, the one or more bits to be carried include all bits of the portion of the first source vector register; and retrieving the one or more additional bits from the scalar register includes retrieving a last subset of bits from the scalar register. Therefore, whether the extraction is from the scalar register or the second source vector register, the extraction of the one or more additional bits follows the same pattern, which results in a simpler implementation, thereby resulting in a simplified implementation. In some configurations, the one or more bits to be carried include a last set of M bits of the portion of the first source vector register from a set of temporary bit positions stored in the scalar register; and retrieving the one or more additional bits from the scalar register includes retrieving bits from the set of temporary bit positions of the scalar register. Therefore, fewer bits need to be carried in the scalar register. In some configurations, the last subset of bits is a most significant bit subset, which results in data being propagated from the most significant bits of the (K-1)th portion to the Kth portion of the vector register. In alternative implementations, data may propagate in the opposite direction, and in such a configuration, the last subset of bits is the least significant subset of bits.

[0071] In some configurations, concatenating the extracted bits includes storing the extracted bits in a first set of consecutive bit positions of the Kth portion of the destination register, and storing the one or more additional bits in a second set of consecutive bit positions of the Kth portion of the destination register. In some configurations, the union of the first subset of bit positions and the second subset of bit positions includes all bit positions of the Kth portion of the destination register. In some configurations, the first set of consecutive bit positions and the second set of consecutive bit positions are non-overlapping bit positions. Thus, all bit positions in the Kth portion of the destination register are defined as one of the one or more additional bits or one of the extracted bits.

[0072] The ordering of the first set of consecutive bit positions and the second set of bit positions may depend on the specific implementation. In some configurations, the first set of consecutive bit positions is the most significant set of bit positions of the Kth portion of the destination register, and the second set of consecutive bit positions is the least significant set of bit positions of the Kth portion of the destination register. Alternatively, the order of processing of the specified vectors may be reversed. Thus, in some configurations, the first set of consecutive bit positions is the least significant set of bit positions of the Kth portion of the destination register, and the second set of consecutive bit positions is the most significant set of bit positions of the Kth portion of the destination register.

[0073] In some configurations, the extracted bits are extracted from consecutive bit positions of the Kth portion of the first source vector register. The consecutive bit positions are specified by the control parameter and may be defined, for example, based on a first bit position and a second bit position, or based on a first bit position and the number of bits to be extracted.

[0074] In some configurations, these continuous bit positions are the lowest effective set of continuous bit positions of this Kth part of this first source vector register. In such configurations, this control parameter only needs to specify the number of continuous bit positions to be extracted. This continuous number of bit positions to be extracted can be specified as an immediate value, or be included in the register specified in the vector extraction and merging instructions. In alternative configurations, these continuous bit positions are the highest effective set of continuous bit positions of this Kth part of this first source vector register. In some configurations, only a subset of the number of continuous bit positions to be extracted that can be feasible can be supported. For example, some configurations can only support continuous bit positions with a length of 8, 16, or 24. Therefore, in such configurations, this control parameter can indirectly specify the number of continuous bit positions to be extracted by selecting one of the supported lengths. This type of configuration reduces the number of bits required to represent this control parameter.

[0075] In some configurations, each portion of each of the designated registers is an N-bit portion; the control parameter indicates a shift distance M of the designated bit number; the one or more additional bits include M bits; and the extracted bits of the K-th portion of the first source vector register include N minus M bits. Thus, the vector extract and merge instruction combines the M bits of the first portion of the second source vector register with the N minus M bits of the first portion of the first source vector register to form the first portion of the destination register. Furthermore, the vector extract and merge instruction combines the M bits of the (K-1)-th portion of the first source vector register with the N minus M bits of the K-th portion of the first source vector register. In other words, the M bits of each portion of the first source vector register are shifted to be stored in the next portion of the destination vector register.

[0076] For the first portion of the specified registers, the one or more additional elements may be selected in various ways. In some configurations, each N-bit portion is divided into a plurality of elements; the shift distance corresponds to an integer number of elements; and for the first portion of the specified registers, the one or more additional bits comprise a most significant subset of elements of the first portion of the second source vector register. Thus, the shift and merge instruction employs the most significant subset of the second source vector register concatenated with bits of the first source vector register to generate a resulting vector register.

[0077] Alternatively, in some configurations, each N-bit portion is divided into a plurality of elements; the shift distance corresponds to an integer number of elements; and for the first portion of the specified registers, the one or more additional bits include a least significant element subset of the first portion of the second source vector register excluding the least significant element. There are some use cases where it may be advantageous to repeatedly apply the vector extract and merge instruction to sequentially generate a shift vector of a shifted number of bits (or number of elements). For example, when implementing a finite impulse response filter, it may be necessary to sequentially generate a vector that is shifted by a single element from a previous vector in the sequence. The vector extract and merge instruction allows a series of shifted vectors to be generated by taking an initial vector (e.g., the second source vector register) and generating a series of vectors shifted by one element. In such cases, a previous destination register may be used as the second source vector register, rather than retaining the first source vector register and the second source vector register. In this case, the position of the necessary bit to be included in the one or more additional bits has been shifted one or more bit positions away from the most significant bit. Therefore, in the case of the first part of the designated register, by selecting the least significant element subset excluding the least significant element as the one or more other bits, the vector extract and merge instruction can be adapted for the case where the second source vector register includes the result of the aforementioned vector extract and merge instruction. In some configurations, the element width can be controlled by the width parameter of the vector extract and merge instruction. In some configurations, the control parameter can indicate which bits to extract, and the element width. In such configurations, in the case of only supporting a limited number of element widths and the number and position of the bits to be extracted therefrom, the number of bits required for the encoding parameters is reduced.

[0078] In some configurations, the destination vector register is the second source vector register, rather than specifying a vector register for each of the first source vector register, the second source vector register, and the destination vector register. Reusing the second source vector register as the destination register reduces register requirements and reduces encoding space required for vector extract and merge instructions.

[0079] As discussed, vector extraction and merging instructions can be implemented flexibly using hardware capable of executing one or more of a plurality of processing beats in a given cycle. In some configurations, the processing circuit is configured to process at least two of the plurality of beats in parallel. The hardware providing this processing circuit may be sufficient to process only the at least two beats, and the processing circuit may be configured to process the beats of adjacent instructions in parallel with processing the at least two of the plurality of beats. Alternatively, the processing circuit may be sufficient to process all of the beats of the plurality of beats in parallel.

[0080] In some configurations, the processing circuit includes insufficient hardware for executing all of the multiple beats of the given vector instruction in parallel. Therefore, the processing circuit may execute a second subset of the beats of the given vector instruction after completing a first subset of the beats. Depending on the specific implementation of the processor, the first subset and the second subset may include a single beat, or may include multiple beats.

[0081] In some configurations, the processing circuit is configured to process all of the multiple beats of the given vector instruction in parallel. A processing circuit with this hardware can still generate and use the beat status information as specified above, but the beat status information will typically indicate that there are no completed beats. Therefore, by defining the beat status information, the architecture can support a range of different specific implementations.

[0082] In some configurations, the decoder circuit generates a data transfer control signal in response to a memory data transfer instruction adjacent to the vector extract and merge instruction in program counter order, the memory data transfer instruction specifies a memory address and a transfer register of the plurality of vector registers; the device further includes a data control circuit that executes a plurality of memory data transfer processing beats in response to the data transfer control signals, each beat including performing a data transfer to a corresponding portion of the transfer register, and sets beat status information indicating which beats of the data transfer instruction have been completed, and suppresses the completed beats of the memory data transfer instruction indicated as completed by the beat status information; and the device is configured to execute a first subset of the plurality of memory data transfer processing beats corresponding to a first subset of the portion of the transfer register when the transfer register is one of the specified registers, which is in parallel with the processing circuit executing a second subset of the plurality of processing beats corresponding to a second subset of the portion of the transfer register in response to the vector extract and merge instruction. The first subset of the beats and the second subset of the beats may each include the same number of beats, or different numbers of beats. For example, in some configurations, the device may have sufficient hardware to perform memory data transfer operations for multiple portions (corresponding to multiple data transfer processing beats), but only have sufficient hardware to perform a single processing beat for the vector extract and merge instruction. Alternatively, the device may have sufficient hardware to perform memory data transfer operations for half of the portions, and have sufficient hardware to perform a processing beat for the vector extract and merge instruction for half of the portions of the vector length. In each of these situations, there is no overlap in data and hardware between the first subset of the multiple processing beats and the second subset of the multiple processing beats. Therefore, a larger instruction throughput can be achieved by providing a processing device that can parallelize the first subset of beats and the second subset of beats.

[0083] In some configurations, the control parameter is specified as an immediate value in the vector extract and merge instruction. In some alternative configurations, the control parameter may be specified as a register in which the control parameter is defined.

[0084] In some configurations, the first portion of the designated registers is the least significant portion of the designated registers, and the last portion of the designated registers is the most significant portion of the designated registers. In alternative configurations, the first portion of the designated registers is the most significant portion of the designated registers, and the last portion of the designated registers is the least significant portion of the designated registers. In this way, a processing device may be provided with circuitry that performs a vector extract and merge instruction by shifting one or more additional bits extracted from a second source vector register into a destination register from the least significant end or the most significant end, depending on a particular implementation choice.

[0085] The concepts described herein may be embodied in computer readable code for manufacturing a device embodying the described concepts. For example, the computer readable code may be used in one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to manufacture an integrated circuit that includes a device implementing the concepts. The above-mentioned computer readable code may additionally or alternatively facilitate the definition, modeling, simulation, verification and / or testing of a device implementing the concepts described herein.

[0086] For example, computer readable code for making devices that implement the concepts described herein may define a code implementation of a hardware description language (HDL) that represents the concepts. For example, the code may define a register transfer level (RTL) abstract concept for defining one or more logic circuits of a device that implements the concepts. The code may define an HDL representing one or more logic circuits that implement the device in Verilog, SystemVerilog, Chisel, or VHDL (very high speed integrated circuit hardware description language) and intermediate representations such as FIRRTL. The computer readable code may provide a definition of the implementation concept using a system-level modeling language such as SystemC and SystemVerilog or other behavioral representations of the concept that can be interpreted by a computer to facilitate simulation, functional and / or formal verification and testing of the concept.

[0087] Additionally or alternatively, the computer readable code may define a low-level description of an integrated circuit component that implements the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including, for example, a GDSII representation. One or more netlists or other computer readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing an apparatus that implements the present invention. Alternatively or in addition, one or more logic synthesis processes may generate a bitstream from the computer readable code that is loaded into a field programmable gate array (FPGA) to configure the FPGA to implement the described concepts. The FPGA may be deployed for the purpose of verifying and testing concepts prior to manufacturing in an integrated circuit, or the FPGA may be deployed directly in a product.

[0088] The computer readable code may include a mixture of code representations for making a device, such as a mixture containing one or more of an RTL representation, a netlist representation, or another computer readable definition for semiconductor design and manufacturing processes to make a device that implements the invention. Alternatively or in addition, a concept may define a combination of a computer readable definition used in a semiconductor design and manufacturing process to make a device and computer readable code definition instructions that are executed by the defined device once it is manufactured.

[0089] Such computer readable code may be provided in any known transitory computer readable medium (e.g., wired or wireless transmission code over a network) or non-transitory computer readable medium (e.g., semiconductor, magnetic disk, or optical disk). An integrated circuit manufactured using the computer readable code may include components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or one or more of other components that implement the concepts alone or together.

[0090] Specific configurations of the present invention will now be described with reference to the accompanying drawings.

[0091] Figure 1 An example of a data processing apparatus 2 supporting the processing of vector instructions is shown schematically. It will be appreciated that this is a simplified diagram for ease of explanation and that in practice the apparatus may have Figure 18 and 9. The apparatus 2 includes a plurality of components which are not shown for the sake of brevity. The apparatus 2 includes a processing circuit 4 for performing data processing in response to instructions decoded by an instruction decoder 6. Program instructions are extracted from a memory system 8 and decoded by an instruction decoder to generate control signals which control the processing circuit 4 to process the instructions in a manner defined by the architecture. For example, the decoder 6 may interpret the opcodes of the decoded instructions and any additional control fields of the instructions to generate control signals which cause the processing circuit 4 to activate appropriate hardware units to perform operations such as arithmetic operations, load / store operations, or logical operations. The apparatus has a set of registers 10 for storing data values ​​to be processed by the processing circuit 4 and control information for configuring the operation of the processing circuit. In response to an arithmetic or logical instruction, the processing circuit 4 reads operands from the register 10 and writes the result of the instruction back to the register 10. In response to a load / store instruction, data values ​​are transferred between the register 10 and the memory system 8 via the processing circuit. The memory system 8 may include one or more cache levels as well as a main memory.

[0092] Registers 10 include a scalar register file 12, which includes a number of scalar registers for storing scalar values ​​including a single data element. Some of the instructions supported by instruction decoder 6 and processing circuitry 4 are scalar instructions that process scalar operands read from scalar registers 12 to generate scalar results that are written back to scalar registers.

[0093] The register 10 also includes a vector register file 14, which includes a number of vector registers each for storing a vector value including a plurality of data elements. In response to a vector instruction, the instruction decoder 6 controls the processing circuit 4 to perform a number of vector processing passes on the corresponding elements of the vector operand read from one of the vector registers 14 to generate a scalar result to be written to the scalar register 12 or another vector result to be written to the vector register 14. Some vector instructions may generate vector results from one or more scalar operands, or may perform additional scalar operations on scalar operands in the scalar register file, and perform vector processing passes on vector operands read from the vector register file 14. Therefore, some instructions may be mixed scalar-vector instructions, for which at least one of the one or more source registers and the destination register of the instruction is the vector register 14, and the other of the one or more source registers and the destination register is the scalar register 12. Vector instructions may also include vector load / store instructions that cause data values ​​to be transferred between the vector register 14 and a location in the memory system 8. The load / store instructions may include consecutive vector load / store instructions, for which the locations in the memory correspond to consecutive address ranges, or scatter / gather type vector load / store instructions, which specify a number of discrete addresses and control the processing circuit 4 to load data from each of those addresses into corresponding elements of the vector register, or to store data from corresponding elements of the vector register to these discrete addresses.

[0094] The processing circuitry 4 may support the processing of vectors having a range of different data element sizes. For example, a 128-bit vector register 14 may be split into sixteen 8-bit data elements, eight 16-bit data elements, four 32-bit data elements, or two 64-bit data elements. A control register within the register bank 10 may specify the data element size currently being used, or alternatively, this may be a parameter to a given vector instruction to be executed.

[0095] The registers 10 also include several control registers for controlling the processing of the processing circuit 4. For example, these may include: a program counter register 16 for storing a program counter address indicating the address of the instruction corresponding to the current execution point being processed; a link register 18 for storing a return address to which the processing is to be directed after a handling function call; a stack pointer register 20 indicating the location of a stack data structure within the memory system 8; and a beat status register 22 for storing beat status information, which will be described in more detail below. It will be understood that these are only some of the types of control information that can be stored, and in fact, a given instruction set of an architecture may store many other control parameters as defined by the architecture. For example, a control register may specify the overall width of a vector register, or may specify the current data element size for a given case of vector processing.

[0096] The processing circuit 4 may include several different hardware blocks for processing different levels of instructions. For example, load / store instructions that interact with the memory system 8 may be processed by a dedicated load / store unit, while arithmetic or logic instructions may be processed by an arithmetic logic unit (ALU). The ALU itself may be further divided into a multiply-accumulate unit (MAC) and another unit, the multiply-accumulate unit being used to perform operations involving multiplication, and the other unit being used to process other kinds of ALU operations. A floating point unit may also be provided, which is used to handle floating point instructions. Compared to vector instructions, pure scalar instructions that do not involve any vector processing may also be handled by separate hardware blocks, or the same hardware blocks may be reused.

[0097] In some applications (e.g., digital signal processing (DSP)), there may be a roughly equal number of ALUs and load / store instructions, and thus some large blocks (e.g., MACs) may remain idle for a significant amount of time. This inefficiency may be exacerbated on vector architectures because execution resources scale with the number of vector lanes to achieve higher performance. On smaller processors (e.g., single issue, in-order cores), the area overhead of a fully scaled-out vector pipeline may be prohibitive. One way to minimize the area impact while making better use of the available execution resources is to overlap the execution of instructions, such as Figure 2 As shown. In this example, the three vector instructions include a load instruction VLDR, a multiply instruction VMUL, and a shift instruction VSHR, and even though there are data dependencies between all of these instructions, they can still be executed simultaneously. This is because element 1 of VMUL only depends on element 1 of Q1, not the entire Q1 register, so execution of VMUL can begin before execution of VLDR is completed. By allowing instructions to overlap, expensive blocks (such as multipliers) can have more time to remain active.

[0098] Therefore, it may be desirable to enable a microarchitecture implementation to overlap the execution of vector instructions. However, if the architecture assumes a fixed amount of instruction overlap, while this may provide high efficiency when the microarchitecture implementation actually matches the amount of overlapping instructions assumed by the architecture, it may cause problems if scaled to a different microarchitecture that uses a different overlap or no overlap at all.

[0099] Alternatively, the architecture may support Figure 3 The execution of vector instructions is divided into parts called "beats", where each beat corresponds to the processing of a portion of a vector of a predetermined size. A beat is an atomic portion of a vector instruction that is either executed in full or not at all and cannot be executed partially. The size of the portion of a vector processed in a beat is defined by the architecture and can be any fraction of a vector. Figure 3 In the example of , a beat is defined as processing corresponding to one-fourth of the vector width, so that each vector instruction has four beats. Clearly, this is just an example, and other architectures can use different numbers of beats (e.g., two or eight). The size of the vector portion corresponding to a beat can be the same as, greater than, or less than the data element size of the processed vector. Therefore, even if the element size varies with the specific implementation or the runtime changes between different instructions, the beat is still a fixed width of vector processing. If the vector portion processed in a beat includes multiple data elements, the carry signal can be disabled at the boundary between the corresponding elements to ensure that each element is processed independently. If the vector portion processed in a beat corresponds to only a portion of the element, and the hardware is not sufficient to calculate several beats in parallel, the carry output generated during one processing beat can be input as a carry input to the subsequent processing beat, so that the results of the two beats form a data element together.

[0100] like Figure 3 As shown, different microarchitectural implementations of processing circuitry 4 may execute different numbers of beats in one "tick" of the abstract architectural clock. Here, a "tick" corresponds to a unit of architectural state advancement (e.g., on a simple architecture, each tick may correspond to updating all architectural states associated with executing instructions, including updating the program counter to point to the next instruction). One of ordinary skill in the art will understand that known microarchitectural techniques (e.g., pipelining) may mean that a single tick may require multiple clock cycles to execute at the hardware level, and in fact a single clock cycle at the hardware level may process multiple portions of multiple instructions. However, this microarchitectural technique is invisible to software because the tick is atomic at the architectural level. For the sake of brevity, the microarchitecture is ignored during further description of the present disclosure.

[0101] like Figure 3As shown in the lower example of , some implementations can schedule all four beats of the vector instruction in the same tick by providing enough hardware resources to process all beats in parallel within one tick. This may be suitable for higher performance implementations. In this case, no overlap between instructions is required at the architectural level, because the entire instruction can be completed in one tick.

[0102] On the other hand, a more area-efficient implementation may provide narrower processing units that can process only two beats per tick, and Figure 3 As shown in the middle example of FIG. 1 , instruction execution may overlap the first and second beats of a second vector instruction executed in parallel with the third or fourth beat of the first instruction, where those instructions are executed on different execution units within the processing circuit (e.g., in Figure 3 , the first instruction is a load instruction executed using a load / store unit, and the second instruction is a multiply-accumulate instruction executed using a MAC).

[0103] A more energy / area efficient implementation may provide narrower hardware units that can process only a single tick at a time, and in this case, each tick can process one tick, where instructions execute as follows: Figure 3 The top example overlaps and staggers one beat (this is the same as the Figure 2 same as the example shown).

[0104] will understand, Figure 3 The overlaps shown are only some examples, and other specific implementations are also possible. For example, some specific implementations of the processing circuit 4 may support multiple instructions to be issued in parallel in the same tick, so that there is a larger instruction throughput. In this case, two or more vector instructions that start together in one cycle may have some ticks overlapping with two or more vector instructions that start in the next cycle.

[0105] In addition to varying the amount of overlap with the implementation to scale to different performance points, the amount of overlap between vector instructions may also vary at run time between different executions of vector instructions within a program. Figure 1 A tick control circuit 30 is shown for controlling the timing of execution of a given instruction relative to previous instructions. This gives the microarchitecture the freedom to choose non-overlapping instructions in certain corner cases that are more difficult to implement or depending on the resources available to the instructions. For example, if there are back-to-back instructions of a given type (e.g., multiply-accumulate) that require the same resources and all available MAC or ALU resources are already in use by another instruction, there may not be enough free resources to start execution of the next instruction, and therefore, rather than overlapping, the issuance of the second instruction may wait until the first is completed.

[0106] While allowing a range of different execution vector instructions may allow for more efficient use of hardware resources across a range of performance points, it may introduce some complexity in the handling of exceptions, or debug events, or other events that trigger a pause of the current execution thread. Figure 2 In the example shown, if an exception occurs on the fourth tick, the register file will contain partial updates from several instructions. One way to handle this would be to treat the partial updates as speculative states that can be restored if an exception occurs, but this can increase the amount of hardware required because it may have to buffer storage requests for storing data out to the memory system 8 until they are dialed out, and additional registers must be provided in hardware for tracking speculative states. Another approach would be to completely disable exceptions taken midway through vector instructions and delay taking the exception until the earliest outstanding instruction has completed, but increasing exception handling latency may be undesirable, and if the exception is a precise error this behavior may undermine the architectural guarantees associated with the error.

[0107] Alternatively, if Figure 4 As shown, the beat status register 22 can be used to record a beat status value, which tracks which beats of adjacent instruction groups have been completed at the time point of an exception, a debug event, or other event that causes the suspension of the current thread. This can help reduce micro-architecture complexity and increase power and area efficiency by exposing the overlapping nature of execution to the architecture.

[0108] exist Figure 4 In the example of , the beat status information tracks the completed beats of a group of three vector instructions A, B, C, where instruction A corresponds to the oldest uncompleted vector instruction, instruction B is the next vector instruction after instruction A, and instruction C is the next vector instruction after instruction B. The symbol Ax refers to the xth beat of instruction A, where for a 4-beat vector implementation, x is between 1 and 4, for example, A2 is the second beat of instruction A. Although Figure 4 An example of using beat status information to track three instructions is shown, but in other examples that allow a larger number of instructions to be partially completed at a given point, the beat status information can track a larger number of instructions. For example, if dual-issue is supported, it may be desirable to indicate the beat progress of more than 3 instructions. Each value of the beat status field is assigned to a given combination of completed beats. For example, a beat status value of 0011 indicates that the first beat and the second beat of instruction A and the first beat of instruction B are completed. The specific mapping of the specific encoding value of the beat status information to the specific beat set of the corresponding instruction group is arbitrary and can be changed. In this example, a beat status value of 0000 indicates that there are no unfinished instructions, and therefore there are no completed beats of unfinished instructions. This can occur, for example, when the processor has executed a scalar instruction.

[0109] Figure 5 Shows some examples of tick status information recorded at the point in time when the currently executing thread is paused. Figure 5 In the top example of , vector instructions are executed using one beat per tick, and a debug event or exception occurs on the fourth tick. Therefore, at this point, the first three beats of instruction A, the first two beats of instruction B, and the first beat of instruction C have completed, but beats A4, B3, C2, D1 are still to be executed. Therefore, the beat status information will have a value of 0111, which is based on Figure 4 The example indicates that beats A1, A2, A3, B1, B2, and C1 have been completed.

[0110] Similarly, in Figure 5 In the bottom of the example, the instructions being executed are such that instructions B and C cannot overlap (e.g., because they need to use the same hardware unit), and therefore this time at the time of the debug event or exception, instructions C and D have not yet started. This time the exception occurring at tick four will trigger the recording of beat status information 0110, which indicates that beats A1, A2, A3, B1, and B2 have completed, but not C1.

[0111] Similarly, using Figure 3 Taking the example of two beats per tick of , if the exception occurs on tick 2, only beats A1 and A2 will have been completed, and the beat status value will be 0010. It should be noted that although the values ​​0001 and 0010 of the beat status information indicate that only one instruction A is partially completed at the time of the exception, the beat status information still indicates which beats of the multiple instruction groups have been completed because the beats of the two instructions B and C identified below have not yet been completed.

[0112] use Figure 3 In the example of four beats per tick, no matter when the exception occurs, the beat status value will be 0000 because there will be no partially completed instructions at the time of the exception, because each instruction will be completed in one tick.

[0113] When a debug event or exception occurs, the return address is set to the current value of the program counter 16, which represents the address of the oldest incomplete instruction. Figure 5 In both examples, the return address will be set to the address of instruction A. The return address may be stored in a variety of places, including at a location on the stack relative to the value of the stack pointer register, or in a return address register.

[0114] like Figure 6As shown, this enables the processor to respond to a return from event request (e.g., when returning from debug mode or an exception handler) to resume processing from a point determined based on the return address and the beat status information in the beat status register 22. In the case of a debug event, the return from event request may be made by the debugger, or in the case of an exception event, the return from event request may be made by the exception handler. After the return from event request, the instruction to be processed is retrieved and resumed from the address indicated by the return address, which in this case corresponds to instruction A. Next, instructions B, C and D (in this example corresponding to Figure 5 ). However, for the first few cycles after the return, any beats indicated by the beat status information as completed are suppressed. The processor may suppress these beats by completely preventing the corresponding processing operation from being executed (e.g., suppressing requests to load or store data, or disabling the ALU or MAC). Alternatively, the operation may still be performed in the case of an ALU operation, but the processor may suppress the writing of the result of the operation (i.e., suppressing the update of part of the destination vector register) so that it does not affect the register state. Once the fourth tick is reached, the pipeline has reached the point where the debug event or exception previously occurred, and processing continues normally. Therefore, for the first few cycles after the exception return, the processor may not perform any useful work, and essentially only re-extracts multiple instructions that were in progress when the original exception or debug event occurred. However, since for some applications, the exception return latency is often not important, this can be a good trade-off for reducing the delay at the time the exception is taken, and this also helps reduce the amount of architectural state that needs to be stored when the exception occurs, because it does not have to speculatively store the results of the unfinished instructions. This method also implements the handling of precise errors where the exception is caused by the beat of a vector instruction.

[0115] In some cases, the beat status information indicating the completed beats of multiple instruction groups can be set in response to a debug event or an exception occurs. However, in some specific implementations, it may be easier to update the beat status register every time an instruction is completed, regardless of whether an exception has occurred, so that if an exception occurs in a subsequent tick, the beat status register 22 has indicated the completed beat of the instruction group.

[0116] Although Figure 4One example encoding of the beat status information is shown, but another possibility is to provide the beat status information as a bitmap including bits, each of which corresponds to a beat of one of the groups of instructions A, B, C, etc., wherein each bit is set to one if the corresponding beat has been completed, and is set to zero if the corresponding beat has not been completed (or vice versa). However, in practice, since subsequent beats of a given instruction cannot be completed if earlier beats have not been completed, it is not necessary to provide a bit for each beat, and it may be more efficient to assign certain encodings of a smaller bit field to specific combinations of completed beats, such as Figure 4 .

[0117] Figure 7 Schematically illustrates the details of the device 30 arranged according to various configurations of the present technology. Specifically, the device 30 is provided with a decoder circuit 38, a processing circuit 40 and a set of registers 32. The registers 32 include one or more scalar registers 34 and one or more vector registers 36. The decoder circuit is arranged to receive instructions (e.g., based on program code generated by a programmer and a compiler) and interpret the instructions based on an instruction set architecture. Specifically, the decoder circuit is arranged to interpret a vector extract and merge instruction, which specifies a first source vector register 44, a second source vector register 46, a destination register 54 and a control parameter 43. Upon receiving the vector extract and merge instruction, the decoder circuit generates a control signal to cause the processing circuit 40 to perform a vector extract and merge process. The processing circuit 40 performs the vector extract and merge process by executing one or more beats 48 of a plurality of processing beats in response to the control signal. Each processing beat corresponds to at least a portion of each of the first source vector register 44 and the destination vector register 54. The processing circuit 40 is arranged to perform one or more processing beats corresponding to one or more portions 48 of the first source vector register 44 and one or more portions 49 of the second source vector register to generate one or more portions 50 to be stored in the destination vector register 50. The processing circuit 40 is arranged to extract one or more bits from the Kth portion 48 of the first source vector register for the Kth processing beat of the plurality of processing beats and concatenate those bits with one or more additional bits. In the case where the Kth beat is the first beat of the plurality of beats, the one or more additional bits are extracted from the first portion (Kth portion, K=1) 49 of the second source vector register. In the case where the Kth beat is a beat other than the first beat (K>1), the one or more additional bits are the carry bit 52 of the (K-1)th beat carry corresponding to the (K-1)th portion of the first source vector register 44. In addition, the processing circuit is arranged to output one or more bits as carry data to be used in the (K+1)th processing beat if the Kth beat is not the last beat of the plurality of beats.

[0118] Figure 8 Schematically illustrates details of a processing device 60 arranged in accordance with some configurations of the present technology. Specifically, the processing device 60 is provided with registers 62, decoder circuits 68, processing circuits 70 and data control circuits 72. The registers 62 include a plurality of scalar registers 64 and a plurality of vector registers 66. The decoder circuits 68 are arranged to generate control signals in response to instructions forming part of an instruction set architecture. The control signals are passed (routed) to the processing circuits 70 and the data control circuits 72. The processing circuits 70 are arranged to execute a plurality of processing ticks in response to vector extract and merge instructions. Details of the processing circuits are similar to Figure 7 The details of the processing circuit 40 mentioned are the same. The data control circuit 72 executes a plurality of memory transfer processing beats in response to data control signals (which are generated by the decoder circuit 68 in response to data transfer instructions). For a given tick, the device 60 is arranged to execute a plurality of beats, the plurality of beats comprising a first subset of a plurality of memory transfer processing beats executed by the data control circuit 72, and a second subset of a plurality of combined processing beats in response to vector extract and merge instructions executed by the processing circuit 70. The device 60 is arranged to execute the first subset of the plurality of beats and the second subset of the plurality of beats while referencing non-overlapping portions of the same vector register 72.

[0119] Fig. 9Schematically illustrate the details of the vector extraction and merging instructions according to some configurations of the present technology. The vector extraction and merging instructions specify a first source vector register, a second source vector register, a destination vector register, and a control parameter M. In the example shown, the processing circuit performs two processing beats, each corresponding to the N-bit portion of the first source vector register, the second source vector register, and the destination register. The first source vector register includes a first N-bit portion 82. The first N-bit portion 82 includes the most significant M bits 84 and the least significant NM bits 86. The processing circuit is arranged to extract the NM bits 86 of the first portion 82 of the first source vector register for the first processing beat corresponding to the first portion 82 of the first source vector register, the first portion 88 of the second source vector register, and the first portion 102 of the destination vector register, and cascade the extracted NM bits with M bits (one or more additional bits) 90, which are extracted from the first portion 88 of the second source vector register. Specifically, the NM bits 86 extracted from the first portion 82 of the first source vector register are stored as the most significant NM bits 98 of the first portion 102 of the destination vector register. The M bits 90 extracted from the first portion 88 of the second source vector register are stored as the least significant M bits 100 of the first portion 102 of the destination vector register. The processing circuit is further configured to carry the most significant M bits 84 of the first portion 82 of the first source vector register as a carry bit 96. The carry bit may be a carry bit that is carried between processing beats executed in parallel or a carry bit that is output to a scalar register that is arranged to carry bits between processing beats executed in non-parallel. In the second processing beat, the M bits 96 carried from the first portion 82 of the first source vector register are stored as the least significant M bits 94 of the second portion of the destination register. During the second processing tick, the processing circuit is arranged to extract the least significant NM bits 95 of the second N-bit portion 80 of the first source vector register and store the NM bits 95 of the second portion 80 of the first source vector register as the most significant NM bits 92 of the second portion 104 of the destination vector register. In this way, the processing circuit supports vector extract and merge instructions across multiple ticks. In this example, the control parameter indicates the number of M bits 84 that carry between the portions (one or more additional bits). In other examples, the control parameter may indicate the number of bits extracted from the first portion 86 of the first source vector register and stored in the first portion of the destination vector register.

[0120] Figures 10 to 12Schematically illustrating bits extracted from a first portion of a second source vector register according to various configurations of the present technology. A specific use case of the vector extract and merge instructions is to generate vectors that are not aligned to 32-bit boundaries. Specifically, some devices are arranged to load data aligned to 32-bit boundaries. Therefore, it is relatively straightforward to generate a vector of data values ​​shifted by 32 bits. However, using only load instructions to generate data that is not aligned to 32-bit boundaries may not be feasible, or may incur a performance penalty, such that using aligned loads may be preferred. One method of generating data that is not aligned to 32-bit boundaries requires performing a shift.

[0121] Fig.10 Schematically illustrate the situation that the data stored in the designated register is 16-bit data. The first source vector register shown is divided into four beats, each including four bytes (32 bits). The data stored in the first source vector register and the second source vector register correspond to different parts of the same data set. The data stored in the second source vector register has been offset by 32 bits from the data loaded into the first source vector register. For 16-bit data, according to the aforementioned use case, it is desirable to generate a vector through shifting 16 bits. In this case, one or more other bits extracted from the second source vector register are bytes 2 and 3 (position 16 to 31) of the first part of the second source vector register. Extracting these bits from the shown part of the second source vector register and the combination of the shifted data stored in the first source vector register causes generating data that are not aligned to 32-bit boundaries in the destination vector register.

[0122] Fig.11 Schematically illustrate the part of the second source vector register that will need to be extracted in order to perform this shift for 8-bit data. Specifically, in order to generate a group of data that is not aligned with 32-bit boundaries by 24 bits, bytes 1, 2 and 3 of the second source vector register are extracted as one or more additional bits in the first processing beat. In order to generate a group of data that is not aligned with 32-bit boundaries by 16 bits, bytes 2 and 3 of the second source vector register are extracted as one or more additional bits in the first processing beat. In order to generate a group of data that is not aligned with 32-bit boundaries by 8 bits, bytes 3 of the second vector register are extracted as one or more additional bits in the first processing beat. In this way, it is feasible to generate a series of vectors with data elements that are not aligned to 32-bit boundaries.

[0123] Fig.12 The portion of the second source vector register that would need to be extracted in order to perform this shift for 8-bit data is schematically shown if the destination data vector is the second source data vector. In the example shown, a sequence of three vector extract and merge instructions is applied. Each of the vector extract and merge instructions specifies as a control parameter a different number of bits by which the first source vector register is shifted. Fig.10 In the example of, the data stored in the second source vector register has been offset by 32 bits from the data loaded into the first source vector register. In the example shown, one or more additional bits extracted from the second source vector register include the least significant byte set of the first part of the second source vector register excluding the least significant byte. In the first vector extraction and merging instruction, the shift of 24 bits (3 bytes) is defined as a control parameter. Therefore, the bytes extracted from the second source vector register are bytes 3, 2 and 1. These are cascaded by processing circuits during multiple processing beats to generate a vector of values ​​that are not aligned with 32-bit boundaries by 24 bits, as the content of the destination vector register for the first vector extraction and merging instruction. In the second vector extraction and merging instruction, the shift of 16 bits (2 bytes) is defined as a control parameter, and the destination vector register of the first vector extraction and merging instruction is used as the second source vector register. Therefore, the bytes extracted from the second source vector register of the second instruction are bytes 3 and 2. These are concatenated by the processing circuit during multiple processing cycles to generate a vector of values ​​that are 16 bits misaligned with the 32-bit boundary as the contents of the destination vector register for the second vector extract and merge instruction. In the third vector extract and merge instruction, a shift of 8 bits (1 byte) is defined as a control parameter, and the destination vector register of the second vector extract and merge instruction is used as the second source vector register. Therefore, the byte extracted from the second source vector register is byte 3. This byte is concatenated by the processing circuit during multiple processing cycles to generate a vector of values ​​that are 8 bits misaligned with the 32-bit boundary as the contents of the destination vector register for the third vector extract and merge instruction.

[0124] Figures 13 to 17Schematically illustrate the sequence of operations implemented by the processing circuit in response to the vector extraction and merging instructions. For illustrative purposes, the use case of the vector that the vector extraction and merging instructions are intended to generate is not aligned to the 32-bit boundary to select the elements of the vector register. It will be obvious to those of ordinary skill in the art that this use case example is purely selected for illustrative purposes, and the technology described herein does not require any relationship between the contents of the first source vector register and the second source vector register. Specifically, it will be obvious that for the general vector extraction and merging instructions described herein, the vector stored in the first source vector register can be any first vector loaded from the memory or generated, for example, due to one or more other operations. Similarly, the second source vector stored in the second source vector register can be any second vector, and in some use cases, the programmer can select the first vector and the second vector so that there is some overlap between the elements present in the first source vector register and the second source vector register. In other use cases, the programmer can select the first source vector and the second source vector so that there is no overlap between the elements present in the first source vector register and the second source vector register.

[0125] Fig.13Schematically illustrates a sequence of operations performed by a processing circuit in response to a vector extraction and merging instruction, which specifies a first source vector register 110, a second source vector register 112, a destination register 114, a scalar register, and control information. Each of the first source vector register 110, the second source vector register 112, and the destination register 114 is arranged as a plurality of parts to be processed in a plurality of processing beats. In the example shown, the processing circuit is arranged to perform a single processing beat for a given tick. Each of these parts includes two elements, and the control information specifies that the shift corresponding to the single element is to be performed. For exemplary purposes only, the first source vector register and the second source vector register are 128-bit vector registers, and are shown as containing a set of numbered data items. Specifically, the first source vector register contains data item 9 down to data item 2, and the second source vector register contains data item 7 down to data item 0. Therefore, the first source vector register and the second source vector register contain 16-bit data items aligned to 32-bit boundaries loaded from the address in the memory. In a first processing tick, the processing circuit extracts the least significant element (data item 2) of the first portion 110 (D) of the first source vector register. The extracted least significant element of the first portion 110 (D) of the first source vector register is concatenated with the most significant element (data item 1) of the first portion 112 (D) of the second source vector register, and the result of the concatenation is stored as the first portion 114 (D) of the destination vector register. During the first processing tick, the most significant element (data item 3) of the first portion 110 (D) of the first source vector register is extracted as carry data 116 and stored as the most significant element in the scalar register. During the second processing tick, the processing circuit extracts the least significant element (data item 4) of the second portion 110 (C) of the first source vector register. The extracted least significant element of the second portion 110 (C) of the first source vector register is concatenated with the carry data 116 stored in the most significant element (data item 3) of the scalar register, and the result of the concatenation is stored in the second portion 114 (C) of the destination vector register. During the second processing tick, the processing circuit also extracts the most significant element (data item 5) of the second portion 110(C) of the first source vector register as the carry data 118 to be stored as the most significant element in the scalar register. During the third processing tick, the processing circuit extracts the least significant element (data item 6) of the third portion 110(B) of the first source vector register. The extracted least significant element of the third portion 110(B) of the first source vector register is concatenated with the carry data 118 stored in the most significant element (data item 5) of the scalar register, and the concatenated result is stored in the third portion 114(B) of the destination vector register.During the third processing tick, the processing circuit also extracts the most significant element (data item 7) of the third portion 110 (B) of the first source vector register as the carry data 120 to be stored as the most significant element in the scalar register. During the fourth processing tick, the processing circuit extracts the least significant element (data item 8) of the fourth portion 110 (A) of the first source vector register. The extracted least significant element of the fourth portion 110 (C) of the first source vector register is concatenated with the carry data 120 stored in the most significant element (data item 7) of the scalar register, and the result of the concatenation is stored in the fourth (last) portion 114 (A) of the destination vector register. In some alternative configurations, during the fourth processing tick, the processing circuit also extracts the most significant element of the fourth portion 110 (A) of the first source vector register as the carry data to be stored as the most significant element in the scalar register. This carry data remains stored in the scalar register after executing the vector extract and merge instruction. Unused elements (such as) of the scalar register. Fig.13 The value in the least significant element (shown in FIG. 1 ) is arbitrary. In some examples, this element may be set to a pseudo value, such as zero. In other examples, it may be set to the value of the adjacent element from the current portion of the first source vector register.

[0126] Fig.14 Schematically illustrates a sequence of operations performed by a processing circuit in response to a vector extract and merge instruction that specifies a first source vector register 140, a second source vector register 142, a destination register 144, a scalar register, and control information. Fig.13 In , each of the first source vector register and the second source vector register contains data items extracted from the memory region aligned to a 32-bit boundary. Fig.13, each of the data items stored in the elements of the first source vector register and the second source vector register is an 8-bit data item. Each of the first source vector register 140, the second source vector register 142 and the destination register 144 is arranged as a plurality of parts to be processed in a plurality of processing beats. In the example shown, the processing circuit is arranged to perform a single processing beat for a given tick. Each of these parts includes four elements, and the control information specifies that the shift corresponding to the two elements is to be performed. In the first processing beat, the processing circuit extracts the two least significant elements (data items 5 and 4) of the first part 140 (D) of the first source vector register. The extracted two least significant elements of the first part 140 (D) of the first source vector register are cascaded with the two most significant elements (data items 3 and 2) of the first part 142 (D) of the second source vector register, and the result of the cascade is stored as the first part 144 (D) of the destination vector register. During the first processing beat, the first part 140 (D) of the first source vector register (data item 7 down to data item 4) is extracted as the carry data 146 stored in the scalar register. During the second processing tick, the processing circuit extracts the two least significant elements (data items 9 and 8) of the second portion 140(C) of the first source vector register. The extracted two least significant elements of the second portion 140(C) of the first source vector register are concatenated with the two most significant elements (data items 7 and 6) of the carry data 146 stored in the scalar register, and the result of the concatenation is stored in the second portion 144(C) of the destination vector register. During the second processing tick, the processing circuit also extracts the second portion 140(C) of the first source vector register (data item 11 down to data item 8) as the carry data 148 to be stored in the scalar register. During the third processing tick, the processing circuit extracts the two least significant elements (data items 13 and 12) of the third portion 140(B) of the first source vector register. The two least significant elements of the third portion 140(B) of the first source vector register are concatenated with the two most significant elements (entries 11 and 10) of the carry data 148 stored in the scalar register, and the result of the concatenation is stored in the third portion 144(B) of the destination vector register. During the third processing tick, the processing circuit also extracts the third portion 140(B) of the first source vector register (entries 15 down to 12) as the carry data 150 to be stored in the scalar register. During the fourth processing tick, the processing circuit extracts the two least significant elements (data items 17 and 16) of the fourth portion 140(A) of the first source vector register.The extracted two least significant elements of the fourth portion 140(A) of the first source vector register are concatenated with the two most significant elements (data items 15 and 14) of the carry data 150 stored in the scalar register, and the result of the concatenation is stored in the fourth (last) portion 144(A) of the destination vector register. In some alternative configurations, during the fourth processing tick, the processing circuit also extracts the fourth portion 140(A) of the first source vector register as the carry data to be stored in the scalar register. This carry data remains stored in the scalar register after executing the vector extract and merge instruction.

[0127] Fig.15 A sequence of operations performed by processing circuitry in response to a vector extract and merge instruction according to an alternative implementation is schematically illustrated. Fig.15 and Fig.14 The difference is that, for each of the first processing beat, the second processing beat, and the third processing beat, the data extracted from the corresponding part of the first source vector register 160 (to be stored as the carry data in the scalar register) is the two most significant elements of the corresponding part and is stored as the two least significant elements of the scalar register. Specifically, unlike Fig.14 The operation of the described is as follows: in a first processing beat, the processing circuit extracts the two most significant elements (data items 7 and 6) of the first portion 160 (D) of the first source vector register to be stored as carry data 166 in the two least significant elements of the scalar register. In a second processing beat, one or more additional data bits are extracted from the two least significant elements of the scalar register, and the processing circuit extracts the two most significant elements (data items 11 and 10) of the second portion 160 (C) of the first source vector register to be stored as carry data 168 in the two least significant elements of the scalar register. In a third processing beat, one or more additional data bits are extracted from the two least significant elements of the scalar register, and the processing circuit extracts the two most significant elements (data items 15 and 14) of the third portion 160 (B) of the first source vector register to be stored as carry data 170 in the two least significant elements of the scalar register. In a fourth processing beat, one or more additional data bits are extracted from the two least significant elements of the scalar register. It will be understood that the location of the carry data in the scalar register is arbitrary, and although Fig.14 and 15 Two possibilities are shown, but other configurations are possible.

[0128] Fig.16Schematically illustrates a sequence of operations performed by a processing circuit in response to a vector extract and merge instruction that specifies a first source vector register 180, a second source vector register 182, a destination register 184, a scalar register, and control information. Each of the first source vector register 180, the second source vector register 182, and the destination register 184 is arranged as multiple portions to be processed in multiple processing ticks. Fig.16 and Fig.15 and Fig.14 The difference is that the processing circuit has hardware capable of executing two beats of multiple processing beats for a given tick. In other words, both of these beats are executed in parallel. Each of the parts of the first source vector register 180 and the second source vector register 182 includes four 8-bit elements, and the control information specifies that the shift corresponding to the two elements is to be performed. In response to the first tick, the processing circuit executes the first processing beat and the second processing beat corresponding to the two least significant parts 180 (C) and 180 (D) of the first source vector register 180. The processing circuit is arranged to extract the two most significant elements (data items 3 and 2) from the least significant part 182 (D) of the second source vector register as one or more additional bits. One or more additional bits are cascaded with the two least significant elements (data items 5 and 4) of the least significant part 180 (D) of the first source vector register. The result of the cascade is stored in the least significant part 184 (D) of the destination vector register. The two most significant elements (data items 7 and 6) of the least significant part 180 (D) of the first source vector register are carried to be used in the second beat. Because the second beat is executed in parallel with the first beat (in the same tick), the two most significant elements (data items 7 and 6) of the least significant part 180 (D) of the first source vector register are carried without the need for a scalar register. Therefore, in the same tick, as part of the second processing beat, the two most significant elements (data items 7 and 6) of the least significant part 180 (D) of the first source vector register are carried as one or more additional bits to be cascaded with the two least significant elements (data items 9 and 8) of the second part 180 (C) of the first source vector register. The result of the cascade is stored in the second part 184 (C) of the destination vector register. The processing circuit is also arranged to store the two most significant elements (data items 11 and 10) from the second part 180 (C) of the first source vector register to the two least significant elements of the scalar register 188 to be carried for processing during the next tick. The processing circuitry is further arranged to set status information in response to the vector extract and merge instruction, the status information indicating that processing has been completed for both the first processing tick and the second processing tick to be performed.

[0129] During the second processing beat, the processing circuit can determine from the status information that the processing of the first processing beat and the second processing beat is completed. Therefore, the processing circuit starts the processing of the third beat corresponding to the third part 180 (B) of the first source vector register. The processing circuit extracts the two least significant elements (data items 13 and 12) from the third part 180 (B) of the first source vector register and concatenates these elements with one or more additional bits. Because the processing circuit can determine that the beat being processed does not include the first beat (the least significant part), the one or more additional bits are extracted from the scalar register 188. Specifically, the one or more additional bits include the two least significant elements (data items 11 and 10) of the scalar register 188, which are extracted and concatenated with the two least significant elements (data items 13 and 12) of the third part 180 (B) of the first source vector register, and the result of the concatenation is stored in the third part 184 (B) of the destination register. The processing circuit is also arranged to extract the two most significant elements (data items 15 and 14) of the third part 180 (B) of the first source vector register to carry to the fourth beat. Because the processing circuit can perform two processing beats at a given tick, beats 3 and 4 are executed in parallel, and the carried data does not need to be stored in the scalar register 188. Instead, the two most significant elements (data items 15 and 14) of the third part 180 (B) of the first source vector register are carried as one or more additional bits to be used in the fourth beat. During the fourth beat, the two least significant elements (data items 17 and 16) of the fourth (most significant) part 180 (A) of the first source vector register are extracted and cascaded with one or more additional bits of the third part of the first source vector register. The result of the cascade is stored in the fourth part (most significant part) 184 (A) of the destination vector register.

[0130] In some alternative arrangements, during the fourth processing tick, the processing circuitry also extracts the fourth portion 180(A) of the first source vector register as carry data to be stored in the scalar register 188. This carry data remains stored in the scalar register 188 after execution of the vector extract and merge instruction, which may be used as part of another instruction.

[0131] Fig.17 An alternative configuration is schematically shown in which a sequence of operations is carried out by processing circuitry in response to a vector extract and merge instruction specifying a first source vector register 240, a second source vector register 242, a destination register 244, a scalar register and control information. Fig.17 and Figures 14 to 16The difference is that the extract and merge instruction has been reversed. Specifically, the vector extract and merge instruction is implemented from the most significant part of the specified register, rather than from the least significant part of the source vector register. In the example shown, the processing circuit is arranged to perform a single processing beat for a given tick. Each of these parts includes four elements, and the control information specifies that the shift corresponding to an element is to be performed. In the first processing beat (in this case, corresponding to the most significant part of the specified register), the processing circuit extracts the three most significant elements (data item 15 down to data item 13) of the first part (most significant part) 240 (A) of the first source vector register. The extracted three most significant elements of the first part 240 (A) of the first source vector register are cascaded with the least significant element (data item 16) of the first part (most significant part) 242 (A) of the second source vector register, and the result of the cascade is stored as the first part 244 (A) of the destination vector register. During a first processing tick, a first portion 240(A) of the first source vector register (data item 15 down to data item 12) is extracted as carry data 246 and stored in a scalar register. During a second processing tick, the processing circuit extracts the three most significant elements of a second portion 240(B) of the first source vector register (data item 11 down to data item 9). The extracted three most significant elements of the second portion 240(B) of the first source vector register are concatenated with the least significant element (data item 12) of the carry data 246 stored in the scalar register, and the result of the concatenation is stored in a second portion 244(B) of the destination vector register. During the second processing tick, the processing circuit also carries the second portion 240(B) of the first source vector register (data item 11 down to data item 8) as carry data 248 to be stored in the scalar register. During a third processing tick, the processing circuit extracts the three most significant elements of a third portion 240(C) of the first source vector register (data item 7 down to data item 5). The extracted three most significant elements of the third portion 240(C) of the first source vector register are concatenated with the least significant element (data item 8) of the carry data 248 stored in the scalar register, and the result of the concatenation is stored in the third portion 244(C) of the destination vector register. During the third processing tick, the processing circuit also extracts the third portion 240(C) of the first source vector register (data item 7 down to data item 4) as the carry data 250 to be stored in the scalar register. In the fourth processing tick, the processing circuit extracts the three most significant elements (data item 3 down to data item 1) of the fourth portion (least significant portion) 210(D) of the first source vector register.The three most significant elements of the fourth portion 210 (D) of the first source vector register are cascaded with the least significant element (data item 4) of the carry data 250 stored in the scalar register, and the result of the cascade is stored in the fourth (least significant) portion 244 (D) of the destination vector register. In some alternative configurations, during the fourth processing beat, the processing circuit also extracts the fourth portion 240 (D) of the first source vector register as the carry data to be stored in the scalar register. This carry data is maintained and stored in the scalar register after executing the vector extraction and merging instructions. As shown in the previous figure, the position of the data element to be carried in the scalar register and the value of the unused element in the scalar register are arbitrary. For example, various combinations of other configurations are feasible, for example, storing elements to carry in the most significant element of the scalar register, and setting the unused elements to zero.

[0132] Fig.18A sequence of steps performed by a processing circuit in response to a vector extract and merge instruction is schematically shown. The process begins at step S170, where it is determined whether a vector extract and merge instruction specifying a first source vector register, a second source vector register, a destination vector register, and a control parameter has been received by a decoder circuit. If not, the process remains at step S170. At step S170, if it is determined that the decoder circuit has received the vector extract and merge instruction, the decoder circuit generates a control signal based on the vector extract and merge instruction. Next, the process proceeds to step S172, where, based on the control signal, a value K is set based on status information. If the status information indicates that a processing beat has not yet been performed, K is set to indicate a first processing beat. On the other hand, if the status information indicates that the first or more beats of a plurality of beats have been completed, K is set to indicate a first uncompleted beat of a plurality of beats. Next, the process proceeds to step S174, where the processing circuit extracts a bit specified by the control parameter from the Kth portion of the first source vector register. Next, the process proceeds to step S176, where it is determined whether K indicates that the portion is the first portion. If so, the process proceeds to step S178, where the processing circuit extracts one or more additional bits from the first portion of the second source vector register (as indicated by the control parameter). Next, the process proceeds to step S182. On the other hand, if it is determined in step S176 that K indicates that the Kth portion is not the first portion, the process proceeds to step S180, where one or more additional bits are obtained as one or more additional bits of the carry from the (K-1)th portion of the first source vector register. For example, if the processing circuit has sufficient hardware to perform more than 1 beat per tick, the carry may be an internal carry within the processing circuit. Alternatively, the carry data may be extracted from a scalar register, where the one or more additional bits have been stored as part of a previous beat of the vector extract and merge instruction. Next, the process proceeds to step S182. In step S182, the extracted one or more bits are concatenated with the one or more additional bits. Next, the process proceeds to step S184, where the result of the concatenation is stored in the Kth portion of the destination register. Next, the process proceeds to step S186, where it is determined whether the Kth portion is the last portion of the first source vector register. If so, the process returns to step S170. If in step S186, it is determined that the Kth portion is not the last portion, the process proceeds to step S188, where a carry is performed on at least one bit in the Kth portion of the first source vector register that has not yet been stored in the destination register for processing in the (K+1)th beat. For example, if the processing circuit has sufficient hardware to perform multiple (several) processing beats per tick, the carry may be an internal carry within the processing circuit. Alternatively, the carry may be performed by storing at least one bit in the Kth portion of the first source vector register to a scalar register specified in the vector extract and merge instruction.Next, the process proceeds to step S190, where K is incremented, and the process returns to step S174.

[0133] although Fig.18 The sequence of steps of has been described by sequentially increasing K, but in the case where hardware sufficient to perform multiple processing beats per tick is provided, the steps corresponding to each beat (each value of K) executed within the same tick are performed in parallel. For example, if beats K and K+1 are performed in parallel, step S174 will include extracting the bits specified by the control parameters from the Kth portion of the first source vector register, which is in parallel with extracting the bits specified by the control parameters for the (K+1)th portion of the first source vector register. One or more additional bits of each of the K and (K+1)th beats will then be extracted in parallel. Possibly, if K indicates that the Kth portion is the first portion, one or more additional bits of the Kth portion will be extracted from the second source vector register, which is in parallel with extracting one or more additional bits of the (K+1)th portion from the Kth portion of the first source vector register. The cascading step S182 will be performed in parallel for the Kth and (K+1)th portions, and the storing step S184 for the Kth and (K+1)th portions will be performed in parallel. The determination at step S186 as to whether K corresponds to the last portion will be made based on the highest portion (most significant portion) of K being processed, and if flow will continue to step S188 based on this determination, the carry will be extracted from the (K+1)th portion for processing in the subsequent tick. It will be appreciated by one of ordinary skill in the art that any number of processing ticks may be performed in parallel, depending on the details provided by the hardware.

[0134] Fig.19 A non-transitory computer-readable medium including computer-readable code for manufacturing a data processing device in various configurations according to the present technology is schematically shown. Manufacturing is performed based on computer-readable code 1002 stored on the non-transitory computer-readable medium 1000. The computer-readable code can be used in one or more stages of a semiconductor design and manufacturing process, which includes an electronic design automation (EDA) stage, to manufacture integrated circuits, which include devices that implement the concepts. The manufacturing process involves applying the computer-readable code 1002 directly to one or more programmable hardware units, such as a field programmable gate array (FPGA), to configure the FPGA to implement the configuration described above, or to facilitate the manufacture of the device as one or more integrated circuits, or to otherwise implement the configuration described above. By way of example, the manufactured design 1004 includes a device 30 having a register 32, a decoder circuit 38, and a processing circuit 40, as described with respect to Figure 7 However, the manufactured design may correspond to a design that can be as described with respect to Figures 9 to 18 The vector extract and merge instructions are implemented as described above. Figure 1, Figure 7 and Figure 8 Any of the circuits described in .

[0135] Fig. 20 The simulator that can be used is shown to be implemented. Although the examples described previously implement the present invention with the device and method for operating the specific processing hardware supporting the technology of interest, it is also possible to provide an instruction execution environment according to the examples described herein, which is implemented by using a computer program. Such computer programs are often called simulators because they provide a software-based implementation of the hardware architecture. The types of simulator computer programs include emulators, virtual machines, models, and binary converters (including dynamic binary converters). In general, the simulator is implemented to run on a host processor 515 that optionally runs a host operating system 510 and supports the simulator program 505. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that are executed at reasonable speeds, but such methods may be justified in some cases, such as when it is necessary to execute another processor native code because of compatibility or reuse reasons. For example, the simulator implementation may provide an instruction execution environment with additional functionality that is not supported by the host processor hardware, or provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques" (Robert Bedichek, Winter 1990 USENIX Conference, pages 53-63).

[0136] Where an implementation has been previously described with reference to a particular hardware architecture or feature, in a simulated implementation, equivalent functionality may be provided by a suitable software architecture or feature. For example, a particular circuit may be provided as computer program logic in a simulated implementation. Similarly, memory hardware (e.g., registers or caches) may be provided as software data structures in a simulated implementation. Where one or more of the hardware elements mentioned in the previously described examples are present in an arrangement on host hardware, some simulated implementations may utilize host hardware (where appropriate).

[0137] The simulator program 505 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provide a virtual hardware interface (instruction execution environment) to the target code 500 (which may include an application, an operating system, and a hypervisor) that is the same as the hardware interface of the hardware architecture modeled by the simulator program 505. Therefore, the program instructions of the target code 500 may be executed within the instruction execution environment using the simulator program 505, so that a host computer 515 that does not actually have the hardware features of the device 30 discussed above may emulate these features. The simulator program may include: a register logic component 532 that is used to emulate the behavior of the register 32; a decoder circuit logic component 538 that is used to emulate the behavior of the decoder circuit 38; and a processing logic component 540 that is used to emulate the behavior of the processing circuit 40. In addition, the simulator program may include logic to implement functions that can be described as described with respect to Figures 9 to 18 The vector extract and merge instructions are implemented as described above. Figure 1 , Figure 7 and Figure 8 Thus, the technology described herein is Fig. 20 In the example, the simulator program 505 can be executed in software.

[0138] Briefly stated as a whole, an apparatus, method, and medium are provided. The apparatus includes a decoder circuit for generating control signals in response to a vector extract and merge instruction, the vector extract and merge instruction specifying a control parameter, a first vector register, a second vector register, and a destination vector register. The apparatus includes a processing circuit for performing a plurality of processing beats in response to the control signals, each beat including processing corresponding to portions of at least the first vector register and the destination vector register. For the Kth beat, the processing includes: extracting bits specified by the control parameter from the Kth portion of the first vector register, concatenating the bits with additional bits, and storing the result in the Kth portion of the destination register. For the first portion, the additional bits are extracted from the first portion of the second vector register, otherwise from the (K-1)th portion of the first vector register.

[0139] In this application, the phrase "configured to..." is used to mean that the elements of a device have a configuration that enables the defined operation to be performed. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0140] Although illustrative configurations have been described in detail herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to these precise configurations and that various changes, additions and modifications may be effected thereto by those skilled in the art without departing from the scope and spirit of the present invention as defined in the appended claims. For example, various combinations of features of the independent claims with features of the dependent claims may be made without departing from the scope of the present invention.

Claims

1. A device, comprising: Multiple vector registers; a decoder circuit that generates a control signal in response to a vector extract and merge instruction that specifies a control parameter and specifies a first source vector register, a second source vector register, and a destination vector register as designated registers of the plurality of vector registers; and a processing circuit, the processing circuit executing a plurality of processing beats in response to the control signal, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, wherein the processing circuit is configured to set beat status information indicating which beats of the vector extract and merge instruction have been completed, and suppress the completed beats of the vector extract and merge instruction indicated as completed by the beat status information, Wherein the combined processing corresponding to the Kth beat of the Kth part of each of the designated registers comprises: extracting bits as specified by the control parameters from the Kth portion of the first source vector register, concatenating the extracted bits with one or more further bits, and storing the result of the concatenation in the Kth portion of the destination register; When the Kth portion is not the last portion of the designated register, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register to be processed in a (K+1)th beat of the plurality of beats; For the first portion of the designated register, the one or more additional bits are extracted from the first portion of the second source vector register; and For each portion other than the first portion of the designated register, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

2. The device according to claim 1, wherein: the decoder circuit being responsive to the vector extract and merge instruction specifying a scalar register; The plurality of beats includes a subset of one or more beats currently being executed, wherein the subset of beats currently being executed excludes the completed beat; and The processing circuit stores at least one carry data item in the scalar register in response to the control signal, the at least one carry data item including one or more bits to be carried between a subset of the one or more beats currently being executed and another subset of one or more beats in the multiple beats.

3. An apparatus according to claim 2, wherein for the first beat of the set of one or more beats currently being executed, and when the beat status information indicates that at least one beat is to be suppressed before executing the vector extract and merge instruction, the processing circuit retrieves the one or more additional bits from the scalar register in response to the control signal.

4. The device according to claim 3, wherein: The one or more bits to be carried include all bits of the portion of the first source vector register; and Retrieving the one or more additional bits from the scalar register includes retrieving a final subset of bits from the scalar register.

5. The device according to claim 3, wherein: The one or more bits to be carried include a final set of M bits from the portion of the first source vector register stored into the temporary set of bit positions in the scalar register; and Retrieving the one or more additional bits from the scalar register comprises retrieving bits from the temporary set of bit positions of the scalar register.

6. An apparatus according to any preceding claim, wherein cascading the extracted bits comprises storing the extracted bits in a first set of consecutive bit positions of the Kth part of the destination register, and storing the one or more additional bits in a second set of consecutive bit positions of the Kth part of the destination register.

7. The apparatus of claim 6, wherein the first set of consecutive bit positions and the second set of consecutive bit positions are non-overlapping bit positions.

8. An apparatus according to claim 6 or claim 7, wherein the first set of consecutive bit positions is the most significant set of bit positions of the Kth portion of the destination register, and the second set of consecutive bit positions is the least significant set of bit positions of the Kth portion of the destination register.

9. An apparatus according to claim 6 or claim 7, wherein the first set of consecutive bit positions is a least significant set of bit positions of the Kth portion of the destination register, and the second set of consecutive bit positions is a most significant set of bit positions of the Kth portion of the destination register.

10. An apparatus according to any preceding claim, wherein the extracted bits are extracted from consecutive bit positions of the Kth part of the first source vector register.

11. The apparatus of claim 10, wherein the consecutive bit positions are a least significant set of consecutive bit positions of the Kth portion of the first source vector register.

12. An apparatus according to any preceding claim, wherein: each portion of each of the designated registers is an N-bit portion; The control parameter indicates a displacement distance M of a specified number of bits; The one or more additional bits include M bits; and The extracted bits from the Kth portion of the first source vector register include N minus M bits.

13. The device according to claim 12, wherein: Each N-bit part is divided into multiple elements; The shift distance corresponds to an integer number of elements; and For the first portion of the designated register, the one or more further bits comprise a least significant subset of the first portion of the second source vector register excluding a least significant element.

14. The device according to claim 12, wherein: Each N-bit part is divided into multiple elements; The shift distance corresponds to an integer number of elements; and For the first portion of the designated register, the one or more further bits comprise a most significant subset of elements of the first portion of the second source vector register.

15. Apparatus according to any preceding claim, wherein the destination vector register is the second source vector register.

16. An apparatus according to any preceding claim, wherein the processing circuit is configured to process at least two of the plurality of beats in parallel.

17. An apparatus as claimed in any preceding claim, wherein the processing circuitry comprises insufficient hardware for executing all of the plurality of beats of the given vector instruction in parallel.

18. An apparatus according to any one of claims 1 to 16, wherein the processing circuit is configured to process all of the multiple beats of the given vector instruction in parallel.

19. An apparatus according to any preceding claim, wherein: the decoder circuit generating a data transfer control signal in response to a memory data transfer instruction adjacent to the vector extract and merge instruction in program counter order, the memory data transfer instruction specifying a memory address and a transfer register of the plurality of vector registers; The apparatus further comprises a data control circuit, the data control circuit executing a plurality of memory data transfer processing beats in response to the data transfer control signal, each beat comprising executing data transfer to a corresponding portion of the transfer register, and setting the beat status information indicating which beats of the data transfer instruction have been completed, and suppressing the completed beats of the memory data transfer instruction indicated as completed by the beat status information; and The apparatus is configured to execute a first subset of the plurality of memory data transfer processing beats corresponding to a first subset of the portion of the transfer register when the transfer register is one of the designated registers, in parallel with the processing circuit executing a second subset of the plurality of processing beats corresponding to a second subset of the portion of the transfer register in response to the vector extract and merge instruction.

20. Apparatus according to any preceding claim, wherein the control parameter is specified as an immediate value in the vector extract and merge instruction.

21. An apparatus as claimed in any preceding claim, wherein the first portion of the designated register is the least significant portion of the designated register and the last portion of the designated register is the most significant portion of the designated register.

22. A method of operating an apparatus comprising a plurality of vector registers, a decoder circuit and a processing circuit, the method comprising: generating control signals using the decoder circuit and in response to a vector extract and merge instruction that specifies control parameters and specifies a first source vector register, a second source vector register, and a destination vector register as designated registers of the plurality of vector registers; as well as executing a plurality of processing beats using the processing circuit and in response to the control signal, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, setting beat status information indicating which beats of the vector extract and merge instructions have been completed, and suppressing the completed beats of the vector extract and merge instructions indicated as completed by the beat status information, Wherein the combined processing corresponding to the Kth beat of the Kth part of each of the designated registers comprises: extracting bits specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more additional bits, and storing the result of the concatenation in the Kth portion of the destination register; When the Kth portion is not the last portion of the designated register, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register to be processed in a (K+1)th beat of the plurality of beats; For the first portion of the designated register, the one or more additional bits are extracted from the first portion of the second source vector register; and For each portion other than the first portion of the designated register, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

23. A computer readable medium storing computer readable code for manufacturing an apparatus, the apparatus comprising: Multiple vector registers; a decoder circuit that generates a control signal in response to a vector extract and merge instruction that specifies a control parameter and specifies a first source vector register, a second source vector register, and a destination vector register as designated registers of the plurality of vector registers; and a processing circuit, the processing circuit executing a plurality of processing beats in response to the control signal, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, wherein the processing circuit is configured to set beat status information indicating which beats of the vector extract and merge instruction have been completed, and suppress the completed beats of the vector extract and merge instruction indicated as completed by the beat status information, Wherein the combined processing corresponding to the Kth beat of the Kth part of each of the designated registers comprises: extracting bits specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more additional bits, and storing the result of the concatenation in the Kth portion of the destination register; When the Kth portion is not the last portion of the designated register, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register to be processed in a (K+1)th beat of the plurality of beats; For the first portion of the designated register, the one or more additional bits are extracted from the first portion of the second source vector register; and For each portion other than the first portion of the designated register, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

24. A computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: a register logic unit, the register logic unit comprising a plurality of vector registers; a decoder logic component that generates a control signal in response to a vector extract and merge instruction that specifies a control parameter and specifies a first source vector register, a second source vector register, and a destination vector register as designated registers of the plurality of vector registers; and a processing logic unit, the processing logic unit executing a plurality of processing beats in response to the control signal, each beat including combined processing corresponding to at least a portion of the first source vector register and the destination vector register, wherein the processing logic unit is configured to set beat status information indicating which beats of the vector extract and merge instructions have been completed, and suppress the completed beats of the vector extract and merge instructions indicated as completed by the beat status information, Wherein the combined processing corresponding to the Kth beat of the Kth part of each of the designated registers comprises: extracting bits specified by the control parameter from the Kth portion of the first source vector register, concatenating the extracted bits with one or more additional bits, and storing the result of the concatenation in the Kth portion of the destination register; When the Kth portion is not the last portion of the designated register, carry at least one bit in the Kth portion of the first source vector register that is not stored in the destination register to be processed in a (K+1)th beat of the plurality of beats; For the first portion of the designated register, the one or more additional bits are extracted from the first portion of the second source vector register; and For each portion other than the first portion of the designated register, the one or more additional bits are carried from the (K-1)th portion of the first source vector register.

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