Self-aligned JFET device

Abstract

JFET transistor devices (100) with reduced pitch may be fabricated using self-alignment techniques while avoiding misalignment that may lead to a decrease in breakdown voltage and / or an increase in RDSon. Thus, compared to conventional devices, the described devices provide additional current channels, increased current, and reduced RDSon for a given active region and gate voltage, while maintaining high BVgs values.

Description

Technical Field

[0001] This specification relates to semiconductor devices. Background Art

[0002] In many transistor-based devices, multiple transistor cells are connected within the active region of the device. Each individual transistor cell can be considered a unit cell for the entire device, and the width of the unit cell can be referred to as the pitch of the device. The operating aspects of the entire device can be determined by the characteristics of the individual transistors included therein and the aggregate or composite characteristics of the multiple transistor cells within the active region.

[0003] For example, the on-state resistance of a transistor (also called source-drain on-state resistance or R DSon ) may indicate the amount of current (e.g., drain current or Id) present for a corresponding drain voltage (e.g., drain-source voltage or Vds). The gate-source breakdown voltage or BVgs may refer to the reverse voltage at which a transistor exhibits a sudden rise in reverse current when the transistor is in the off state.

[0004] Reducing the size of each unit cell within a given active area of ​​a transistor device (i.e., reducing the pitch) provides more individual transistor cells within the active area, thus conceptually (for a given gate voltage) providing additional current channels, increased current, and R DSon However, it may be difficult or impossible to reduce the device pitch to a desired level using conventional techniques. Furthermore, attempts to reduce the pitch of conventional device structures may result in undesirable consequences if any misalignment occurs. For example, such misalignment may result in performance degradation, such as a reduction in BVgs of the overall device or R DSon increases, and yield and reliability decreases. Summary of the invention

[0005] According to one general aspect, a junction field effect transistor (JFET) semiconductor device may include: a substrate including a drain region of the JFET; a drift region disposed on the substrate; and a lower gate disposed on the drift region. The JFET semiconductor device may include a source region having a lower source region disposed on the lower gate and extending laterally beyond the lower gate, and an upper source region disposed on the lower source region; and an upper gate formed on the lower source region and at least partially surrounding the upper source region and extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.

[0006] According to another general aspect, a junction field effect transistor (JFET) semiconductor device may include: a substrate including a drain region of the JFET semiconductor device; a drift region disposed on the substrate; and a plurality of unit cells disposed in a grid on the drift region. Each unit cell may include: a lower gate disposed on the drift region; a source region having a lower source region disposed on the lower gate and extending laterally beyond the lower gate, and an upper source region disposed on the lower source region; and an upper gate formed on the lower source region and at least partially surrounding the upper source region and extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.

[0007] According to another general aspect, a method of manufacturing a semiconductor device may include: forming a lower source region implant and an upper gate implant through a first opening in a mask disposed on a substrate; forming a first spacer on a sidewall of the mask to define a second opening smaller than the first opening; and forming a lower gate through the second opening. The method may include: forming a second spacer on the first spacer to define a third opening smaller than the second opening; and forming an upper source region through the third opening and within the upper gate implant, thereby defining a remaining portion of the upper gate implant as an upper gate of a junction field effect transistor (JFET), wherein the substrate provides a drain of the JFET.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description that follows. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top view of a self-aligned JFET device.

[0010] Figure 2 Shows a cross section along AA Figure 1 Cross-sectional view of a self-aligned JFET device.

[0011] Figure 3 The cross section along BB is shown. Figure 1 Cross-sectional view of a self-aligned JFET device.

[0012] Figure 4 The cross section along BB is shown. Figure 1 A cross-sectional view of a first alternative implementation of a self-aligned JFET device.

[0013] Figure 5 The cross section along BB is shown. Figure 1 A cross-sectional view of a second alternative implementation of a self-aligned JFET device.

[0014] Figure 6 Shown for manufacturing Figure 1 First cross-sectional view of the fabrication process of the self-aligned JFET.

[0015] Figure 7 Shown for manufacturing Figure 1 A second cross-sectional view of the self-aligned JFET manufacturing process.

[0016] Figure 8 Shown for manufacturing Figure 1 A third cross-sectional view of the manufacturing process of the self-aligned JFET.

[0017] Fig. 9 Shown for manufacturing Figure 1 FIG. 4 is a fourth cross-sectional view of the manufacturing process of the self-aligned JFET.

[0018] Fig.10 Shown for manufacturing Figure 1 Fifth cross-sectional view of the self-aligned JFET manufacturing process.

[0019] Fig.11 Shown for manufacturing Figure 1 FIG. 6 is a sixth cross-sectional view of the manufacturing process of the self-aligned JFET.

[0020] Fig.12 Shown for manufacturing Figure 1 FIG. 7 is a seventh cross-sectional view of the manufacturing process of the self-aligned JFET.

[0021] FIG. 13A to FIG. 13C Shown is a method for providing Figure 7 , Fig. 9 and Fig.11 A cross-sectional view of an example manufacturing process of a self-aligned spacer in FIG.

[0022] Fig.14 yes Figures 6 to 12 A first cross-sectional view of process modeling of a manufacturing process of FIG. 1 , the first cross-sectional view showing an upper gate implantation process.

[0023] Fig.15 yes Figures 6 to 12 A second cross-sectional view of process modeling of a manufacturing process of FIG. 1 , wherein the second cross-sectional view illustrates a channel implantation process.

[0024] Fig.16 yes Figures 6 to 12 A third cross-sectional view of process modeling of a manufacturing process of FIG. 4 , the third cross-sectional view illustrating a lower gate implantation process.

[0025] Fig.17 yes Figures 6 to 12 A fourth cross-sectional view of process modeling of a manufacturing process of FIG. 4 , wherein the fourth cross-sectional view illustrates a low-doped region implantation process.

[0026] Fig.18yes Figures 6 to 12 A fifth cross-sectional view of process modeling of a manufacturing process of FIG. 1 , wherein the fifth cross-sectional view shows a source region implantation process.

[0027] Fig.19 yes Figures 6 to 12 0026] A sixth cross-sectional view of process modeling of a manufacturing process of FIG. 1, the sixth cross-sectional view showing a partially completed JFET device cell.

[0028] Fig. 20 is a graph showing the device spacing and R DSon A graph showing the relationship between .

[0029] Fig.21 It is shown Figure 1 A graph showing the relationship between the gate-source breakdown voltage and the low-doped region of a JFET device.

[0030] Fig.22A and Fig. 22B yes Figure 1 and Fig.14 Figure 2. Cross-sectional view of process modeling of a JFET device showing current flow with and without gate alignment of the upper and lower gates.

[0031] Fig.23 is to show the upper gate alignment / lower gate alignment with R DSon A graph showing the relationship between .

[0032] Fig.24 is shown for making about Figures 1 to 23 A flow chart of an example implementation of a JFET device is described. DETAILED DESCRIPTION

[0033] The present disclosure relates to JFET transistor devices with reduced pitch (e.g., less than 5 microns). JFET transistor devices can be fabricated using self-aligned techniques that enable device pitches to be smaller than those obtainable using conventional mask-based lithography techniques while avoiding R DSon Increased misalignment. Thus, the described device provides additional current channels (for a given active area and gate voltage) and increased current and reduced R compared to conventional devices. DSon , while maintaining an acceptable BV value.

[0034] Figure 1 A top view of a self-aligned JFET device including a plurality of individual JFET device cells, each of which is referred to herein as a JFET 100, is shown. Figure 1In the example of FIG. 1 , a plurality of source regions or source region grids 102 having a first conductivity type (e.g., n-type) are each shown to be at least partially surrounded by a low-doped BVgs enhancement region 106 of the first conductivity type. That is, the BVgs enhancement region 106 should be understood as having a doping lower than the doping of the source regions 102, as explained in more detail below. For example, the BVgs enhancement region 106 may have a doping level that is 20% or less (e.g., 10% or 15%) of the doping of the source regions 102.

[0035] Each BVgs enhancement region 106 is at least partially surrounded by an upper gate 104 having a second conductivity type (eg, p-type). Figure 2 The lower gate 204 in Figure 1 is not visible in the top view, but is shown below, for example, in Figures 2 to 5 In other words, Figure 1 In the top view of FIG. 1 , the upper gate 104, the BVgs enhancement region 106 and the source region 102 are located at the lower gate (eg Figure 2 The lower gate 204 is vertically above the lower gate 204 and hides the view of the lower gate.

[0036] In this specification, the vertical direction V refers to a plane surface connecting and perpendicular to the upper gate 104 and the lower gate 204 and the underlying substrate (eg Figure 2 The z-axis of the planar surface of the substrate 206) is such that the vertical direction V extends to Figure 1 The lateral direction L refers to a direction perpendicular to the vertical direction V along the x-axis and / or the y-axis.

[0037] As shown and explained in detail below, Figure 1 The structure thus forms a JFET 100 in which a current channel is formed between the upper gate 104 and the lower gate 204. Therefore, current flows from the source region 102, initially in the lateral direction between the upper gate 104 and the lower gate 204, and then in the vertical direction to the Figure 1 of paper and flows to Figure 1 The drain of a JFET device (e.g. Figure 2 The drain 208, at Figure 1 not visible in the top view of the image).

[0038] To control this current flow, a gate contact 108 of the second conductivity type is formed that is connected to both the upper gate 104 and the lower gate 204. Thus, a single common gate voltage can be applied to control Figure 1 All individual JFET cells 100 of the JFET device.

[0039] In addition, Figure 1In the embodiment, a termination region 110 having a second conductivity type is defined adjacent to an active region 112 in which various JFET cells are formed. It will be appreciated that Figure 1 is a partial view of the active area 112 and the termination region 110. In an example implementation, the termination region 110 completely surrounds the active area 112. For example, the termination region 110 can define the outer perimeter of the active area 112. In some implementations, the termination region 110 can include implants and / or trench structures to terminate the active area 112. Figure 1 The termination region 110 may help maintain the electric fields associated with the operation of the various JFETs within the active region 112 of the semiconductor device. Figure 1 The breakdown voltage of the JFET is close to a maximum BV limited by the material properties. For example, the termination region 110 can prevent breakdown below the rated voltage of the JFET 100, for example, by terminating high electric fields during operation of the JFET.

[0040] Therefore, in Figure 1 In FIG. 1 , each JFET cell 100 defines a unit cell of a JFET device, wherein a row of unit cells extends in the x-direction. Figure 1 As shown in , the pitch of a JFET device may be defined as the distance along the y-axis between adjacent rows of unit cells, or alternatively as the width of a unit cell in the y-direction.

[0041] Figure 1 The cross-section lines of views AA and BB are shown, wherein Figure 2 Shows a cross section along AA Figure 1 a first cross-sectional view of the JFET (ie, a cross-section taken along the y-axis and viewed in the x-direction), and Figure 3 The cross section along BB is shown. Figure 1 0048. A second cross-sectional view of the JFET (ie, a cross-section taken along the x-axis and viewed in the y-direction) of FIG.

[0042] More specifically, in Figure 2 , the source region 102 is shown to include an upper source region 102a and a lower source region 102b. As shown, the upper source region 102a is at least partially surrounded by a BVgs enhancement region 106, which itself is at least partially surrounded by an upper gate 104. The lower source region 102b extends along the lower gate 204 under the upper gate 104, the BVgs enhancement region 106 and the upper source region 102a and defines a channel region L ch , as described in more detail below.

[0043] Further in Figure 2, the drain contact 208 has a drain region formed in a substrate 206 having a first conductivity type (e.g., n-type). The voltage blocking drift region 202 is formed on the substrate 206, for example as an epitaxial layer, and may include a relatively highly doped region 202a. The drift region 202 and the substrate 206 may be formed using, for example, silicon carbide (SiC), Si, gallium nitride (GaN), aluminum nitride (AlN), or any other semiconductor material.

[0044] Figure 2 Further shown is source metal 214, which is shown in FIG. Figure 1 As shown, the source contact 212 facilitates electrical contact between the source metal 214 and the source region 102 , while the dielectric layer 216 provides insulation between the source metal 214 and the BVgs enhancement region 106 , the upper gate 104 , and the drift region 202 .

[0045] In operation, certain gate and drain voltages are applied so that current 211 (shown as drain current Id) can flow through the upper source region 102a and laterally through the channel region L ch And flows vertically through the drift region 202 and reaches the drain substrate 206. More specifically, as shown, a channel region L may be defined in a lateral direction between an inner edge of the upper gate adjacent to the BVgs enhancement region 106 and an outer edge of the lower gate 204. ch .

[0046] Still in Figure 2 Middle, lateral distance L go refers to the gate offset between the edge of the upper gate 104 and the edge of the lower gate 204. That is, as shown, the outer edge of the upper gate 104 can extend beyond the outer edge of the lower gate 204 by a distance L go As described in detail below, for example with respect to FIGS. 22 and Fig.23 , gate offset L go Prevent channel L ch The depletion region in the channel extends beyond the L ch , the extension of the depletion region beyond the channel will have the unintended and undesirable effect of turning off the JFET cell 100. For example, when the JFET cell 100 is designed as a normally-on device, too small a gate offset L go Will allow channel L ch In other words, reducing L go Often increases R DSon ,like Fig.23In some embodiments, the upper gate 104 and the lower gate 204 may not have a structural offset, but may be offset during the manufacturing process (e.g., using a specified spacer) to account for the wider extension of the lower gate 204. That is, the lateral extension of the buried lower gate 204 formed using a higher ion implantation energy may be larger than the energy used for the ion implantation of the upper gate 104. In example implementations, the spacer width, and therefore the resulting offset, may be as small as 0um (no offset) or as large as 0.7um.

[0047] Figure 2 Further shown is the positioning of the BVgs enhancement region 106 between the upper gate 104 and the upper source region 102a. Thus, the BVgs enhancement region 106 prevents contact between the relatively highly doped upper source region and the relatively highly doped upper gate 104, thereby allowing a higher source doping with a reduced source contact resistivity to be achieved compared to the source contact resistivity that could be achieved in a device without the BVgs enhancement region. Otherwise, contact between the two highly doped regions 102a, 104 may result in a lower BVgs for the JFET 100. However, by including the BVgs enhancement region 106 as shown, contact between the two highly doped regions 102a, 104 is prevented and the BVgs of the device is increased.

[0048] Figure 3 The cross section along BB is shown. Figure 1 A cross-sectional view of a self-aligned JFET device. Figure 3 In the example of FIG. 1 , gate contact 312 and gate metal 314 (shown in FIG. 1 for top view visibility) are shown in FIG. Figure 1 The gate electrode 104 (omitted in the figure) is shown as being positioned to make electrical contact with both the upper gate 104 and the lower gate 204 using the gate contact region 108a. The insulating dielectric layer 216 is further shown to provide insulation between the source metal 214 and the gate metal 314.

[0049] exist Figure 3 In the example of JFET 100, gate contact region 108a includes an overlap region 302 that partially overlaps upper gate 104, channel region, and lower gate 204. For example, gate contact region 108a may be spaced from upper gate 104 and channel region by a distance (d < L ) less than the channel length of JFET 100. ch ) partially overlaps and thus does not contact the higher doped portion of the source region.

[0050] exist Figure 4In the example of , an alternative implementation of the gate contact region 108, shown as the gate contact region 108b, is embedded into the JFET cell 100 (i.e., embedded into the JFET cell) to define an overlap region 402. More specifically, as shown, the gate contact region 108b defines the overlap region 402 as extending through the upper gate 104, the lower source region 102b, and the BVgs enhancement region 106. Thus, Figure 4 The gate contact region 108b extends through the channel region L ch And enters the upper source region 102a. In this embodiment, the doping in the gate contact region compensates the doping of the source region. Although this simplifies the device manufacturing process, the source region doping can be limited to avoid degradation of BVgs.

[0051] exist Figure 5 In an alternative example of , the gate contact region 108c extends into the upper gate 104, the lower gate 204, and the lower source region 102b without extending into the upper source region 102a to define an overlap region 502. In other words, the gate contact region 108c is embedded in the extended JFET cell without overlapping the upper source region 102a. For example, the distance between the gate contact region 108c and the upper source region 102a may be between 0.5 μm and 5 μm.

[0052] Therefore, the gate contact region 108c extends to the channel L ch However, in Figure 5 In the example, with Figure 4 Compared to the example of , the BVgs enhancement region 106 is not included, and the gate contact region 108c can be further extended into each JFET cell and closer to the upper source region 102a. Figure 5 In the example of FIG. 5 , gate-source leakage may be reduced by the structure shown, where the upper source region 102 a does not overlap with the gate contact region 108 c (ie, the overlap region 502 does not extend into the upper source region 102 a ).

[0053] Figures 6 to 12 Shown for manufacturing Figure 1 A cross-sectional view of example stages of a fabrication process for a self-aligned JFET structure. Figure 6 In the example, the first mask 606 is used to process Figure 2 As shown, a first mask 606 may be used to define an opening through which a channel implant 602 and an upper gate implant 604 may be formed. For example, SiO2, polysilicon, silicon nitride (e.g., Si3N4), or a combination thereof may be used to form the first mask 606. The opening defined by the mask 606 may be, for example, 4.5 microns or less.

[0054] The channel implant 602 and the upper gate implant 604 may be formed using ion implantation or any suitable technique. As will be apparent from the following description, the channel implant 602 may be used to form Figures 1 to 5 The lower source region 102b and the upper gate implant 604 may be used to form Figures 1 to 5 The upper gate 104 is formed by a plurality of electrodes.

[0055] exist Figure 7 In the embodiment, a first spacer 702 is formed on the sidewall of the first mask 606. FIG. 13A to FIG. 13C Techniques for forming the first spacer 702 (and subsequent spacers) are described. The first spacer 702 is thus defined so that it is possible to form Figure 8 The lower gate 804 may be formed by a self-aligned mask (which may be referred to as a second mask) of the lower gate 804 shown in FIG. 8 . For example, the lower gate 804 may be formed using local ion implantation using the first spacer 702 as a second mask.

[0056] Because the first spacer 702 effectively makes the opening in the first mask 606 smaller than Figure 6 The lower gate 804 can be offset from the upper gate 604 by L if necessary. go Offset, as described above Figure 2 Therefore, it will be appreciated that controlling the thickness of the first spacer 702 thus controls or affects the gate offset L go range.

[0057] In more detail, the formation of the lower gate 804 may require or induce relatively high energy dopants below the channel implant 602. Therefore, these high energy dopants are likely to diffuse laterally after forming (e.g., implanting) the lower gate 804. As mentioned above and described below with respect to Fig.22A , Fig. 22B and Fig.23 In detail, this diffusion can cause the expansion of the lower gate 804 and the L go In this case, the channel L ch The depletion of L can extend beyond the lower gate 804 and can block current through the channel. Therefore, the formation of the spacer 702 and the lower gate 804 can be calibrated to ensure that the desired L go If the extension of the lower gate 804 is comparable to the extension of the upper gate 604, some embodiments may omit the first spacer formation (ie, the lower gate 804 may be formed using the same mask as the upper gate 604).

[0058] exist Fig. 9 In the embodiment of the present invention, the second spacer 902 is formed on the sidewalls of the first spacer (second mask) 702, and thus defines the third mask. Fig.10 As shown in FIG. 1 , the second spacer 902 may be used to implant (eg, using localized ion implantation) or otherwise form or define the source region portion 1002 and the lowly doped region 1006 .

[0059] For example, in Fig.10 In the embodiment, as described above, an upper gate 604 having the second conductivity type has been formed. Using the second spacer 902, an implant having the first conductivity type can be performed to compensate the exposed portion of the upper gate 604 from the second conductivity to the first conductivity at a relatively low doping (i.e., forming a low-doped region by compensating the second conductivity type with doping of the first conductivity type), while maintaining the source region portion 1002 at the same conductivity type as the first conductivity type. Figure 6 The existing channel is implanted at a consistent doping level with the source region 602 .

[0060] exist Fig.11 In the embodiment of the present invention, the third spacer 1102 is formed on the sidewall of the second spacer (third mask) 902, and the fourth mask is defined thereby. Fig.12 As shown in FIG. 1 , the third spacer 1102 may be used to implant or otherwise form or define an upper source region 1202a that is spaced apart from a lower source region 1202b (received by Figure 6 The earlier source region 602 and Fig.10 The source region 1202 is defined together with the low-doped region 1006. Meanwhile, the remaining portion of the low-doped region 1006 forms a BVgs enhancement region 1206.

[0061] Therefore, in Figures 6 to 12 In the example of FIG. 1 , spacers 702, 902, 1102 effectively form a self-aligned mask, so that a separate photolithography mask (such as first mask 606) is not required. In addition, by using spacers from a previous fabrication step as a self-aligned mask in a subsequent fabrication step, it is possible to form the self-aligned mask with greater accuracy than is possible using conventional techniques. Figures 1 to 5 For example, the described techniques do not need to take into account the misalignment margin of conventional masks, which may be, for example, 0.3 microns or more.

[0062] For example, the first spacer (second mask) 702 may have a width of up to 0.5 microns. The second spacer (third mask) 902 may have a width of up to 0.5 microns. The third spacer (fourth mask) 1102 may have a width of up to 0.2 microns. The aforementioned widths are provided for example, and different widths may be used, and one or more of the spacers / masks 702, 902, 1102 may be omitted. The various spacers / masks 702, 902, 1102 may be formed using, for example, SiO2, polysilicon, Si3N4, or combinations thereof.

[0063] Thus, for example, using the techniques described herein, one can make Figure 1 The pitch of the device is, for example, less than 5 microns, such as 3 microns or 2 microns or less. Figure 1 , the active area 112 can accommodate a larger number of JFET cells (ie, more JFET device cells 100). Therefore, as mentioned above and with reference to Figure 2 and drain current 211, compared with conventional technology, Figures 6 to 12 Technology achieves more current and reduced R DSon . For example, the following Fig. 20 Explain and describe the spacing and R DSon A simplified example of the relationship between .

[0064] FIG. 13A to FIG. 13C Shown is a method for providing Figure 7 , Fig. 9 and Fig.11 A cross-sectional view of an example fabrication process of a self-aligned spacer in FIG. Fig.13A In the embodiment, a mask 1306 is formed on an epitaxial layer 1304 formed on a substrate 1302. The mask 1306 represents a photolithography mask, such as Figure 6 Mask 606.

[0065] exist Fig. 13B In the embodiment, a conformal spacer material 1308 is deposited over the epitaxial layer 1304 and the mask 1306. Subsequently, in Fig. 13C , an anisotropic etch (etch back) process is performed to leave spacers 1310 on the sidewalls of mask 1306, as shown. Thus, spacers 1310 illustrate the Figures 7 to 12 The width of the spacer 1310 may be controlled by controlling the process parameters of the etching process.

[0066] Fig.14 yes Figures 6 to 12 The first cross-sectional view of the process modeling of the manufacturing process of the present invention shows the upper gate injection process. That is, Fig.14 Shows Figure 6 , where a mask 606 may be used to form an upper gate implant 604 using a p-type dopant, such as aluminum (Al).

[0067] Fig.15 yes Figures 6 to 12 A second cross-sectional view of process modeling of a manufacturing process of FIG. 1 , wherein the second cross-sectional view illustrates a channel implantation process. Fig.15 Shows Figure 6 , showing an example implantation of channel implant 602.

[0068] Fig.16 yes Figures 6 to 12 A third cross-sectional view of process modeling of a manufacturing process of FIG. 4 , the third cross-sectional view illustrating a lower gate implantation process. Fig.16 Shows Figure 7 and Figure 8 A more detailed example of where spacer 702 is used to form a lower gate implant 804.

[0069] Fig.17 yes Figures 6 to 12 A fourth cross-sectional view of process modeling of a manufacturing process of FIG. 4 , wherein the fourth cross-sectional view illustrates a low-doped region implantation process. Fig.17 Shows Fig. 9 and Fig.10 A more detailed example of where spacer 902 is used to form a low doped region 1006.

[0070] Fig.18 yes Figures 6 to 12 A fifth cross-sectional view of process modeling of a manufacturing process of FIG. 1 , wherein the fifth cross-sectional view shows a source region implantation process. Fig.18 Shows Fig.11 and Fig.12 A more detailed example of where spacer 1102 is used to form source region implant 1202.

[0071] Fig.19 yes Figures 6 to 12 FIG. 6 is a sixth cross-sectional view of process modeling of a manufacturing process, the sixth cross-sectional view showing a completed JFET device. Fig.19 A JFET device with net active doping is shown.

[0072] Fig. 20 is a graph showing the device spacing and R DSon As shown by line 2002, the decrease in spacing is related to R DSon is related to the reduction of .

[0073] Fig.21 It is shown Figure 1 A graph showing the relationship between the BVgs of a JFET device and a low-doped region (eg, the BVgs enhancement region 106). Fig.21 As shown in FIG. 1 , I to V curves 2102, 2104, 2106 show that as the width W_BVER of the BV enhancement region 106 increases, BVgs (e.g., the maximum rating of Vgs) also increases. As mentioned above, because the gate contact region 108 and the source region 102 are highly doped, the direct contact of these regions can allow (e.g., due to tunneling) to form a pn junction with a low BV. Therefore, these regions are separated by a low doped region, resulting in the BVgs enhancement shown and described.

[0074] Fig.22A and Fig. 22B yes Figure 1 and Fig.14 A cross-sectional view of process modeling of a JFET device of FIG. 1 , which shows the current flow as a function of the gate alignment of the upper gate 104 and the lower gate 204. Specifically, Fig.22A shows a sufficient positive gate offset L go This enables normally-on JFET operation, where the upper gate 104 extends laterally beyond the lower gate 204, where current flows through the current channel L ch As shown, the depletion region 2202 does not extend beyond the channel.

[0075] However, in Fig. 22B In, when L go Very small or when there is negative L go When (i.e., the lower gate 204 extends laterally beyond the upper gate 104), the depletion region 2204 extends beyond the channel region L ch The expansion of the depletion region 2204 prevents current from flowing through the channel L ch , so that R DSon increases, turning off the JFET device and preventing the normally-on operation of the JFET device.

[0076] As described herein, the desired gate offset L may be maintained by go The lower gate 204 is formed in such a manner as to maintain the normally-on operation of the JFET device. Figure 7 and Figure 8 , the thickness of the spacer 702 and the implant energy level of the lower gate implant 804 can be calibrated to ensure that the gate offset L is maintained. go For example, L go It can be maintained at 0.05 microns or less, such as 0.01 microns.

[0077] Fig.23 It is further shown that L go With R DSon As shown by line 2302, L go The increase in R DSon The corresponding decrease in ch The corresponding increase in current.

[0078] Fig.24 is shown for making about Figures 1 to 23 A flowchart of an example implementation of a JFET device is described. Fig.24In the example of , a lower source region implant (which includes a channel region) and an upper gate implant (2402) are formed through a first opening in a mask disposed over a drift region, which itself is disposed over a substrate, as described and shown above. A first spacer is formed on the sidewalls of the mask to reduce the first opening (2404), i.e., to form a second opening having a reduced size compared to the first opening. Subsequently, a lower gate implant (2406) can be formed through the second opening and disposed over the drift region such that the lower source region is disposed over the lower gate implant. As described above, the formation (e.g., implantation) of the lower gate implant can be calibrated to ensure that a desired gate offset L between the upper gate implants is maintained. go .

[0079] A second spacer may be formed on the first spacer to further reduce the size of the opening (2408), i.e., to form a third opening. A low-doped region may be formed through the third opening and disposed on the lower source region while maintaining the doping level of the lower source region implant (e.g., by doping compensation) (2410).

[0080] A third spacer may be formed on the second spacer to further reduce the size of the opening (2412), i.e., to form a fourth opening. An upper source region implant may be formed through the fourth opening to define an upper source region and a BVgs enhancement region and an upper gate disposed on the lower source region (2414). That is, the upper gate may be defined as the remaining portion of the upper gate implant formed through the first opening in operation 2402.

[0081] therefore, Figures 1 to 24 An example implementation of a JFET device comprising a plurality of unit cells of individual JFET cells is shown, wherein the unit cells are arranged in a grid arrangement such that rows or sections of unit cells have alternating gate-source contact layouts, and the pitch of the JFET device may be 5 microns or less, such as 2 or 3 microns. Such a JFET device may be constructed in a self-aligned manner, wherein spacers formed in one operation may be used as an actual mask during an implantation step of a subsequent operation.

[0082] Many variations of the described embodiments may also be provided. For example, the described embodiments include a gate source contact 108 connected to both the upper gate 104 and the lower gate 204 and not connected to the source region 102. However, other configurations are possible. For example, the lower gate 204 may be connected to the source contact to form an integrated body diode, in which case the channel conduction may be completely controlled by the upper gate 104.

[0083] In a first example implementation, referred to as Example 1, a junction field effect transistor (JFET) semiconductor device includes:

[0084] a substrate including a drain region of the JFET;

[0085] a drift region, wherein the drift region is disposed on the substrate;

[0086] A lower gate, wherein the lower gate is arranged on the drift region;

[0087] a source region having a lower source region disposed on the lower gate and extending laterally beyond the lower gate, and an upper source region disposed on the lower source region; and

[0088] An upper gate is formed on the lower source region and at least partially surrounds the upper source region and extends laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.

[0089] Example 2 of the JFET semiconductor device of Example 1 further includes a gate contact region that contacts the upper gate and the lower gate to provide a common gate contact for the JFET semiconductor device.

[0090] Example 3 includes the JFET semiconductor device of Example 2, wherein a channel length of the JFET semiconductor device is defined in the lower source region as an overlap of an outer edge of the lower gate and an inner edge of the upper gate.

[0091] Example 4 includes the JFET semiconductor device of Example 3, wherein the gate contact region partially overlaps the upper gate by a distance less than the channel length.

[0092] Example 5 includes the JFET semiconductor device of Example 2, wherein the gate contact region partially overlaps the lower source region.

[0093] Example 6 includes the JFET semiconductor device of Example 1, wherein a gate-source breakdown voltage (BVgs) enhancement region is formed on the lower source region and disposed between the upper source region and the upper gate.

[0094] Example 7 includes the JFET semiconductor device of Example 6, wherein the BVgs enhancement region has a doping level that is 20% or less of a doping level of the upper source region.

[0095] Example 8 includes the JFET semiconductor device of Example 1, wherein the substrate and the drift region include silicon carbide (SiC).

[0096] Example 9 includes the JFET semiconductor device of Example 1, wherein the gate offset is 0.05 microns or less.

[0097] Example 10 includes the JFET semiconductor device of Example 1, wherein the JFET semiconductor device is normally-on.

[0098] In an eleventh example implementation referred to as Example 11, a junction field effect transistor (JFET) semiconductor device includes:

[0099] A substrate, the substrate comprising a drain region of the JFET semiconductor device;

[0100] a drift region disposed on the substrate; and

[0101] A plurality of unit cells are arranged in a grid form on the drift region, wherein each unit cell includes

[0102] A lower gate, wherein the lower gate is arranged on the drift region;

[0103] a source region having a lower source region disposed on the lower gate and extending laterally beyond the lower gate, and an upper source region disposed on the lower source region; and

[0104] An upper gate is formed on the lower source region and at least partially surrounds the upper source region and extends laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.

[0105] Example 12 includes the JFET semiconductor device of Example 11, wherein a pitch defined between adjacent unit cells of the JFET semiconductor device is 5 micrometers or less.

[0106] Example 13 includes a JFET semiconductor device according to Example 11, wherein each unit cell includes a gate-source breakdown voltage (BVgs) enhancement region, and the gate-source breakdown voltage (BVgs) enhancement region is formed on the lower source region and between the upper source region and the upper gate.

[0107] Example 14 includes the JFET semiconductor device of Example 11, wherein the gate offset is 0.05 microns or less.

[0108] Example 15 includes the JFET semiconductor device of Example 11, wherein each unit cell includes a gate contact region that contacts the upper gate and the lower gate to provide a common gate contact for the JFET semiconductor device.

[0109] In a sixteenth example implementation referred to as Example 16, a method of manufacturing a semiconductor device includes:

[0110] forming a lower source region implant and an upper gate implant through a first opening in a mask disposed on the substrate;

[0111] forming a first spacer on a sidewall of the mask to define a second opening smaller than the first opening;

[0112] forming a lower gate through the second opening;

[0113] A second spacer is formed on the first spacer to define a second opening smaller than the second opening.

[0114] three openings; and

[0115] forming an upper source region through the third opening and within the upper gate implant, thereby defining a remaining portion of the upper gate implant as an upper gate of a junction field effect transistor (JFET),

[0116] The substrate provides a drain of the JFET.

[0117] Example 17 includes the method of Example 16, wherein forming the lower source region implant and the upper gate implant includes:

[0118] The lower source region implant is formed under the upper gate implant.

[0119] Example 18 includes the method of Example 16, wherein forming the lower gate through the second opening includes:

[0120] The lower gate is formed below the lower source region implant, wherein the upper gate implant extends laterally beyond the lower gate to define a gate offset between the upper gate implant and the lower gate.

[0121] Example 19 includes the method according to Example 16, further comprising:

[0122] forming a third spacer on the first spacer to define a fourth opening having a size between a size of the second opening and a size of the third opening; and

[0123] A low-doped region is formed through the third opening before forming the second spacer.

[0124] Example 17 includes the method of Example 19, wherein forming the upper source region maintains a portion of the lowly doped region at a gate-source breakdown voltage (BV gs ) enhancement zone.

[0125] It should be understood that in the foregoing description, when an element such as a layer, a region, a substrate or a part is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, the element shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application (if any) may be revised to narrate the example relationships described in the specification or shown in the accompanying drawings.

[0126] As used in this specification and claims, unless the context clearly indicates a particular case, the singular form may include the plural form. In addition to the orientation shown in the drawings, spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent can include lateral adjacent or horizontal adjacent.

[0127] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0128] Although certain features of the described implementations have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

[0129] Although certain features of the described specific implementations have been illustrated as described herein, many modifications, substitutions, variations and equivalents will now occur to those skilled in the art. It should therefore be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments.

Claims

1. A junction field effect transistor (JFET) semiconductor device (100), comprising: a substrate (206), the substrate comprising a drain region of the JFET (100); A drift region (202), the drift region being disposed on the substrate (206); A lower gate (204), the lower gate being arranged on the drift region (202); a source region (102), the source region having a lower source region (102b) disposed on the lower gate (204) and extending laterally beyond the lower gate (204), and an upper source region (102a) disposed on the lower source region (102b); and an upper gate (104) formed on the lower source region (102b) and at least partially surrounding the upper source region (102a) and extending laterally beyond the lower gate (204) to define a gate offset L between the upper gate (104) and the lower gate (204); go .

2. The JFET semiconductor device according to claim 1, further comprising a gate contact region (108a) contacting the upper gate (104) and the lower gate (204) to provide a common gate contact for the JFET semiconductor device.

3. The JFET semiconductor device according to claim 2, wherein a channel length of the JFET semiconductor device is defined in the lower source region (102b) as an overlap of an outer edge of the lower gate (204) and an inner edge of the upper gate (104).

4. The JFET semiconductor device according to claim 3, wherein the gate contact region (108a) partially overlaps the upper gate (104) at a distance less than the channel length.

5. The JFET semiconductor device according to claim 2, wherein the gate contact region (108a) partially overlaps the lower source region (102b).

6. The JFET semiconductor device according to claim 1, further comprising a gate-source breakdown voltage BVgs enhancement region (106), wherein the gate-source breakdown voltage BVgs enhancement region is formed on the lower source region (102b) and is disposed between the upper source region (102a) and the upper gate (104).

7. The JFET semiconductor device according to claim 6, wherein the BVgs enhancement region (106) has a doping level that is 20% or less of a doping level of the upper source region (102a).

8. The JFET semiconductor device according to claim 1, wherein the substrate (206) and the drift region comprise silicon carbide (SiC).

9. The JFET semiconductor device according to claim 1, wherein the gate is offset by L go is 0.05 microns or less.

10. The JFET semiconductor device of claim 1, wherein the JFET semiconductor device is normally-on.

11. A junction field effect transistor (JFET) semiconductor device (100), comprising: A substrate (206), the substrate comprising a drain region of the JFET semiconductor device (100); A drift region (202), the drift region being disposed on the substrate (206); and A plurality of unit cells are arranged in a grid form on the drift region, wherein each unit cell includes A lower gate (204), the lower gate being arranged on the drift region (202); a source region (102), the source region having a lower source region (102b) disposed on the lower gate (204) and extending laterally beyond the lower gate (204), and an upper source region (102a) disposed on the lower source region (102b); and an upper gate (104) formed on the lower source region (102b) and at least partially surrounding the upper source region (102a) and extending laterally beyond the lower gate (204) to define a gate offset L between the upper gate (104) and the lower gate (204); go . 12 . The JFET semiconductor device according to claim 11 , wherein a pitch defined between adjacent unit cells of the JFET semiconductor device is 5 micrometers or less.

13. The JFET semiconductor device according to claim 11, wherein each unit cell comprises a gate-source breakdown voltage BVgs enhancement region (106), wherein the gate-source breakdown voltage BVgs enhancement region is formed on the lower source region (102b) and between the upper source region (102a) and the upper gate (104).

14. The JFET semiconductor device according to claim 11, wherein the gate offset is 0.05 microns or less.

15. The JFET semiconductor device of claim 11, wherein each unit cell comprises a gate contact region (108a) contacting the upper gate (104) and the lower gate (204) to provide a common gate contact for the JFET semiconductor device.

16. A method for manufacturing a semiconductor device, the method comprising: forming (2402) a lower source region implant (1202b) and an upper gate implant (604) through a first opening in a mask (606) disposed on the substrate; forming (2404) a first spacer (702) on a sidewall of the mask (606) to define a second opening smaller than the first opening; forming (2406) a lower gate (804) through the second opening; forming (2408) a second spacer (902) on the first spacer (702) to define a third opening smaller than the second opening; as well as An upper source region (1202a) is formed (2414) through the third opening and within the upper gate implant, thereby defining the remaining portion of the upper gate implant (604) as an upper gate of a junction field effect transistor (JFET), wherein the substrate provides a drain of the JFET.

17. The method of claim 16, wherein forming the lower source region implant and the upper gate implant comprises: The lower source region implant (1202b) is formed below the upper gate implant (604).

18. The method according to claim 16, wherein forming the lower gate through the second opening comprises: The lower gate (804) is formed below the lower source region implant (1202b), wherein the upper gate implant (604) extends laterally beyond the lower gate (804) to define a gate offset between the upper gate implant (604) and the lower gate (804).

19. The method according to claim 16, further comprising: forming (2412) a third spacer (1102) on the first spacer (702) to define a fourth opening having a size between a size of the second opening and a size of the third opening; as well as A low doped region is formed (2410) through the third opening before forming the second spacer.

20. The method of claim 19, wherein forming the upper source region (1202a) maintains a portion of the lowly doped region at a gate-source breakdown voltage BV positioned between the upper source region (1202a) and the upper gate. gs Enhanced zone.

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