Chip laser marking alignment method and system, storage medium and electronic equipment

Abstract

The invention provides an alignment method and system for chip laser marking, a storage medium and electronic equipment, and the method comprises the steps: S1), providing a wafer, the wafer comprises a plurality of system-on-chip, the 2N system-on-chip is marked as an auxiliary positioning chip, and the 2N auxiliary positioning chips are equally divided into N groups of chips; s2) identifying a first group of chips through images; s3) when all of the first group of chips pass identification, taking the position coordinates of the first group of chips as alignment reference points; identifying the second group of chips by the image when the identification is not completely passed; and S4) repeatedly executing the step S3 until all the Kth group of chips pass identification, and taking the position coordinates of the Kth group of chips as alignment reference points. According to the alignment method and system for chip laser marking, the storage medium and the electronic equipment provided by the invention, the problems that alignment fails and laser marking operation cannot be continued due to the fact that two preset auxiliary alignment chips cannot be recognized in existing chip laser marking can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to an alignment method, system, storage medium and electronic equipment for chip laser marking. Background Art

[0002] With the rapid development of the "Beyond Moore" era, as an important continuation of the life cycle of Moore's Law, 2.5D advanced packaging has become a major technical highlight in the development process of semiconductor products from two-dimensional to three-dimensional, and is also developing rapidly in applications such as supercomputers and artificial intelligence.

[0003] In the 2.5D packaging process, a laser marking process is used to print product traceability information such as product batches on the silicon surface of the chip. In order to ensure that the printed information can be accurately printed at a fixed position on each chip and that the position does not shift, it is necessary to set up an alignment chip before the laser marking operation. During the operation, the alignment reference points of the alignment chip are identified to establish reference coordinates, and the position of each chip is calculated based on this. Since the SOC chips (multi-system integrated chips) prepared by 2.5D packaged chips are large in size, the number of them on a wafer is only dozens to hundreds. Therefore, no separate marking pattern is set on the wafer for alignment. Usually, the graphic features of the SOC chip itself are used as feature marks for image recognition. There are generally two such SOC chips used for alignment, one on the left and one on the right. The positions of these two chips are used as reference points to calculate the positions of other chips.

[0004] However, if an abnormality occurs in the SOC chip of a 2.5D packaged chip during the previous process, the SOC chip will not be prepared according to the normal process, and the abnormal SOC chip will be replaced with a filling chip (broken die, single chip). Since the size and appearance of the filling chip are different from those of the SOC, during the laser marking process, the machine moves to a fixed position to identify the image features of the SOC chip for comparison to further confirm the position information. Therefore, if an abnormality occurs during the preparation of the SOC chip used for alignment, it will be replaced by a filling chip. The image features of the filling chip are different from those of the SOC chip, which will cause the alignment to fail and be unable to operate. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a chip laser marking alignment method, system, storage medium and electronic device, which are used to solve the problem that the two preset auxiliary alignment chips cannot be identified in the existing chip laser marking, resulting in alignment failure and inability to continue the laser marking operation.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a chip laser marking alignment method, the alignment method comprising:

[0007] S1) providing a wafer for pre-marking operation, wherein the wafer comprises a plurality of system-level chips arranged in rows and columns, wherein 2N system-level chips are marked as auxiliary positioning chips, the 2N auxiliary positioning chips are evenly divided into N groups of chips, two auxiliary positioning chips in each group of chips are located in the same row, and the positions of the two auxiliary positioning chips in each group of chips are equally spaced, and N≥2;

[0008] S2) image recognition of two auxiliary positioning chips in the first group of chips;

[0009] S3) when all the two auxiliary positioning chips in the first group of chips have passed the recognition, the position coordinates of the two auxiliary positioning chips in the first group of chips are used as the alignment reference points; when all the two auxiliary positioning chips in the first group of chips have not passed the recognition, the image recognition of the two auxiliary positioning chips in the second group of chips is continued;

[0010] S4) Repeat step S3) until all the two auxiliary positioning chips in the Kth group of chips are identified, and use the position coordinates of the two auxiliary positioning chips in the Kth group of chips as alignment reference points, 1≤K≤N.

[0011] Optionally, one of the auxiliary positioning chips in each group of chips is defined as a first chip, and another of the auxiliary positioning chips is defined as a second chip; and the method for image recognition of the two auxiliary positioning chips in each group of chips includes:

[0012] K1) collecting a characteristic image of the first chip;

[0013] K2) Retrieving the standard image of the first chip, and comparing the characteristic image of the first chip with the standard image of the first chip; if they are the same, it is considered that the first chip has passed the image recognition and the subsequent step K3) is performed; if they are not the same, it is considered that the first chip has failed the image recognition;

[0014] K3) collecting a characteristic image of the second chip;

[0015] K4) Retrieving the standard image of the second chip, and comparing the characteristic image of the second chip with the standard image of the second chip; if they are the same, it is considered that the second chip has passed the image recognition; if they are not the same, it is considered that the second chip has not passed the image recognition.

[0016] Optionally, the 2N auxiliary positioning chips are respectively located in N rows.

[0017] Optionally, one of the auxiliary positioning chips in the N groups of chips is located in the same column, and another of the auxiliary positioning chips in the N groups of chips is also located in the same column.

[0018] Optionally, one of the auxiliary positioning chips and another of the auxiliary positioning chips in each group of chips is separated by one of the system-level chips.

[0019] The present invention also provides a chip laser marking alignment system, the alignment system comprising:

[0020] An image reading unit, used for acquiring a characteristic image of the auxiliary positioning chip;

[0021] An image storage unit, used for storing the characteristic image and the standard image of the auxiliary positioning chip;

[0022] An image comparison unit, used to determine whether the characteristic image of the auxiliary positioning chip is the same as the standard image of the auxiliary positioning chip;

[0023] The deviation calculation unit is used to calculate the position deviation between the characteristic image of the auxiliary positioning chip and the standard image of the auxiliary positioning chip.

[0024] The present invention also provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the chip laser marking alignment method as described above is implemented.

[0025] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any of the chip laser marking alignment methods described above is implemented.

[0026] As described above, the chip laser marking alignment method, system, storage medium and electronic device of the present invention are provided with multiple groups of auxiliary alignment chips when the chip is aligned. When one or more groups of auxiliary alignment chips cannot be identified, other groups of auxiliary alignment chips can be identified to ensure effective alignment and allow the laser marking operation to continue. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a flow chart of the chip laser marking alignment method of the present invention.

[0028] Figure 2 Shown is a schematic structural diagram of a wafer undergoing the pre-marking operation of the present invention.

[0029] Figure 3 Shown is a schematic diagram of the alignment system of the present invention.

[0030] Component number description

[0031] 10 Wafer

[0032] 11 System-on-Chip

[0033] 111 auxiliary positioning chip

[0034] 112 Filling Chip

[0035] 21 The first set of chips

[0036] 211 First Chip

[0037] 212 Second Chip

[0038] 201 Image reading unit

[0039] 202 Image storage unit

[0040] 203 Image Comparison Unit

[0041] 204 Deviation calculation unit DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0043] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0044] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0045] It should be noted that the diagrams provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the diagrams only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed arbitrarily, and the layout of the components may also be more complicated. In order to make the diagrams as concise as possible, not all structures are marked in the drawings.

[0046] This embodiment provides a chip laser marking alignment method, such as Figure 1 As shown, the alignment method includes: step S1) to step S4).

[0047] Step S1), providing a pre-marked wafer 10, the wafer 10 includes a plurality of system-level chips 11 arranged in rows and columns, and 2N system-level chips 11 are marked as auxiliary positioning chips 111, the 2N auxiliary positioning chips are evenly divided into N groups of chips, and the two auxiliary positioning chips in each group of chips are located in the same row, N≥2.

[0048] In this embodiment, Figure 2 As shown, there are dozens of system-level chips 11 arranged in an array in the wafer 10. In the 2.5D packaged product, the image features of the system-level chips 11 are used as feature points for image recognition and comparison; when there is no process abnormality, the size, model, and image features of these system-level chips 11 are the same. However, when a process abnormality occurs, some of the system-level chips 11 damaged by the process abnormality will have vacancies and be filled with filling chips 112, which will cause the image features of these system-level chips 11 with process abnormalities to be different from those of normal system-level chips 11; in the existing alignment method, two system-level chips 11 located in the same row of the wafer 10 are used as auxiliary positioning chips 111. When the image features of the two auxiliary positioning chips 111 are both After image recognition, the position coordinates of the two auxiliary positioning chips 111 are used to establish alignment reference points, and the coordinate positions of the remaining system-level chips 11 are calculated; however, when the auxiliary positioning chip 111 has a process abnormality and is filled with the filling chip 112, it cannot pass the image recognition, and the alignment reference points cannot be effectively established, and the coordinate positions of the remaining system-level chips 11 cannot be calculated; therefore, 2N system-level chips 11 are marked as auxiliary positioning chips 111, and each two auxiliary positioning chips 111 are grouped together for image recognition to establish alignment reference points. When one group of chips 110 cannot pass the image recognition, the other group of chips is used for image recognition instead until the alignment reference points can be established, which can effectively ensure the normal progress of the laser marking process.

[0049] Step S2), image recognition of the two auxiliary positioning chips in the first group of chips 21, in this step, as Figure 2As shown, one of the auxiliary positioning chips in the first group of chips 21 is defined as a first chip 211, and another auxiliary positioning chip is defined as a second chip 212. The method for image recognition of the first chip 211 and the second chip 212 includes: steps K1) to K4).

[0050] Step K1), collecting a characteristic image of the first chip 211 .

[0051] In this embodiment, image information of the first chip 211 is captured and used as a feature image. The feature image includes size and shape features of the first chip 211 .

[0052] Step K2) retrieves the standard image of the first chip 211, and compares the characteristic image of the first chip 211 with the standard image of the first chip 211; if they are the same, it is considered that the first chip has passed the image recognition and the subsequent step K3) is executed; if they are not the same, it is considered that the first chip has not passed the image recognition.

[0053] In the present embodiment, when no process abnormality occurs, each auxiliary positioning chip 111 (each system-level chip 11) has the same image feature. The image of the auxiliary positioning chip 111 without process abnormality is used as the standard image. By comparing the standard image with the feature image, it can be determined whether the first chip 211 has a process abnormality. When an abnormality occurs, the position deviation of the first chip 211 cannot be determined by the image details in the feature image, that is, the alignment reference point of the first chip 211 cannot be established. When no abnormality occurs, the position deviation of the first chip 211 can be determined based on the image details in the feature image, and the alignment reference point of the first chip 211 can be established.

[0054] Step K3) acquiring a characteristic image of the second chip 212 .

[0055] In this embodiment, similar to step K1), image information of the second chip 212 is captured, and the captured image information is used as a characteristic image of the second chip 212 , wherein the characteristic image includes size and morphological features of the second chip 212 .

[0056] Step K4) retrieves the standard image of the second chip 212, and compares the characteristic image of the second chip 212 with the standard image of the second chip; if they are the same, it is considered that the second chip has passed the image recognition; if they are different, it is considered that the second chip has not passed the image recognition.

[0057] In this embodiment, similar to step K2), the characteristic image of the second chip 212 is compared with the standard image of the second chip. When an abnormality occurs in the chip preparation process, the position deviation of the second chip 212 cannot be determined by the image details in the characteristic image of the chip, that is, the alignment reference point of the second chip 212 cannot be established; when no abnormality occurs, the position deviation of the second chip 212 can be determined based on the image details in the characteristic image, and the alignment reference point of the second chip 212 can be established.

[0058] Step S3) When all the two auxiliary positioning chips in the first group of chips 21 pass the recognition, the position coordinates of the two auxiliary positioning chips in the first group of chips 21 are used as alignment reference points; when not all the two auxiliary positioning chips in the first group of chips 21 pass the recognition, continue to image recognize the two auxiliary positioning chips in the second group of chips.

[0059] In this embodiment, the reference coordinates can be established through the alignment reference points of the first chip 21 and the second chip, and the coordinate positions of the remaining system-level chips 11 can be calculated from the reference coordinates. However, if any auxiliary positioning chip in the first group of chips 21 fails to pass the identification, the reference coordinates cannot be effectively established, and the coordinate positions of the remaining system-level chips 11 cannot be obtained.

[0060] Step S4) Repeat steps S2) to S3) until all two auxiliary positioning chips in the Kth group of chips are identified, and use the position coordinates of the two auxiliary positioning chips in the Kth group of chips as alignment reference points, 1≤K≤N.

[0061] In this embodiment, when the first group of chips cannot establish the reference coordinates, the second group of chips can be converted to establish the reference coordinates. When the second group of chips cannot establish the reference coordinates, the third group of chips can be converted to establish the reference coordinates. This process is repeated until the two auxiliary positioning chips in the Kth group of chips are all identified. At this time, the position coordinates of the two auxiliary positioning chips in the Kth group of chips are used as the alignment reference points, and the reference coordinates are established to further obtain the coordinate positions of the remaining system-level chips 11 to complete the laser marking operation.

[0062] Specifically, the two auxiliary positioning chips in each group of chips are located in the same row, and the interval between the two auxiliary positioning chips in each group of chips is the same, for example, Figure 2 The interval shown is one system-level chip, so that the two auxiliary positioning cores in each group of chips have the same interval.

[0063] More specifically, the 2N auxiliary positioning chips 111 are respectively located in N rows. During image recognition, the image reading unit selects rows in order. When a group of chips in the previous row cannot be recognized, it quickly switches to the next row for shooting, thereby shortening the positioning time. Preferably, one of the auxiliary positioning chips in the N groups of chips is located in the same column, and another auxiliary positioning chip in the N groups of chips is also located in the same column, so as to facilitate the image reading unit to quickly shoot according to the preset position.

[0064] Please refer to Figure 3 , Figure 3 The present invention provides a chip laser marking alignment system, the alignment system comprising:

[0065] An image reading unit 201 is used to obtain a characteristic image of the auxiliary positioning chip;

[0066] An image storage unit 202, used to store the characteristic image and standard image of the auxiliary positioning chip;

[0067] The image comparison unit 203 is used to determine whether the characteristic image of the auxiliary positioning chip is the same as the standard image of the auxiliary positioning chip.

[0068] The deviation calculation unit 204 is used to calculate the position deviation between the characteristic image of the auxiliary positioning chip and the standard image of the auxiliary positioning chip; and the deviation calculation unit can also calculate the positions of the remaining system-level chips based on the positions of the two auxiliary positioning chips and the position deviation.

[0069] The present invention also provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program can be used to execute the above Figure 1 A chip laser marking alignment method is provided.

[0070] Specifically, the storage medium may include, but is not limited to, a floppy disk, an optical disk, a CD-ROM (compact disk-read only memory), a magneto-optical disk, a ROM (read only memory), a RAM (random access memory), an EPROM (erasable programmable read only memory), an EEPROM (electrically erasable programmable read only memory), a magnetic card or an optical card, a flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions. In addition, the storage medium may be a product that is not connected to a computer device, or a component that is connected to a computer device for use.

[0071] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to realize the above Figure 1 Provided is the alignment method for chip laser marking.

[0072] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The information system involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processors involved in each embodiment provided in this application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., but are not limited to this.

[0073] In summary, the chip laser marking alignment method, system, storage medium and electronic device of the present invention are provided with multiple groups of auxiliary alignment chips when the chip is aligned. When one or more groups of auxiliary alignment chips cannot be identified, other groups of auxiliary alignment chips can be identified to ensure effective alignment and allow the laser marking operation to continue.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A chip laser marking alignment method, characterized in that: The alignment method comprises: S1) providing a wafer for pre-marking operation, wherein the wafer comprises a plurality of system-level chips arranged in rows and columns, wherein 2N system-level chips are marked as auxiliary positioning chips, the 2N auxiliary positioning chips are evenly divided into N groups of chips, two auxiliary positioning chips in each group of chips are located in the same row, and the positions of the two auxiliary positioning chips in each group of chips are equally spaced, and N≥2; S2) image recognition of two auxiliary positioning chips in the first group of chips; S3) when all the two auxiliary positioning chips in the first group of chips have passed the recognition, the position coordinates of the two auxiliary positioning chips in the first group of chips are used as the alignment reference points; when all the two auxiliary positioning chips in the first group of chips have not passed the recognition, the image recognition of the two auxiliary positioning chips in the second group of chips is continued; S4) Repeat step S3) until all the two auxiliary positioning chips in the Kth group of chips are identified, and use the position coordinates of the two auxiliary positioning chips in the Kth group of chips as alignment reference points, 1≤K≤N.

2. The chip laser marking alignment method according to claim 1, characterized in that: One of the auxiliary positioning chips in each group of chips is defined as a first chip, and another of the auxiliary positioning chips is defined as a second chip; The method of image recognition of two auxiliary positioning chips in each group of chips includes: K1) collecting a characteristic image of the first chip; K2) Retrieving a standard image of the first chip, and comparing the characteristic image of the first chip with the standard image of the first chip; if they are the same, it is considered that the first chip has passed the image recognition and the subsequent step K3) is performed; if they are not the same, it is considered that the first chip has failed the image recognition; K3) collecting a characteristic image of the second chip; K4) Retrieving a standard image of the second chip, and comparing the characteristic image of the second chip with the standard image of the second chip; if they are the same, it is considered that the second chip has passed image recognition; if they are not the same, it is considered that the second chip has failed image recognition.

3. The chip laser marking alignment method according to claim 1, characterized in that: The 2N auxiliary positioning chips are respectively located in N rows.

4. The chip laser marking alignment method according to claim 3, characterized in that: One of the auxiliary positioning chips in the N groups of chips is located in the same column, and another of the auxiliary positioning chips in the N groups of chips is also located in the same column.

5. The chip laser marking alignment method according to claim 4, characterized in that: One of the auxiliary positioning chips in each group of chips is separated from another of the auxiliary positioning chips by one system-level chip.

6. A chip laser marking alignment system, characterized in that: The alignment system comprises: An image reading unit, used for acquiring a characteristic image of the auxiliary positioning chip; An image storage unit, used for storing the characteristic image and the standard image of the auxiliary positioning chip; An image comparison unit, used to determine whether the characteristic image of the auxiliary positioning chip is the same as the standard image of the auxiliary positioning chip; The deviation calculation unit is used to calculate the position deviation between the characteristic image of the auxiliary positioning chip and the standard image of the auxiliary positioning chip.

7. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the chip laser marking alignment method according to any one of claims 1 to 5 is implemented.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the chip laser marking alignment method described in any one of claims 1 to 5 is implemented.

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