Edge polishing detection method, device and medium

Abstract

This disclosure provides a method, apparatus, and medium for detecting edge polishing; the detection method includes: uniformly forming recesses on the edge portion of a test wafer that has undergone an edge grinding process using a laser beam; detecting the subsurface damage depth generated by the edge grinding process based on the inner wall morphology of each recess; and determining the polishing removal amount of the edge polishing process based on the subsurface damage depth.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus and medium for detecting edge polishing. Background Technology

[0002] As the integration density of semiconductor devices increases, there is a demand for wafer edges to be as free of contamination as possible and have low roughness. Typically, the wafer edges undergo the following processing steps to remove edge damage and achieve a mirror finish: edge grinding and edge polishing. In the edge grinding process, a metal or resin grinding wheel of a set grit is used to grind the wafer edges at high speed. During this grinding process, mechanical damage is inevitably caused to the wafer edge surface and the subsurface at a shallow depth. This damage can be eliminated by the edge polishing process.

[0003] However, if some of the damage is too deep to be completely eliminated by the edge polishing process, the mechanical damage remaining at the wafer edge will reduce the strength of the wafer, leading to the risk of wafer breakage during the processing of semiconductor devices. Summary of the Invention

[0004] This disclosure provides a method, apparatus, and medium for detecting edge polishing; it can reduce edge roughness and the incidence of edge defects after the edge polishing process.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, this disclosure provides a method for detecting edge polishing, the method comprising:

[0007] A laser beam is used to uniformly create recesses on the edge portion of a test wafer that has undergone edge grinding.

[0008] The depth of subsurface damage caused by the edge grinding process is determined based on the inner wall morphology of each cavity;

[0009] The amount of material removed during the edge polishing process is determined based on the subsurface damage depth.

[0010] In some optional examples, detecting the subsurface damage depth resulting from the edge grinding process based on the inner wall morphology of each recess includes:

[0011] Obtain an image of the inner wall morphology of each cavity;

[0012] Identify the cracks in each image that extend from the edge of each pit into the interior of each pit;

[0013] The subsurface damage depth is determined based on the length of the crack inside each cavity.

[0014] In some optional examples, determining the subsurface damage depth based on the length of the crack within each cavity includes:

[0015] Determine the maximum length of the crack from the lengths of all the cracks inside the cavities;

[0016] The maximum length is determined as the subsurface damage depth.

[0017] In some optional examples, determining the subsurface damage depth based on the length of the crack within each cavity includes:

[0018] Obtain the mean and variance of the lengths of the cracks inside all the pits, and determine the subsurface damage depth according to the mean and variance.

[0019] In some optional examples, determining the polishing removal amount of the edge polishing process based on the subsurface damage depth includes:

[0020] The correction value for the polishing removal amount is determined according to the subsurface damage depth;

[0021] The amount of polishing removal in the edge polishing process is determined based on the baseline polishing removal amount and the correction value.

[0022] In some optional examples, a recess is uniformly formed on the edge portion of a test wafer that has undergone edge grinding using a laser beam, including:

[0023] At least one detection location is uniformly distributed at the edge portion of the test wafer;

[0024] The laser beam bombards the chamfered surfaces and edge surfaces on the upper and lower surfaces at each detection location to create the recesses.

[0025] In some optional examples, after the test wafer has undergone the edge polishing process according to the polishing removal amount, the method further includes:

[0026] When the pits at the edge of the test wafer still exist, subsurface damage is detected based on the morphology of the inner wall of each pit.

[0027] When no subsurface damage is present, the test wafer is polished again at the edges to eliminate the pits.

[0028] In some optional examples, after the test wafer has undergone the edge polishing process according to the polishing removal amount, the method further includes:

[0029] When there are no pits at the edge of the test wafer, the test wafer is subjected to a final polishing process.

[0030] In some optional examples, after determining the polishing removal amount of the edge polishing process based on the subsurface damage depth, the method further includes mixing the test wafer into the wafer to be processed and performing the edge polishing process according to the polishing removal amount of the edge polishing process.

[0031] Secondly, this disclosure provides an edge polishing detection device, the device comprising:

[0032] The cavity forming unit is configured to uniformly form cavities on the edge portion of a test wafer that has undergone edge grinding using a laser beam;

[0033] The detection unit is configured to determine the subsurface damage depth caused by the edge grinding process based on the inner wall morphology of each recess.

[0034] The determining unit is configured to determine the amount of polishing removal in the edge polishing process based on the subsurface damage depth.

[0035] Thirdly, this disclosure provides an edge polishing detection apparatus, the apparatus comprising: a processor and a memory; the processor being configured to execute instructions stored in the memory to implement the edge polishing detection method as described in the first aspect.

[0036] Fourthly, this disclosure provides a computer storage medium storing at least one instruction, which is executed by a processor to implement the edge polishing detection method as described in the first aspect.

[0037] This disclosure provides a method, apparatus, and medium for detecting edge polishing. After a laser beam bombards a recess on the edge of a test wafer that has undergone edge grinding, the subsurface damage depth is detected based on the inner wall morphology of the recess. The polishing removal amount of the subsequent edge polishing process is determined based on the subsurface damage depth. This method can eliminate mechanical damage generated in the edge grinding process to the maximum extent, improve the elimination rate of mechanical damage in the edge polishing process, and reduce the edge roughness and edge defect incidence after the edge polishing process. Attached Figure Description

[0038] Figure 1 A cross-sectional view of the outer surface of the wafer provided in this disclosure in the height direction of the wafer.

[0039] Figure 2 This is a schematic diagram of a detection method for edge polishing provided in this disclosure.

[0040] Figure 3This is a top view of the surface of the test wafer provided in this disclosure.

[0041] Figure 4 This is a schematic diagram of the components of an edge polishing detection device provided in this disclosure.

[0042] Figure 5 This is a schematic diagram of the composition of another edge polishing detection device provided in this disclosure.

[0043] Figure 6 This is a schematic diagram of the structure of an edge polishing detection device provided in this disclosure. Detailed Implementation

[0044] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0045] In this disclosure, Figure 1 This is a cross-sectional view of the outer surface of wafer 1 along the wafer height direction. Figure 1 In this embodiment, wafer 1 includes an upper surface 2 and a lower surface 3. Since these two surfaces are aligned with the radial direction of wafer 1, they can also be referred to as the radial surface portion of the wafer in this embodiment. Furthermore, wafer 1 also includes an edge portion 7 formed by a chamfered surface 4 on the upper surface side, a chamfered surface 5 on the lower surface side, and an edge surface 6. For the edge portion 7, the chamfered surface 4 on the upper surface side and the chamfered surface 5 on the lower surface side are inclined relative to the upper surface 2 and the lower surface 3. The edge surface 6 is the portion of the edge portion 7 excluding the chamfered surface 4 on the upper surface side and the chamfered surface 5 on the lower surface side, and is perpendicular to the upper surface 2 and the lower surface 3. The edge surface 6 can also be a curved surface. The boundaries between the chamfered surface 4 on the upper surface side and the chamfered surface 5 on the lower surface side and the edge surface 6 are as follows: Figure 1 As shown, it is usually formed smoothly.

[0046] During wafer fabrication, the edges of the diced wafers typically have sharp edges, burrs, chipped edges, and even cracks, resulting in a rough surface. Edge grinding not only removes these damages but also provides a smoother surface for subsequent edge polishing. Specifically, edge grinding involves fixing the wafer on a rotatable hard platform. A high-speed rotating grinding wheel is positioned along the edge of the wafer. By controlling the hard platform, the wafer and the grinding wheel rotate at high speed relative to each other. Simultaneously, an appropriate amount of grinding fluid is applied to grind the wafer edges to achieve the required diameter tolerances and edge contour shape, completing the edge grinding process. Since the grinding wheel is usually made of metal or resin, the high-speed relative rotation between the wafer and the grinding wheel inevitably causes mechanical damage to the wafer's edge surface and the subsurface at a shallow depth. It should be noted that the "subsurface" refers to the material layer below the wafer surface, such as a region only a few micrometers to tens of micrometers deep. Compared to direct mechanical damage on the wafer surface, subsurface damage is a type of hidden damage that cannot be directly observed by the naked eye. After edge grinding, the wafer edges can be polished using methods such as chemical-mechanical polishing (CMP). This edge polishing process not only removes or mitigates mechanical damage but also further reduces the roughness of the wafer edges.

[0047] However, during wafer fabrication, the depth of mechanical damage to the surface and subsurface varies at different locations on the wafer edge. In order to eliminate as much of this mechanical damage as possible during the edge polishing process, the mechanical damage at different locations on the wafer edge needs to be considered when determining the amount of polishing removal in the edge polishing process.

[0048] Based on this, see Figure 2 This disclosure illustrates a method for detecting edge polishing, which includes steps S201 to S203.

[0049] In step S201, a recess is uniformly formed on the edge portion of the test wafer that has undergone edge grinding by using a laser beam.

[0050] In this disclosure, you can choose Figure 1 Wafer 10 is shown as the test wafer 1. Combined with... Figure 3 The top view of the test wafer 10 shown exemplarily includes a region 3-5 mm from the periphery of the test wafer 10 toward the center O of the test wafer. Figure 3 The annular region between the dashed circle and the solid circle is defined as the edge portion 7 of test wafer 10. Based on this definition, Figure 3The edge portion 7 shown includes Figure 1 The chamfered surface 4 on the upper surface side, the chamfered surface 5 on the lower surface side, and the edge surface 6 are shown.

[0051] In the specific implementation process, in order to comprehensively detect the subsurface damage depth of the edge portion caused by the edge grinding process, this disclosure uniformly arranges multiple detection positions on the edge portion 7 of the test wafer after the edge grinding process has been completed, and a recess is created at each detection position by bombardment with a laser beam. It should be noted that the depth of the recess can be determined based on the target removal amount of the edge polishing process and the grit of the grinding wheel used when the test wafer is chamfered. In some examples, when using 800-grit to 3000-grit grinding wheels to chamfer the test wafer, the depth of the recess is typically 2 micrometers to 20 micrometers.

[0052] Understandably, these pits do not damage the final test wafer because they can be removed in subsequent edge polishing processes, compared to the conventional approach that requires destructive detection of subsurface damage on the test wafer.

[0053] In some examples, such as Figure 3 As shown, using the line connecting the notch of the test wafer to the center O as a reference, the wafer is rotated counterclockwise successively at a set angle θ to obtain uniformly distributed detection positions. In some examples, the set angle θ can be 30 degrees, 45 degrees, 60 degrees, 90 degrees, etc.

[0054] In some examples, since semiconductor device manufacturing processes are typically performed only on the upper surface of the wafer, the chamfered surface 4 on the upper surface side of the edge portion 7 at each detection location can be bombarded with a laser beam to create a recess.

[0055] In some examples, in order to obtain the damage depth caused by the edge grinding process more accurately, the chamfered surface 4 on the upper surface side, the chamfered surface 5 on the lower surface side, and the edge surface 6 on the edge portion 7 at each detection position can be bombarded with a laser beam to create a cavity.

[0056] In step S202, the subsurface damage depth generated by the edge grinding process is detected based on the inner wall morphology of each cavity.

[0057] It should be noted that almost all mechanical damage on the edge surface of the test wafer can be removed during the edge polishing process. However, mechanical damage at a shallower depth (subsurface) from the edge surface of the test wafer may not be completely eliminated if the conventional edge polishing process is performed using the default polishing removal amount (also referred to as the reference polishing removal amount in this disclosure) due to the varying depth of the damage. Therefore, after detecting the subsurface damage depth of the inner wall of each recess corresponding to each detection location in step S202, the reference polishing removal amount can be corrected based on these subsurface damage depths. Performing the edge polishing process according to the corrected polishing removal amount can remove as much subsurface damage as possible.

[0058] In some possible implementations, detecting the subsurface damage depth generated by the edge grinding process based on the inner wall morphology of each recess includes:

[0059] Obtain an image of the inner wall morphology of each cavity;

[0060] Identify the cracks in each image that extend from the edge of each pit into the interior of each pit;

[0061] The subsurface damage depth is determined based on the length of the crack inside each cavity.

[0062] Specifically, the above implementation can employ techniques such as optical microscopy, scanning electron microscopy (SEM), atomic force microscopy (AFM), and X-ray microtomography to acquire images of the inner wall morphology of each cavity. Next, image analysis and processing can be used to filter out image regions that significantly differ from the background of the cavity's inner wall, and to identify the presence of crack patterns within these regions. After identifying the crack patterns, the subsurface damage depth at each cavity can be determined by measuring the length of the cracks. For example, using the height direction of the test wafer as the projection direction, the length of the crack within the cavity in this projection direction can be determined as the subsurface damage depth of that cavity.

[0063] It should be noted that the subsurface damage depth at each detection location on the edge of the test wafer is different. In this disclosure, the subsurface damage depth at all detection locations is statistically analyzed, and the subsurface damage depth used to characterize the overall edge of the test wafer is determined based on the statistical results.

[0064] In some examples, determining the subsurface damage depth based on the length of the crack within each pit includes:

[0065] Determine the maximum length of the crack from the lengths of all the cracks inside the cavities;

[0066] The maximum length is determined as the subsurface damage depth.

[0067] In the example above, specifically, if the polishing removal amount is corrected according to the subsurface damage depth determined by the maximum length of the crack, then performing the edge polishing process according to the corrected polishing removal amount will remove these cracks to the maximum extent, thereby eliminating the subsurface damage at the edge of the test wafer.

[0068] In some examples, determining the subsurface damage depth based on the length of the crack within each pit includes:

[0069] Obtain the mean and variance of the lengths of the cracks inside all the pits, and determine the subsurface damage depth according to the mean and variance.

[0070] In the example above, specifically, the mean length of the crack can be used as the center, and the numerical range of the depth of most subsurface damage can be determined according to a set number of variance ranges (e.g., 3 or 6 variance ranges). The subsurface damage depth can then be determined based on this numerical range. The polishing removal amount is then corrected based on the subsurface damage depth. Performing an edge polishing process according to the corrected polishing removal amount will eliminate most of the cracks, thereby eliminating most of the subsurface damage at the edge of the test wafer.

[0071] In step S203, the amount of polishing removal in the edge polishing process is determined based on the subsurface damage depth.

[0072] In this disclosure, after obtaining the subsurface damage depth characterizing the overall edge of the test wafer through the above step S202, the reference polishing removal amount of the default setting of the edge polishing equipment can be corrected based on the subsurface damage depth to obtain the polishing removal amount used when performing the edge polishing process.

[0073] In some examples, determining the amount of polishing removed in the edge polishing process based on the subsurface damage depth includes:

[0074] The correction value for the polishing removal amount is determined according to the subsurface damage depth;

[0075] The amount of polishing removal in the edge polishing process is determined based on the baseline polishing removal amount and the correction value.

[0076] In the above example, specifically, when the subsurface damage depth is less than or equal to the reference polishing removal amount, it means that performing the edge polishing process according to the reference polishing removal amount can remove all the subsurface damage. When the subsurface damage depth is greater than the reference polishing removal amount, it means that performing the edge polishing process according to the reference polishing removal amount cannot remove all the subsurface damage at the edge. The reference polishing removal amount needs to be corrected so that when the corrected polishing removal amount is used as the polishing removal amount of the edge polishing process, the subsurface damage can be removed to the maximum extent.

[0077] The above technical solution involves using a laser beam to bombard the recesses at the edge of a test wafer after edge grinding. The subsurface damage depth is then detected based on the inner wall morphology of the recesses, and the amount of material removed in the subsequent edge polishing process is determined based on this subsurface damage depth. This approach maximizes the elimination of mechanical damage generated during the edge grinding process, improves the elimination rate of mechanical damage in the edge polishing process, and reduces the edge roughness and edge defect incidence rate after the edge polishing process.

[0078] After performing the edge polishing process based on the above technical solution, the pits on the edge of the test wafer can be detected to determine whether the pits exist.

[0079] In some examples, if the pits at the edge of the test wafer are absent, it indicates that the edge polishing process has removed the pits, and the mechanical damage appearing on the inner wall of the pits is also eliminated. In this case, the test wafer that has completed the edge polishing process can be subjected to subsequent wafer processing processes, such as the final polishing process.

[0080] In some examples, if the pits still exist, the presence of subsurface damage can be further detected based on the morphology of the inner wall of each pit. It should be noted that this detection process is the same as the method for detecting internal cracks in pits described in the aforementioned technical solutions, and will not be repeated here.

[0081] When the pit does not have the subsurface damage, it means that the aforementioned edge polishing process has completely removed the subsurface damage at the edge of the test wafer. Then, the test wafer can be subjected to the edge polishing process again to eliminate the pit.

[0082] If the pit still has the subsurface damage, it means that the subsurface damage at the edge of the test wafer is too deep and cannot be removed even if the edge polishing process is performed again. In this case, the test wafer can be considered as a test wafer with edge subsurface damage and no further processing steps will be performed.

[0083] In actual production, considering production costs and efficiency, it may not be possible to form pits on all foundry wafers. Therefore, in some examples, after determining the polishing removal amount of the edge polishing process based on the subsurface damage depth, the method may further include mixing a test wafer into the wafer to be processed and performing an edge polishing process according to the polishing removal amount of the edge polishing process.

[0084] For example, recesses can be uniformly formed on the edges of five test wafers. These test wafers with recesses are then mixed with 100 wafers to be processed, allowing them to undergo subsequent edge polishing processes sequentially on the same edge polishing equipment. After the edge polishing process, by inspecting the recesses on the test wafers—such as their depth, size variations, or complete elimination—it can be inferred whether the polishing process achieved uniformity in edge treatment and whether there are differences in efficiency or effectiveness when the polishing equipment processes wafers at different stages. Based on these inspection results, edge polishing process parameters can be optimized, such as adjusting polishing force, time, and polishing fluid flow rate. Furthermore, these inspection results can also reflect equipment wear and consumable storage conditions, providing a basis for equipment maintenance and consumable replacement.

[0085] It should be noted that after completing the wafer fabrication process using the above method, the defects at the edges of the resulting wafer are significantly reduced. In particular, edge defects such as notches and / or scratches and / or cracks can be reduced or even eliminated.

[0086] Based on the same inventive concept as the aforementioned technical solution, see [link to inventive concept]. Figure 4 The present disclosure illustrates an edge polishing detection device 40, which includes:

[0087] The cavity forming unit 401 is configured to uniformly form cavities on the edge portion of a test wafer that has undergone edge grinding using a laser beam;

[0088] The detection unit 402 is configured to determine the subsurface damage depth caused by the edge grinding process based on the inner wall morphology of each recess.

[0089] The determining unit 403 is configured to determine the amount of polishing removal in the edge polishing process based on the subsurface damage depth.

[0090] In some examples, the detection unit 402 is configured as follows:

[0091] Obtain an image of the inner wall morphology of each cavity;

[0092] Identify the cracks in each image that extend from the edge of each pit into the interior of each pit;

[0093] The subsurface damage depth is determined based on the length of the crack inside each cavity.

[0094] In some examples, the detection unit 402 is configured as follows:

[0095] Determine the maximum length of the crack from the lengths of all the cracks inside the cavities;

[0096] The maximum length is determined as the subsurface damage depth.

[0097] In some examples, the detection unit 402 is configured as follows:

[0098] Obtain the mean and variance of the lengths of the cracks inside all the pits, and determine the subsurface damage depth according to the mean and variance.

[0099] In some examples, the determining unit 403 is configured as follows:

[0100] The correction value for the polishing removal amount is determined according to the subsurface damage depth;

[0101] The amount of polishing removal in the edge polishing process is determined based on the baseline polishing removal amount and the correction value.

[0102] In some examples, the recess forming unit 401 is configured as follows:

[0103] At least one detection location is uniformly distributed at the edge portion of the test wafer;

[0104] The laser beam bombards the chamfered surfaces and edge surfaces on the upper and lower surfaces at each detection location to create the recesses.

[0105] In some examples, the detection unit 402 is further configured as follows:

[0106] After the edge polishing process is performed on the test wafer according to the polishing removal amount, if the pits on the edge portion of the test wafer still exist, the presence of subsurface damage is detected based on the inner wall morphology of each pit.

[0107] See Figure 5 The device 40 further includes an execution unit 404 configured to: when there is no subsurface damage, perform edge polishing on the test wafer again to eliminate the pits.

[0108] In some examples, the execution unit 404 is further configured to perform a final polishing process on the test wafer after the edge polishing process is performed on the test wafer according to the polishing removal amount, when the pits on the edge portion of the test wafer are no longer present.

[0109] Please refer to Figure 6 This diagram illustrates a structural block diagram of an edge polishing detection device 40 provided in an exemplary embodiment of this disclosure. In some examples, the edge polishing detection device 40 can be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The edge polishing detection device 40 has communication capabilities and can access a wired or wireless network. The edge polishing detection device 40 can refer to one of multiple terminals; those skilled in the art will understand that the number of such terminals can be more or less. In some examples, the edge polishing detection device 40 can receive data based on the accessed wired or wireless network. It is understood that the edge polishing detection device 40 undertakes the computation and processing work of the technical solution of this disclosure, and this disclosure does not limit this aspect.

[0110] like Figure 6 As shown, the computing device in this disclosure may include one or more components such as a processor 610 and a memory 620.

[0111] Optionally, the processor 610 connects various parts within the computing device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 620, and by calling data stored in the memory 620. Optionally, the processor 610 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 610 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used to handle wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 610, but may be implemented using a separate chip.

[0112] The memory 620 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 620 may include a non-transitory computer-readable storage medium. The memory 620 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 620 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0113] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0114] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the edge polishing detection method as described in the above embodiments.

[0115] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the edge polishing detection method described in the above embodiments.

[0116] Using the methods described above helps to obtain wafers with higher edge quality. In particular, these methods can reduce or even eliminate edge defects such as notches and / or scratches and / or cracks.

[0117] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0118] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0119] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for detecting edge polishing, characterized in that, The detection method for edge polishing includes: A laser beam is used to uniformly create recesses on the edge portion of a test wafer that has undergone edge grinding. The depth of subsurface damage caused by the edge grinding process is determined based on the inner wall morphology of each cavity; The amount of material removed during the edge polishing process is determined based on the subsurface damage depth. The step of detecting the subsurface damage depth generated by the edge grinding process based on the inner wall morphology of each cavity includes: Obtain an image of the inner wall morphology of each cavity; Identify the cracks in each image that extend from the edge of each pit into the interior of each pit; The subsurface damage depth is determined based on the length of the crack inside each cavity; The method further includes, after the test wafer has undergone the edge polishing process according to the polishing removal amount: When the pits at the edge of the test wafer still exist, subsurface damage is detected based on the morphology of the inner wall of each pit. When no subsurface damage is present, the test wafer is polished again at the edges to eliminate the pits; The method further includes, after the test wafer has undergone the edge polishing process according to the polishing removal amount, performing a final polishing process on the test wafer when the pits at the edge of the test wafer are no longer present.

2. The edge polishing detection method according to claim 1, characterized in that, Determining the subsurface damage depth based on the length of the crack within each cavity includes: Determine the maximum length of the crack from the lengths of all the cracks inside the cavities; The maximum length is determined as the subsurface damage depth.

3. The edge polishing detection method according to claim 1, characterized in that, Determining the subsurface damage depth based on the length of the crack within each cavity includes: Obtain the mean and variance of the lengths of the cracks inside all the pits, and determine the subsurface damage depth according to the mean and variance.

4. The edge polishing detection method according to claim 1, characterized in that, The step of determining the polishing removal amount in the edge polishing process based on the subsurface damage depth includes: The correction value for the polishing removal amount is determined according to the subsurface damage depth; The amount of polishing removal in the edge polishing process is determined based on the baseline polishing removal amount and the correction value.

5. The edge polishing detection method according to claim 1, characterized in that, A laser beam is used to uniformly form recesses on the edge portion of a test wafer that has undergone edge grinding, including: At least one detection location is uniformly distributed at the edge portion of the test wafer; The laser beam bombards the chamfered surfaces and edge surfaces on the upper and lower surfaces at each detection location to create the recesses.

6. The method for detecting edge polishing according to any one of claims 1 to 5, characterized in that, After determining the polishing removal amount of the edge polishing process based on the subsurface damage depth, the method further includes mixing the test wafer into the wafer to be processed and performing the edge polishing process according to the polishing removal amount of the edge polishing process.

7. An edge polishing detection apparatus for implementing the edge polishing detection method as described in any one of claims 1 to 6, characterized in that, The device includes: The cavity forming unit is configured to uniformly form cavities on the edge portion of a test wafer that has undergone edge grinding using a laser beam; The detection unit is configured to determine the subsurface damage depth caused by the edge grinding process based on the inner wall morphology of each recess. The determining unit is configured to determine the amount of polishing removal in the edge polishing process based on the subsurface damage depth.

8. A detection device for edge polishing, characterized in that, The apparatus includes a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the edge polishing detection method as described in any one of claims 1 to 6.

9. A computer storage medium, characterized in that, The computer storage medium stores at least one instruction, which is executed by a processor to implement the edge polishing detection method as described in any one of claims 1 to 6.

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