A phase estimation method, a signal processing channel and a storage medium

Abstract

A phase estimation method, a signal processing channel and a storage medium are applied to the technical field of signal processing. The phase estimation method comprises the following steps: obtaining an original input signal and an initial phase value interval; calculating a target Fibonacci sequence; determining an initial left test phase value and an initial right test phase value based on the target Fibonacci sequence, and calculating an amplitude estimation value; performing test phase value iteration based on the target Fibonacci sequence; if the length of the target Fibonacci sequence does not meet a preset length, reducing the length by 1, adding 1 to the iteration number, and continuing the test phase value iteration; if the length meets the preset length, obtaining the phase corresponding to the amplitude estimation minimum value based on the current iteration left test phase value and the iteration right test phase value. Since the amplitude estimation value of the to-be-tested signal is analyzed to perform phase estimation, and then the phase is searched based on the target Fibonacci sequence, the phase corresponding to the amplitude estimation minimum value can be obtained, so that the phase estimation process is simplified.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, specifically to a phase estimation method, a signal processing channel, and a storage medium. Background Technology

[0002] Digital-to-analog converters (DACs), as crucial devices for converting digital signals into analog signals, are widely used across various industries. However, due to nonlinear factors such as component mismatch within the DAC, the output of the DAC always contains signals other than the main input signal, thus affecting the DAC's spurious-free dynamic range (SFDR). Harmonics and spurious signals corresponding to the main signal in the DAC's output signal have a significant impact on SFDR.

[0003] Current technical solutions primarily utilize other analytical instruments to analyze the analog signal output by the DAC, directly analyzing the harmonic phase or spurious phase. However, this requires high precision from the analytical instruments, which are expensive, and the complex process makes it unsuitable for large-scale applications. Therefore, new technical solutions are needed to obtain the phase of harmonics or spurious signals generated by the DAC. Summary of the Invention

[0004] The main technical problem addressed in this application is how to simplify the acquisition of the phase of harmonics or spurious signals generated by the DAC.

[0005] According to the first aspect, one embodiment provides a phase estimation method, including:

[0006] Obtain the original input signal and the initial phase value interval [an^0, bn^0]; where an^0 is the initial left-end phase value and bn^0 is the initial right-end phase value;

[0007] Determine the target error value, and calculate the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0]; wherein the length of the target Fibonacci sequence F(D) is D;

[0008] Based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], the initial left test phase value xn^0 and the initial right test phase value yn^0 are determined, and the amplitude estimates of the initial left test phase value xn^0 and the initial right test phase value yn^0 are calculated respectively to obtain the amplitude estimates of the corresponding test phase values.

[0009] Determine whether the length D of the target Fibonacci sequence F(D) satisfies the preset length;

[0010] If not satisfied, test phase value iteration is performed based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimates, to obtain the iterated left test phase value xn^K and the iterated right test phase value yn^K. Based on the amplitude estimates, the amplitude estimates corresponding to the current iterated left test phase value xn^K and the iterated right test phase value yn^K are calculated, where K is the iteration number and its initial value is 1, and xn^K and yn^K are the iterated left test phase value and the iterated right test phase value corresponding to the Kth iteration, respectively. The length D of the target Fibonacci sequence F(D) is reduced by 1 and the iteration number K is increased by 1, and it is continued to determine whether the preset length is satisfied.

[0011] If satisfied, the iteration of the test phase value ends, and the phase corresponding to the minimum amplitude estimate is obtained based on the current left test phase value xn^K and right test phase value yn^K.

[0012] In some embodiments, the amplitude estimation calculation includes: generating a cancellation signal based on the harmonic frequencies and harmonic amplitudes of the harmonics of the original input signal or based on the spurious frequencies and spurious amplitudes of the spurious signals of the original input signal, and the corresponding test phase value; superimposing the cancellation signal and the original input signal to obtain a digital signal under test; inputting the digital signal under test into a DAC for digital-to-analog conversion to obtain an analog signal under test; and performing spectral analysis on the analog signal under test to obtain the amplitude estimate of the corresponding test phase value.

[0013] In some embodiments, calculating the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0] includes:

[0014] The target value of the target Fibonacci sequence F(D) is calculated based on the following formula:

[0015] δ=(bn^0-an^0) / ε;

[0016] Wherein, δ is the target value, and ε is the target error value;

[0017] When the Dth value in the Fibonacci sequence is greater than or equal to the target value, the length of the Fibonacci sequence is determined to be D, so as to obtain the target Fibonacci sequence F(D).

[0018] In some embodiments, determining the initial left test phase value xn^0 and the initial right test phase value yn^0 based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0] includes:

[0019] The initial left test phase value xn^0 is calculated using the following formula:

[0020] xn^0=an^0+f(D-2) / f(D)*(bn^0-an^0);

[0021] Where f(D-2) is the (D-2)th value in the target Fibonacci sequence F(D), and F(D) is the Dth value in the target Fibonacci sequence F(D);

[0022] The initial right test phase value yn^0 is calculated using the following formula:

[0023] yn^0=an^0+f(D-1) / f(D)*(bn^0-an^0);

[0024] Where f(D-1) is the (D-1)th value in the target Fibonacci sequence F(D).

[0025] In some embodiments, the test phase value iteration includes:

[0026] If the test phase value iteration is performed for the first time, it is determined whether the amplitude estimate corresponding to the initial left test phase value xn^0 is greater than the amplitude estimate corresponding to the initial right test phase value yn^0.

[0027] If it is greater than, then the initial phase value interval [an^0, bn^0] is subjected to the first iteration of the phase value interval to obtain the right-hand phase value bn^1 and the left-hand phase value an^1; where bn^1 = bn^0, an^1 = xn^0; the initial right test phase value yn^0 is assigned to the left test phase value xn^1 to obtain xn^1 = yn^0, and the preset single-peak function search method calculates the right test phase value yn^1 using the following formula:

[0028] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1);

[0029] If the value is less than the given value, a second iteration of the phase value interval [an^0, bn^0] is performed to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; where an^1 = an^0, bn^1 = yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1 = xn^0, and the preset single-peak function search method calculates the iterative left test phase value xn^1 using the following formula:

[0030] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1);

[0031] If the test phase value is iterated for the (K+1)th time, it is determined whether the amplitude estimate corresponding to the left test phase value xn^K is greater than the amplitude estimate corresponding to the right test phase value yn^K.

[0032] If the value is greater than the given value, the initial phase value interval [an^K, bn^K] is subjected to a first iteration to obtain the right-hand phase value bn^(K+1) and the left-hand phase value an^(K+1); where bn^(K+1) = bn^K and an^(K+1) = xn^K; the right-hand test phase value yn^K is assigned to the left-hand test phase value xn^(K+1) to obtain xn^(K+1) = yn^K, and the preset single-peak function search method calculates the right-hand test phase value yn^K using the following formula:

[0033] yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1));

[0034] If it is less than, then a second iteration of the phase value interval [an^K, bn^K] is performed to obtain the iterative right phase value bn^(K+1) and the iterative left phase value an^(K+1); where an^(K+1) = an^K, bn^(K+1) = yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1) = xn^K, and the preset single-peak function search method calculates the iterative left test phase value xn^(K+1) using the following formula:

[0035] xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)).

[0036] In some embodiments, the test phase value iteration includes:

[0037] If the test phase value iteration is performed for the first time, it is determined whether the amplitude estimate corresponding to the initial left test phase value xn^0 is greater than the amplitude estimate corresponding to the initial right test phase value yn^0.

[0038] If the value is greater than the given value, a second iteration of the phase value interval [an^0, bn^0] is performed to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; where an^1 = an^0, bn^1 = yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1 = xn^0, and the preset single-peak function search method calculates the iterative left test phase value xn^1 using the following formula:

[0039] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1);

[0040] If it is less than, then the initial phase value interval [an^0, bn^0] is subjected to the first iteration of the phase value interval to obtain the right-hand phase value bn^1 and the left-hand phase value an^1; where bn^1 = bn^0, an^1 = xn^0; the initial right test phase value yn^0 is assigned to the left test phase value xn^1 to obtain xn^1 = yn^0, and the preset single-peak function search method calculates the right test phase value yn^1 using the following formula:

[0041] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1);

[0042] If the test phase value is iterated for the (K+1)th time, it is determined whether the amplitude estimate corresponding to the left test phase value xn^K is greater than the amplitude estimate corresponding to the right test phase value yn^K.

[0043] If the value is greater than the given value, a second iteration of the phase value interval [an^K, bn^K] is performed to obtain the iterative right phase value bn^(K+1) and the iterative left phase value an^(K+1); where an^(K+1) = an^K and bn^(K+1) = yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1) = xn^K, and the preset single-peak function search method calculates the iterative left test phase value xn^(K+1) using the following formula:

[0044] xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1));

[0045] If it is less than, then the initial phase value interval [an^K, bn^K] is subjected to the first iteration of the phase value interval to obtain the phase value bn^(K+1) on the right end of the iteration and the phase value an^(K+1) on the left end of the iteration; where bn^(K+1)=bn^K, an^(K+1)=xn^K; the iteration right test phase value yn^K is assigned to the iteration left test phase value xn^(K+1) to obtain xn^(K+1)=yn^K, and the preset single-peak function search method calculates the iteration right test phase value yn^K by the following formula:

[0046] yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)).

[0047] In some embodiments, the step of calculating the amplitude estimates corresponding to the current iterative left test phase value xn^K and iterative right test phase value yn^K based on the amplitude estimates includes:

[0048] If the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, then the amplitude estimate corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimate corresponding to the iterative left test phase value xn^1, and the amplitude estimate is calculated for the iterative right test phase value yn^1 to obtain the amplitude estimate corresponding to the iterative right test phase value yn^1.

[0049] If the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), then the amplitude estimate corresponding to the iterative right test phase value yn^K is assigned to the amplitude estimate corresponding to the iterative left test phase value xn^(K+1), and the amplitude estimate is calculated for the iterative right test phase value yn^(K+1) to obtain the amplitude estimate corresponding to the iterative right test phase value yn^(K+1).

[0050] If the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, then the amplitude estimate corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimate corresponding to the iterative right test phase value yn^1, and the amplitude estimate is calculated for the iterative left test phase value xn^1 to obtain the amplitude estimate corresponding to the iterative left test phase value xn^1.

[0051] If the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), then the amplitude estimate corresponding to the iterative left test phase value xn^K is assigned to the amplitude estimate corresponding to the iterative right test phase value yn^(K+1), and the amplitude estimate is calculated for the iterative left test phase value xn^(K+1) to obtain the amplitude estimate corresponding to the iterative left test phase value xn^(K+1).

[0052] In some embodiments, obtaining the phase corresponding to the minimum amplitude estimate based on the current iterative left test phase value xn^K and iterative right test phase value yn^K includes:

[0053] Obtain the average phase value of the current iterative left test phase value xn^K and iterative right test phase value yn^K, and use it as the phase corresponding to the minimum amplitude estimate.

[0054] In some embodiments, obtaining the phase corresponding to the minimum amplitude estimate based on the current iterative left test phase value xn^K and iterative right test phase value yn^K includes:

[0055] Obtain the average phase value of the current iterative left test phase value xn^K and iterative right test phase value yn^K, and shift the average phase value by a preset phase to obtain the phase corresponding to the minimum amplitude estimate.

[0056] In some embodiments, if the average phase value is between [0, π), then the preset phase of the translation is π;

[0057] If the average phase value is between [π, 2π), then the preset phase of the translation is -π.

[0058] The phase after translation is the sum of the average phase value and the preset phase after translation.

[0059] In some embodiments, the initial phase value interval [an^0, bn^0] is generated in the following manner:

[0060] The phase value 0 is configured as the initial left-end phase value an^0, and the phase value 2π is configured as the initial right-end phase value bn^0, so as to obtain the initial phase value interval [an^0, bn^0].

[0061] or,

[0062] Obtain the estimated phase empirical value, and generate the initial phase value interval [an^0, bn^0] based on the estimated phase empirical value.

[0063] In some embodiments, obtaining the estimated phase empirical value includes:

[0064] After a known input signal is input into the DAC, the phase estimate value corresponding to the harmonic frequency or spurious frequency of the known input signal is obtained;

[0065] Based on the frequency relationship between the known input signal and the original input signal, the estimated phase empirical value corresponding to the harmonics of the original input signal is obtained from the phase estimation value; or...

[0066] Based on the frequency relationship between the known input signal and the original input signal, and the frequency relationship between the spurious frequency of the known input signal and the spurious frequency of the original input signal, the estimated phase empirical value corresponding to the spurious signal of the original input signal is obtained from the phase estimation value.

[0067] In some embodiments, the spectral analysis of the simulated test signal includes:

[0068] The simulated test signal is input into a spectrum analyzer for spectrum analysis.

[0069] or,

[0070] The simulated test signal is input to an analog-to-digital converter for analog-to-digital conversion and then subjected to Fourier transform for spectrum analysis.

[0071] In some embodiments, for harmonics, the frequency of the corresponding cancellation signal is the harmonic frequency of the harmonics of the original input signal; for spurious signals, the frequency of the corresponding cancellation signal is the spurious frequency of the spurious signals of the original input signal.

[0072] According to the second aspect, one embodiment provides a signal processing channel for implementing the phase estimation method as described in the first aspect, the signal processing channel including at least two DDS phase accumulators, each of the signal processing lines containing the DDS phase accumulators being connected in parallel, the number of which is defined as an integer H greater than 1;

[0073] One of the signal processing lines, which includes a DDS phase accumulator, generates the original input signal after phase-amplitude conversion and attenuation processing. The remaining signal processing lines, which also include DDS phase accumulators, generate harmonic cancellation signals or spurious cancellation signals based on the corresponding test phase values ​​after phase-amplitude conversion.

[0074] In some embodiments, the signal processing channel is used to process multiple harmonics, or multiple spurious signals, or at least one harmonic and at least one spurious signal. If the value of H is ≥3, the remaining other signal processing lines containing DDS phase accumulators are used to generate cancellation signals corresponding to multiple harmonics, or cancellation signals corresponding to multiple spurious signals, or cancellation signals corresponding to at least one harmonic and at least one spurious signal respectively.

[0075] Among them, the maximum number of times the remaining other signal processing lines containing DDS phase accumulators are called is equal to the sum of the number of harmonics and the number of spurious signals.

[0076] In some embodiments, the signal processing channel further includes a phase counter and a memory. The phase counter is used to accumulate the test phase value corresponding to the cancellation signal during the iteration of the test phase value. The memory is used to store each corresponding test phase value and its corresponding amplitude estimate.

[0077] In some embodiments, the total number L of harmonics and spurious emissions to be processed is obtained;

[0078] Divide the total number L by H-1 and round up to get the number of times the signal processing channel is called;

[0079] Based on the number of times the signal processing channel is invoked, the phase counter and memory are reset to clear the historically saved amplitude estimates and their corresponding test phase values.

[0080] According to a third aspect, one embodiment provides a computer-readable storage medium storing a program that can be executed by a processor to implement the method as described in the first aspect.

[0081] According to the phase estimation method, signal processing channel, and storage medium of the above embodiments, when the original input signal and the cancellation signal are superimposed, if the phase of the harmonic frequency or spurious frequency corresponding to the original input signal is in phase with the phase of the harmonic frequency or spurious frequency corresponding to the cancellation signal, the amplitude estimate of the harmonic frequency or spurious frequency corresponding to that phase reaches its maximum value; conversely, if the phases are out of phase, the amplitude estimate of the harmonic frequency or spurious frequency corresponding to that phase reaches its minimum value, and the phase and amplitude estimate of the cancellation signal exhibit a one-dimensional single-peak function. Therefore, the target error value is first determined, and the target Fibonacci sequence is calculated based on the target error value and the initial phase value interval. Phase search is performed based on the target Fibonacci sequence and the initial phase value interval, and the test phase value is iterated based on the initial left test phase value and the initial right test phase value. The corresponding cancellation signal is generated based on the searched test phase value. Then, the cancellation signal and the original input signal are superimposed, and digital-to-analog conversion is performed by a DAC. Finally, the analog signal output by the digital-to-analog converter is analyzed to obtain the amplitude estimate of the harmonic frequency or spurious frequency. Finally, at the end of the test phase value iteration, the phase corresponding to the minimum amplitude estimate is obtained based on the current left and right test phase values. Since the phase estimation process is mainly simplified by superimposing the canceled signal and the original input signal, analyzing the amplitude estimates corresponding to harmonic or spurious frequencies in the simulated test signal, and then performing a phase search based on the target Fibonacci sequence, the phase corresponding to the minimum amplitude estimate can be obtained. Attached Figure Description

[0082] Figure 1 This is a schematic diagram of the structure of a signal processing channel according to one embodiment;

[0083] Figure 2 This is a schematic diagram of the signal processing channel in another embodiment;

[0084] Figure 3 A flowchart illustrating the phase estimation process of a signal processing channel according to one embodiment;

[0085] Figure 4 A record diagram of test phase value iterations for one embodiment;

[0086] Figure 5 A record diagram of test phase value iterations for another embodiment;

[0087] Figure 6 This is a schematic flowchart of a phase estimation method according to one embodiment. Detailed Implementation

[0088] The present application will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; the relevant operations can be fully understood based on the description in the specification and general technical knowledge in the art.

[0089] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0090] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0091] In some embodiments of this application, the superposition of two signals of the same frequency is utilized. If the two signals are in phase, the superposition amplitude will increase; if the two signals are out of phase, the superposition amplitude will cancel each other out. Furthermore, the superposition amplitude exhibits a one-dimensional single-peak function. That is, the amplitude estimate of the superposition of the canceled signal and the original input signal also exhibits a one-dimensional single-peak function. Therefore, a phase search is performed based on the target Fibonacci sequence and the initial phase value interval. The test phase value is iterated based on the initial left and right test phase values. At the end of the test phase value iteration, the phase estimate is obtained based on the current iterated left and right test phase values. Since the phase estimation process is mainly simplified by superimposing the canceled signal and the original input signal, analyzing the amplitude estimates corresponding to harmonic or spurious frequencies in the simulated test signal, and then performing a phase search based on the target Fibonacci sequence, the phase corresponding to the minimum amplitude estimate can be obtained.

[0092] Some embodiments provide a signal processing channel; please refer to [the relevant documentation]. Figure 1The signal processing channel includes at least two DDS phase accumulators 10, and the signal processing lines where each DDS phase accumulator 10 is located are connected in parallel, and the number of them connected in parallel is defined as an integer H greater than 1.

[0093] The DDS phase accumulator 10 is used to accumulate phase values ​​based on the received frequency control word, obtaining the accumulated phase value. Please refer to [reference needed]. Figure 2 In some embodiments, the components within the signal processing circuit where each DDS phase accumulator 10 is located are connected in series. For example, the DDS phase accumulator 10 includes a phase adder and a phase register connected in series. The phase register outputs the current accumulated phase to the phase adder. The phase adder adds the frequency control word to the accumulated phase output by the phase register and sends the result to the phase register for the next phase accumulation. In some embodiments, the frequency control word can be generated by a processor, which can also be used to adjust the initial phase of the phase register. In some embodiments, the processor can be implemented based on devices with data processing capabilities such as CPUs, FPGAs, and microcontrollers. The frequency control word is determined by the frequency of the input signal, the clock frequency, and the total number of bits in the DDS phase accumulator 10.

[0094] In some embodiments, each signal processing line containing a DDS phase accumulator 10 can be configured with a phase amplitude mapping module 20. The phase amplitude mapping module 20 is used to obtain the corresponding signal amplitude based on the phase accumulation value output by the corresponding DDS phase accumulator 10, and output the corresponding digital waveform signal. In some embodiments, the phase amplitude mapping module 20 can obtain the signal amplitude corresponding to the phase accumulation value based on a phase lookup table, for example, a sine lookup table. In some embodiments, the phase amplitude mapping module 20 can also calculate the signal amplitude corresponding to the phase accumulation value in real time based on algorithms such as coordinate rotation.

[0095] In some embodiments, the signal processing lines where each DDS phase accumulator 10 is located can also share a phase amplitude mapping module 20, for example, the phase amplitude mapping module 20 is multiplexed among the various DDS phase accumulators 10.

[0096] In some embodiments, the digital waveform signal output by the phase amplitude mapping module 20 can be converted from digital to analog by the digital-to-analog converter unit 30 to output an analog waveform signal. In some embodiments, the digital-to-analog converter unit 30 can be based on an analog-to-digital converter to realize the digital-to-analog conversion of the signal. In some embodiments, the digital-to-analog converter unit 30 may further include a signal adder, which is used to superimpose multiple digital waveform signals before outputting them to the analog-to-digital converter to realize the digital-to-analog conversion of the superimposed signal.

[0097] In the above embodiments, each signal processing line containing a DDS phase accumulator 10 is used to generate one digital waveform signal. Therefore, each adjustment of the signal processing line can generate one digital waveform signal to correspond to a harmonic or spurious cancellation signal. Each adjustment of the signal processing channel can generate multiple digital waveform signals corresponding to the number of DDS phase accumulators 10 to correspond to multiple harmonics, multiple spurious signals, or spurious and harmonic cancellation signals.

[0098] The above is a description of the signal processing channel; please refer to it. Figure 3 The following section provides a detailed explanation of the phase estimation process based on the signal processing channel.

[0099] The original input signal is acquired. One of the signal processing channels, which includes a DDS phase accumulator 10, generates the original input signal after phase-amplitude conversion and attenuation processing.

[0100] In some embodiments, the signal processing circuit may also include an attenuator to perform signal attenuation processing based on the attenuator.

[0101] In some embodiments, the harmonics of the original input signal may include one or more harmonics, such as the second or third harmonic, or multiple harmonics such as the second and third harmonics. Therefore, the cancellation signal can be the signal corresponding to the second or third harmonic, or the signal corresponding to multiple harmonics such as the second and third harmonics. In some embodiments, the spurious signals of the original input signal may include one or more spurious signals. Therefore, the cancellation signal can be the signal corresponding to one spurious signal, or the signal corresponding to multiple spurious signals. In this embodiment, the harmonics and spurious signals of the original input signal refer to the harmonics and spurious signals generated after the original input signal is input to the DAC.

[0102] Obtain the initial phase value interval [an^0, bn^0]. Here, an^0 is the initial left-hand phase value, and bn^0 is the initial right-hand phase value. n is a positive integer greater than or equal to 1, corresponding to either a spurious signal or a harmonic; for example, n=1 corresponds to the second harmonic, n=2 corresponds to the third harmonic, and n=3 corresponds to a spurious signal.

[0103] In some embodiments, phase value 0 is configured as the initial left-hand phase value an^0, and phase value 2π is configured as the initial right-hand phase value bn^0 to obtain the initial phase value interval [an^0, bn^0]. In this embodiment, the desired phase value is searched based on the full range of phases. After the canceled signal and the original input signal are superimposed, there is a maximum and a minimum value in the amplitude estimate across the full range of phases. Therefore, the phase value corresponding to either the maximum or the minimum value can be searched.

[0104] In some embodiments, an estimated phase empirical value is obtained, and an initial phase value interval [an^0, bn^0] is generated based on the estimated phase empirical value. In some embodiments, the initial phase value interval [an^0, bn^0] can be generated based on a preset range before and after the estimated phase empirical value. For example, the estimated phase empirical value is used as the center position, and phase values ​​that are larger than the estimated phase empirical value by a preset phase value are used as the initial right-end phase value bn^0, and phase values ​​that are smaller than the estimated phase empirical value by a preset phase value are used as the initial left-end phase value an^0. In some embodiments, for each original input signal without an estimated phase empirical value, the entire phase range can be used as the initial phase value interval [an^0, bn^0]. For each original input signal with an estimated phase empirical value, the initial phase value interval [an^0, bn^0] generated based on the estimated phase empirical value is used.

[0105] In some embodiments, after obtaining a known input signal input to the DAC, the phase estimate value corresponding to the harmonic frequency or spurious frequency of the known input signal is obtained. Since there is a certain relationship between the frequency and phase of a signal, the phase corresponding to the harmonic frequency or spurious frequency of the original input signal can be estimated based on the frequency of the known input signal and the phase estimate value corresponding to the harmonic frequency or spurious frequency of the known input signal. For example, if the frequencies of the known input signal and the original input signal are different, the estimated phase value corresponding to the harmonic frequency of the original input signal is obtained from the phase estimate value corresponding to the harmonic frequency based on the frequency relationship between the known input signal and the original input signal. Alternatively, the estimated phase value corresponding to the spurious frequency of the original input signal is obtained from the phase estimate value corresponding to the spurious frequency based on the frequency relationship between the known input signal and the original input signal, and the frequency relationship between the spurious frequency of the known input signal and the spurious frequency of the original input signal. For example, if the frequencies of the known input signal and the original input signal are the same, the phase estimate value corresponding to the harmonic frequency is used as the estimated phase value corresponding to the harmonic frequency of the original input signal. For example, if the spurious frequency of the input signal is known to be the same as the spurious frequency of the original input signal, then the phase estimate corresponding to the spurious frequency is used as the empirical value of the estimated phase corresponding to the spurious frequency of the original input signal.

[0106] In the above embodiments, when signals of the same frequency are input to the same digital-to-analog converter, the phases of the resulting harmonics are basically consistent. Therefore, for a known input signal whose phase estimation has already been completed, subsequent processing can be performed based on the obtained estimated phase, without the need for repeated acquisition. Furthermore, for the original input signal whose phase estimation has not been completed, the phase of the corresponding harmonic of the original input signal can be predicted based on the phase of the known input signal's harmonics, and then phase estimation can be performed on the original input signal based on the predicted phase. This further simplifies the acquisition complexity and improves the accuracy of phase estimation.

[0107] In some embodiments, when generating the initial phase value interval [an^0, bn^0] based on the estimated phase empirical value, the estimated phase empirical value is used as the center to determine the initial phase value interval [an^0, bn^0], where an^0 = bc, bn^0 = b + c, and b is the estimated phase empirical value, and c is the preset phase value. In this embodiment, since the estimated phase empirical value has already been obtained, the initial phase value interval [an^0, bn^0] can be determined within a smaller phase range, thus reducing the amount of data calculation and improving the calculation accuracy.

[0108] Determine the target error value, and calculate the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0].

[0109] In some embodiments, the target value of the target Fibonacci sequence F(D) is calculated based on the following formula:

[0110] δ=(bn^0-an^0) / ε;

[0111] Where δ is the target value and ε is the target error value;

[0112] In some embodiments, when the Dth value in the Fibonacci sequence is greater than or equal to the aforementioned target value, the length of the Fibonacci sequence is determined to be D, so as to obtain the target Fibonacci sequence F(D). In this embodiment, the Fibonacci sequence is an infinitely long sequence, so it is necessary to first determine the target value of the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0], and then determine the length D of the target Fibonacci sequence F(D) based on the target value.

[0113] In some embodiments, the smaller the target error value and the larger the length of the target Fibonacci sequence F(D), the higher the accuracy of the final phase estimation result. Therefore, the target error value can be determined according to the actual situation.

[0114] The initial left test phase value xn^0 and the initial right test phase value yn^0 are determined based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0].

[0115] In some embodiments, when determining the initial left test phase value xn^0 and the initial right test phase value yn^0 based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], the initial left test phase value xn^0 is calculated using the following formula:

[0116] xn^0=an^0+f(D-2) / f(D)*(bn^0-an^0);

[0117] Where f(D-2) is the (D-2)th value in the target Fibonacci sequence F(D), and F(D) is the Dth value in the target Fibonacci sequence F(D).

[0118] The initial right test phase value yn^0 is calculated using the following formula:

[0119] yn^0=an^0+f(D-1) / f(D)*(bn^0-an^0);

[0120] Where f(D-1) is the (D-1)th value in the target Fibonacci sequence F(D).

[0121] Amplitude estimates are calculated for the initial left test phase value xn^0 and the initial right test phase value yn^0, respectively.

[0122] In some embodiments, when calculating the amplitude estimate, a cancellation signal is first generated based on the harmonic frequencies and amplitude values ​​of the harmonics of the original input signal, or based on the spurious frequencies and amplitude values ​​of the spurious signals of the original input signal, and the corresponding test phase value. For example, when calculating the amplitude estimate for the initial right test phase value yn^0, the corresponding test phase value is the initial right test phase value yn^0.

[0123] In some embodiments, when generating cancellation signals, the remaining signal processing lines in the signal processing channel, which include the DDS phase accumulator 10, generate cancellation signals corresponding to harmonics or cancellation signals corresponding to spurious signals based on the phase values ​​in the corresponding phase table to be measured after phase-amplitude conversion.

[0124] In some embodiments, before generating the cancellation signal, the original input signal can be first input to a digital-to-analog converter (DAC) for digital-to-analog conversion to obtain the corresponding analog input signal output by the DAC. Then, spectral analysis is performed on the analog input signal to obtain an estimate of the harmonic amplitude of the original input signal. Alternatively, the spurious frequencies and spurious amplitudes of the original input signal can be obtained, for example, based on information known from other measuring devices.

[0125] In some embodiments, the analog input signal can be converted to a digital signal using an analog-to-digital converter (ADC). Then, a time-domain to frequency-domain transformation, such as a Fast Fourier Transform (FFT), is performed on the digital signal using a processor or external data processing device. The transformed frequency-domain signal is then analyzed to obtain an estimate of the harmonic amplitude of the original input signal. Since the FFT frequency may have inaccuracies, the obtained amplitude estimate can be selected as the amplitude corresponding to the harmonic frequency or as the maximum amplitude within the frequency range surrounding the harmonic frequency.

[0126] In some embodiments, when generating cancellation signals, for harmonics, the frequency of the corresponding cancellation signal is the harmonic frequency of the harmonics of the original input signal, and for spurious signals, the frequency of the corresponding cancellation signal is the spurious frequency of the spurious signals of the original input signal.

[0127] In some embodiments, when attenuating to obtain the original input signal, the amplitude of the digital signal under test (DSB) after superimposing the canceled signal on the original input signal can be such that it meets or is less than the maximum input range of the digital-to-analog converter (DAC). In some embodiments, when the amplitude of the digital signal under test meets the maximum input range of the DAC, the DAC can be fully utilized to improve the accuracy of subsequent data processing. In some embodiments, the amplitude of the attenuation of the original input signal can be controlled by a processor or by an external data processing device.

[0128] In some embodiments, the remaining signal processing lines containing the DDS phase accumulator 10 may generate a cancellation signal corresponding to a harmonic or a cancellation signal corresponding to a spurious signal. In some embodiments, the remaining signal processing lines containing the DDS phase accumulator 10 may generate multiple cancellation signals corresponding to harmonics, multiple cancellation signals corresponding to spurious signals, or at least one cancellation signal corresponding to a harmonic and at least one cancellation signal corresponding to a spurious signal. This can be generated separately based on multiple signal processing lines containing the DDS phase accumulator 10, or multiplexed based on a single signal processing line containing the DDS phase accumulator 10.

[0129] For example, if the value of H is ≥ 3, the remaining signal processing lines containing the DDS phase accumulator 10 are used to generate multiple harmonic cancellation signals, multiple spurious cancellation signals, or at least one harmonic and at least one spurious cancellation signal. The maximum number of times the remaining signal processing lines containing the DDS phase accumulator 10 can be called is equal to the sum of the number of harmonics and the number of spurious signals. Each call to the signal processing line generates one harmonic cancellation signal or one spurious cancellation signal.

[0130] Then, the cancel signal and the original input signal are superimposed to obtain the digital test signal. The digital test signal is then input into the DAC for digital-to-analog conversion to obtain the analog test signal. The analog test signal is then subjected to spectrum analysis to obtain the amplitude estimate of the harmonic frequency or spurious frequency corresponding to the test phase value.

[0131] In some embodiments, the simulated test signal can also be converted from analog to digital using an analog-to-digital converter (ADC) to obtain a corresponding digital signal. Then, a processor or external data processing device can perform a time-domain to frequency-domain transformation on this digital signal, such as a Fast Fourier Transform (FFT). The transformed frequency-domain signal is then analyzed to obtain amplitude estimates corresponding to harmonic or spurious frequencies in the simulated test signal. In some embodiments, the simulated test signal can also be directly input to a spectrum analyzer for spectral analysis.

[0132] After completing the amplitude estimation, determine whether the length D of the target Fibonacci sequence F(D) meets the preset length.

[0133] If the length D does not meet the preset length, then test phase value iteration is performed based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimates, to obtain the iterated left test phase value xn^K and the iterated right test phase value yn^K, where K is the iteration number and its initial value is 1. In some embodiments, when iterating the test phase value based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimates, if it is the first test phase value iteration, the iteration process is as follows:

[0134] First, determine whether the amplitude estimate corresponding to the initial left test phase value xn^0 is greater than the amplitude estimate corresponding to the initial right test phase value yn^0.

[0135] If the amplitude estimate corresponding to the initial left test phase value xn^0 is greater than the amplitude estimate corresponding to the initial right test phase value yn^0, then the first iteration of the phase value interval [an^0, bn^0] is performed, that is, the phase value interval is reduced to the right. At this time, the phase value at the right end remains unchanged, and the left test phase value is assigned to the phase value at the left end of the iteration to obtain the phase value at the right end of the iteration bn^1 and the phase value at the left end of the iteration an^1. Where bn^1 = bn^0, an^1 = xn^0. When performing the first iteration of the phase value interval, the flag sign = 0 can be set.

[0136] Simultaneously, the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, resulting in xn^1 = yn^0, and the iterative right test phase value yn^1 is calculated using the following formula:

[0137] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1).

[0138] If the amplitude estimate corresponding to the initial left test phase value xn^0 is less than the amplitude estimate corresponding to the initial right test phase value yn^0, then the second iteration of the phase value interval [an^0, bn^0] is performed, that is, the phase value interval is reduced to the left. At this time, the phase value at the left end remains unchanged, and the right test phase value is assigned to the phase value at the right end of the iteration to obtain the iterated right phase value bn^1 and the iterated left phase value an^1; where an^1 = an^0, bn^1 = yn^0; when performing the second iteration of the phase value interval, the flag sign = 1 can be set.

[0139] Simultaneously, the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, resulting in yn^1 = xn^0, and the iterative left test phase value xn^1 is calculated using the following formula:

[0140] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1).

[0141] The aforementioned test phase value iteration is the phase corresponding to the minimum value of the search amplitude estimate. In some embodiments, the phase corresponding to the maximum value of the search amplitude estimate can also be iterated based on the test phase value. The process is symmetrical and reversed from the above process, which will be briefly described below.

[0142] In some embodiments, it is first determined whether the amplitude estimate corresponding to the initial left test phase value xn^0 is greater than the amplitude estimate corresponding to the initial right test phase value yn^0.

[0143] If the value is greater than the given value, then the second iteration of the phase value interval [an^0, bn^0] is performed to obtain the phase value bn^1 on the right side of the iteration and the phase value an^1 on the left side of the iteration. Simultaneously, the initial left test phase value xn^0 is assigned to the right test phase value yn^1, and the left test phase value xn^1 is calculated. The specific process will not be elaborated further.

[0144] If the value is less than the specified value, the first iteration of the phase value interval [an^0, bn^0] is performed to obtain the phase value bn^1 on the right side of the iteration and the phase value an^1 on the left side of the iteration. At the same time, the initial right test phase value yn^0 is assigned to the left test phase value xn^1 of the iteration, and the right test phase value yn^1 of the iteration is calculated. The specific process will not be elaborated here.

[0145] In the above embodiments, when iterating the test phase value based on the target Fibonacci sequence F(D), since the length of the target Fibonacci sequence F(D) is fixed, the number of test phase value iterations can be determined. Furthermore, during each test phase value iteration, the initial right test phase value yn^0 can be assigned to the iterated left test phase value xn^1, or the initial left test phase value xn^0 can be assigned to the iterated right test phase value yn^1. This means that for each test phase value iteration, only a new phase value interval endpoint and a new test phase value need to be calculated, thereby reducing the amount of data computation.

[0146] The above explains the relevant information for the first test phase value iteration. If the (K+1)th test phase value iteration is performed, the iteration process is as follows:

[0147] First, determine whether the amplitude estimate corresponding to the left test phase value xn^K is greater than the amplitude estimate corresponding to the right test phase value yn^K. Here, K is the iteration number and its initial value is 1, and xn^K and yn^K are the left test phase value and the right test phase value corresponding to the Kth iteration, respectively.

[0148] If the amplitude estimate corresponding to the left test phase value xn^K is greater than the amplitude estimate corresponding to the right test phase value yn^K, then the first iteration of the phase value interval [an^K, bn^K] is performed, i.e., the phase value interval is reduced to the right. At this time, the right-end phase value remains unchanged, and the left test phase value is assigned to the left-end phase value to obtain the right-end phase value bn^(K+1) and the left-end phase value an^K. Where bn^(K+1) = bn^K, and an^(K+1) = xn^K. During the first iteration of the phase value interval, the flag sign = 0 can be set.

[0149] Simultaneously, the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), resulting in xn^(K+1) = yn^K. The preset single-peak function search method calculates the iterative right test phase value yn^(K+1) using the following formula:

[0150] yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)).

[0151] If the amplitude estimate corresponding to the left test phase value xn^K is less than the amplitude estimate corresponding to the right test phase value yn^K, then the second iteration of the phase value interval [an^K, bn^K] is performed, that is, the phase value interval is reduced to the left. At this time, the phase value at the left end remains unchanged, and the right test phase value is assigned to the phase value at the right end of the iteration to obtain the right phase value bn^(K+1) and the left phase value an^(K+1); where an^(K+1) = an^K, bn^(K+1) = yn^K; where, when performing the second iteration of the phase value interval, the flag sign = 1 can be set.

[0152] Simultaneously, the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), resulting in yn^(K+1) = xn^K. The preset single-peak function search method calculates the iterative left test phase value xn^(K+1) using the following formula:

[0153] xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)).

[0154] The aforementioned test phase value iteration corresponds to the phase corresponding to the minimum value of the search amplitude estimate. In some embodiments, the phase corresponding to the maximum value of the search amplitude estimate can also be searched based on the test phase value iteration. The process is symmetrical and reversed from the above process. For details, please refer to the process of the first test phase value iteration, which will not be repeated here. In the above embodiments, each test phase value iteration only requires the additional calculation of a new phase value interval endpoint and a new test phase value, thereby reducing the amount of data computation.

[0155] Then, based on the amplitude estimates, the amplitude estimates corresponding to the current iterative left test phase value xn^K and the iterative right test phase value yn^K are calculated. For example, when calculating the amplitude estimates corresponding to the current iterative left test phase value xn^1 and the iterative right test phase value yn^1, the length of the target Fibonacci sequence F(D) is decreased by 1 and the iteration count is increased by 1, and the determination of whether the preset length is met is continued. For example, when calculating the amplitude estimates corresponding to the current iterative left test phase value xn^(K+1) and the iterative right test phase value yn^(K+1), the length of the target Fibonacci sequence F(D) is decreased by 1 and the iteration count is increased by 1, and the determination of whether the preset length is met is continued.

[0156] In some embodiments, if the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, i.e., the flag sign = 0, then the amplitude estimate corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimate corresponding to the iterative left test phase value xn^1, and the amplitude estimate of the iterative right test phase value yn^1 is calculated to obtain the amplitude estimate corresponding to the iterative right test phase value yn^1.

[0157] In some embodiments, if the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), i.e., the flag sign = 0, then the amplitude estimate corresponding to the iterative right test phase value yn^K is assigned to the amplitude estimate corresponding to the iterative left test phase value xn^(K+1), and the amplitude estimate of the iterative right test phase value yn^(K+1) is calculated to obtain the amplitude estimate corresponding to the iterative right test phase value yn^(K+1).

[0158] In some embodiments, if the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, i.e., the flag sign = 1, then the amplitude estimate corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimate corresponding to the iterative right test phase value yn^1, and the amplitude estimate of the iterative left test phase value xn^1 is calculated to obtain the amplitude estimate corresponding to the iterative left test phase value xn^1.

[0159] In some embodiments, if the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), i.e., the flag sign = 1, then the amplitude estimate corresponding to the iterative left test phase value xn^K is assigned to the amplitude estimate corresponding to the iterative right test phase value yn^(K+1), and the amplitude estimate is calculated for the iterative left test phase value xn^(K+1) to obtain the amplitude estimate corresponding to the iterative left test phase value xn^(K+1). If the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1.

[0160] If the length D meets the preset length, the test phase value iteration ends, and the current iterative left test phase value xn^K and iterative right test phase value yn^K are output. Based on the current iterative left test phase value xn^K and iterative right test phase value yn^K, the phase corresponding to the minimum amplitude estimate is obtained.

[0161] In some embodiments, the average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is obtained as the phase corresponding to the minimum amplitude estimate. For example, if the phase corresponding to the minimum amplitude estimate is directly searched iteratively based on the test phase values, the average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is directly used as the phase corresponding to the minimum amplitude estimate.

[0162] In some embodiments, the average phase value of the current iterative left test phase value xn^K and iterative right test phase value yn^K is obtained, and the average phase value is shifted by a preset phase to obtain the phase corresponding to the minimum amplitude estimate. For example, if the phase corresponding to the maximum amplitude estimate is directly searched based on the test phase values, then the average phase value needs to be inverted before the phase corresponding to the minimum amplitude estimate can be obtained.

[0163] In some embodiments, if the average phase value is between [0, π), the preset phase of the translation is π; if the average phase value is between [π, 2π), the preset phase of the translation is -π, and the phase after translation is the sum of the average phase value and the preset phase of translation. In this embodiment, based on the phase range in which the average phase value lies, different addition and subtraction operations are performed on the average phase value so that the phase after translation is always a positive value, for the convenience of subsequent use and calculation.

[0164] In the above embodiments, since there is a fixed relationship between the left test phase value and the right test phase value and the right end phase value and the left end phase value, they can be converted to each other based on this fixed relationship. Therefore, in the above embodiments, the phase corresponding to the minimum amplitude estimation value can be obtained based on the left test phase value and the right test phase value, and the phase corresponding to the minimum amplitude estimation value can also be obtained based on the right end phase value and the left end phase value.

[0165] In some embodiments, during the above-mentioned test phase value iteration, the signal processing channel may further include a phase counter and a memory. The phase counter is used to accumulate the test phase value corresponding to the cancellation signal during the test phase value iteration, and the memory is used to store each corresponding test phase value and its corresponding amplitude estimate.

[0166] In the above embodiments, although the phase of the final estimated output is called the estimated phase of the harmonic or the estimated phase of the spurious, it should be clarified that it is the inverse phase of the phase of the real harmonic, and there is a phase difference of π between it and the phase of the real harmonic. Therefore, the phase of the output can be directly used when generating the cancellation signal corresponding to the harmonic or spurious.

[0167] In the above embodiments, the signal processing channel can process at least one harmonic or spurious signal, or it can process both harmonics and spurious signals. In some embodiments, the total number L of harmonics and spurious signals to be processed is obtained, and the total number L is divided by H-1 and rounded up to obtain the number of times the signal processing channel is invoked. Based on the number of times the signal processing channel is invoked, the phase counter and memory are reset to clear the historically saved amplitude estimates and their corresponding phase values. Each invoke of the signal processing channel can process H-1 harmonics or spurious signals.

[0168] In some embodiments, a reset operation is required when calling the signal processing channel to avoid mutual interference. For example, if it is detected that the signal processing channel has been cleared before calling the signal processing channel, a reset is not required; if it is detected that the signal processing channel has not been cleared before calling the signal processing channel, a reset and clearing operation is required. Therefore, when resetting the phase counter and memory according to the number of times the signal processing channel is called, the number of times the signal processing channel is called can be the same as the number of times the reset is performed. For example, a reset and clearing operation is performed before each call to the signal processing channel. When it is detected that the signal processing channel has been cleared, the number of times the signal processing channel is called can be less than the number of times the reset is performed.

[0169] The following examples illustrate this point.

[0170] Assume the input frequency of the original input signal is f_in = 30MHz. Then, calculate the frequency control word based on the input frequency f_in, and then calculate the phase sequence output by the DDS phase accumulator 10. Address the sine lookup table according to the output phase sequence to obtain the full-scale signal. Multiply this full-scale signal by an attenuation coefficient α = 0.95 before inputting it to the DAC. Assume the harmonics whose phases are to be estimated are the second and third harmonics, then their frequencies are f_2 = 2 * f_in = 60MHz and f_3 = 3 * f_in = 90MHz, respectively.

[0171] Let the initial phase value interval be [an^0, bn^0] = [0, 1], corresponding to a phase value of [0, 2π]. That is, the initial left-end phase value an^0 is 0, and the initial right-end phase value bn^0 is 2π. Assuming the target error value is ε = 0.01, the target Fibonacci sequence F(D) target value δ = (bn^0 - an^0) / ε = 100. Therefore, the target Fibonacci sequence can be calculated as follows:

[0172] F(D)=[1,1,2,3,5,8,13,21,34,55,89,144];

[0173] That is, the sequence length D is equal to 12.

[0174] The left test phase value xn^0 = an^0 + (55 / 144)*(bn^0 - an^0) = 0.382, that is, the phase value is 0.382*2π. The initial right test phase value yn^0 = an^0 + (59 / 144)*(bn^0 - an^0) = 0.618, that is, the phase value is 0.618*2π.

[0175] In some embodiments, an estimated empirical value of the phase can also be obtained, and the phase value interval [an^0, bn^0] = [0.4, 0.5] can be determined based on the estimated empirical value of the phase. Assuming the target error value is ε = 0.005, the target value of the target Fibonacci sequence F(D) is δ = (bn^0 - an^0) / ε = 0. Therefore, the target Fibonacci sequence can be calculated as F(D) = [1, 1, 2, 3, 5, 8, 13, 21], that is, the sequence length D is equal to 8.

[0176] The initial left test phase value xn^0 = an^0 + (8 / 21)*(bn^0 - an^0) = 0.4381, that is, the phase value is 0.4381*2π. The initial right test phase value yn^0 = an^0 + (13 / 21)*(bn^0 - an^0) = 0.4619, that is, the phase value is 0.4619*2π.

[0177] Based on the frequencies f_n of the second and third harmonics, the amplitude estimates of the second and third harmonics of the original input signal, and the phase values ​​corresponding to xn^0 = 0.382 and yn^0 = 0.618, cancellation signals corresponding to the second and third harmonics are generated. These cancellation signals are then superimposed on the original input signal and input to the DAC. A spectrum analyzer is used to analyze the output signal of the DAC, recording the amplitude estimates corresponding to xn^0 and yn^0.

[0178] Determine if the sequence length D is greater than 2.

[0179] If the length D is greater than 2, then test the phase value iteration and search for the minimum value of the amplitude estimate. Please refer to the iteration results. Figure 4 and Figure 5 That is, to determine in turn whether the amplitude estimate corresponding to xn^0 of the second harmonic and the third harmonic is greater than the amplitude estimate corresponding to yn^0.

[0180] If so, the phase value interval is reduced to the right. The right-end phase value remains unchanged, and the left test phase value is assigned to the left-end iteration phase value, i.e., bn^1 = bn^0, an^1 = xn^0. Simultaneously, the initial right test phase value yn^0 is assigned to the left-end iteration test phase value xn^1, i.e., xn^1 = yn^0, and the right test phase value is recalculated.

[0181] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1);

[0182] And set the flag sign_n = 0, at which point the iteration count K is 1.

[0183] If not, the phase value interval is reduced to the left. The left-end phase value remains unchanged, and the right-end test phase value is assigned to the right-end iteration phase value, i.e., an^1 = an^0, bn^1 = yn^0. Simultaneously, the initial left-end test phase value xn^0 is assigned to the right-end iteration test phase value yn^1, i.e., yn^1 = xn^0, and the left-end test phase value is recalculated.

[0184] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1),

[0185] And set the flag sign_n = 1, at which point the iteration count K is 1.

[0186] If the flag sign_n = 0, the amplitude estimate corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimate corresponding to the iterative left test phase value xn^1, and the amplitude estimate is calculated for the iterative right test phase value yn^1 to obtain the amplitude estimate corresponding to the iterative right test phase value yn^1.

[0187] If the flag sign_n = 1, then the amplitude estimate corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimate corresponding to the iterative right test phase value yn^1, and the amplitude estimate of the iterative left test phase value xn^1 is calculated to obtain the amplitude estimate corresponding to the iterative left test phase value xn^1.

[0188] Decrease the length D of the target Fibonacci sequence F(D) by 1 and increment the iteration count K by 1, then continue with the length determination above.

[0189] If the length D is less than or equal to 2, then output based on the current iteration number K:

[0190] φn=(xn^K+yn^K) / 2.

[0191] The above is a description of the signal processing channel.

[0192] Some embodiments provide a phase estimation method that can be applied to the signal processing channel described above. Please refer to... Figure 6 The method for obtaining harmonic phase includes the following steps:

[0193] Step 100: Obtain the original input signal and the initial phase value interval, determine the target error value, and calculate the target Fibonacci sequence based on the target error value and the initial phase value interval. Where an^0 is the initial left-hand phase value and bn^0 is the initial right-hand phase value. The length of the target Fibonacci sequence F(D) is D.

[0194] Step 110: Determine the initial left test phase value and the initial right test phase value based on the target Fibonacci sequence and the initial phase value interval, and calculate the amplitude estimate. Based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], determine the initial left test phase value xn^0 and the initial right test phase value yn^0, and calculate the amplitude estimate for each: Generate a cancellation signal based on the harmonic frequencies and harmonic amplitudes of the original input signal's harmonics or the spurious frequencies and spurious amplitudes of the original input signal, and the corresponding test phase values; Superimpose the cancellation signal and the original input signal to obtain the digital test signal; Input the digital test signal into a DAC for digital-to-analog conversion to obtain the analog test signal; Perform spectrum analysis on the analog test signal to obtain the amplitude estimate of the harmonic frequency or spurious frequency corresponding to the test phase value.

[0195] Step 120: Determine whether the length of the target Fibonacci sequence meets the preset length.

[0196] Step 130: If satisfied, obtain the phase corresponding to the minimum amplitude estimate based on the current iterative left test phase value and iterative right test phase value. End the test phase value iteration and output the current iterative left test phase value xn^K and iterative right test phase value yn^K. Obtain the phase corresponding to the minimum amplitude estimate based on the current iterative left test phase value xn^K and iterative right test phase value yn^K. Here, K is the iteration number and its initial value is 1, and xn^K and yn^K are the iterative left test phase value and iterative right test phase value corresponding to the Kth iteration, respectively.

[0197] Step 140: If not satisfied, perform test phase value iteration and decrement the length of the target Fibonacci sequence by 1. Based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimates, perform test phase value iteration to obtain the iterated left test phase value xn^K and the iterated right test phase value yn^K. Based on the amplitude estimates, calculate the amplitude estimates corresponding to the current iterated left test phase value xn^K and the iterated right test phase value yn^K, respectively. Decrement the length D of the target Fibonacci sequence F(D) by 1 and increment the iteration count K by 1, and continue to determine whether the preset length is satisfied.

[0198] Some embodiments provide a computer-readable storage medium storing a program that can be executed by a processor to implement the phase estimation method described above.

[0199] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the processor 30 executes the program in the memory, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash drive, or portable hard drive, and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the processor 30 executes the program in the memory, all or part of the functions in the above embodiments can be achieved.

[0200] The above examples illustrate this application only to aid understanding and are not intended to limit its scope. Those skilled in the art to which this application pertains can make various simple deductions, modifications, or substitutions based on the ideas presented.

Claims

1. A phase estimation method, characterized in that, include: Obtain the original input signal and the initial phase value interval [an^0, bn^0]; where an^0 is the initial left-end phase value and bn^0 is the initial right-end phase value; Determine the target error value, and calculate the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0]; wherein the length of the target Fibonacci sequence F(D) is D; Based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], the initial left test phase value xn^0 and the initial right test phase value yn^0 are determined, and the amplitude estimates of the initial left test phase value xn^0 and the initial right test phase value yn^0 are calculated respectively to obtain the amplitude estimates of the corresponding test phase values. Determine whether the length D of the target Fibonacci sequence F(D) satisfies the preset length; If not satisfied, test phase value iteration is performed based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimates, to obtain the iterated left test phase value xn^K and the iterated right test phase value yn^K. Based on the amplitude estimates, the amplitude estimates corresponding to the current iterated left test phase value xn^K and the iterated right test phase value yn^K are calculated, where K is the iteration number and its initial value is 1, and xn^K and yn^K are the iterated left test phase value and the iterated right test phase value corresponding to the Kth iteration, respectively. The length D of the target Fibonacci sequence F(D) is reduced by 1 and the iteration number K is increased by 1, and it is continued to determine whether the preset length is satisfied. If satisfied, the test phase value iteration ends, and the phase corresponding to the minimum amplitude estimate is obtained based on the current left test phase value xn^K and right test phase value yn^K. The amplitude estimation calculation includes: generating a cancellation signal based on the harmonic frequencies and harmonic amplitudes of the harmonics of the original input signal or the spurious frequencies and spurious amplitudes of the spurious signals of the original input signal, and the corresponding test phase value; superimposing the cancellation signal and the original input signal to obtain a digital signal under test; inputting the digital signal under test into a DAC for digital-to-analog conversion to obtain an analog signal under test; and performing spectral analysis on the analog signal under test to obtain the amplitude estimate of the corresponding test phase value.

2. The phase estimation method as described in claim 1, characterized in that, The calculation of the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0] includes: The target value of the target Fibonacci sequence F(D) is calculated based on the following formula: δ=(bn^0-an^0) / ε; Wherein, δ is the target value, and ε is the target error value; When the Dth value in the Fibonacci sequence is greater than or equal to the target value, the length of the Fibonacci sequence is determined to be D, so as to obtain the target Fibonacci sequence F(D).

3. The phase estimation method as described in claim 1, characterized in that, The determination of the initial left test phase value xn^0 and the initial right test phase value yn^0 based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0] includes: The initial left test phase value xn^0 is calculated using the following formula: xn^0=an^0+f(D-2) / f(D)*(bn^0-an^0); Where f(D-2) is the (D-2)th value in the target Fibonacci sequence F(D), and F(D) is the Dth value in the target Fibonacci sequence F(D); The initial right test phase value yn^0 is calculated using the following formula: yn^0=an^0+f(D-1) / f(D)*(bn^0-an^0); Where f(D-1) is the (D-1)th value in the target Fibonacci sequence F(D).

4. The phase estimation method as described in claim 3, characterized in that, The test phase value iteration includes: If the test phase value iteration is performed for the first time, it is determined whether the amplitude estimate corresponding to the initial left test phase value xn^0 is greater than the amplitude estimate corresponding to the initial right test phase value yn^0. If it is greater than, then the initial phase value interval [an^0, bn^0] is subjected to the first iteration of the phase value interval to obtain the right-hand phase value bn^1 and the left-hand phase value an^1; where bn^1=bn^0, an^1=xn^0; the initial right test phase value yn^0 is assigned to the left test phase value xn^1 to obtain xn^1=yn^0, and the preset single-peak function search method calculates the right test phase value yn^1 using the following formula: yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1); If the value is less than the given value, a second iteration of the phase value interval [an^0, bn^0] is performed to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; where an^1 = an^0, bn^1 = yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1 = xn^0, and the preset single-peak function search method calculates the iterative left test phase value xn^1 using the following formula: xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1); If the test phase value is iterated for the (K+1)th time, it is determined whether the amplitude estimate corresponding to the left test phase value xn^K is greater than the amplitude estimate corresponding to the right test phase value yn^K. If it is greater than, then perform the first iteration of the iterative phase value interval [an^K, bn^K] to obtain the right-hand phase value bn^(K+1) and the left-hand phase value an^(K+1); where bn^(K+1) = bn^K, and an^(K+1) = xn^K; assign the right-hand test phase value yn^K to the left-hand test phase value xn^(K+1) to obtain xn^(K+1) = yn^K, and the preset single-peak function search method calculates the right-hand test phase value yn^K using the following formula: yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)); If it is less than, then a second iteration of the phase value interval [an^K, bn^K] is performed to obtain the iterative right phase value bn^(K+1) and the iterative left phase value an^(K+1); where an^(K+1) = an^K, bn^(K+1) = yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1) = xn^K, and the preset single-peak function search method calculates the iterative left test phase value xn^(K+1) using the following formula: xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)).

5. The phase estimation method as described in claim 3, characterized in that, The test phase value iteration includes: If the test phase value iteration is performed for the first time, it is determined whether the amplitude estimate corresponding to the initial left test phase value xn^0 is greater than the amplitude estimate corresponding to the initial right test phase value yn^0. If the value is greater than the given value, a second iteration of the phase value interval [an^0, bn^0] is performed to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; where an^1 = an^0, bn^1 = yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1 = xn^0, and the preset single-peak function search method calculates the iterative left test phase value xn^1 using the following formula: xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1); If it is less than, then the initial phase value interval [an^0, bn^0] is subjected to the first iteration of the phase value interval to obtain the right-hand phase value bn^1 and the left-hand phase value an^1; where bn^1=bn^0, an^1=xn^0; the initial right test phase value yn^0 is assigned to the left test phase value xn^1 to obtain xn^1=yn^0, and the preset single-peak function search method calculates the right test phase value yn^1 using the following formula: yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1); If the test phase value is iterated for the (K+1)th time, it is determined whether the amplitude estimate corresponding to the left test phase value xn^K is greater than the amplitude estimate corresponding to the right test phase value yn^K. If the value is greater than the given value, a second iteration of the phase value interval [an^K, bn^K] is performed to obtain the iterative right phase value bn^(K+1) and the iterative left phase value an^(K+1); where an^(K+1) = an^K and bn^(K+1) = yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1) = xn^K, and the preset single-peak function search method calculates the iterative left test phase value xn^(K+1) using the following formula: xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)); If it is less than, then the first iteration of the iterative phase value interval [an^K, bn^K] is performed to obtain the phase value bn^(K+1) on the right end of the iteration and the phase value an^(K+1) on the left end of the iteration; where bn^(K+1)=bn^K, an^(K+1)=xn^K; the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1) to obtain xn^(K+1)=yn^K, and the preset single-peak function search method calculates the iterative right test phase value yn^K by the following formula: yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)).

6. The phase estimation method as described in claim 4 or 5, characterized in that, The step of calculating the amplitude estimates corresponding to the current iterative left test phase value xn^K and iterative right test phase value yn^K based on the amplitude estimates includes: If the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, then the amplitude estimate corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimate corresponding to the iterative left test phase value xn^1, and the amplitude estimate is calculated for the iterative right test phase value yn^1 to obtain the amplitude estimate corresponding to the iterative right test phase value yn^1. If the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), then the amplitude estimate corresponding to the iterative right test phase value yn^K is assigned to the amplitude estimate corresponding to the iterative left test phase value xn^(K+1), and the amplitude estimate is calculated for the iterative right test phase value yn^(K+1) to obtain the amplitude estimate corresponding to the iterative right test phase value yn^(K+1). If the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, then the amplitude estimate corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimate corresponding to the iterative right test phase value yn^1, and the amplitude estimate is calculated for the iterative left test phase value xn^1 to obtain the amplitude estimate corresponding to the iterative left test phase value xn^1. If the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), then the amplitude estimate corresponding to the iterative left test phase value xn^K is assigned to the amplitude estimate corresponding to the iterative right test phase value yn^(K+1), and the amplitude estimate is calculated for the iterative left test phase value xn^(K+1) to obtain the amplitude estimate corresponding to the iterative left test phase value xn^(K+1).

7. The phase estimation method as described in claim 4, characterized in that, The step of obtaining the phase corresponding to the minimum amplitude estimate based on the current iterative left test phase value xn^K and iterative right test phase value yn^K includes: Obtain the average phase value of the current iterative left test phase value xn^K and iterative right test phase value yn^K, and use it as the phase corresponding to the minimum amplitude estimate.

8. The phase estimation method as described in claim 5, characterized in that, The step of obtaining the phase corresponding to the minimum amplitude estimate based on the current iterative left test phase value xn^K and iterative right test phase value yn^K includes: Obtain the average phase value of the current iterative left test phase value xn^K and iterative right test phase value yn^K, and shift the average phase value by a preset phase to obtain the phase corresponding to the minimum amplitude estimate.

9. The phase estimation method as described in claim 8, characterized in that, If the average phase value is between [0, π), then the preset phase of the translation is π; If the average phase value is between [π, 2π), then the preset phase of the translation is -π. The phase after translation is the sum of the average phase value and the preset phase after translation.

10. The phase estimation method as described in claim 1, characterized in that, The initial phase value interval [an^0, bn^0] is generated in the following way: The phase value 0 is configured as the initial left-end phase value an^0, and the phase value 2π is configured as the initial right-end phase value bn^0, so as to obtain the initial phase value interval [an^0, bn^0]. or, Obtain the estimated phase empirical value, and generate the initial phase value interval [an^0, bn^0] based on the estimated phase empirical value.

11. The phase estimation method as described in claim 10, characterized in that, The process of obtaining the estimated phase empirical value includes: After a known input signal is input into the DAC, the phase estimate value corresponding to the harmonic frequency or spurious frequency of the known input signal is obtained; Based on the frequency relationship between the known input signal and the original input signal, the estimated phase empirical value corresponding to the harmonics of the original input signal is obtained from the phase estimation value; or... Based on the frequency relationship between the known input signal and the original input signal, and the frequency relationship between the spurious frequency of the known input signal and the spurious frequency of the original input signal, the estimated phase empirical value corresponding to the spurious signal of the original input signal is obtained from the phase estimation value.

12. The phase estimation method as described in claim 1, characterized in that, The spectral analysis of the simulated test signal includes: The simulated test signal is input into a spectrum analyzer for spectrum analysis. or, The simulated test signal is input to an analog-to-digital converter for analog-to-digital conversion and then subjected to Fourier transform for spectrum analysis.

13. The phase estimation method as described in claim 1, characterized in that, For harmonics, the frequency of the corresponding cancellation signal is the harmonic frequency of the harmonics of the original input signal; for spurious signals, the frequency of the corresponding cancellation signal is the spurious frequency of the spurious signals of the original input signal.

14. A signal processing channel, characterized in that, For implementing the phase estimation method as described in any one of claims 1 to 13, the signal processing channel includes at least two DDS phase accumulators, and the signal processing lines where each DDS phase accumulator is located are connected in parallel, the number of which is defined as an integer H greater than 1; One of the signal processing lines, which includes a DDS phase accumulator, generates the original input signal after phase-amplitude conversion and attenuation processing. The remaining signal processing lines, which also include DDS phase accumulators, generate harmonic cancellation signals or spurious cancellation signals based on the corresponding test phase values ​​after phase-amplitude conversion.

15. The signal processing channel as described in claim 14, characterized in that, The signal processing channel is used to process multiple harmonics, or multiple spurious signals, or at least one harmonic and at least one spurious signal. If the value of H is ≥3, the remaining other signal processing lines containing DDS phase accumulators are used to generate cancellation signals corresponding to multiple harmonics, or cancellation signals corresponding to multiple spurious signals, or cancellation signals corresponding to at least one harmonic and at least one spurious signal respectively. Among them, the maximum number of times the remaining other signal processing lines containing DDS phase accumulators are called is equal to the sum of the number of harmonics and the number of spurious signals.

16. The signal processing channel as described in claim 15, characterized in that, The signal processing channel also includes a phase counter and a memory. The phase counter is used to accumulate the test phase value corresponding to the cancellation signal during the iteration of the test phase value. The memory is used to store each corresponding test phase value and its corresponding amplitude estimate.

17. The signal processing channel as described in claim 16, characterized in that, Obtain the total number L of harmonics and spurious emissions to be processed; Divide the total number L by H-1 and round up to get the number of times the signal processing channel is called; Based on the number of times the signal processing channel is invoked, the phase counter and memory are reset to clear the historically saved amplitude estimates and their corresponding test phase values.

18. A computer-readable storage medium, characterized in that, The medium stores a program that can be executed by a processor to implement the method as described in any one of claims 1-13.

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