Multi-channel DDC parallel processing method capable of being dynamically configured

Abstract

The invention belongs to the field of digital signal processing, and particularly relates to a multipath DDC parallel processing method capable of dynamic configuration, and the basic principle of the method is that dynamic parameter configuration is carried out on multipath DDCs in an FPGA, so that the frequency and bandwidth of each path of DDC can be different according to different requirements, and the bandwidth of each path of DDC can be adjusted according to different requirements. The multiple paths of DDCs run in parallel, multiple frequency points and multiple frequency bands of signals in the analog bandwidth are processed at the same time, and data acquisition of different requirements of a time domain, frequency, a modulation domain or multi-domain mixing is met. According to the processing method, parallel processing of multiple paths of DDCs can be implemented, different frequencies and bandwidths are configured, and in different working modes, DDC parameters can be dynamically configured according to judgment, so that the DDC processing process can quickly respond to signal changes, timely tracking and accurate capturing of dynamic signals are facilitated, and the processing efficiency is improved. And the use requirement of multi-signal locking analysis in a complex signal environment can be met.

Description

Technical Field

[0001] The present application belongs to the field of digital signal processing, and specifically relates to a dynamically configurable multi-channel DDC parallel processing method. Background Art

[0002] Among the existing implementation schemes for multi-channel signal processing, some are system hardware parallel down-conversion schemes, which are different from the implementation mechanism of the FPGA-based parallel processing technology implemented by the present invention, and have high additional hardware costs, high equipment power consumption, and poor flexibility; some schemes are implemented in combination with a channelized manner, and the sub-channel bandwidth is generally a fixed bandwidth and cannot be changed in real time; some schemes implement parallel processing for multi-channel direction finding parallel processing, and the DDCs of multiple channels are changed at the same time, and multiple channels cannot be processed with different bandwidths respectively. Summary of the invention

[0003] The method implemented by the method of the present invention can configure each DDC to a different digital intermediate frequency and a different bandwidth, which is mainly used to meet the needs of parallel analysis of sub-bands with different bandwidths at multiple frequency points within the analog bandwidth. The method of the present invention is implemented based on its own application background, and the application background and processing method are different from the prior art. Its technical solution is:

[0004] A dynamically configurable multi-channel DDC parallel processing method comprises the following steps:

[0005] Step 1: For an acquisition system with an ADC sampling rate of fs, after receiving the sampled data, the FPGA completes the routing processing of the sampled data to multiple DDCs in the FPGA;

[0006] Step 2: The software enables the N DDC paths used in the FPGA through the bus interface, and configures the variable frequency F and variable bandwidth BW parameter settings of each DDC path;

[0007] Step 3: FPGA obtains the digital baseband signal data of each DDC channel, and transmits it to the control unit through the bus interface for time domain, frequency domain, modulation domain, or multi-domain mixed data analysis and processing; if each channel is enabled to continue, repeat step 3; if the channel selection enable fails, the current channel DDC is reset to a low-power state to be selected, and return to step 2.

[0008] Preferably, the variable frequency F in step 2 is in the range of 0 <F<fs。

[0009] Preferably, the variable bandwidth BW described in step 2 is in the range of: 0.0000048828125*fs≤BW≤0.78125*fs.

[0010] Preferably, in step 2, the frequency and bandwidth of each DDC path can be dynamically configured, and according to different configuration modes, the DDC path can be operated in a working state adapted to signal processing;

[0011] In fixed mode, it is suitable for monitoring and analyzing relatively stable signals. Multiple DDCs working in parallel can simultaneously analyze multiple narrowband stable signals within a wide band.

[0012] In the frequency automatic mode, it can dynamically capture the signal with relatively stable locking bandwidth but dynamic frequency, which is suitable for tracking and locking analysis of frequency hopping signals and adapting to tracking and locking processing of hopping signals;

[0013] In bandwidth automatic mode, the fine bandwidth adaptive processing of frequency-stable signals can be dynamically identified and configured to adapt to signal interference application scenarios.

[0014] Preferably, in different modes, the adjustment steps are as follows:

[0015] Step 21: Select one of the N DDCs, configure it to be in a suspended state, and return to step 21; configure it to be in a working state, and proceed to step 22;

[0016] Step 22: Configuration mode selection, if the fixed mode is selected, go to step 23; if the frequency automatic mode is selected, go to step 24; if the bandwidth automatic mode is selected, go to step 27;

[0017] Step 23: In the fixed mode, the frequency F and bandwidth BW parameters are manually set, and the parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and then returns to step 22; or until the channel working state is changed, and then returns to step 21;

[0018] Step 24: In the frequency automatic mode, the user manually sets the bandwidth BW parameter, automatically searches for the frequency F in the range of 0 to fs, and determines its bandwidth BW now , proceed to step 25;

[0019] Step 25: When BW now Satisfy BW*95%≤BW now ≤BW*105%, lock the center frequency F of the discrimination bandwidth now If it is F, go to step 26; at the same time, go to step 24 and continue searching;

[0020] Step 26: The frequency F and bandwidth BW parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and then returns to step 22; or until the channel working state is changed, and then returns to step 21;

[0021] Step 27: In bandwidth automatic mode, the user manually sets the frequency F parameter, and the maximum bandwidth BW max The current bandwidth BW is automatically determined and the process goes to step 28. At the same time, step 27 is performed to continue the search.

[0022] Step 28: The frequency F and bandwidth BW parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and returns to step 22; or until the channel working state is changed, returns to step 21.

[0023] Preferably, the discrimination bandwidth in step 24 and step 27 satisfies the x dB bandwidth estimation and β bandwidth estimation methods.

[0024] Preferably, the BW in step 27 max =fs / 1.28.

[0025] Preferably, the maximum number of DDC channels N used in step 2 is limited by FPGA resources, and the maximum value of N is determined according to different types of FPGAs and FPGA resource configurations.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The intermediate frequency and bandwidth of each DDC can be dynamically configured to meet the processing requirements of different frequency points and bandwidths within the analog bandwidth; secondly, narrowband monitoring can be performed simultaneously on multiple frequency bands that need to be monitored within the band, and multi-channel parallel fine processing of signals at different frequency points and bands can be completed. The benefit is that different application processing can be performed on each DDC, which can provide more accurate data for specific back-end processing needs. Multi-channel DDC processing can more effectively utilize signal resources within the analog bandwidth, deeply mine in-band signal information, and more carefully and accurately observe, measure, discover, and identify signals, thereby improving the value of frequency band utilization. Third, DDC parameters can be dynamically configured based on the discrimination implementation parameters, so that the DDC processing process can quickly respond to signal changes, which is conducive to the timely tracking and accurate capture of dynamic signals, and can meet the use requirements of multi-signal locking analysis in complex signal environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1This is a schematic diagram of the parameters of the filtering method of this application. DETAILED DESCRIPTION

[0029] The following will be combined with the embodiments of the present invention and the drawings of the specification to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] The idea of ​​the inventive method is a method for implementing multi-channel DDC parallel processing with dynamically configurable frequency and bandwidth for each DDC in FPGA after acquiring ADC sampling data. The basic principle of the method of the present invention is to implement dynamic parameter configuration for multiple DDCs in FPGA, so that the frequency and bandwidth of each DDC can be different according to different requirements. Multiple DDCs run in parallel, and implement simultaneous processing of multiple frequency points and multiple frequency bands of signals within the analog bandwidth to meet the different requirements of time domain, frequency, modulation domain, or multi-domain mixed data acquisition. The processing method can implement parallel processing of multiple DDCs. In the above figure, the ADC samples at a sampling rate of fs to obtain a digital signal at a rate of fs. The ADC sampling data is output to the back end, received by the FPGA, and then distributed in parallel to each DDC module implemented in the FPGA for parallel processing of multiple DDCs. The variable frequency setting is used to configure the digitally controlled oscillator of each DDC to realize a digital local oscillator signal in the frequency range of 0 to fs, which is used to perform digital mixing with the sampling data generated by the ADC to obtain a digital baseband signal of the required frequency. The variable bandwidth setting is used to select the bandwidth of the variable bandwidth low-pass filter after mixing, to meet the needs of different bandwidth filtering processing under different decimation ratios, and to realize the filtering output processing of the digital baseband signal. The digital baseband signal can be used for different analysis needs in the time domain, frequency, modulation domain, or multi-domain mixing. Based on the signal analysis requirements, the multi-channel DDC can be configured to use 1 to N arbitrary multiple channels for parallel processing. The DDC channels that do not need to be turned on can be controlled to perform logic reset and power-off processing to save FPGA power consumption. The frequency and bandwidth settings of each DDC can be set independently according to the signal analysis requirements. The DDC signal processing is flexible and the configuration can be updated at any time.

[0031] A dynamically configurable multi-channel DDC parallel processing method, the innovation of which is that the frequency and bandwidth of each DDC channel can be dynamically configured, and according to different configuration modes, the DDC channel can work in a working state that adapts to signal processing. In fixed mode, it is suitable for monitoring and analyzing relatively stable signals. Multi-channel DDC parallel operation can simultaneously analyze multiple narrowband stable signals in the broadband; in frequency automatic mode, it can dynamically capture and lock signals with relatively stable bandwidth but dynamic frequency, which is suitable for tracking and locking analysis of frequency hopping signals, and adapts to tracking and locking processing of hopping signals; in bandwidth automatic mode, it can dynamically identify and configure fine bandwidth adaptive processing of frequency-stable signals, and adapt to signal interference application scenarios.

[0032] A dynamically configurable multi-channel DDC parallel processing method comprises the following steps:

[0033] Step 1: For an acquisition system with an ADC sampling rate of fs, after receiving the sampled data, the FPGA completes the routing processing of the sampled data to multiple DDCs in the FPGA;

[0034] Step 2: The software enables the N DDC paths used in the FPGA through the bus interface, and configures the variable frequency F and variable bandwidth BW parameter settings of each DDC path;

[0035] Step 3: FPGA obtains the digital baseband signal data of each DDC channel, and transmits it to the control unit through the bus interface for time domain, frequency domain, modulation domain, or multi-domain mixed data analysis and processing; if each channel is enabled to continue, repeat step 3; if the channel selection enable fails, the current channel DDC is reset to a low-power state to be selected, and return to step 2.

[0036] The variable frequency F described in step 2 has a range of 0 <F<fs。

[0037] The variable bandwidth BW described in step 2 has a range of

[0038] 0.0000048828125*fs≤BW≤0.78125*fs.

[0039] In step 2, the frequency and bandwidth of each DDC path can be dynamically configured, and according to different configuration modes, the DDC path can be operated in a working state suitable for signal processing;

[0040] In fixed mode, it is suitable for monitoring and analyzing relatively stable signals. Multiple DDCs working in parallel can simultaneously analyze multiple narrowband stable signals within a wide band.

[0041] In the frequency automatic mode, it can dynamically capture the signal with relatively stable locking bandwidth but dynamic frequency, which is suitable for tracking and locking analysis of frequency hopping signals and adapting to the tracking and locking processing of hopping signals. In the bandwidth automatic mode, it can dynamically identify and configure the fine bandwidth adaptive processing of the frequency stable signal to adapt to the signal interference application scenario. In different modes, the adjustment steps are as follows:

[0042] Step 21: Select one of the N DDCs, configure it to be in a suspended state, and return to step 21; configure it to be in a working state, and proceed to step 22;

[0043] Step 22: Configuration mode selection, if the fixed mode is selected, go to step 23; if the frequency automatic mode is selected, go to step 24; if the bandwidth automatic mode is selected, go to step 27;

[0044] Step 23: In the fixed mode, the frequency F and bandwidth BW parameters are manually set, and the parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and then returns to step 22; or until the channel working state is changed, and then returns to step 21;

[0045] Step 24: In the frequency automatic mode, the user manually sets the bandwidth BW parameter, automatically searches for the frequency F in the range of 0 to fs, and determines its bandwidth BW now , proceed to step 25;

[0046] Step 25: When BW now Satisfy BW*95%≤BW now ≤BW*105%, lock the center frequency F of the discrimination bandwidth now If it is F, go to step 26; at the same time, go to step 24 and continue searching;

[0047] Step 26: The frequency F and bandwidth BW parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and then returns to step 22; or until the channel working state is changed, and then returns to step 21;

[0048] Step 27: In bandwidth automatic mode, the user manually sets the frequency F parameter, and the maximum bandwidth BW max The current bandwidth BW is automatically determined and the process goes to step 28. At the same time, step 27 is performed to continue the search.

[0049] Step 28: The frequency F and bandwidth BW parameters are sent to the FPGA to make the DDC channel data processing effective, change the channel configuration mode selection, and return to step 22; or until the channel working state is changed, return to step 21.

[0050] The determination bandwidth described in step 24 and step 27 satisfies the x dB bandwidth estimation and β bandwidth estimation methods.

[0051] BW described in step 27 max =fs / 1.28.

[0052] The maximum number of DDC channels N used in step 2 is limited by FPGA resources.

[0053] The maximum value of N is determined based on different FPGA models and FPGA resource configurations.

[0054] The basic principle of the method of the present invention is to implement dynamic parameter configuration for multiple DDCs in FPGA, so that the frequency and bandwidth of each DDC can be different according to different requirements. Multiple DDCs run in parallel, and implement simultaneous processing of multiple frequency points and multiple frequency bands of signals in the analog bandwidth to meet the different data acquisition requirements of time domain, frequency, modulation domain, or multi-domain mixing. Compared with the scheme implemented by multi-channel hardware parallel, the method of the present invention can save a lot of hardware resources and hardware costs, and reduce equipment power consumption; compared with the method of implementing multi-channel parallel processing in a channelized manner, the digital intermediate frequency frequency and bandwidth of the method of the present invention can be dynamically configured, and the flexibility is large; compared with the application of multi-channel direction finding parallel processing, the method of the present invention can process each channel with different bandwidths, with different application directions and more flexible application methods. The processing method of the present invention can implement parallel processing of multiple DDCs and configure different frequencies and bandwidths. It can more effectively utilize the signal resources in the analog bandwidth, deeply mine the signal information in the band, observe, measure, discover, and identify signals more carefully and accurately, and improve the value of frequency band utilization. The dynamic configuration of parameters enables the DDC processing to quickly respond to signal changes, which is conducive to the timely tracking and accurate capture of dynamic signals, and can meet the requirements of multi-signal locking analysis in complex signal environments.

Claims

1. A dynamically configurable multi-channel DDC parallel processing method, characterized in that: The following steps are involved: Step 1: For an acquisition system with an ADC sampling rate of fs, after receiving the sampled data, the FPGA completes the routing processing of the sampled data to multiple DDCs in the FPGA; Step 2: The software enables the N DDC paths used in the FPGA through the bus interface, and configures the variable frequency F and variable bandwidth BW parameter settings of each DDC path; Step 3: FPGA obtains the digital baseband signal data of each DDC channel, and transmits it to the control unit through the bus interface for time domain, frequency domain, modulation domain, or multi-domain mixed data analysis and processing; if each channel is enabled to continue, repeat step 3; if the channel selection enable fails, the current channel DDC is reset to a low-power state to be selected, and return to step 2.

2. The dynamically configurable multi-channel DDC parallel processing method according to claim 1, characterized in that: The variable frequency F described in step 2 has a range of 0 <F<fs。 3. The dynamically configurable multi-channel DDC parallel processing method according to claim 1, characterized in that: The variable bandwidth BW described in step 2 has a range of 0.0000048828125*fs≤BW≤0.78125*fs.

4. The dynamically configurable multi-channel DDC parallel processing method according to claim 1, characterized in that: In step 2, the frequency and bandwidth of each DDC path can be dynamically configured, and according to different configuration modes, the DDC path can be operated in a working state suitable for signal processing; In fixed mode, it is suitable for monitoring and analyzing relatively stable signals. Multiple DDCs working in parallel can simultaneously analyze multiple narrowband stable signals within a wide band. In the frequency automatic mode, it can dynamically capture the signal with relatively stable locking bandwidth but dynamic frequency, which is suitable for tracking and locking analysis of frequency hopping signals and adapting to tracking and locking processing of hopping signals; In bandwidth automatic mode, the fine bandwidth adaptive processing of frequency-stable signals can be dynamically identified and configured to adapt to signal interference application scenarios.

5. The dynamically configurable multi-channel DDC parallel processing method according to claim 1, characterized in that: In different modes, the adjustment steps are as follows: Step 21: Select one of the N DDCs, configure it to be in a suspended state, and return to step 21; configure it to be in a working state, and proceed to step 22; Step 22: Configuration mode selection, if the fixed mode is selected, go to step 23; if the frequency automatic mode is selected, go to step 24; if the bandwidth automatic mode is selected, go to step 27; Step 23: In fixed mode, the frequency F and bandwidth BW parameters are manually set, and the parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and then returns to step 22; or Until the working state of the passage is changed, return to step 21; Step 24: In the frequency automatic mode, the user manually sets the bandwidth BW parameter, automatically searches for the frequency F in the range of 0 to fs, and determines its bandwidth BW now , proceed to step 25; Step 25: When BW now Satisfy BW*95%≤BW now ≤BW*105%, lock the center frequency F of the discrimination bandwidth now If it is F, go to step 26; at the same time, go to step 24 and continue searching; Step 26: The frequency F and bandwidth BW parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and then returns to step 22; or until the channel working state is changed, and then returns to step 21; Step 27: In bandwidth automatic mode, the user manually sets the frequency F parameter, and the maximum bandwidth BW max The current bandwidth BW is automatically determined and the process goes to step 28. At the same time, step 27 is performed to continue the search. Step 28: The frequency F and bandwidth BW parameters are sent to the FPGA to make the DDC channel data processing effective. The FPGA obtains the digital baseband signal data of the DDC channel and continues to perform subsequent data analysis and processing until the channel configuration mode selection is changed, and returns to step 22; or until the channel working state is changed, returns to step 21.

6. The dynamically configurable multi-channel DDC parallel processing method according to claim 5, characterized in that: The determination bandwidth described in step 24 and step 27 satisfies the x dB bandwidth estimation and β bandwidth estimation methods.

7. The dynamically configurable multi-channel DDC parallel processing method according to claim 5, characterized in that: BW described in step 27 max =fs / 1.

28.

8. The dynamically configurable multi-channel DDC parallel processing method according to claim 1, characterized in that: The maximum number of DDC channels N used in step 2 is limited by FPGA resources, and the maximum value of N is determined according to different FPGA models and FPGA resource configurations.

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