Readout circuit and display device including the same

Abstract

The invention relates to a readout circuit and a display device including the same. The display device includes a display panel and a readout circuit. The display panel includes a pixel including a light emitting element, and a sensor and a dummy sensor including a light sensing element. The readout circuit outputs a readout signal based on a sensing signal received from the sensor and a dummy sensing signal received from the dummy sensor. The readout circuit includes a reference current transmitter that outputs a reference signal corresponding to the dummy sensing signal, and a sensing circuit that outputs a readout signal corresponding to a difference between the sensing signal and the reference signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0100640 filed in the Korean Intellectual Property Office on August 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device capable of detecting biometric information of a user. Background Art

[0004] The display device provides various functions for providing information to the user by displaying an image or communicating with the user by detecting the user's input. The display device may provide a function of detecting the user's biometric information. Examples of biometric information include fingerprints, blood pressure, and pulse.

[0005] The capacitive scheme for recognizing biometric information detects a change in capacitance between electrodes and determines the biometric information based on the detected change. The optical scheme for recognizing biometric information detects incident light by using an optical sensor and determines the biometric information based on the detected light. The ultrasonic scheme for recognizing biometric information detects vibration by using a piezoelectric material, etc. and determines the biometric information based on the detected vibration. Summary of the invention

[0006] At least one embodiment of the present disclosure provides a display device including a sensor capable of detecting biometric information.

[0007] At least one embodiment of the present disclosure provides a readout circuit capable of accurately detecting a sensing signal from a sensor.

[0008] According to an embodiment, a display device includes a display panel and a readout circuit. The display panel includes pixels including light-emitting elements, and a sensor including a light-sensing element and a dummy sensor. The readout circuit outputs a readout signal based on a sensing signal received from the sensor and a dummy sensing signal received from the dummy sensor. The readout circuit includes a reference current transmitter and a sensing circuit, the reference current transmitter outputs a reference signal corresponding to the dummy sensing signal, and the sensing circuit outputs a readout signal corresponding to a difference between the sensing signal and the reference signal.

[0009] In an embodiment, the sensing circuit may include: a current transmitter that outputs a transmitter signal corresponding to a difference between a sensing signal and a reference signal; a current storage unit that stores the transmitter signal; and an analog-to-digital converter that outputs a readout signal by converting the transmitter signal from the current storage unit into a digital signal.

[0010] In an embodiment, the current storage unit may include a first storage unit and a second storage unit, the first storage unit storing a transmitter signal corresponding to a difference between a reference signal and a sensing signal received during a first period, and the second storage unit storing a transmitter signal corresponding to a difference between the reference signal and a sensing signal received during a second period different from the first period.

[0011] In an embodiment, the first storage unit may include a first capacitor storing the transmitter signal during the first period, and a second capacitor storing the transmitter signal during the first period.

[0012] In an embodiment, the second storage unit may include a third capacitor storing the transmitter signal during the second period, and a fourth capacitor storing the transmitter signal during the second period.

[0013] In an embodiment, the current storage unit may further include an amplifier including a first input terminal, a second input terminal and an output node, and receiving a reference voltage from the first input terminal, receiving a transmitter signal from the second input terminal, and outputting a current corresponding to the transmitter signal to the output node.

[0014] In an embodiment, the first storage unit may include: a first transistor connected between a first voltage terminal and a first node and including a gate electrode connected to a second node; a first capacitor connected between the first voltage terminal and the second node; a first switching circuit electrically connecting an input node receiving a transmitter signal with a second node in response to a first switching signal and transmitting the transmitter signal to a second input terminal of the amplifier in response to a second switching signal; a second transistor connected between the first node and the second voltage terminal and including a gate electrode connected to a third node; a second capacitor connected between the third node and the second voltage terminal; and a second switching circuit electrically connecting an output node of the amplifier with the third node in response to the second switching signal.

[0015] In an embodiment, the second storage unit may include: a third transistor connected between the first voltage terminal and the fourth node and including a gate electrode connected to the fifth node; a third capacitor connected between the first voltage terminal and the fifth node; a third switching circuit electrically connecting an input node receiving a transmitter signal with the fifth node in response to a third switching signal and transmitting the transmitter signal to the second input terminal of the amplifier in response to a fourth switching signal; a fourth transistor connected between the fourth node and the second voltage terminal and including a gate electrode connected to the sixth node; a fourth capacitor connected between the sixth node and the second voltage terminal; and a fourth switching circuit electrically connecting the output node of the amplifier with the sixth node in response to the fourth switching signal.

[0016] In an implementation, the reference current conveyor may output a first reference voltage signal and a second reference voltage signal corresponding to the dummy sensing signal.

[0017] In an embodiment, the current transmitter may include: a first current mirror circuit, receiving a sensing signal, a first reference voltage signal, a second reference voltage signal, a first bias voltage, and a second bias voltage to output a voltage signal; a buffer circuit, receiving the voltage signal and the reference voltage to output the first voltage and the second voltage; and a second current mirror circuit, receiving the first voltage, the second voltage, the first bias voltage, and the second bias voltage to output a transmitter signal.

[0018] In an embodiment, the display panel may include a display area in which the light emitting element and the sensor are disposed, and a non-display area in which the dummy sensor is disposed.

[0019] In an embodiment, the sensor may further include a sensor driving circuit connected to the light sensing element and outputting a sensing signal corresponding to the external light.

[0020] In an embodiment, the sensor driving circuit may include: a reset transistor including a first electrode for receiving a reset voltage, a second electrode connected to a first sensing node, and a gate electrode for receiving a reset signal; an amplification transistor including a first electrode for receiving a driving voltage, a second electrode connected to a second sensing node, and a gate electrode connected to the first sensing node; and an output transistor including a first electrode connected to the second sensing node, a second electrode connected to a readout line for outputting a sensing signal, and a gate electrode for receiving a scan signal.

[0021] In an implementation, the dummy sensor may further include a sensor driving circuit connected to the light sensing element and outputting a dummy sensing signal corresponding to the external light.

[0022] According to an embodiment, a sensing circuit includes a reference current transmitter and a readout circuit. The reference current transmitter outputs a reference signal corresponding to a dummy sensing signal from a dummy sensor. The sensing circuit outputs a readout signal corresponding to a difference between the reference signal and a sensing signal received from the sensor. The sensing circuit includes: a current transmitter that outputs a transmitter signal corresponding to a difference between the sensing signal and the reference signal; a current storage unit that stores the transmitter signal; and an analog-to-digital converter that outputs the readout signal by converting the transmitter signal from the current storage unit into a digital signal.

[0023] In an embodiment, the current storage unit may include a first storage unit and a second storage unit, the first storage unit storing a transmitter signal corresponding to a difference between a reference signal and a sensing signal received during a first period, and the second storage unit storing a transmitter signal corresponding to a difference between the reference signal and a sensing signal received during a second period different from the first period.

[0024] In an embodiment, the first storage unit may include a first capacitor storing the transmitter signal during the first period, and a second capacitor storing the transmitter signal during the first period. The second storage unit may include a third capacitor storing the transmitter signal during the second period, and a fourth capacitor storing the transmitter signal during the second period.

[0025] In an embodiment, the current storage unit may further include an amplifier including a first input terminal, a second input terminal and an output node, and receiving a reference voltage from the first input terminal, receiving a transmitter signal from the second input terminal, and outputting a current corresponding to the transmitter signal to the output node.

[0026] In an embodiment, the first storage unit may include: a first transistor connected between a first voltage terminal and a first node and including a gate electrode connected to a second node; a first capacitor connected between the first voltage terminal and the second node; a first switching circuit electrically connecting an input node receiving a transmitter signal with a second node in response to a first switching signal and transmitting the transmitter signal to a second input terminal of the amplifier in response to a second switching signal; a second transistor connected between the first node and the second voltage terminal and including a gate electrode connected to a third node; a second capacitor connected between the third node and the second voltage terminal; and a second switching circuit electrically connecting an output node of the amplifier with the third node in response to the second switching signal.

[0027] In an embodiment, the second storage unit may include: a third transistor connected between the first voltage terminal and the fourth node and including a gate electrode connected to the fifth node; a third capacitor connected between the first voltage terminal and the fifth node; a third switching circuit electrically connecting an input node receiving a transmitter signal with the fifth node in response to a third switching signal and transmitting the transmitter signal to the second input terminal of the amplifier in response to a fourth switching signal; a fourth transistor connected between the fourth node and the second voltage terminal and including a gate electrode connected to the sixth node; a fourth capacitor connected between the sixth node and the second voltage terminal; and a fourth switching circuit electrically connecting the output node of the amplifier with the sixth node in response to the fourth switching signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1is a perspective view of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0030] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 4 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0032] Figure 5 is a circuit diagram of a pixel of a display panel according to an embodiment of the present disclosure.

[0033] Figure 6 yes Figure 5 A timing diagram of the operation of a pixel is shown in FIG.

[0034] Fig. 7A is a circuit diagram of a sensor according to an embodiment of the present disclosure.

[0035] Figure 7B is a circuit diagram of a dummy sensor according to an embodiment of the present disclosure.

[0036] Figure 8 yes Fig. 7A The timing diagram of the operation of the sensor is shown in FIG.

[0037] Fig. 9 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0038] Fig.10 is a diagram showing a circuit configuration of a readout circuit according to an embodiment of the present disclosure.

[0039] Fig.11 yes Fig.10 0 is a timing diagram of the operation of the readout circuit shown in FIG.

[0040] Fig.12 is a block diagram of a readout circuit according to an embodiment of the present disclosure.

[0041] Fig.13 is a block diagram of the sensing circuit and the reference current transmitter.

[0042] Fig.14 is a circuit diagram of a buffer circuit and a second current mirror circuit in a current conveyor according to an embodiment of the present disclosure.

[0043] Fig.15 is a circuit diagram of a current storage unit according to an embodiment of the present disclosure.

[0044] Fig.16 yes Fig.15 0 is a timing diagram of the operations of the first storage unit and the second storage unit shown in . DETAILED DESCRIPTION

[0045] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals may represent the same components.

[0046] In this specification, the statement that a first component (or region, layer, part, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is interposed therebetween.

[0047] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view of a display device DD according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view of a display device DD according to an embodiment of the present disclosure.

[0049] refer to Figure 1 and Figure 2 The display device DD may be a device that is activated according to an electrical signal. For example, the display device DD may be a mobile phone, a tablet PC, a car navigation system, a game console, or a wearable device, but is not limited thereto. Figure 1 The display device DD is shown to be a mobile phone.

[0050] In addition, despite the Figure 1 , a rigid type display device DD having a block form is shown, but the embodiments of the present disclosure are not limited thereto. For example, the display device DD may be a foldable, rollable, or slidable display device DD.

[0051] The top surface of the display device DD may be defined as a display surface IS, and may have a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the display device DD may be provided to a user through the display surface IS. Hereinafter, a normal direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the meaning of "when viewed from above the plane" may mean "when viewed in the third direction DR3". That is, the plane may be parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0052] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which the image IM is displayed. The user visually perceives the image IM through the transmission area TA. In an embodiment, the transmission area TA is shown in the shape of a quadrilateral whose corners are rounded. However, this is shown as an example. For example, the transmission area TA may have various shapes and is not limited to any specific shape.

[0053] The border area BZA is adjacent to the transmission area TA. The border area BZA may have a predetermined color. The border area BZA may surround the transmission area TA. Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is shown as an example. For example, the border area BZA may be disposed adjacent to only one side of the transmission area TA, or may be omitted.

[0054] The display device DD can sense external input applied from the outside. The external input may include various types of input provided from the outside of the display device DD. For example, in addition to contact with a part of the body (such as the user's hand US_F), the external input may also include an external input (e.g., hovering) applied when the user's hand US_F approaches the display device DD or is adjacent to the display device DD within a predetermined distance. In addition, the external input may be of various types, such as force, pressure, temperature, light, etc. The external input may be provided by a separate device, such as an active pen or a digitizer pen. In addition, the display device DD can detect biometric information of the user applied from the outside.

[0055] The display device DD may include a window WM and a case EDC. For example, the window WM and the case EDC may be coupled to each other, and other components of the display device DD such as a display module DM may be accommodated therein.

[0056] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may include a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded to each other by an adhesive, or may include a glass substrate and a plastic film bonded to each other by an adhesive.

[0057] The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the configuration of the display device DD accommodated in the internal space from external impacts. A battery module for providing power for the overall operation of the display device DD may be interposed between the display module DM and the housing EDC.

[0058] The display module DM may include a display panel DP and an anti-reflection layer CFL.

[0059] The display panel DP may generate an image. The display panel DP may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro-LED display panel, or a nano-LED display panel. Hereinafter, it is described that the display panel DP is an organic light-emitting display panel.

[0060] The display panel DP includes a base layer BL, a pixel layer PXL, and an encapsulation layer TFE. The display panel DP according to an embodiment of the present disclosure is a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel folded relative to a folding axis, or a rigid display panel.

[0061] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, but its material is not limited thereto. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, and the like.

[0062] The pixel layer PXL is disposed on the base layer BL. The pixel layer PXL may include a circuit layer DP_CL and an element layer DP_ED. The circuit layer DP_CL is interposed between the base layer BL and the element layer DP_ED.

[0063] The circuit layer DP_CL includes at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an "intermediate insulating layer". In an embodiment, the intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit and a sensor driving circuit, the pixel driving circuit being included in each of a plurality of pixels for displaying an image, and the sensor driving circuit being included in each of a plurality of sensors for identifying external information. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0064] As an example of the present disclosure, each of the multiple sensors may be a fingerprint recognition sensor, a proximity sensor, or an iris recognition sensor. In addition, each of the multiple sensors may be an optical sensor that recognizes biometric information in an optical scheme. According to an embodiment of the present disclosure, external input (e.g., a user's touch) and biometric information such as a fingerprint may be sensed by using multiple sensors. Therefore, the display device DD does not need to include a separate input sensing layer for sensing external input. In this case, the thickness of the display device DD may be further reduced. Therefore, flexibility may be increased, and the display device DD may therefore be implemented in various types. For example, the display device DD may be implemented as the above-mentioned foldable, rollable, or slidable display device.

[0065] The element layer DP_ED may include a light emitting element included in each of the pixels and a light sensing element included in each of the sensors. As an example of the present disclosure, the light sensing element may be a photodiode. The light sensing element may be a sensor that detects or responds to light reflected by a user's fingerprint. Fig. 9 The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0066] The encapsulation layer TFE encapsulates the element layer DP_ED. In an embodiment, the encapsulation layer TFE includes at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0067] The anti-reflection layer CFL may be disposed on the display panel DP. The anti-reflection layer CFL may reduce the reflectivity of external light incident from outside the display device DD. The anti-reflection layer CFL may be formed on the display panel DP by a continuous process, but the present disclosure is not limited thereto. For example, the anti-reflection layer CFL may include a color filter, a black matrix, and a planarization layer. The color filter may have a given arrangement. For example, the color filter may be arranged according to the emission color of the pixels included in the display panel DP. In an embodiment, the anti-reflection layer CFL includes a black matrix and a reflection adjustment layer. The reflection adjustment layer may selectively absorb light reflected from inside the display panel DP and / or the electronic device or light in a partial band of incident light from outside the display panel DP and / or the electronic device. In an embodiment, the anti-reflection layer CFL is a polarizing film.

[0068] The display device DD according to an embodiment of the present disclosure further includes an adhesive layer AL. The window WM may be attached to the anti-reflection layer CFL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure sensitive adhesive (PSA).

[0069] Figure 3 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0070] refer to Figure 3 The display device DD includes a display panel DP, a driving controller 100 (e.g., a controller circuit), a data driver 200 (e.g., a first driver circuit), a scanning and sensor driver 300 (e.g., a second driver circuit), a light emitting driver 400 (e.g., a third driver circuit), a readout circuit 500 and a voltage generator 600.

[0071] The driving controller 100 receives an input image signal RGB and a control signal CTRL. The driving controller 100 generates an output image signal DATA by converting the data format of the input image signal RGB so as to be suitable for the display panel DP and the data driver 200. The driving controller 100 outputs a scan control signal SCS, a data control signal DCS, an emission control signal ECS, and a readout control signal RCS.

[0072] The data driver 200 receives a data control signal DCS and an output image signal DATA from the driving controller 100. The data driver 200 converts the output image signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm (where m is an integer greater than 1). The data signal may be an analog voltage corresponding to a grayscale of the output image signal DATA.

[0073] The voltage generator 600 generates voltages for operating the display panel DP. In an embodiment, the voltage generator 600 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, a reset voltage VRST, a sensor driving voltage VCOM, and a bias voltage VBIAS.

[0074] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, reset lines RSL, emission lines EML1 to EMLn, data lines DL1 to DLm, readout lines RL1 to RLk, pixels PX, sensors FX and dummy sensors DX, where n and k are integers greater than 1.

[0075] The display panel DP may include a transmissive area TA (refer to Figure 1) of the display area DA and the frame area BZA ( Figure 1 The pixels PX and the sensors FX may be disposed in the display area DA.

[0076] The scanning and sensor driver 300 , the light emitting driver 400 , and the dummy sensor DX may be located in the non-display area NDA of the display panel DP.

[0077] In an embodiment, the scan and sensor driver 300 is disposed adjacent to a first side of the display area DA in the display panel DP. The scan and sensor driver 300 receives a scan control signal SCS from the drive controller 100. The scan and sensor driver 300 may output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 in response to the scan control signal SCS, and may output a reset signal to the reset line RSL. The scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 and the reset line RSL extend from the scan and sensor driver 300 in a first direction DR1.

[0078] The light emitting driver 400 is disposed adjacent to the second side of the display area DA in the display panel DP. The light emitting driver 400 receives an emission control signal ECS from the driving controller 100. The light emitting driver 400 may output emission signals to the emission lines EML1 to EMLn in response to the emission control signal ECS. The emission lines EML1 to EMLn may extend from the light emitting driver 400 in a direction opposite to the first direction DR1.

[0079] The scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, the reset lines RSL and the emission lines EML1 to EMLn may be arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm may extend from the data driver 200 in a direction opposite to the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1.

[0080] The plurality of pixels PX are electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, the emission lines EML1 to EMLn, and the data lines DL1 to DLm. In an embodiment, each of the plurality of pixels PX is electrically connected to four scan lines and one emission line. For example, Figure 3 As shown in FIG, the pixels PX of the first row may be connected to the scan lines GIL1, GCL1, GWL1, and GWL2 and the emission line EML1. In addition, the pixels PX of the second row may be connected to the scan lines GIL2, GCL2, GWL2, and GWL3 and the emission line EML2.

[0081] Each of the plurality of pixels PX includes a light-emitting element ED (refer to Figure 5 ), and a pixel driving circuit PDC (refer to Figure 5 ) for controlling emission of the light-emitting element ED. The pixel driving circuit PDC may include one or more transistors and one or more capacitors. The scan and sensor driver 300 and the light-emitting driver 400 may include transistors formed by the same process as the pixel driving circuit PDC.

[0082] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2 from a voltage generator 600.

[0083] Each of the sensors FX includes a photosensing element OPD (refer to Fig. 7A ), and a sensor driving circuit SDC (refer to Fig. 7A ). The sensor driving circuit SDC may include transistors formed by the same process as the pixel driving circuit PDC.

[0084] Each of the sensors FX may be connected to a corresponding one of the scan lines GWL1 to GWLn and a corresponding one of the readout lines RL1 to RLk. The sensors FX may be commonly connected to a reset line RSL. In an embodiment, the number of sensors FX is less than the number of pixels PX. However, the present disclosure is not limited thereto. In an embodiment, the number of sensors FX provided on the display panel DP is greater than or equal to the number of pixels PX. In an embodiment, the number of readout lines RL1 to RLk is less than the number of data lines DL1 to DLm. That is, k < m. However, the present disclosure is not limited thereto. In an embodiment, the number of readout lines RL1 to RLk provided on the display panel DP is greater than or equal to the number of data lines DL1 to DLm.

[0085] The dummy sensor DX may be connected to a corresponding one of the scan lines GWL1 to GWLn (e.g., scan line GWL1) and a dummy readout line DRL.

[0086] Although one dummy sensor DX is shown in Figure 3 , the display device DD may include a plurality of dummy sensors DX. Figure 3 The dummy sensor DX is shown as being interposed between the display area DA and the light-emitting driver 400, but the present disclosure is not limited thereto. The dummy sensor DX may be located at any position in the non-display area NDA of the display panel DP. For example, the dummy sensor DX may be provided between the display area DA and the scan and sensor driver 300, or between the display area DA and the data driver 200.

[0087] The readout circuit 500 receives a readout control signal RCS from the driving controller 100. The readout circuit 500 may receive readout signals from the readout lines RL1 to RLk in response to the readout control signal RCS, generate a readout signal FSS from the readout signals, and then may provide the readout signal FSS to the driving controller 100.

[0088] In an embodiment, the sensor FX and the readout circuit 500 operate in a biometric sensing mode and a touch sensing mode, in which biometric information such as a user's fingerprint or blood pressure is sensed, and in which a touch input of the user is sensed. In the biometric sensing mode, the readout signal FSS provided from the readout circuit 500 to the drive controller 100 may be a sensing signal corresponding to the user's biometric information (blood pressure, fingerprint, etc.). In the touch sensing mode, the readout signal FSS provided from the readout circuit 500 to the drive controller 100 may be a signal indicating a touch position of the user.

[0089] exist Figure 3 In the example shown in , the scanning and sensor driver 300 is arranged to face the light emitting driver 400, and the pixel PX is interposed therebetween, but the present disclosure is not limited thereto. For example, the scanning and sensor driver 300 and the light emitting driver 400 may be positioned side by side adjacent to one of the first side and the second side of the display area DA in the display panel DP. In an embodiment, the scanning and sensor driver 300 and the light emitting driver 400 are integrated into a single circuit.

[0090] Figure 4 According to the embodiments of the present disclosure Figure 3 FIG. 1 is an enlarged plan view of a partial area of ​​the display panel DP.

[0091] refer to Figure 4 , pixels PXR, PXG and PXB are located on the display panel DP. The pixel PXR includes a light emitting element ED_R and a pixel driving circuit PDC; the pixel PXG includes a light emitting element ED_G and a pixel driving circuit PDC; and the pixel PXB includes a light emitting element ED_B and a pixel driving circuit PDC. Each of the sensors FX includes a light sensing element OPD and a sensor driving circuit SDC.

[0092] refer to Figure 4 , the pixels PXR and PXB and the sensor FX are arranged in odd rows, that is, in the first row and the third row. In an embodiment, in the first row and the third row, the pixels PXR and PXB and the sensor FX are alternately arranged in the first direction DR1. Only the pixel PXG is located in the second row.

[0093] In an embodiment, the pixel PXR includes a light emitting element ED_R that emits light of a first color, for example, red (R). The pixel PXG may include a light emitting element ED_G that emits light of a second color, for example, green (G). The pixel PXB may include a light emitting element ED_B that emits light of a third color, for example, blue (B).

[0094] like Figure 4 As shown in , the pixels PXR and PXB may be alternately and repeatedly positioned in the second direction DR2 as well as the first direction DR1. Each of the pixels PXG may be arranged between two light sensing elements OPD in the second direction DR2.

[0095] The arrangement structure of the pixels PX and the sensors FX is not limited to Figure 4 The arrangement structure can be changed in various ways.

[0096] In an embodiment, the light emitting element ED_R has a size larger than that of the light emitting element ED_G. In addition, the light emitting element ED_B may have a size greater than or equal to that of the light emitting element ED_R. The size of each of the light emitting elements ED_R, ED_G, and ED_B is not limited thereto, and various modifications and applications may be made. For example, in an embodiment of the present disclosure, the light emitting elements ED_R, ED_G, and ED_B may have the same size as each other.

[0097] In addition, the shape of each of the light emitting elements ED_R, ED_G, and ED_B may be variously transformed into a polygon, a circle, an ellipse, etc. In an embodiment, the shapes of the light emitting elements ED_R, ED_G, and ED_B are different from each other. For example, the light emitting element ED_G may have a circular shape, and each of the light emitting elements ED_R and ED_B may have a quadrilateral shape.

[0098] In an embodiment, the size of the area occupied by the sensor driving circuit SDC is different from the size of the area occupied by the pixel driving circuit PDC.

[0099] Figure 5 is a circuit diagram of a pixel of the display panel DP according to an embodiment of the present disclosure.

[0100] Figure 5 Shows Figure 3 One pixel PXij among the pixels PX shown in . Figure 3 Each of the plurality of pixels PX shown in FIG. 1 may have a Figure 5 The pixel PXij has the same circuit configuration as shown in .

[0101] refer to Figure 5, the pixel PXij includes a pixel driving circuit PDC and at least one light emitting element ED. The light emitting element ED may be a light emitting diode. As an example of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer. The pixel driving circuit PDC according to the embodiment includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a capacitor Cst.

[0102] The third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 may be N-type transistors using an oxide semiconductor as a semiconductor layer. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto. In an embodiment, all of the first transistor T1 to the seventh transistor T7 are P-type transistors. In an embodiment, all of the first transistor T1 to the seventh transistor T7 are N-type transistors. In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 is an N-type transistor, and the other transistors are P-type transistors. The configuration of the pixel driving circuit PDC according to an embodiment of the present disclosure is not limited to Figure 5 The embodiment shown in . Figure 5 The pixel driving circuit PDC shown in FIG. 1 is only an example. For example, the configuration of the pixel driving circuit PDC may be variously modified and implemented.

[0103] The pixel PXij is electrically connected to the scan lines GILi, GCLi, GWLi, and GWLi+1, the emission lines EMLi, and the data lines DLj, where 1≤i≤n, and 1≤j≤m. The scan lines GILi, GCLi, GWLi, and GWLi+1 can transmit scan signals GIi, GCi, GWi, and GWi+1, respectively. The emission lines EMLi can transmit emission signals EMi. The data lines DLj transmit data signals Dj. The data signals Dj can have the same value as that input to the display device DD (reference Figure 3 ) The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3 and the fourth driving voltage line VL4 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1 and the second initialization voltage VINT2 respectively.

[0104] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through a fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through a sixth transistor T6, and a gate electrode (or gate terminal, third electrode) connected to one end of the capacitor Cst. According to the switching operation of the second transistor T2, the first transistor T1 can receive the data signal Dj transmitted through the data line DLj, and then can provide a driving current Id to the light emitting element ED.

[0105] The second transistor T2 includes a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLi. The second transistor T2 may be turned on in response to a scan signal GWi transmitted through the scan line GWLi, and may transmit a data signal Dj transmitted through the data line DLj to the first electrode of the first transistor T1. For example, the scan signal GWi may be applied to the gate terminal of the second transistor T2.

[0106] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLi. The third transistor T3 may be turned on in response to a scan signal GCi transmitted through the scan line GCLi, and therefore, the gate electrode and the second electrode of the first transistor T1 may be connected, that is, the first transistor T1 may be diode-connected. For example, the scan signal GCi may be applied to the gate terminal of the third transistor T3.

[0107] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the fourth driving voltage line VL4 through which the second initialization voltage VINT2 is transmitted, and a gate electrode connected to the scan line GILi. The fourth transistor T4 can be turned on in response to the scan signal GIi transmitted through the scan line GILi, so that the second initialization voltage VINT2 is transmitted to the gate electrode of the first transistor T1. For example, the scan signal GIi can be applied to the gate terminal of the fourth transistor T4. Therefore, an initialization operation of initializing the voltage of the gate electrode of the first transistor T1 can be performed.

[0108] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emission line EMLi.

[0109] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the emission line EMLi.

[0110] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously in response to the emission signal EMi transmitted through the emission line EMLi. In this way, the first drive voltage ELVDD can be compensated by the diode-connected first transistor T1 so as to be provided to the light emitting element ED. For example, the emission signal EMi can be applied to the gate terminals of the fifth transistor T5 and the sixth transistor T6.

[0111] The seventh transistor T7 includes a first electrode connected to the anode of the light emitting element ED, a second electrode connected to the third driving voltage line VL3, and a gate electrode connected to the scanning line GWLi+1. The seventh transistor T7 is turned on in response to the scanning signal GWi+1 transmitted through the scanning line GWLi+1 to electrically connect the anode of the light emitting element ED and the third driving voltage line VL3. For example, the scanning signal GWi+1 may be applied to the gate terminal of the seventh transistor T7.

[0112] One end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The structure of the pixel PXij according to the embodiment is not limited to Figure 5 For example, the number of transistors included in one pixel PXij, the number of capacitors included in the pixel PXij, and the connection relationship between the transistors and the capacitors can be variously modified.

[0113] Figure 6 Is used to describe Figure 5 A timing diagram of the operation of a pixel PXij is shown in FIG.

[0114] refer to Figure 5 and Figure 6 , a frame Fs (or frame period) may include an emission period EP and a non-emission period NEP. The emission period EP may correspond to a low level period (i.e., an effective period) of the emission signal EMi. The non-emission period NEP may correspond to a high level period (i.e., a non-effective period) of the emission signal EMi.

[0115] The non-emission period NEP may include an initialization period and a data programming and compensation period.

[0116] When the scan signal GIi having a high level is supplied through the scan line GILi during the initialization period, the fourth transistor T4 is turned on. The second initialization voltage VINT2 is transferred to the gate electrode of the first transistor T1 through the fourth transistor T4 to initialize the first transistor T1.

[0117] Next, when a scan signal GCi having a high level is provided through the scan line GCLi during the data programming and compensation period, the third transistor T3 is turned on. The first transistor T1 is diode-connected by the third transistor T3 and is therefore turned on to be forward biased. At this time, when a scan signal GWi having a low level is provided through the scan line GWLi, the second transistor T2 is turned on. In this case, a compensation voltage obtained by subtracting a threshold voltage of the first transistor T1 from a voltage of the data signal Dj provided from the data line DLj is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 may be the compensation voltage.

[0118] When the first driving voltage ELVDD and the compensation voltage are respectively applied to opposite ends of the capacitor Cst, charges corresponding to a difference between the first driving voltage ELVDD and the compensation voltage may be stored in the capacitor Cst.

[0119] At the same time, the seventh transistor T7 is turned on in response to the scan signal GWi+1 having a low level transmitted through the scan line GWLi+1. When the seventh transistor T7 is turned on, the anode of the light emitting element ED is electrically connected to the third driving voltage line VL3. Therefore, the anode of the light emitting element ED can be initialized to the first initialization voltage VINT1.

[0120] Next, during the emission period EP, the emission signal EMi provided from the emission line EMLi changes from a high level to a low level. During the emission period EP, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission signal EMi having a low level. In this case, a driving current Id according to a voltage difference between a gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD is generated, and the driving current Id is provided to the light emitting element ED through the sixth transistor T6, and the driving current Id flows through the light emitting element ED. The light emitting element ED can emit light having a brightness corresponding to the driving current Id.

[0121] Fig. 7A According to the embodiments of the present disclosure Figure 3 Circuit diagram of the Sensor FX.

[0122] Fig. 7A Shows Figure 3 One sensor FXij among the multiple sensors FX shown in . Figure 3 Each of the plurality of sensors FX shown in FIG. 1 may have a Fig. 7A The same circuit configuration as the sensor FXij shown in .

[0123] The sensor FXij is electrically connected to the sensor scanning line SLi, the reset line RSL, and the readout line RLj.

[0124] The sensor FXij includes a light sensing element OPD and a sensor driving circuit SDC. The light sensing element OPD may be a photodiode. As an example of the present disclosure, the light sensing element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. The light sensing anode O_AE of the light sensing element OPD may be connected to the first sensing node SN1, and its cathode may be connected to the sixth driving voltage line VL6 transmitting the bias voltage VBIAS. In an embodiment, the bias voltage VBIAS is connected to the sixth driving voltage line VL6 provided to the bias voltage VBIAS. Figure 5 The second driving voltage ELVSS of the cathode of the light emitting element ED shown in is the same voltage.

[0125] The sensor driving circuit SDC includes three transistors ST1 to ST3. The three transistors ST1 to ST3 may include a reset transistor ST1, an amplifying transistor ST2, and an output transistor ST3. Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, while the other transistors may be N-type transistors. In an embodiment, the reset transistor ST1 is Figure 5 The third transistor T3 of the pixel PXij shown in FIG. 1 is the same N-type transistor, and each of the amplifying transistor ST2 and the output transistor ST3 is the same as the third transistor T3 of the pixel PXij shown in FIG. Figure 5 The first transistor T1 and the second transistor T2 of the pixel PXij shown in FIG. are the same P-type transistors. However, the present disclosure is not limited thereto. In an embodiment, all the reset transistors ST1, the amplifying transistors ST2, and the output transistors ST3 are P-type transistors. In an embodiment, all the reset transistors ST1, the amplifying transistors ST2, and the output transistors ST3 are N-type transistors.

[0126] The reset transistor ST1 includes a first electrode connected to a reset voltage line VL5 receiving a reset voltage VRST, a second electrode connected to a first sensing node SN1, and a gate electrode connected to a reset line RSL receiving a reset signal RST. The reset transistor ST1 may reset the potential of the first sensing node SN1 to the reset voltage VRST in response to the reset signal RST. In an embodiment, the reset voltage VRST has a voltage level lower than the bias voltage VBIAS.

[0127] The amplifying transistor ST2 includes a first electrode connected to a seventh driving voltage line VL7 receiving a sensor driving voltage VCOM, a second electrode connected to a second sensing node SN2, and a gate electrode connected to a first sensing node SN1. Figure 5The amplifying transistor ST2 may provide a current corresponding to the potential of the first sensing node SN1 to the second sensing node SN2.

[0128] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the readout line RLj, and a gate electrode connected to the sensor scanning line SLi receiving the sensor scanning signal Si. The output transistor ST3 can output a sensing signal FSj to the readout line RLj in response to the sensor scanning signal Si.

[0129] The circuit configuration of the sensor drive circuit SDC according to the embodiment of the present disclosure is not limited to Fig. 7A The circuit configuration shown in . Fig. 7A The sensor driving circuit SDC shown in FIG. 1 is merely an example, and the configuration of the sensor driving circuit SDC may be variously modified and implemented.

[0130] Figure 7B is a circuit diagram of a dummy sensor DX according to an embodiment of the present disclosure.

[0131] Figure 7B The dummy sensor shown in can have Fig. 7A The same circuit configuration is used for the sensor FXij shown in FIG. Figure 7B In the circuit components of the dummy sensor DX shown in FIG. 1 , the same reference numerals are used for the same circuit components as those of the sensor FXij, and additional description is omitted to avoid redundancy.

[0132] The dummy sensor DX is electrically connected to the sensor scan line SLi, the reset line RSL, and the dummy readout line DRL. In an embodiment, the sensor scan line SLi may be Figure 3 The dummy sensor DX outputs a dummy sensing signal DFS to the dummy readout line DRL. The dummy readout line DRL is a line different from any one of the readout lines (eg, RL1 to RLk).

[0133] Figure 8 Is used to describe Fig. 7A Timing diagram of the operation of sensor FXij shown in .

[0134] refer to Fig. 7A and Figure 8 When the reset signal RST turns to a high level, the reset transistor ST1 is turned on. When the reset transistor ST1 is turned on, the first sensing node SN1 may be initialized to a reset voltage VRST.

[0135] After the reset signal RST transitions to a low level, the sensor FXij is exposed to light during an exposure period LE. When a user's hand touches the display surface of the display panel DP, the light sensing element OPD may generate photo charges corresponding to light reflected by the user's hand, and the generated photo charges may be accumulated in the first sensing node SN1.

[0136] The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the amount of charge of the first sensing node SN1 input to a gate electrode of the amplifying transistor ST2 .

[0137] When the sensor scanning signal Si is at a non-active level (i.e., a high level), the output transistor ST3 is turned off. When the sensor scanning signal Si is turned to an active level (i.e., a low level), the output transistor ST3 is turned on. When the output transistor ST3 is turned on, a sensing signal FSj corresponding to the current flowing through the amplifying transistor ST2 can be output to the readout line RLj.

[0138] In an embodiment, the sensor scanning signal Si is Figure 5 and Figure 6 That is, the pixels PXij and the sensors FXij located in the i-th row can receive the same scanning signal GWi.

[0139] In an embodiment, during a biometric sensing mode (e.g., a fingerprint sensing mode), the optical sensing element OPD may generate a photocharge corresponding to light reflected by a ridge of a fingerprint or a valley between ridges of a fingerprint. During the fingerprint sensing mode, a sensing signal FSj output from the sensor FXij may be a signal corresponding to the user's fingerprint.

[0140] In an embodiment, in a biometric sensing mode (e.g., a blood pressure sensing mode), the optical sensing element OPD may generate a photocharge corresponding to light reflected from a blood vessel located below the cortex of the user's skin. During systole, blood moves to the peripheral arteries, thereby increasing arterial blood volume. On the other hand, during diastole, blood flows back to the heart, thereby reducing arterial blood volume. This change in blood volume changes the reflected light. During the blood pressure sensing mode, the sensing signal FSj output from the sensor FXij may be a signal corresponding to the user's blood pressure.

[0141] In an embodiment, in a touch sensing mode, the light sensing element OPD may generate light charges corresponding to light reflected by a user's touch. A sensing signal FSj output from the sensor FXij during the touch sensing mode may be a signal indicating whether a user has performed a touch operation.

[0142] Fig. 9is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Fig. 9 Shows Figure 5 The first transistor T1 and the third transistor T3 shown in FIG. Fig. 7A The portion of the reset transistor ST1 is shown in FIG.

[0143] refer to Fig. 9 , the display panel DP may include a base layer BL, a circuit layer DP_CL disposed on the base layer BL, a device layer DP_ED, and an encapsulation layer TFE.

[0144] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In an embodiment, the synthetic resin layer is a polyimide-based resin layer, but its material is not limited thereto. The synthetic resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, polyisoprene, an ethylene-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, and the like.

[0145] At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of a plurality of layers. The plurality of inorganic layers may constitute barrier layers BR1 and BR2 and / or a buffer layer BFL to be described later. The barrier layers BR1 and BR2 and the buffer layer BFL may be selectively provided.

[0146] The barrier layers BR1 and BR2 may prevent foreign matter from being introduced from the outside. The barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may include a plurality of layers, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0147] The barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. The first back metal layer BMC1 may be interposed between the first barrier layer BR1 and the second barrier layer BR2. In an embodiment of the present disclosure, the first back metal layer BMC1 may be omitted.

[0148] The buffer layer BFL may be disposed on the barrier layers BR1 and BR2. The buffer layer BFL may increase the bonding force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0149] The first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern may include low temperature polycrystalline silicon.

[0150] Fig. 9 Only a portion of the first semiconductor pattern disposed on the buffer layer BFL is shown. Another portion of the first semiconductor pattern may also be disposed in another region. The first semiconductor pattern may be arranged across the pixel according to a specific rule. Depending on whether the first semiconductor pattern is doped, the first semiconductor pattern may have different electrical characteristics. The first semiconductor pattern may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a region doped with a P-type dopant, and the N-type transistor may include a region doped with an N-type dopant. The second region may be an undoped region or a region doped with a concentration lower than that in the first region.

[0151] In an embodiment, the conductivity of the first region is greater than the conductivity of the second region. The first region can be basically used as an electrode or a signal line. The second region can basically correspond to the active region (or channel) of the transistor. In other words, a part of the semiconductor pattern can be the active region of the transistor. Another part thereof can be the source or drain of the transistor. Another part thereof can be a connecting electrode or a connecting signal line.

[0152] The first electrode SE1, the channel portion A1, and the second electrode D1 of the first transistor T1 are formed of the first semiconductor pattern. The first electrode SE1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions.

[0153] exist Fig. 9 FIG. 4 shows a portion of a connection signal line CSL formed by the first semiconductor pattern. The connection signal line CSL may be electrically connected to the sixth transistor T6 (reference Figure 5 )'s second electrode.

[0154] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels in common and may cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 is a single silicon oxide layer. The insulating layer of the circuit layer DP_CL and the first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but is not limited thereto.

[0155] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be a part of the metal pattern. The third electrode G1 of the first transistor T1 overlaps with the channel portion A1 of the first transistor T1. In the process of doping the first semiconductor pattern, the third electrode G1 of the first transistor T1 may function as a mask. The third electrode G1 may include, but is not limited to, titanium (Ti), silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum (Mo), aluminum (Al), an alloy containing aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0156] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0157] The upper electrode UE and the second back metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1. The upper electrode UE may be a portion of the metal pattern. A portion of the third electrode G1 and the upper electrode UE overlapping the portion of the third electrode G1 may define a capacitor Cst (reference Figure 5 ). In an embodiment of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. In this case, the upper electrode UE may be disposed on the insulating pattern, and the upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0158] The second back metal layer BMC2 may be disposed to correspond to the lower portion of the oxide thin film transistor (eg, the third transistor T3). In an embodiment, the second back metal layer BMC2 receives a constant voltage or signal. For example, the constant voltage may be a direct current (DC) voltage.

[0159] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE and the second back metal layer BMC2. The third insulating layer 30 may have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0160] The second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions distinguished from each other according to whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter referred to as the "reduction region") has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as the "non-reduction region"). The reduction region may be substantially used as a source / drain region or a signal line of a transistor. The non-reduction region substantially corresponds to an active region (alternatively, a semiconductor region or a channel) of a transistor. In other words, a portion of the second semiconductor pattern may be an active region of a transistor; another portion thereof may be a source / drain region of a transistor; and another portion thereof may be a signal transmission region.

[0161] The first electrode SE3, the channel portion A3 and the second electrode D3 of the third transistor T3 are formed by the second semiconductor pattern. The first electrode SE3 and the second electrode D3 include metal reduced from a metal oxide semiconductor. The first electrode SE3 and the second electrode D3 may extend from the channel portion A3 in opposite directions in cross section.

[0162] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap the plurality of pixels in common and may cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0163] The third electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The third electrode G3 may be a part of the metal pattern. The third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3. The third electrode G3 may be used as a mask in the process of doping the second semiconductor pattern. In an embodiment of the present disclosure, the fourth insulating layer 40 may be replaced by an insulating pattern.

[0164] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the third electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0165] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating the first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50.

[0166] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include a polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylate-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof, but is not particularly limited thereto.

[0167] The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and may cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0168] The first electrode layer may be disposed on the circuit layer DP_CL. The pixel defining layer PDL is formed on the first electrode layer. The first electrode layer may include a first anode R_AE and a light sensing anode O_AE. In an embodiment, the first anode R_AE and the light sensing anode O_AE are disposed on the seventh insulating layer 70. The first anode R_AE may be connected to the second connection electrode CNE20 through a third contact hole CH3 penetrating the seventh insulating layer 70. Fig. 9 Only the light emitting element ED_R (reference Figure 4 However, the first electrode layer may further include a first anode R_AE corresponding to the light emitting element ED_G (reference Figure 4 ) and the second anode corresponding to the light emitting element ED_B (reference Figure 4 ) of the third anode.

[0169] The first film opening PDL-OP1 and the second film opening PDL-OP2 are disposed on the pixel defining layer PDL. The first film opening PDL-OP1 exposes at least a portion of the first anode R_AE. The second film opening PDL-OP2 exposes at least a portion of the light sensing anode O_AE.

[0170] In an embodiment of the present disclosure, the pixel defining layer PDL further includes a black material. The pixel defining layer PDL may further include a black organic dye / pigment, such as carbon black, aniline black, etc. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a liquid-repelling organic material.

[0171] like Fig. 9As shown in , the display panel DP may include an emission region PXA-R and a non-emission region NPXA-R adjacent to the emission region PXA-R. The non-emission region NPXA-R may surround the emission region PXA-R. In an embodiment, the emission region PXA-R is defined as a partial region corresponding to the first anode R_AE exposed by the first film opening PDL-OP1.

[0172] The light emitting layer may be disposed on the first electrode layer. The light emitting layer may include a red light emitting layer, a green light emitting layer, and a blue light emitting layer. The red light emitting layer, the green light emitting layer, and the blue light emitting layer may be disposed in an area corresponding to the first film opening PDL-OP1. The red light emitting layer, the green light emitting layer, and the blue light emitting layer may be disposed in an area corresponding to the first film opening PDL-OP1. Figure 4 The red pixel PXR, green pixel PXG and blue pixel PXB shown in FIG are formed separately. Each of the red light emitting layer, the green light emitting layer and the blue light emitting layer may include an organic material and / or an inorganic material. The red light emitting layer, the green light emitting layer and the blue light emitting layer may generate a predetermined colored light. For example, the light emitting layer R_EL may generate red light. Fig. 9 It is shown that the light emitting layer R_EL is provided in a region corresponding to the first film opening PDL-OP1.

[0173] In the embodiment, patterned red light-emitting layers, green light-emitting layers, and blue light-emitting layers are described. However, a single light-emitting layer may be commonly provided in a plurality of emission regions. In this case, the light-emitting layer may generate white light or blue light. In addition, the light-emitting layer may have a multilayer structure referred to as "series".

[0174] The light-emitting layer R_EL may include a low-molecular organic material or a high-molecular organic material as a light-emitting material. The cathode CE is disposed on the light-emitting layer R_EL. As an example of the present disclosure, the cathode CE may be commonly disposed in the emission region PXA-R, the non-emission region NPXA-R, and the non-pixel region NPA. For example, a single layer may be used to implement the cathode CE overlapping the emission region PXA-R, the non-emission region NPXA-R, and the non-pixel region NPA.

[0175] The circuit layer DP_CL may also include a sensor driving circuit SDC (refer to Fig. 7A). For ease of description, a reset transistor ST1 of a sensor driving circuit SDC is shown. A first electrode STS1, a channel portion STA1, and a second electrode STD1 of the reset transistor ST1 are formed by a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 may include a metal reduced from a metal oxide semiconductor. A fourth insulating layer 40 is provided to cover the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. A third electrode STG1 of the reset transistor ST1 is provided on the fourth insulating layer 40. In an embodiment, the third electrode STG1 is a part of the metal pattern. The third electrode STG1 of the reset transistor ST1 overlaps with the channel portion STA1 of the reset transistor ST1.

[0176] In an embodiment of the present disclosure, the reset transistor ST1 is disposed on the same layer as the third transistor T3. That is, the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1 may be formed by the same process as the first electrode SE3, the channel portion A3, and the second electrode D3 of the third transistor T3. The third electrode STG1 of the reset transistor ST1 may be simultaneously formed by the same process as the third electrode G3 of the third transistor T3. The first electrode and the second electrode of each of the amplifying transistor ST2 and the output transistor ST3 of the sensor driving circuit SDC may be formed by the same process as the first electrode SE1 and the second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 may be formed on the same layer by the same process. Therefore, since an additional process for forming the reset transistor ST1 is not required, the manufacturing cost may be reduced and the process efficiency may be improved.

[0177] The device layer DP_ED may further include a light sensing device OPD (refer to Fig. 7A ). Fig. 9 Only one light sensing element OPD is shown.

[0178] The light sensing element OPD may include a light sensing anode O_AE, a photoelectric conversion layer O_RL, and a photocathode O_CE. The light sensing anode O_AE may be disposed on the same layer as the first electrode layer. That is, the light sensing anode O_AE may be disposed on the circuit layer DP_CL and may be formed simultaneously by the same process as the first anode R_AE. Fig. 9 As shown in , the display panel DP may further include a sensing area SA and a non-sensing area NSA adjacent to the sensing area SA. The non-sensing area NSA may surround the sensing area SA. In an embodiment, the sensing area SA is defined as a partial area corresponding to the light sensing anode O_AE exposed by the second film opening PDL-OP2.

[0179] The second film opening PDL-OP2 of the pixel defining layer PDL exposes at least a portion of the light sensing anode O_AE. The photoelectric conversion layer O_RL is disposed on the portion of the light sensing anode O_AE exposed by the second film opening PDL-OP2. The photoelectric conversion layer O_RL may include an organic photosensitive material. The photocathode O_CE may be disposed on the photoelectric conversion layer O_RL. The photocathode O_CE may be formed simultaneously by the same process as the cathode CE. As an example of the present disclosure, the photocathode O_CE may be integrated with the cathode CE.

[0180] Each of the light sensing anode O_AE and the photocathode O_CE may receive an electrical signal. The photocathode O_CE may receive a signal different from the signal of the light sensing anode O_AE. Therefore, a predetermined electric field may be formed between the light sensing anode O_AE and the photocathode O_CE. The photoelectric conversion layer O_RL generates an electrical signal corresponding to the light incident on the sensor. The photoelectric conversion layer O_RL may generate charges by absorbing the energy of the incident light. For example, the photoelectric conversion layer O_RL may include a photosensitive semiconductor material.

[0181] The charges generated by the photoelectric conversion layer O_RL change the electric field between the light sensing anode O_AE and the photocathode O_CE. The amount of charge generated by the photoelectric conversion layer O_RL may vary depending on whether light is incident on the light sensing element OPD, the amount of light incident on the light sensing element OPD, and the intensity of light incident on the light sensing element OPD. Therefore, the electric field formed between the light sensing anode O_AE and the photocathode O_CE may be changed. The light sensing element OPD according to an embodiment of the present disclosure may obtain one of the user's fingerprint, blood pressure, and touch information by a change in the electric field between the light sensing anode O_AE and the photocathode O_CE. For example, one of the user's fingerprint, blood pressure, and touch information may be determined based on a change in the electric field between the light sensing anode O_AE and the photocathode O_CE.

[0182] However, this is explained by way of example. The light sensing element OPD may include a phototransistor using the photoelectric conversion layer O_RL as an active layer. In this case, the light sensing element OPD may obtain fingerprint information by sensing the amount of current flowing through the phototransistor. The light sensing element OPD according to an embodiment of the present disclosure may include various photoelectric conversion elements capable of generating electrical signals in response to changes in the amount of light, but the present disclosure is not limited to the embodiments.

[0183] The encapsulation layer TFE is disposed on the element layer DP_ED. The encapsulation layer TFE includes at least one inorganic layer or at least one organic layer. In an embodiment of the present disclosure, the encapsulation layer TFE includes two inorganic layers and an organic layer disposed therebetween. In an embodiment of the present disclosure, the encapsulation layer TFE is a thin film encapsulation layer including a plurality of inorganic layers and a plurality of organic layers stacked alternately.

[0184] The inorganic layer of the encapsulation layer TFE can protect the light emitting element ED_R and the light sensing element OPD from moisture / oxygen, and the organic layer of the encapsulation layer TFE can protect the light emitting element ED_R and the light sensing element OPD from foreign matter. The inorganic layer of the encapsulation layer TFE may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., but is not limited thereto. The organic layer of the encapsulation layer TFE may include an acrylic-based organic layer, but is not limited thereto.

[0185] Fig.10 is a diagram showing a circuit configuration of a readout circuit 500 according to an embodiment of the present disclosure.

[0186] Fig.10 The entire circuit configuration of the readout circuit 500 is shown as follows: Figure 3 ) is a circuit related to the j-th readout line RLj receiving the sensing signal FSj.

[0187] refer to Fig.10 , the readout circuit 500 may include a sensing circuit 510 , a sample and hold circuit 520 , and an analog-to-digital converter (ADC) 530 .

[0188] The sensing circuit 510 includes an operational amplifier AMP, a capacitor C_F, and a switch SW_A. A reference voltage Vref may be input to a non-inverting input terminal (+) of the operational amplifier AMP, and the jth readout line RLj (e.g., RL1) may be connected to an inverting input terminal (-) of the operational amplifier AMP. That is, a sensing signal FSj may be provided to an inverting input terminal (-) of the operational amplifier AMP. The capacitor C_F may be connected between the inverting input terminal (-) of the operational amplifier AMP and an output terminal VOL of the operational amplifier AMP, and the switch SW_A may be connected in parallel across the capacitor C_F.

[0189] The sample and hold circuit 520 may include a first switch SW_R, a first capacitor C_R, a second switch SW_S, and a second capacitor C_S. The first switch SW_R and the first capacitor C_R may be referred to as a “first sampling circuit.” The second switch SW_S and the second capacitor C_S may be referred to as a “second sampling circuit.”

[0190] Fig.11 yes Fig.10 A timing diagram of the operation of the readout circuit 500 is shown in FIG.

[0191] refer to Fig.10 and Fig.11 , when the first switch signal RS is at a high level during the first period OP1, the switch SW_A is turned on. When the switch SW_A is turned on, the jth readout line RLj (e.g., RL1) is electrically connected to the output terminal VOL of the operational amplifier AMP. Therefore, the capacitor C_F can be initialized. When the first switch signal RS transitions to a low level, the sensing circuit 510 can operate as an integrator.

[0192] When the second switch signal SHR is at a high level during the second period OP2, the first switch SW_R is turned on. When the first switch SW_R is turned on, the first capacitor C_R is charged with the voltage of the output terminal VOL of the sensing circuit 510. For example, the first switch SW_R may be turned on at a time point when the photocharge of the light sensing element OPD is not transferred to the jth readout line RLj as the sensing signal FSj. Therefore, the first capacitor C_R may be charged with the first sampling signal V_SHR corresponding to the noise.

[0193] When the scan signal GWi transitions to a low level during the third period OP3, Fig. 7A , the output transistor ST3 shown in is turned on. Therefore, the current of the second sense node SN2 can be transferred to the j-th readout line RLj as the sensing signal FSj through the output transistor ST3. When the third switch signal SHS is at a high level during the third period OP3, the second switch SW_S is turned on. In this case, when the second switch SW_S is turned on, the second capacitor C_S is charged with the voltage of the output terminal VOL of the sensing circuit 510. Therefore, the second sampling signal V_SHS corresponding to the sensing signal FSj can be charged into the second capacitor C_S.

[0194] The analog-to-digital converter 530 converts a difference (or a difference value) between the first sampling signal V_SHR of the first capacitor C_R and the second sampling signal V_SHS of the second capacitor C_S into a digital signal (or a digital code) to output a readout signal FSS.

[0195] The first switching signal RS for periodically turning on the switch SW_A may be output during the reset time to reset the voltage of the output terminal VOL of the operational amplifier AMP.

[0196] The sensing signal FSj is proportional to the amount of photocharge generated by the light sensing element OPD. Because the current amount changes between the time point when no light is detected and the time point when light is detected is small, the voltage difference between the first sampling signal V_SHR and the second sampling signal V_SHS is also small. It may be necessary to increase the capacitance of the capacitor C_F to ensure a sufficient voltage difference between the first sampling signal V_SHR and the second sampling signal V_SHS. However, increasing the capacitance may increase the circuit area of ​​the readout circuit 500.

[0197] Fig.12 is a block diagram of a readout circuit 500 - 1 according to an embodiment of the present disclosure. In an embodiment, the readout circuit 500 is replaced with the readout circuit 500 - 1 .

[0198] refer to Fig.12 , the readout circuit 500 - 1 includes a sensing circuit 1000 and a reference current conveyor 2000 (eg, circuit).

[0199] The sensing circuit 1000 may include a current conveyor 1100 (eg, a circuit), a current storage unit 1200 , and an analog-to-digital converter 1300 .

[0200] The current transmitter 1100 receives a sensing signal FSj from the sensor FXij through the jth readout line RLj. In addition, the current transmitter 1100 receives a reference signal IREF from the reference current transmitter 2000. The current transmitter 1100 outputs a transmitter signal ICC based on the sensing signal FSj and the reference signal IREF. In an embodiment, the current transmitter 1100 does not include any capacitor.

[0201] In an embodiment, the transmitter signal ICC is the difference between the sense signal FSj and the reference signal IREF.

[0202] The current storage unit 1200 stores the transmitter signal ICC and outputs a first voltage signal VCM1 and a second voltage signal VCM2. The current storage unit 1200 may store many values ​​of the transmitter signal ICC over time to represent an analog signal. In an embodiment, the first voltage signal VCM1 corresponds to the transmitter signal ICC during a first cycle, and the second voltage signal VCM2 corresponds to the transmitter signal ICC during a second cycle different from the first cycle. For example, the first voltage signal VCM1 may be a first analog signal determined according to a first value of the transmitter signal ICC during the first cycle, and the second voltage signal VCM2 may be a second analog signal determined according to a second value of the transmitter signal ICC during the second cycle.

[0203] The analog-to-digital converter 1300 outputs a read signal FSS based on the first voltage signal VCM1 and the second voltage signal VCM2. In an embodiment, the analog-to-digital converter 1300 outputs a read signal FSS based on a difference between the first voltage signal VCM1 and the second voltage signal VCM2. For example, a difference signal may be calculated by subtracting one voltage signal (e.g., VCM1) from the other voltage signal (e.g., VCM2) of the voltage signals (e.g., VCM1 and VCM2), and the analog-to-digital converter 1300 may convert the difference signal into the read signal FSS.

[0204] The reference current conveyor 2000 outputs a reference signal IREF based on a dummy sensing signal DFS received from the dummy sensor DX through the dummy readout line DRL.

[0205] Fig.13 is a block diagram showing a circuit configuration of a sensing circuit 1000 and a reference current conveyer 2000 according to an embodiment.

[0206] refer to Fig.13 , the sensing circuit 1000 includes a current conveyor 1100 , a current storage unit 1200 and an analog-to-digital converter 1300 .

[0207] The current conveyor 1100 includes a first current mirror circuit MIR1 , a buffer circuit BF1 , and a second current mirror circuit MIR2 .

[0208] The first current mirror circuit MIR1 receives the sensing signal FSj, the reference voltage signals RV1 and RV2 , and the bias voltages VBP and VBN to output a voltage signal V0 .

[0209] The buffer circuit BF1 receives the voltage signal V0 and the reference voltage VREF to output a first voltage V1 and a second voltage V2 .

[0210] The second current mirror circuit MIR2 receives the first voltage V1 , the second voltage V2 , and the bias voltages VBP and VBN to output a transmitter signal ICC.

[0211] The current memory unit 1200 includes a first memory cell MC1 and a second memory cell MC2 .

[0212] Each of the first storage unit MC1 and the second storage unit MC2 stores the transmitter signal ICC. The first storage unit MC1 and the second storage unit MC2 may selectively store the transmitter signal ICC in response to the switch signal. For example, the first storage unit MC1 may store the transmitter signal ICC during the first cycle, and the second storage unit MC2 may store the transmitter signal ICC during the second cycle.

[0213] The first memory cell MC1 outputs the first voltage signal VCM1 corresponding to the transmitter signal ICC in response to the switching signal. For example, the first memory cell MC1 may output the first voltage signal VCM1 corresponding to the transmitter signal ICC during the first period.

[0214] The second storage unit MC2 outputs the second voltage signal VCM2 corresponding to the transmitter signal ICC in response to the switching signal. For example, the second storage unit MC2 may output the second voltage signal VCM2 corresponding to the transmitter signal ICC during the second period.

[0215] The analog-to-digital converter 1300 outputs a readout signal FSS based on the first voltage signal VCM1 and the second voltage signal VCM2 .

[0216] The reference current conveyor 2000 includes a buffer circuit BF3 and a third current mirror circuit MIR3. In an embodiment, the reference current conveyor 2000 does not include any capacitor.

[0217] The buffer circuit BF3 receives the dummy sensing signal DFS and the reference voltage VREF to output reference voltage signals RV1 and RV2. The buffer circuit BF3 may be an operational amplifier having an inverting input terminal receiving the dummy sensing signal DFS and a non-inverting input terminal receiving the reference voltage VREF.

[0218] The third current mirror circuit MIR3 receives the reference voltage signals RV1 and RV2 and the bias voltages VBP and VBN.

[0219] Fig.14 is a circuit diagram of a buffer circuit BF1 and a second current mirror circuit MIR2 in a current conveyor 1100 according to an embodiment of the present disclosure.

[0220] refer to Fig.14 , the buffer circuit BF1 includes transistors TR1 to TR22.

[0221] The transistor TR1 is connected between the first node N1 and the third node N3, and includes a gate electrode connected to the first input node IN1. The transistor TR2 is connected between the second node N2 and the third node N3, and includes a gate electrode connected to the second input node IN2. The transistor TR22 is connected between the third node N3 and the second voltage terminal VIN2, and includes a gate electrode connected to the bias voltage VBN. <2> of the gate electrode.

[0222] The transistor TR3 is connected between the fourth node N4 and the fifth node N5, and includes a gate electrode connected to the first input node IN1. The transistor TR4 is connected between the fourth node N4 and the sixth node N6, and includes a gate electrode connected to the second input node IN2.

[0223] The transistor TR5 is connected between the first voltage terminal VIN1 and the fourth node N4 and includes a transistor for receiving the bias voltage VBP. <2> The transistor TR6 is connected between the first voltage terminal VIN1 and the first node N1, and includes a gate electrode connected to the seventh node N7. The transistor TR7 is connected between the first node N1 and the seventh node N7, and includes a gate electrode receiving the bias voltage VBP. <0> The transistor TR8 is connected between the seventh node N7 and the eighth node N8, and includes a gate electrode receiving the bias voltage VBP. <1> The transistor TR9 is connected between the seventh node N7 and the eighth node N8, and includes a gate electrode receiving a bias voltage VBN. <1> of the gate electrode.

[0224] The transistor TR10 is connected between the eighth node N8 and the fifth node N5 and includes a transistor for receiving the bias voltage VBN. <0> The transistor TR11 is connected between the fifth node N5 and the second voltage terminal VIN2, and includes a gate electrode connected to an eighth node N8.

[0225] The transistor TR12 is connected between the first voltage terminal VIN1 and the second node N2, and includes a gate electrode connected to the seventh node N7. The transistor TR13 is connected between the second node N2 and the ninth node N9, and includes a gate electrode connected to the seventh node N7. <0> The transistor TR14 is connected between the ninth node N9 and the tenth node N10, and includes a gate electrode receiving the bias voltage VBP. <1> The transistor TR15 is connected between the ninth node N9 and the tenth node N10, and includes a gate electrode receiving a bias voltage VBN. <1> of the gate electrode.

[0226] The transistor TR16 is connected between the tenth node N10 and the sixth node N6 and includes a transistor for receiving the bias voltage VBN. <0> The transistor TR17 is connected between the sixth node N6 and the second voltage terminal VIN2, and includes a gate electrode connected to an eighth node N8.

[0227] The transistors TR18, TR19, TR20, and TR21 are sequentially connected in series between the first voltage terminal VIN1 and the second voltage terminal VIN2. The transistor TR18 includes a gate electrode connected to a ninth node N9. The transistor TR19 includes a gate electrode receiving a bias voltage VBP. <0> The transistor TR20 includes a gate electrode receiving a bias voltage VBN. <0> The transistor TR21 includes a gate electrode connected to the tenth node N10.

[0228] The first input node IN1 receives a first signal X, and the second input node IN2 receives a second signal Y. In an embodiment, the first signal X is from Fig.13The voltage signal V0 output by the first current mirror circuit MIR1 shown in FIG. 1 and the second signal Y are the reference voltage VREF.

[0229] In an embodiment, the first voltage terminal VIN1 receives a first power supply voltage VDD, and the second voltage terminal VIN2 receives a second power supply voltage VSS. In an embodiment, the first power supply voltage VDD is higher than the second power supply voltage VSS. In an embodiment, the second power supply voltage VSS is a ground voltage.

[0230] In an embodiment, the buffer circuit BF1 outputs a voltage signal V0 (reference voltage) corresponding to the difference between the first signal X supplied to the first input node IN1 and the second signal Y supplied to the second input node IN2. Fig.13 ) and the reference voltage VREF) corresponding to the first voltage V1 and the second voltage V2. In an embodiment, the voltage of the ninth node N9 is the first voltage V1, and the voltage of the tenth node N10 is the second voltage V2. The first voltage V1 and the second voltage V2 are provided as inputs to the second current mirror circuit MIR2.

[0231] The second current mirror circuit MIR2 includes transistors TR31 , TR32 , TR33 , and TR34 .

[0232] The transistors TR31, TR32, TR33, and TR34 are sequentially connected in series between the first voltage terminal VIN1 and the second voltage terminal VIN2. The transistor TR31 includes a gate electrode connected to a ninth node N9. The transistor TR32 includes a gate electrode receiving a bias voltage VBP. <0> The transistor TR33 includes a gate electrode receiving a bias voltage VBN. <0> The transistor TR34 includes a gate electrode connected to the tenth node N10.

[0233] The second current mirror circuit MIR2 receives the first voltage V1, the second voltage V2 and the bias voltage VBP <0> and VBN <0> , to output the transmitter signal ICC.

[0234] In an embodiment, Fig.13 The buffer circuit BF3 of the reference current conveyor 2000 shown in FIG. 1 has a structure similar to Fig.14 The circuit configuration of the buffer circuit BF1 in the current conveyor 1100 is shown in FIG.

[0235] Fig.15 is a circuit diagram of a current storage unit 1200 according to an embodiment of the present disclosure.

[0236] refer to Fig.15 The current storage unit 1200 includes an operational amplifier (or simply referred to as an amplifier) ​​AMP1, a first storage unit MC1 and a second storage unit MC2.

[0237] The operational amplifier AMP1 includes a first input terminal, a second input terminal, an output node (or a twelfth node) N12, and transistors TR41 to TR46.

[0238] The transistor TR41 is connected between the third voltage terminal VIN3 and the fifth voltage terminal VIN5 and includes a gate electrode connected to the fifth voltage terminal VIN5. The transistor TR42 is connected between the third voltage terminal VIN3 and the eleventh node N11 and includes a gate electrode connected to the fifth voltage terminal VIN5.

[0239] The transistor TR43 is connected between the eleventh node N11 and the twelfth node N12 and includes a gate electrode connected to the first input terminal The first input terminal receives a reference voltage VREF.

[0240] The transistor TR44 is connected between the eleventh node N11 and the thirteenth node N13 and includes a gate electrode connected to the second input terminal The second input terminal is commonly connected to a twenty-second node N22 of the first and second memory cells MC1 and MC2.

[0241] The transistor TR45 is connected between the twelfth node N12 and the fifth voltage terminal VIN5, and includes a gate electrode connected to the thirteenth node N13. The transistor TR46 is connected between the thirteenth node N13 and the fifth voltage terminal VIN5, and includes a gate electrode connected to the thirteenth node N13.

[0242] The first memory cell MC1 includes transistors TR51 and TR52 , switches (or switch circuits) SW11 to SW15 , and capacitors CA1 and CA2 .

[0243] The transistor TR51 is connected between the fourth voltage terminal VIN4 and the 21st node N21, and includes a gate electrode connected to the 23rd node N23. The transistor TR52 is connected between the 21st node N21 and the fifth voltage terminal VIN5, and includes a gate electrode connected to the 24th node N24.

[0244] The capacitor CA1 is connected between the fourth voltage terminal VIN4 and the twenty-third node N23. The capacitor CA2 is connected between the twenty-fourth node N24 and the fifth voltage terminal VIN5.

[0245] The switch SW11 is connected between the third input node IN3 and the 21st node N21, and is controlled in response to the switch signal P1. The switch SW12 is connected between the 23rd node N23 and the 21st node N21, and is controlled in response to the switch signal P1. The switch SW13 is connected between the 21st node N21 and the 22nd node N22, and is controlled in response to the switch signal P1A. The switch SW14 is connected between the 24th node N24 and the 12th node N12 of the operational amplifier AMP1, and is controlled in response to the switch signal P1A. The switch SW15 is connected between the 21st node N21 and the output node OUT1, and is controlled in response to the switch signal P3.

[0246] The second memory cell MC2 includes transistors TR61 and TR62 , switches SW21 to SW25 , and capacitors CB1 and CB2 .

[0247] The transistor TR61 is connected between the fourth voltage terminal VIN4 and the thirty-first node N31, and includes a gate electrode connected to the thirty-third node N33. The transistor TR62 is connected between the thirty-first node N31 and the fifth voltage terminal VIN5, and includes a gate electrode connected to the thirty-fourth node N34.

[0248] The capacitor CB1 is connected between the fourth voltage terminal VIN4 and the thirty-third node N33. The capacitor CB2 is connected between the thirty-fourth node N34 and the fifth voltage terminal VIN5.

[0249] The switch SW21 is connected between the third input node IN3 and the thirty-first node N31, and is controlled in response to the switch signal P2. The switch SW22 is connected between the thirty-third node N33 and the thirty-first node N31, and is controlled in response to the switch signal P2. The switch SW23 is connected between the thirty-first node N31 and the twenty-second node N22, and is controlled in response to the switch signal P2A. The switch SW24 is connected between the thirty-fourth node N34 and the twelfth node N12 of the operational amplifier AMP1, and is controlled in response to the switch signal P2A. The switch SW25 is connected between the thirty-first node N31 and the output node OUT2, and is controlled in response to the switch signal P3.

[0250] Fig.16 yes Fig.15 0 is a timing diagram of the operations of the first memory cell MC1 and the second memory cell MC2 shown in FIG.

[0251] refer to Fig.15 and Fig.16, when the switch signal P1 is at a high level during the first period PP1, the switches SW11 and SW12 are turned on. Therefore, a voltage corresponding to the transmitter signal ICC may be stored in the capacitor CA1 through the switches SW11 and SW12.

[0252] Meanwhile, when the switch signal P1A is at a high level during a portion of the first period PP1, the switches SW13 and SW14 are turned on. When the switch SW13 is turned on, the current signal OP_ICC corresponding to the voltage level of the 22nd node N22 flows to the 12th node N12. Therefore, the voltage corresponding to the transmitter signal ICC can be stored in the capacitor CA2.

[0253] When the switch signal P2 is at a high level during the second period PP2, the switches SW21 and SW22 are turned on. Therefore, a voltage corresponding to the transmitter signal ICC may be stored in the capacitor CB1 through the switches SW21 and SW22.

[0254] Meanwhile, when the switch signal P2A is at a high level during a portion of the second period PP2, the switches SW23 and SW24 are turned on. When the switch SW23 is turned on, the current signal OP_ICC corresponding to the voltage level of the 22nd node N22 flows to the 12th node N12. Therefore, the voltage corresponding to the transmitter signal ICC can be stored in the capacitor CB2.

[0255] When the switch signals P1 and P1A are at a low level during the second period PP2 and the third period PP3, all the switches SW11 to SW14 are turned off. Therefore, current flows through the transistors TR51 and TR52 according to the voltage stored in the capacitors CA1 and CA2.

[0256] When the switching signal P3 is at a high level during the third period PP3 , the switch SW15 may be turned on and may output the voltage of the twenty-first node N21 as the first voltage signal VCM1 .

[0257] When the switch signals P2 and P2A are at a low level during the third period PP3, all the switches SW21 to SW24 are turned off. Therefore, current flows through the transistors TR61 and TR62 according to the voltage stored in the capacitors CB1 and CB2.

[0258] When the switching signal P3 is at a high level during the third period PP3 , the switch SW25 may be turned on and may output the voltage of the thirty-first node N31 as the second voltage signal VCM2 .

[0259] The transmitter signal ICC corresponding to the sensing signal FSj received during the first period PP1 is stored in the capacitors CA1 and CA2 of the first storage unit MC1. The transmitter signal ICC corresponding to the sensing signal FSj received during the second period PP2 is stored in the capacitors CB1 and CB2 of the second storage unit MC2.

[0260] When the sensor scan signal Si (reference Fig. 7A ) is at a high level during the first period PP1, the transfer signal ICC at a time point when the photo charges of the light sensing element OPD are not transferred to the jth readout line RLj as the sensing signal FSj may be transferred to the first storage cell MC1. Therefore, the capacitors CA1 and CA2 may be charged with a voltage corresponding to the noise.

[0261] When the sensor scan signal Si (reference Fig. 7A ) is at a low level during the first period PP1, the photocharge of the light sensing element OPD is transferred to the j-th readout line RLj as the sensing signal FSj, and thus the transmitter signal ICC corresponding to the photocharge of the light sensing element OPD may be transferred to the second storage unit MC2. Therefore, the capacitors CB1 and CB2 may be charged with a voltage corresponding to the photocharge of the light sensing element OPD.

[0262] In other words, during the third period PP3 , the first voltage signal VCM1 and the second voltage signal VCM2 may have a predetermined voltage difference.

[0263] Analog-to-digital converter 1300 (reference Fig.13 ) converts the difference between the first voltage signal VCM1 and the second voltage signal VCM2 into a digital signal (or digital code) to output a readout signal FSS.

[0264] The readout circuit of the display device according to the above-described embodiment does not include an internal capacitor, and therefore does not require time to reset the internal capacitor. Therefore, the readout circuit can operate at high speed. In addition, the readout circuit does not include an internal capacitor, and therefore the circuit area can be minimized. In an embodiment, the readout circuit does not include an internal capacitor that needs to be reset. For example, elements 510 and 520 including internal capacitors C_F and C_R can be replaced with current transmitters 1100 and 2000 that do not use internal capacitors. In an embodiment, the readout circuit constitutes transmitters 1100 and 2000 and ADC 1300, and the current storage unit 1200 is considered to be a structure separated from the readout circuit.

[0265] The readout circuit may include an amplifier, and the amplifier may remove common mode noise. Thus, the dynamic range of the sensing signal from the sensor may be increased.

[0266] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: A display panel including pixels including light emitting elements, and sensors including light sensing elements and dummy sensors; as well as a readout circuit configured to output a readout signal based on a sensing signal received from the sensor and a dummy sensing signal received from the dummy sensor, Wherein, the readout circuit comprises: a reference current transmitter configured to output a reference signal corresponding to the dummy sensing signal; and The sensing circuit is configured to output the readout signal corresponding to the difference between the sensing signal and the reference signal.

2. The display device according to claim 1, wherein: The sensing circuit comprises: a current transmitter configured to output a transmitter signal corresponding to the difference between the sensing signal and the reference signal; a current storage unit configured to store the transmitter signal; and An analog-to-digital converter is configured to output the readout signal by converting the transmitter signal from the current storage unit into a digital signal.

3. The display device according to claim 2, wherein: The current storage unit comprises: a first storage unit configured to store the transmitter signal corresponding to a difference between the reference signal and the sensing signal received during a first period; and A second storage unit is configured to store the transmitter signal corresponding to a difference between the reference signal and the sensing signal received during a second period different from the first period.

4. The display device according to claim 3, wherein: The first storage unit comprises: a first capacitor configured to store the transmitter signal during the first period; and A second capacitor is configured to store the transmitter signal during the first period.

5. The display device according to claim 4, wherein: The second storage unit comprises: a third capacitor configured to store the transmitter signal during the second period; and A fourth capacitor is configured to store the transmitter signal during the second period.

6. The display device according to claim 3, wherein: The current storage unit further includes: An amplifier includes a first input terminal, a second input terminal, and an output node, and is configured to receive a reference voltage from the first input terminal, receive the transmitter signal from the second input terminal, and output a current corresponding to the transmitter signal to the output node.

7. The display device according to claim 6, wherein: The first storage unit comprises: a first transistor connected between the first voltage terminal and the first node and including a gate electrode connected to the second node; a first capacitor connected between the first voltage terminal and the second node; a first switch circuit configured to electrically connect an input node receiving the transmitter signal with the second node in response to a first switch signal, and to pass the transmitter signal to the second input terminal of the amplifier in response to a second switch signal; a second transistor connected between the first node and the second voltage terminal and including a gate electrode connected to a third node; a second capacitor connected between the third node and the second voltage terminal; and The second switch circuit is configured to electrically connect the output node of the amplifier to the third node in response to the second switch signal.

8. The display device according to claim 7, wherein: The second storage unit comprises: a third transistor connected between the first voltage terminal and a fourth node and including a gate electrode connected to a fifth node; a third capacitor connected between the first voltage terminal and the fifth node; a third switch circuit configured to electrically connect the input node receiving the transmitter signal with the fifth node in response to a third switch signal, and to transmit the transmitter signal to the second input terminal of the amplifier in response to a fourth switch signal; a fourth transistor connected between the fourth node and the second voltage terminal and including a gate electrode connected to a sixth node; a fourth capacitor connected between the sixth node and the second voltage terminal; and The fourth switch circuit is configured to electrically connect the output node of the amplifier to the sixth node in response to the fourth switch signal.

9. The display device according to claim 2, wherein: The reference current conveyor outputs a first reference voltage signal and a second reference voltage signal corresponding to the dummy sensing signal.

10. The display device according to claim 9, wherein: The current conveyor comprises: a first current mirror circuit configured to receive the sensing signal, the first reference voltage signal, the second reference voltage signal, a first bias voltage, and a second bias voltage to output a voltage signal; a buffer circuit configured to receive the voltage signal and a reference voltage to output a first voltage and a second voltage; and The second current mirror circuit is configured to receive the first voltage, the second voltage, the first bias voltage, and the second bias voltage to output the transmitter signal.

11. The display device according to claim 1, wherein: The display panel includes a display area and a non-display area, the light emitting element and the sensor are arranged in the display area, and the dummy sensor is arranged in the non-display area.

12. The display device according to claim 1, wherein: The sensor comprises: sensor light sensing element; and A sensor driving circuit is connected to the sensor light sensing element and configured to output the sensing signal corresponding to the external light.

13. The display device according to claim 12, wherein: The sensor driving circuit comprises: a reset transistor including a first electrode for receiving a reset voltage, a second electrode connected to the first sensing node, and a gate electrode for receiving a reset signal; an amplifying transistor including a first electrode for receiving a driving voltage, a second electrode connected to a second sensing node, and a gate electrode connected to the first sensing node; and The output transistor includes a first electrode connected to the second sensing node, a second electrode connected to a readout line for outputting the sensing signal, and a gate electrode for receiving a scanning signal.

14. The display device according to claim 1, wherein: The dummy sensor further includes a sensor driving circuit connected to the light sensing element and configured to output the dummy sensing signal corresponding to external light.

15. A readout circuit comprising: a reference current transmitter configured to output a reference signal corresponding to a dummy sensing signal from the dummy sensor; as well as a sensing circuit configured to output a readout signal corresponding to a difference between the reference signal and a sensing signal received from a sensor, Wherein, the sensing circuit comprises: a current transmitter configured to output a transmitter signal corresponding to the difference between the sensing signal and the reference signal; a current storage unit configured to store the transmitter signal; and An analog-to-digital converter is configured to output the readout signal by converting the transmitter signal from the current storage unit into a digital signal.

16. The readout circuit according to claim 15, wherein: The current storage unit comprises: a first storage unit configured to store the transmitter signal corresponding to a difference between the reference signal and the sensing signal received during a first period; and A second storage unit is configured to store the transmitter signal corresponding to a difference between the reference signal and the sensing signal received during a second period different from the first period.

17. The readout circuit according to claim 16, wherein: The current storage unit further includes: An amplifier includes a first input terminal, a second input terminal, and an output node, and is configured to receive a reference voltage from the first input terminal, receive the transmitter signal from the second input terminal, and output a current corresponding to the transmitter signal to the output node.

18. The readout circuit according to claim 16, wherein: The first storage unit comprises: a first capacitor configured to store the transmitter signal during the first period; and a second capacitor configured to store the transmitter signal during the first period, and Wherein, the second storage unit includes: a third capacitor configured to store the transmitter signal during the second period; and A fourth capacitor is configured to store the transmitter signal during the second period.

19. The readout circuit according to claim 17, wherein: The first storage unit comprises: a first transistor connected between the first voltage terminal and the first node and including a gate electrode connected to the second node; a first capacitor connected between the first voltage terminal and the second node; a first switch circuit configured to electrically connect an input node receiving the transmitter signal with the second node in response to a first switch signal, and to pass the transmitter signal to the second input terminal of the amplifier in response to a second switch signal; a second transistor connected between the first node and the second voltage terminal and including a gate electrode connected to a third node; a second capacitor connected between the third node and the second voltage terminal; and The second switch circuit is configured to electrically connect the output node of the amplifier to the third node in response to the second switch signal.

20. The readout circuit according to claim 19, wherein: The second storage unit comprises: a third transistor connected between the first voltage terminal and a fourth node and including a gate electrode connected to a fifth node; a third capacitor connected between the first voltage terminal and the fifth node; a third switch circuit configured to electrically connect the input node receiving the transmitter signal with the fifth node in response to a third switch signal, and to transmit the transmitter signal to the second input terminal of the amplifier in response to a fourth switch signal; a fourth transistor connected between the fourth node and the second voltage terminal and including a gate electrode connected to a sixth node; a fourth capacitor connected between the sixth node and the second voltage terminal; and A fourth switch circuit is configured to electrically connect the output node of the amplifier to the sixth node in response to the fourth switch signal.

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