Solid state storage device and data access method thereof

Abstract

The invention relates to a solid-state storage device and a data access method thereof. The invention provides a solid-state storage device which is electrically connected to a host. The solid state storage device includes: a controller; a non-volatile memory; and a volatile memory. The volatile memory includes a submission queue and a completion queue. The controller obtains the access instruction from the host and records the access instruction in a submission queue. The access instruction corresponds to a first logical address. The controller determines whether a first write instruction exists in the queue to generate a determination result, where the first write instruction corresponds to a second logical address, and the second logical address is the same as the first logical address. The controller determines the processing mode of the access instruction according to the judgment result.

Description

Technical Field

[0001] The present invention relates to a solid-state storage device, and in particular to a solid-state storage device and a data access method thereof. Background Art

[0002] Solid-state storage devices use non-volatile memory to store data. With the development of technology, they have been widely used in different computer systems. However, due to the characteristics of non-volatile memory, the number of times data is read and written to the non-volatile memory is closely related to the service life of the non-volatile memory. If the host frequently accesses the non-volatile memory (such as NAND flash memory) in the solid-state storage device, it is easy to cause the service life of the non-volatile memory to be reduced. Summary of the invention

[0003] Therefore, the present invention provides a solid-state storage device and a data access method thereof to solve the above-mentioned problems.

[0004] In one embodiment, the present invention provides a solid-state storage device configured to be electrically connected to a host. The solid-state storage device includes: a controller; a non-volatile memory electrically connected to the controller; and a volatile memory electrically connected to the controller, wherein the volatile memory includes a commit queue and a completion queue. The controller is configured to obtain an access instruction from the host and record the access instruction in the commit queue, wherein the access instruction corresponds to a first logical address. The controller determines whether there is a first write instruction in the commit queue to generate a judgment result, wherein the first write instruction corresponds to a second logical address, and the second logical address is the same as the first logical address. The controller determines a processing method for the access instruction based on the judgment result.

[0005] In another embodiment, the present invention further provides a data access method for a solid-state storage device, wherein the solid-state storage device is electrically connected to a host. The solid-state storage device includes a controller, a volatile memory, and a non-volatile memory. The method includes: using the controller to obtain an access instruction from the host, and recording the access instruction in a commit queue of the volatile memory, wherein the access instruction corresponds to a first logical address; using the controller to determine whether there is a first write instruction in the commit queue, wherein the first write instruction corresponds to a second logical address, and the second logical address is the same as the first logical address; and using the controller to determine a processing method for the access instruction according to the determination result. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a block diagram showing a computer system according to an embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a flow chart of related operations of a write instruction according to an embodiment of the present invention.

[0008] Figure 3A and 3B According to the present invention Figure 2 Schematic diagram of the submission queue and completion queue of a solid-state storage device in an embodiment of the present invention.

[0009] Figures 4A to 4C According to the present invention Figure 5 Schematic diagram of the submission queue and completion queue of a solid-state storage device in an embodiment of the present invention.

[0010] Figure 5 FIG. 4 is a flow chart of related operations of a read instruction according to another embodiment of the present invention.

[0011] Figure 6 FIG. 4 is a flow chart of related operations of a write instruction according to another embodiment of the present invention.

[0012] Figure 7 FIG. 4 is a flow chart of a data access method for a solid-state storage device according to an embodiment of the present invention.

[0013] Fig. 8A According to the present invention Figure 7 Flow chart of a data access method 800A for a read instruction in an embodiment.

[0014] Figure 8B According to the present invention Figure 7 Flow chart of a data access method 800B for a write instruction in an embodiment.

[0015] Figures 9A to 9C According to the present invention Figure 6 Schematic diagram of a submission queue and a completion queue of a solid-state storage device in an embodiment of DETAILED DESCRIPTION

[0016] The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the scope of the subsequent patent application.

[0017] It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processing, components and / or components, but do not exclude the addition of more technical features, values, method steps, operation processing, components, components, or any combination of the above.

[0018] The terms "first", "second", "third", etc. used in the patent application are used to modify the components in the patent application. They are not used to indicate a priority order, a prior relationship, or that one component precedes another component, or a temporal sequence in the execution of method steps. They are only used to distinguish components with the same name.

[0019] The term "configured to" may describe or claim that various units, circuits, or other components are "configured to" perform a task or tasks. In such contexts, the term "configured to" is used to imply structure by indicating that the units / circuits / components include structure (e.g., circuitry) that performs those task(s) during operation. Thus, even when the specified unit / circuit / component is not currently operating (e.g., not turned on), the unit / circuit / component may still be said to be configured to perform the task. The units / circuit / components used with the term "configured to" include hardware - e.g., circuits, memory (storing program instructions executable to perform operations), etc. In addition, "configured to" may include generic structures (e.g., generic circuitry) that are manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the task(s) to be solved. "Configured to" may also include adapting a manufacturing process (eg, a semiconductor manufacturing facility) to produce devices (eg, integrated circuits) adapted to perform or execute one or more tasks.

[0020] Figure 1 It is a block diagram showing a computer system according to an embodiment of the present invention.

[0021] like Figure 1 As shown, the computer system 1 includes a solid-state storage device 10 and a host 20, wherein the solid-state storage device 10 is electrically connected to the host 20 via a bus 11 to perform command and data transmission. In some embodiments, the bus 11 can be a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA) bus, a Peripheral Component Interconnect Express (PCI Express, PCIe) bus, etc., but the present disclosure is not limited thereto.

[0022] The solid-state storage device 10 includes a controller 102, a volatile memory 106, and a non-volatile memory 108. The controller 102 is electrically connected to the volatile memory 106 and the non-volatile memory 108, and is used to control data access of the volatile memory 106 and the non-volatile memory 108. In some embodiments, the controller 102 may be, for example, a general-purpose processor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc., but the present disclosure is not limited thereto.

[0023] The volatile memory 106 includes, for example, a dynamic random access memory (DRAM) and / or a static random access memory (SRAM), but the present disclosure is not limited thereto. In some embodiments, the volatile memory 106 may be disposed outside the controller 102, for example. In other embodiments, the volatile memory 106 may be integrated into the controller 102, for example. The non-volatile memory 108 may be, for example, a NAND flash memory for storing write data provided by the host 20.

[0024] The host 20 includes, for example, a processor 202 and a system memory 204, and the processor 202 is electrically connected to the system memory 204. In some embodiments, the processor 202 includes, for example, a central processing unit (CPU), a general purpose processor, a microprocessor, etc., but the disclosure is not limited thereto. In addition, the processor 202 includes a controller (not shown) for controlling data access to the system memory 204. The system memory 204 includes, for example, a dynamic random access memory, but the disclosure is not limited thereto.

[0025] In some embodiments, the host 20 may support the non-volatile memory communication protocol (NVM Express, NVME), and the system memory 204 is configured with a submission queue 2041, a completion queue 2042, and a data buffer 2043. The submission queue 2041 is used to record the access instructions issued by the processor 202, and the completion queue 2042 is used to record the status of the solid-state storage device 10 in response to the completed access instructions. The data buffer 2043 is used to store the data that the host 20 wants to write to the solid-state storage device 10 and to store the data read by the host 20 from the solid-state storage device 10.

[0026] In some embodiments, the solid-state storage device 10 may support, for example, the non-volatile memory communication protocol (NVM Express, NVME), and the controller 102 may retrieve access instructions, such as write instructions, read instructions, etc., from the submission queue 2041 of the host 20. The volatile memory 106 is configured with a submission queue 1061 and a completion queue 1062. The submission queue 1061 is used to record the access instructions retrieved from the host 20, and the completion queue 1062 is used to record the status of the access instructions completed by the solid-state storage device 10.

[0027] The non-volatile memory 108 includes a plurality of blocks, and each block includes a plurality of pages. For example, the non-volatile memory 108 includes 1024 blocks, and each block includes 64 pages. Assuming that the capacity of each page is 16Kbytes, the capacity of each block is 1Mbyte. The above data is only for illustration, and the manufacturer of the non-volatile memory 108 can determine the number of pages in each block and the capacity of each page.

[0028] Figure 2 FIG. 4 is a flow chart of related operations of a write instruction according to an embodiment of the present invention. Figure 3A and 3B According to the present invention Figure 2 Schematic diagram of the submission queue 1061 and the completion queue 1062 of the solid-state storage device 10 in an embodiment of the present invention.

[0029] In some embodiments, when the host 20 wants to store a write data to the solid-state storage device 10, the processor 202 stores the write data corresponding to a write command CMD1 to the data buffer 2043 of the system memory 204 (arrow 222), and writes the write command CMD1 to the commit queue 2041 (arrow 224). For example, the content of the write command CMD1 includes the logical address of the write data, such as 0x2000, and the size of the write data, such as 16K bytes.

[0030] In some embodiments, the controller 102 of the solid-state storage device 10 may periodically check whether there is a new access instruction in the commit queue 2041. The controller 102 of the solid-state storage device 10 may fetch the write instruction CMD1 from the commit queue 2041 (arrow 226), and record the fetched write instruction CMD1 in the commit queue 1061 of the volatile memory 106 (arrow 228). Figure 3A shown.

[0031] It should be noted that for the solid state storage device 10, the write command from the host 20 may have a long response time. Therefore, in the embodiment of the present invention, after the controller 102 retrieves the write command CMD1 from the commit queue 2041, it does not execute the retrieved write command CMD1, but waits for the next access command. At this time, the write command CMD1 is in a pending status and remains recorded in the commit queue 1061, and the write data corresponding to the write command CMD1 remains stored in the data buffer 2043 of the host 20.

[0032] The controller 102 may determine the timing of executing the write command CMD1. The following is only an explanation of the execution flow of the write command CMD1 when the controller 102 determines to execute the write command CMD1.

[0033] When the controller 102 decides to execute the write instruction CMD1, Figure 2 As shown, the controller 102 retrieves the write command CMD1 from the commit queue 1061 (arrow 230), and receives the write data corresponding to the write command CMD1 from the data buffer 2043 according to the content of the write command CMD1 (arrow 232). The controller 102 temporarily stores the write data in the volatile memory 106 (arrow 234), and then programs the write data into the non-volatile memory 108 (arrow 236).

[0034] When the write data has been successfully programmed into the non-volatile memory 108, the controller 102 writes the command completion information corresponding to the write command CMD1 into the completion queue 1062 (arrow 238), and deletes the write command CMD1 from the commit queue 1061 (arrow 240). Figure 3B The controller 102 then writes the command completion information corresponding to the write command CMD1 into the completion queue 2042 of the host 20 (arrow 242), and deletes the entry corresponding to the write command CMD1 in the commit queue 2041 of the host 20 (arrow 244).

[0035] In some embodiments, the controller 102 may set the phase tag corresponding to the instruction completion information corresponding to the write instruction CMD1 in the completion queue 2042 to 1, and send an interrupt signal to the processor 202 to notify the processor 202 that new instruction completion information has been submitted to the completion queue 2042. When the processor 202 receives the interrupt signal, the processor 202 may use the set phase tag to check the new item in the completion queue 2042. When the new item reports that the instruction is executed successfully, the processor 202 will end the related events of the write instruction CMD1 and record that the data of the write instruction CMD1 has been successfully written to the solid-state storage device 10.

[0036] It should be noted that in the embodiment of the present invention, after the controller 102 retrieves the write command CMD1 from the commit queue 2041, it does not execute the retrieved write command CMD1, but waits for the next access command. Figure 2 In the embodiment, during the period from when the controller 102 records the captured write command CMD1 in the commit queue 1061 of the volatile memory 106 (arrow 228) to when the controller 102 captures the write command CMD1 from the commit queue 1061 (arrow 230), the controller 102 may process at least one other access command.

[0037] Specifically, for the solid-state storage device 10, the write command from the host 20 may have a long response time, so the controller 102 may keep the write command CMD1 in a pending state after capturing the write command CMD1 from the commit queue 2041, and wait for the next access command. This method can help the solid-state storage device 10 to more efficiently process the subsequent read commands and write commands issued by the host 20. For details, please refer to Figure 5 and Figure 6 Embodiment of the invention.

[0038] Figure 5 FIG. 4 is a flow chart of related operations of a read instruction according to another embodiment of the present invention. Figures 4A to 4C According to the present invention Figure 5 Schematic diagram of the submission queue 1061 and the completion queue 1062 of the solid-state storage device 10 in an embodiment of the present invention.

[0039] In some embodiments, when the host 20 wants to store the first data to the solid-state storage device 10, the processor 202 stores the first data corresponding to a write command CMD1 to the data buffer 2043 (arrow 522), and writes the write command CMD1 to the commit queue 2041 (arrow 524). For example, the write command CMD1 is, for example, to write a first data of 16K bytes to the logical address 0x2000. The content of the write command CMD1 includes the logical address 0x2000 of the first data, and the size of the first data, 16K bytes.

[0040] In some embodiments, the controller 102 of the solid-state storage device 10 may periodically check whether there is a new access command in the commit queue 2041. The controller 102 may fetch the write command CMD1 from the commit queue 2041 (arrow 526), ​​and record the fetched write command CMD1 in the commit queue 1061 of the volatile memory 106 (arrow 528). Figure 4A shown.

[0041] As mentioned above, after the controller 102 retrieves the write command CMD1 from the commit queue 2041, it does not execute the retrieved write command CMD1, which means that the controller 102 does not immediately write the first data corresponding to the write command CMD1 to the non-volatile memory 108. At this time, the write command CMD1 is in a pending status, and the controller 102 waits for the next access command. At this time, the write command CMD1 remains recorded in the commit queue 1061, and the first data corresponding to the write command CMD1 remains stored in the data buffer 2043 on the host 20 side.

[0042] Assume that the host 20 subsequently issues a read command CMD2 to read the first data from the solid-state storage device 10, that is, the read command CMD2 indicates that the first data located at the logical address 0x2000 is to be read. The content of the read command CMD2 includes the logical address 0x2000 of the first data to be read. At this time, the processor 202 writes the read command CMD2 to the commit queue 2041 (arrow 532).

[0043] Next, the controller 102 fetches the read command CMD2 from the commit queue 2041 (arrow 534), and records the fetched read command CMD2 in the commit queue 1061 of the volatile memory 106 (arrow 536). Figure 4B shown.

[0044] In the embodiment of the present invention, when the controller 102 receives a read instruction from the host 20, the controller 102 first determines whether there is a write instruction with the same logical address as the read instruction in the commit queue 1061, and determines the processing method of the read instruction according to the determination result.

[0045] Figure 5 and FIG. 4A to FIG. 4C 1 is a schematic diagram showing how the read instruction is processed when a write instruction having the same logical address as the read instruction exists in the commit queue 1061. The controller 102 reads the read instruction CMD2 from the commit queue 1061 (arrow 538), and determines that a write instruction CMD1 having the same logical address 0x2000 as the read instruction CMD2 exists in the commit queue 1061. Figure 4B As shown. Next, the controller 102 reads the first data corresponding to the write command CMD1 temporarily stored in the data buffer 2043 from the system memory 204 according to the write command CMD1 (arrow 540), and temporarily stores the read first data in the volatile memory 106 (arrow 542). Next, the controller 102 reads the first data from the volatile memory 106 again (arrow 544), and transmits the read first data to the host 10, so that the first data is stored in the data buffer 2043 of the system memory 204 (arrow 546).

[0046] For example, although the controller 102 executes the read instruction CMD2, because the logical address of the read instruction CMD2 is the same as the logical address of the write instruction CMD1 previously recorded in the submission queue 1061, the controller 102 reads the first data corresponding to the write instruction CMD1 from the data buffer 2043 of the host 20 based on the physical space configuration information of the write instruction CMD1, wherein the physical space configuration information refers to the physical storage address information of the first data in the data buffer 2043 of the host 20, which can be defined by the physical region page (PRP) information of the NVME standard or the scatter / gather list (GSL), but the present invention is not limited to this.

[0047] When the controller 102 successfully transmits the first data to the host 20 and stores it in the data buffer 2043 of the system memory 204, the controller 102 records the command completion information corresponding to the read command CMD2 (or the read command CMD2) to the completion queue 1062 (arrow 548), and deletes the read command CMD2 from the submission queue 1061 (arrow 550). Figure 4C The controller 102 then writes the command completion information corresponding to the read command CMD2 into the completion queue 2042 of the host 20 (arrow 552), and deletes the entry corresponding to the read command CMD2 in the submission queue 2041 of the host 20 (arrow 554).

[0048] In some embodiments, the controller 102 may set the phase tag corresponding to the instruction completion information of the read instruction CMD2 in the completion queue 2042 to 1, and send an interrupt signal to the processor 202 to notify the processor 202 that new instruction completion information is submitted to the completion queue 2042. When the processor 202 receives the interrupt signal, the processor 202 may use the phase tag to check the newly submitted items in the completion queue 2042. When the newly submitted item indicates that the read instruction CMD2 is executed successfully, the processor 202 will end the related events of the read instruction CMD2, and record that the first data of the read instruction CMD2 has been successfully written to the data buffer 2043 of the system memory 204.

[0049] It should be noted that if FIG. 4A to FIG. 4C As shown, during the execution of the above-mentioned read command CMD2, the write command CMD1 still exists in the commit queue 1061 of the solid-state storage device 10, which means that the controller 102 has not programmed the first data corresponding to the write command CMD1 into the non-volatile memory 108. In other words, the write command CMD1 is still in a pending status, and the first data corresponding to the write command CMD1 is still stored in the data buffer 2043 of the host 20.

[0050] Figure 6 FIG. 4 is a flow chart of related operations of a write instruction according to another embodiment of the present invention. Figures 9A to 9C According to the present invention Figure 6 Schematic diagram of the submission queue 1061 and the completion queue 1062 of the solid-state storage device 10 in an embodiment of the present invention.

[0051] In some embodiments, when the host 20 wants to store the first data to the solid-state storage device 10, the processor 202 stores the first data corresponding to a write command CMD1 to the data buffer 2043 (arrow 622), and writes the write command CMD1 to the commit queue 2041 (arrow 624). For example, the write command CMD1 is, for example, to write a first data of 16K bytes to the logical address 0x2000. The content of the write command CMD1 includes the logical address 0x2000 of the first data, and the size of the first data, 16K bytes.

[0052] In some embodiments, the controller 102 of the solid-state storage device 10 may periodically check whether there is a new access command in the commit queue 2041. The controller 102 may fetch the write command CMD1 from the commit queue 2041 (arrow 626), and record the fetched write command CMD1 in the commit queue 1061 of the volatile memory 106 (arrow 628). Fig. 9A shown.

[0053] Similarly, after the controller 102 retrieves the write command CMD1 from the commit queue 2041, it does not execute the retrieved write command CMD1, which means that the controller 102 does not immediately write the first data corresponding to the write command CMD1 to the non-volatile memory 108. At this time, the write command CMD1 is in a pending status, and the controller 102 waits for the next access command. At this time, the write command CMD1 remains recorded in the commit queue 1061, and the first data corresponding to the write command CMD1 remains stored in the data buffer 2043 of the host 20.

[0054] Assume that the host 20 subsequently issues a write instruction CMD3 to write the second data to the solid-state storage device 10, wherein the write instruction CMD3 indicates that the second data is to be written to the location at the logical address 0x2000. The content of the write instruction CMD3 includes the logical address 0x2000 of the second data to be written. At this time, the processor 202 stores the second data corresponding to the write instruction CMD3 to the data buffer 2043 (arrow 630), and writes the write instruction CMD3 to the commit queue 2041 (arrow 632). In some embodiments, the physical space configuration information corresponding to the write instructions CMD1 and CMD2 is not the same, that is, the first data corresponding to the write instruction CMD1 and the second data corresponding to the write instruction CMD2 are stored in different physical address spaces in the data buffer 2043.

[0055] Next, the controller 102 of the solid-state storage device 10 may fetch the write command CMD3 from the commit queue 2041 (arrow 634), and record the fetched write command CMD3 in the commit queue 1061 of the volatile memory 106 (arrow 636). Fig. 9B shown.

[0056] In the embodiment of the present invention, when the controller 102 receives a write instruction from the host 20, the controller 102 first determines whether there is a previous write instruction with the same logical address as the write instruction in the commit queue 1061, and determines how to process the write instruction based on the determination result.

[0057] Figure 6 and 9A to 9C 6 is a schematic diagram showing how the write command is processed when there is a previous write command with the same logical address as the write command in the submit queue 1061. When the controller 102 determines that the logical address of the write command CMD3 issued by the host 20 is the same as the logical address of the write command CMD1, the controller 102 deletes the write command CMD1 from the submit queue 1061 (arrow 638) and retains the write command CMD3, and records the command completion information of the write command CMD1 (or the write command CMD1) to the completion queue 1062 (arrow 640). Fig. 9C The controller 102 then writes the command completion information of the write command CMD1 into the completion queue 2042 of the host 20 (arrow 642), and deletes the entry corresponding to the write command CMD1 in the commit queue 2041 of the host 20 (arrow 644).

[0058] For example, the controller 102 may set the phase tag corresponding to the instruction completion information of the write instruction CMD1 in the completion queue 2042 to 1, and send an interrupt signal to the processor 202 to notify the processor 202 that new instruction completion information is submitted to the completion queue 2042. Therefore, when the processor 202 receives the interrupt signal, the processor 202 can use the phase tag to check the newly submitted items in the completion queue 2042. When the newly submitted item reports that the instruction is executed successfully, the processor 202 will end the related events of the write instruction CMD1 and record that the first data of the write instruction CMD1 has been successfully written to the solid-state storage device 10.

[0059] It should be noted that if Fig. 9CAs shown, although the write command CMD3 has replaced the original write command CMD1 in the commit queue 1062 of the solid-state storage device 10, the controller 102 will not execute the write command CMD3, that is, the controller 102 does not program the second data corresponding to the write command CMD3 into the non-volatile memory 108. In other words, the second data corresponding to the write command CMD3 is still stored in the data buffer 2043 of the host 20, and the write command CMD3 is in a pending state, while the controller 102 waits for the next access command.

[0060] In addition, in the above embodiment, from the time when the controller 102 fetches the write command CMD1 from the commit queue 2041 (arrow 626) to the time when the controller 102 records the command completion information of the write command CMD1 to the completion queue 1062 (arrow 640), that is, from the time when the solid-state storage device 10 receives the write command CMD1 to the time when the host 20 responds that the write command CMD1 has been completed, the first data corresponding to the write command CMD1 has never been programmed into the non-volatile memory 108. In this way, the number of times the non-volatile memory 108 is accessed can be reduced, thereby increasing the service life of the non-volatile memory 108.

[0061] Figure 7 FIG. 7 is a flow chart of a data access method 700 for a solid-state storage device according to an embodiment of the present invention.

[0062] In step 710, the controller 102 of the solid-state storage device 10 obtains an access instruction from the host 20 and records the access instruction in the commit queue 1061 of the solid-state storage device 10. The access instruction includes a read instruction and a write instruction. Then, in step 720, the controller 102 determines whether there is a write instruction with the same logical address as the access instruction in the commit queue 1061 of the solid-state storage device 10. Finally, in step 730, the processing method of the access instruction is determined according to the determination result.

[0063] Fig. 8A According to the present invention Figure 7 Flow chart of a data access method 800A for a read instruction in an embodiment.

[0064] In step 802 , the controller 102 of the solid-state storage device 10 obtains a read command from the host 20 , and records the read command in the commit queue 1061 of the solid-state storage device 10 .

[0065] In step 804, the controller 102 determines whether there is a write instruction with the same logical address as the read instruction in the commit queue 1061. If the controller 102 determines that there is a write instruction with the same logical address as the read instruction in the commit queue 1061, step 806 is executed. If the controller 102 determines that there is no write instruction with the same logical address as the read instruction in the commit queue 1061, step 808 is executed. For example, the controller 102 may search for the logical addresses of all items corresponding to the write instructions previously stored in the commit queue 1061, and determine whether there is a write instruction with the same logical address as the read instruction in the items.

[0066] As described above, in the embodiment of the present invention, after the controller 102 of the solid-state storage device 10 captures the write instruction from the host 20, it does not execute the captured write instruction in succession, but waits for the next access instruction. At this time, the write instruction will be in a pending state and remain recorded in the submission queue 1061 of the solid-state storage device 10, and the first data corresponding to the write instruction remains stored in the data buffer 2043 of the host 20. Therefore, when the controller 102 of the solid-state storage device 10 subsequently receives a read instruction, the write instruction with the same logical address as the read instruction may still remain recorded in the submission queue 1061 of the solid-state storage device 10 and be in a pending state.

[0067] In step 806 , the controller 102 obtains first data corresponding to the write command from the system memory 204 of the host 20 , and stores the first data in the volatile memory 106 of the solid-state storage device 10 .

[0068] In step 808, the controller 102 reads the second data corresponding to the read command from the non-volatile memory 108 and stores the second data in the volatile memory 106. For example, because the logical addresses of one or more write commands previously written into the commit queue 1061 are different from the logical address corresponding to the read command, it means that the second data corresponding to the logical address of the read command has been programmed into the non-volatile memory 108, and the second data needs to be read from the non-volatile memory 108 according to the read command.

[0069] In step 810, the controller 102 responds to the read command to transmit the first data or the second data to the host 20. For example, the controller 102 determines where to obtain the data required by the read command based on the result of determining whether there is a write command with the same logical address as the read command in the commit queue 1061, and returns the first data or the second data corresponding to the read command to the host 20.

[0070] In step 812, the controller 102 records the command completion information of the read command in the completion queue 1062, and deletes the read command from the commit queue 1061. For example, when the controller 102 successfully transmits the first data or the second data corresponding to the read command to the host 20, the controller 102 records the command completion information corresponding to the read command in the completion queue 1061, and deletes the read command from the commit queue 1061. In addition, the controller 102 may also write the command completion information of the read command into the completion queue 2042 of the host 20, and delete the read command from the commit queue 2041 of the host 20.

[0071] In step 814, the controller 102 waits for the next access command. In some embodiments, the access command may be a write command or a read command, and each time the controller 102 obtains a new access command from the commit queue 2041 of the host 20, the controller 102 searches the commit queue 1061 of the solid-state storage device 10 for a previous write command with the same logical address.

[0072] Figure 8B According to the present invention Figure 7 Flow chart of a data access method 800B for a write instruction in an embodiment.

[0073] In step 850 , the controller 102 of the solid-state storage device 10 obtains a first write command from the host 20 , and records the first write command in the commit queue 1061 of the solid-state storage device 10 .

[0074] In step 852, the controller 102 determines whether there is a second write instruction with the same logical address as the first write instruction in the commit queue 1061. If the controller 102 determines that there is a second write instruction with the same logical address as the first write instruction in the commit queue 1061, step 854 is executed. If the controller 102 determines that there is no second write instruction with the same logical address as the first write instruction in the commit queue 1061, step 856 is executed. For example, the controller 102 may search for the logical addresses of all items corresponding to the write instructions previously stored in the commit queue 1061, and determine whether there is a second write instruction with the same logical address as the first write instruction in the items.

[0075] In step 854, the controller 102 records the instruction completion information of the second write instruction to the completion queue 1062, and deletes the second write instruction from the commit queue 1061. For example, when the controller 102 determines that there is a second write instruction with the same logical address as the first write instruction in the commit queue 1061, the controller 102 deletes the second write instruction from the commit queue 1061, and records the instruction completion information of the second write instruction to the completion queue 1061. In addition, the controller 102 may also write the instruction completion information of the second write instruction to the completion queue 2042 of the host 20, and delete the second write instruction from the commit queue 2041 of the host 20.

[0076] In step 856, the controller 102 waits for the next access command. In some embodiments, the access command may be a write command or a read command, and each time the controller 102 obtains a new access command from the commit queue 2041 of the host 20, the controller 102 searches the commit queue 1061 of the solid-state storage device 10 for a previous write command with the same logical address.

[0077] In some embodiments, when the memory space usage of the non-volatile memory 108 exceeds a predetermined threshold (eg, above 90%), the controller 102 activates Figure 7 8, thereby reducing the memory space usage of the volatile memory 106 and reducing the number of accesses to the non-volatile memory 108. In some embodiments, the solid-state storage device 10 may also Figure 7 The process of FIG. 8 is designed as a basic processing flow of access instructions, rather than being activated only under specific conditions.

[0078] In the embodiment of the present invention, when the access instruction received by the solid-state storage device 10 is a write instruction, the write instruction is not executed continuously, that is, the data corresponding to the write instruction is not programmed into the non-volatile memory 108, but the write instruction is kept in a pending state and waits for the next access instruction. In addition, according to whether the next access instruction is a read instruction or a write instruction, the controller 102 of the solid-state storage device 10 can Fig. 8A or Figure 8B The process is used to process the corresponding read instruction or write instruction.

[0079] According to the embodiment of the present invention, the number of read, write and erase operations of the non-volatile memory 108 can be greatly reduced, thereby increasing the service life of the non-volatile memory 108. In addition, because the number of write operations of the non-volatile memory 108 is greatly reduced, the number of invalid data in the data blocks in the non-volatile memory 108 can be reduced, so the controller 102 can reduce the frequency of garbage collection operations on the non-volatile memory 108, thereby avoiding the situation where the internal bandwidth of the solid-state storage device 10 is occupied by the garbage collection operations. Furthermore, according to the embodiment of the present invention, the controller 102 does not program the data of the write command into the non-volatile memory 108, but allows the data of the write command to be temporarily stored in the system memory 204 of the host 20, so that the memory usage space of the volatile memory 106 in the solid-state storage device 10 can be reduced, thereby improving the processing performance of the solid-state storage device 10.

[0080] Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

[0081] Explanation of symbols

[0082] 1: Computer System

[0083] 10: Solid-state storage device

[0084] 11: Bus

[0085] 20: Host

[0086] 102: Controller

[0087] 106: Volatile memory

[0088] 108: Non-volatile memory

[0089] 202: Processor

[0090] 204: System memory

[0091] 1061, 2041: Submit queue

[0092] 1062, 2042: Complete the queue

[0093] 2043: Data buffer

[0094] 222-244, 522-554, 622-644: Arrow

[0095] 800A, 800B: Method

[0096] 710-730, 802-814, 850-856: Steps

[0097] CMD1, CMD2, CMD3: access instructions

Claims

1. A solid-state storage device configured to be electrically connected to a host, the solid-state storage device comprising: Controller; a non-volatile memory electrically connected to the controller; as well as a volatile memory electrically connected to the controller, wherein the volatile memory includes a commit queue and a completion queue; wherein the controller is configured to obtain an access instruction from the host and record the access instruction in the commit queue, wherein the access instruction corresponds to a first logical address; The controller is configured to determine whether there is a first write instruction in the commit queue to generate a determination result, wherein the first write instruction corresponds to a second logical address, and the second logical address is the same as the first logical address; The controller is configured to determine a processing method of the access instruction according to the determination result.

2. The solid-state storage device according to claim 1, wherein: When the access instruction is a read instruction, and the controller determines that the commit queue has the first write instruction, the processing method includes: The controller is configured to obtain first data associated with the first write command from a system memory of the host according to the first write command, and store the first data in the volatile memory; The controller is configured to read the first data from the volatile memory and provide the first data to the host; and The controller is configured to record the read command in the completion queue and delete the read command from the commit queue.

3. The solid-state storage device according to claim 1, wherein: When the access instruction is a read instruction, and the controller determines that the commit queue does not have the first write instruction, the processing method includes: The controller is configured to obtain second data associated with the read command from the non-volatile memory according to the read command, and write the second data into the volatile memory; The controller is configured to read the second data from the volatile memory and provide the second data to the host; and The controller is configured to record the read command in the completion queue and delete the read command from the commit queue.

4. The solid-state storage device according to claim 1, wherein: When the access instruction is a second write instruction, and the controller determines that the commit queue has the first write instruction, the processing method includes: The controller is configured to record the first write command in the completion queue and delete the first write command from the commit queue.

5. The solid-state storage device according to claim 4, wherein: The second write command is in a pending state, and the controller does not program write data corresponding to the second write command into the non-volatile memory.

6. The solid-state storage device according to claim 1, wherein: When the access instruction is a second write instruction and the controller determines that the first write instruction does not exist in the commit queue, the processing method includes: the controller is configured to wait for the next access instruction and keep the second write instruction in a pending state.

7. A data access method for a solid-state storage device, wherein the solid-state storage device is electrically connected to a host and comprises a controller, a volatile memory and a non-volatile memory, the method comprising: Obtaining an access instruction from the host using the controller, and recording the access instruction in a commit queue of the volatile memory, wherein the access instruction corresponds to a first logical address; Using the controller to determine whether there is a first write instruction in the commit queue to generate a determination result, wherein the first write instruction corresponds to a second logical address, and the second logical address is the same as the first logical address; as well as The controller is used to determine a processing method of the access instruction according to the determination result.

8. The method according to claim 7, wherein: When the access instruction is a read instruction, and the controller determines that the commit queue has the first write instruction, the processing method includes: Using the controller to obtain first data related to the first write instruction from the system memory of the host according to the first write instruction, and storing the first data in the volatile memory; reading the first data from the volatile memory using the controller and providing the first data to the host; and The controller is used to record the read command in the completion queue of the volatile memory, and delete the read command from the commit queue.

9. The method according to claim 7, wherein: When the access instruction is a read instruction, and the controller determines that the commit queue does not have the first write instruction, the processing method includes: Using the controller to obtain second data related to the read instruction from the non-volatile memory according to the read instruction, and storing the second data in the volatile memory; reading the second data from the volatile memory using the controller, and providing the second data to the host; and The controller is used to record the read command in the completion queue of the volatile memory, and delete the read command from the commit queue.

10. The method according to claim 7, wherein: When the access instruction is a second write instruction, and the controller determines that the first write instruction exists in the commit queue, the processing method includes: using the controller to record the first write instruction in the completion queue, and deleting the first write instruction from the commit queue.

11. The method according to claim 10, wherein: The second write command is in a pending state, and the controller does not program write data corresponding to the second write command into the non-volatile memory.

12. The method according to claim 7, wherein: When the access instruction is a second write instruction, and the controller determines that the first write instruction does not exist in the commit queue, the processing method includes: the controller waits for the next access instruction and keeps the second write instruction in a pending state.

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