Storage system, memory and stripe-based data caching method

Abstract

The invention discloses a storage system, a memory and a stripe-based data caching method, and belongs to the technical field of storage. According to the memory, the buffer is arranged in the tube core, and the check data between the currently written data and the written data of the stripe is cached to the buffer under the condition that the data is written into the data page of the stripe, so that a storage space does not need to be allocated to the check page of the stripe from a buffer space of a controller; therefore, a larger space can be allocated to the data pages in the cache space, so that the random read-write performance of the memory is improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage system, a memory, and a stripe-based data caching method. Background Art

[0002] With the development of storage technology, a storage device includes a controller and a memory. The controller adopts a redundant array of independent disks (RAID) strategy to stripe the physical pages in the memory. Specifically, each stripe includes multiple physical pages in the memory, wherein the physical page used to store user data (i.e., data stored by the user) is called a data page, and the physical page used to store verification data is called a verification page.

[0003] Part of the total cache space in the controller is allocated to the check page of the stripe, and the other part is allocated to the data page of the stripe. The cache space allocated to the check page is used to cache the check data to be stored in the check page of the stripe, and the cache space allocated to the data page is used to cache the information involved in the process of reading and writing the data page (such as user data or address mapping table, etc.). As the number of stripes opened in the memory increases, the cache space allocated to the check page also increases accordingly. However, the total cache space size of the controller is limited, which will make the cache space allocated to the data page smaller, resulting in a decrease in the random read and write performance of the memory. Summary of the invention

[0004] The embodiments of the present application provide a storage system, a memory, and a stripe-based data caching method, which can improve the random read and write performance of the memory. The technical solution is as follows:

[0005] In a first aspect, a storage system is provided, the storage system comprising a memory and a controller, the memory comprising a plurality of dies, each of the dies comprising a plurality of physical pages, the physical pages in the plurality of dies forming a plurality of stripes, at least one of the plurality of dies further comprising a buffer, and the memory being coupled to the controller;

[0006] A controller is configured to send a first write instruction to the memory, wherein the first write instruction indicates writing first data to a first physical page of a first stripe among the plurality of stripes;

[0007] The memory is configured to cache first check data between first data and written data of a first stripe through a first buffer in at least one die in response to a first write instruction, and write the first data to a first physical page.

[0008] In a possible implementation, the first die where the first buffer is located further includes an XOR circuit, which is coupled to the first buffer; and the memory is further configured as follows:

[0009] Through the XOR circuit, an XOR operation is performed on the first data and the second verification data in the first buffer to obtain the first verification data, which is output to the first buffer. The second verification data is the verification data between the written data.

[0010] In a possible implementation, each die includes multiple planes, each plane includes multiple physical pages, and the first stripe includes multiple physical pages in one plane in each die.

[0011] In a possible implementation, the first buffer is located in the die where the check page of the first stripe is located.

[0012] In a possible implementation, each die includes multiple planes, each plane includes multiple physical pages, and the first stripe includes multiple physical pages in each plane in each die.

[0013] In a possible implementation, the first buffer and the first physical page are both located in a first die of the at least one die;

[0014] The controller is further configured to send a second write instruction to the memory, the second write instruction instructing to write second data to a second physical page of the first stripe in the first die;

[0015] The memory is further configured to cache third verification data between the second data and the first verification data through the first buffer in response to the second write instruction, and write the second data to the second physical page.

[0016] In a possible implementation, each die includes a buffer, and the controller is further configured to:

[0017] If the first physical page is the last data page of the first stripe in the first tube core, and the first physical page is not the last data page of the first stripe, the control memory writes the first verification data in the first buffer into the second buffer of the second tube core, and the second tube core is the tube core where the next data page of the first physical page on the first stripe is located.

[0018] In one possible implementation, the controller is further configured to send a read instruction to the memory if the first physical page is the last data page of the first stripe in the first die, and the first physical page is not the last data page of the first stripe, the read instruction instructing to read data cached in the first buffer;

[0019] The memory is further configured to read the first verification data from the first buffer in response to the read instruction and send the first verification data to the controller;

[0020] The controller is further configured to send a cache instruction to the memory based on the first verification data, wherein the cache instruction instructs to cache the first verification data in the second cache;

[0021] The memory is further configured to cache the first verification data in the second cache in response to the cache instruction.

[0022] In a possible implementation, each die includes an XOR circuit and a buffer, and the XOR circuit of each die is coupled to the buffer of the die; the controller is further configured to:

[0023] In the case that the data in the first physical page is abnormal, the memory is controlled to read the data in the third physical page of the first stripe in each tube core to the XOR circuit of each tube core respectively, and the XOR circuit performs an XOR operation on the data in the third physical page of the first stripe in the tube core to obtain target intermediate verification data, and outputs the target intermediate verification data to the buffer in the tube core, and the third physical page is a physical page on which no data abnormality occurs on the first stripe;

[0024] The memory is controlled to read target intermediate verification data from buffers in the plurality of dies respectively, and the first data is reconstructed based on the plurality of target intermediate verification data read.

[0025] In a possible implementation, the controller is further configured to:

[0026] If the first physical page is the last data page of the first stripe, the memory is controlled to write the first check data in the first buffer into the check page of the stripe.

[0027] In a possible implementation, the controller is further configured to send a read instruction to the memory if the first physical page is the last data page of the first stripe, the read instruction instructing to read the data cached in the first buffer;

[0028] The memory is further configured to read the first verification data from the first buffer in response to the read instruction and send the first verification data to the controller;

[0029] The controller is further configured to send a third write instruction to the memory based on the first verification data, wherein the third write instruction instructs writing the first verification data to the verification page;

[0030] The memory is further configured to write first verification data to the verification page in response to a third write instruction.

[0031] In one possible implementation, a physical page includes a storage unit, which is used to store N bits of data. Each of the at least one die includes N buffers, each buffer corresponds to one bit of the N bits, and each buffer is used to cache the check data of the data page of the stripe on the corresponding bit, where N is an integer greater than or equal to 1.

[0032] In a possible implementation, the buffer is a latch or a static random access memory.

[0033] In a second aspect, a memory is provided, the memory comprising a plurality of dies, each of the dies comprising a plurality of physical pages, the physical pages in the plurality of dies forming a plurality of stripes, at least one of the plurality of dies further comprising a buffer, the memory being configured as follows:

[0034] receiving a first write instruction, the first write instruction instructing to write first data to a first physical page of a first stripe among the plurality of stripes;

[0035] In response to a first write instruction, first check data between the first data and the written data of the first stripe is cached through a first buffer in at least one die, and the first data is written to the first physical page.

[0036] In a possible implementation, the first die where the first buffer is located further includes an XOR circuit, which is coupled to the first buffer; and the memory is further configured as follows:

[0037] Through the XOR circuit, an XOR operation is performed on the first data and the second verification data in the first buffer to obtain the first verification data, which is output to the first buffer. The second verification data is the verification data between the written data.

[0038] In a possible implementation, each die includes multiple planes, each plane includes multiple physical pages, and the first stripe includes multiple physical pages in one plane in each die.

[0039] In a possible implementation, the first buffer is located in the die where the check page of the first stripe is located.

[0040] In a possible implementation, each die includes multiple planes, each plane includes multiple physical pages, and the first stripe includes multiple physical pages in each plane in each die.

[0041] In a possible implementation, the first buffer and the first physical page are both located in a first die in the at least one die; and the memory is further configured as:

[0042] receiving a second write instruction, the second write instruction instructing to write second data to a second physical page of the first stripe in the first die;

[0043] In response to the second write instruction, the third verification data between the second data and the first verification data is cached through the first buffer, and the second data is written to the second physical page.

[0044] In a possible implementation, the memory is further configured as:

[0045] receiving a read instruction from a controller, the read instruction instructing to read data cached in the first buffer;

[0046] In response to the read instruction, read the first verification data from the first buffer, and send the first verification data to the controller;

[0047] Receive a cache instruction from a controller, the cache instruction instructing to cache the first verification data in a second cache of a second die, where the second die is a die where a next data page of the first physical page on the first stripe is located;

[0048] In response to the cache instruction, the first verification data is cached in the second cache.

[0049] In a possible implementation, each die includes an XOR circuit and a buffer, and the XOR circuit of each die is coupled to the buffer of the die; the memory is configured as:

[0050] In the event that a fault occurs in the first physical page, the data stored in the third physical page on the third stripe in each tube core is read into the XOR circuit of each tube core, and the XOR circuit performs an XOR operation on the data stored in each third physical page on the third stripe in the tube core to obtain the target intermediate check data of the first stripe, and outputs the target intermediate check data to the connected buffer. The third physical page is a physical page on the first stripe where no data abnormality occurs.

[0051] In a possible implementation, the memory is further configured as:

[0052] receiving a read instruction from a controller, the read instruction instructing to read data cached in the first buffer;

[0053] In response to the read instruction, first verification data is read from the first buffer and the first verification data is sent to the controller.

[0054] In one possible implementation, a physical page includes a storage unit, which is used to store N bits of data. Each of the at least one die includes N buffers, each buffer corresponds to one bit of the N bits, and each buffer is used to cache the check data of the data page of the stripe on the corresponding bit, where N is an integer greater than or equal to 1.

[0055] In a possible implementation, the buffer is a latch or a static random access memory.

[0056] In a third aspect, a stripe-based data caching method is provided, the method being applied to a memory and a memory controller, the method comprising:

[0057] The controller sends a first write instruction to the memory, the first write instruction instructing to write first data to a first physical page of a first stripe, the first stripe being provided by a plurality of dies in the memory;

[0058] In response to the first write instruction, the memory caches the first check data between the first data and the written data of the first stripe through a first buffer in at least one die, and writes the first data to the first physical page.

[0059] In a possible implementation, caching, by a first buffer in at least one die, first check data between the first data and the written data of the first stripe includes:

[0060] An XOR circuit connected to the first buffer performs an XOR operation on the first data and the second verification data in the first buffer to obtain first verification data, which is output to the first buffer. The second verification data is verification data between the written data.

[0061] In a possible implementation, the method further includes:

[0062] The controller sends a second write instruction to the memory, where the second write instruction instructs writing second data to a second physical page of the first stripe in the first die;

[0063] In response to the second write instruction, the memory caches the third verification data between the second data and the first verification data through the first buffer, and writes the second data to the second physical page.

[0064] In a possible implementation, the method further includes:

[0065] If the first physical page is the last data page of the first stripe in the first tube core, and the first physical page is not the last data page of the first stripe, the controller controls the memory to write the first verification data in the first buffer into the second buffer of the second tube core, the first tube core is the tube core where the first buffer and the first physical page are located, and the second tube core is the tube core where the next data page of the first physical page on the first stripe is located.

[0066] In a possible implementation, the controller controls the memory to write the first verification data in the first buffer into the second buffer of the second die, including:

[0067] The controller sends a read instruction to the memory, the read instruction instructing to read the data cached in the first buffer;

[0068] The memory reads the first verification data from the first buffer in response to the read instruction, and sends the first verification data to the controller;

[0069] The controller sends a cache instruction to the memory based on the first verification data, wherein the cache instruction instructs to cache the first verification data in the second cache;

[0070] The memory caches the first verification data in the second cache in response to the cache instruction.

[0071] In a possible implementation, the method further includes:

[0072] In the case that the data in the first physical page is abnormal, the controller controls the memory to read the data in the third physical page of the first stripe in each tube core to the XOR circuit of each tube core respectively, and the XOR circuit performs an XOR operation on the data in the third physical page of the first stripe in the tube core to obtain target intermediate verification data, and outputs the target intermediate verification data to the buffer in the tube core, and the third physical page is a physical page on which no data abnormality occurs on the first stripe;

[0073] The controller controls the memory to read target intermediate verification data from the buffers in the plurality of dies respectively, and reconstructs the first data based on the plurality of read target intermediate verification data.

[0074] In a possible implementation, the method further includes: if the first physical page is the last data page of the first stripe, the controller controls the memory to write the first check data in the first buffer into the check page of the stripe.

[0075] In a possible implementation, the controller controls the memory to write the first check data in the first buffer into the check page of the stripe, including:

[0076] The controller sends a read instruction to the memory, the read instruction instructing to read the data cached in the first buffer;

[0077] The memory reads the first verification data from the first buffer in response to the read instruction, and sends the first verification data to the controller;

[0078] The controller sends a third write instruction to the memory based on the first verification data, wherein the third write instruction instructs writing the first verification data to the verification page;

[0079] The memory writes the first verification data into the verification page in response to the third write instruction.

[0080] In a fourth aspect, a computer-readable storage medium is provided, in which at least one program code is stored. The program code is read by a processor in a controller of the memory to execute the operations performed by the controller in the method provided in the second aspect above, or the program code is read by the memory to execute the operations performed by the memory in the method provided in the second aspect above.

[0081] The technical solution provided by the embodiment of the present application is to set a cache in the tube core of the memory. When writing data to the data page of the stripe, the verification data between the currently written data and the data already written to the stripe is cached in the cache, thereby eliminating the need to allocate storage space for the verification page of the stripe from the cache space of the controller, so that more space in the cache space can be allocated to the data page, thereby improving the random read and write performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 is a schematic diagram of a storage system according to an exemplary embodiment;

[0083] Figure 2 is a schematic diagram of a memory card according to an exemplary embodiment;

[0084] Figure 3 is a schematic diagram of a solid state drive according to an exemplary embodiment;

[0085] Figure 4 is a schematic diagram of a memory according to an exemplary embodiment;

[0086] Figure 5 is a schematic diagram of a tube die according to an exemplary embodiment;

[0087] Figure 6 is a schematic diagram of a plane according to an exemplary embodiment;

[0088] Figure 7 is a schematic diagram showing a DIE RAID policy striping configuration according to an exemplary embodiment;

[0089] Figure 8 is a schematic diagram of a Plane RAID policy striping configuration according to an exemplary embodiment;

[0090] Fig. 9 is a schematic diagram of a peripheral circuit according to an exemplary embodiment;

[0091] Fig.10 is a schematic diagram of a controller according to an exemplary embodiment;

[0092] Fig.11is a flow chart showing a stripe-based data caching method according to an exemplary embodiment;

[0093] Fig.12 is a schematic diagram of a DIE RAIN data writing workflow according to an exemplary embodiment;

[0094] Fig.13 is a schematic diagram of another DIE RAIN data writing workflow according to an exemplary embodiment;

[0095] Fig.14 is a schematic diagram of another DIE RAIN data writing workflow according to an exemplary embodiment;

[0096] Fig.15 is a schematic diagram of another DIE RAIN data writing workflow according to an exemplary embodiment;

[0097] Fig.16 is a schematic diagram of a DIE RAIN data reading workflow according to an exemplary embodiment;

[0098] Fig.17 is a schematic diagram of another DIE RAIN data reading workflow according to an exemplary embodiment;

[0099] Fig.18 is a schematic diagram of another DIE RAIN data reading workflow according to an exemplary embodiment;

[0100] Fig.19 is a schematic diagram of a data writing workflow of Plane RAIN according to an exemplary embodiment;

[0101] Fig. 20 is a schematic diagram of another data writing workflow of Plane RAIN according to an exemplary embodiment;

[0102] Fig.21 is a schematic diagram of another data writing workflow of Plane RAIN according to an exemplary embodiment;

[0103] Fig. 22 is a schematic diagram of another data writing workflow of Plane RAIN according to an exemplary embodiment;

[0104] Fig.23 is a schematic diagram of another data writing workflow of Plane RAIN according to an exemplary embodiment;

[0105] Fig.24is a schematic diagram of a data reading workflow of Plane RAIN according to an exemplary embodiment;

[0106] Fig.25 It is a schematic diagram of another data reading workflow of Plane RAIN according to an exemplary embodiment. DETAILED DESCRIPTION

[0107] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0108] In this application, the terms "first", "second", etc. are used to distinguish the same or similar items with substantially the same role and function. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.

[0109] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first element can be referred to as a second element, and similarly, a second element can also be referred to as a first element. Both the first element and the second element can be elements, and in some cases, can be separate and different elements.

[0110] Here, at least one means one or more than one, for example, at least one element can be one element, two elements, three elements, or any other integer greater than or equal to one. At least two means two or more than two, for example, at least two elements can be two elements, three elements, or any other integer greater than or equal to two.

[0111] Figure 1 is a schematic diagram of a storage system according to an exemplary embodiment. The storage system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0112] like Figure 1 As shown, the system 100 includes a host 101 and a storage subsystem 102. The host 101 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 101 may be configured to send data to the storage 103. Alternatively, the host 101 may be configured to receive data from the storage 103.

[0113] The storage subsystem 102 includes one or more memories 103 and a controller 104. Each memory 103 is coupled to the storage controller 104. The memory 103 can be any memory disclosed in the present disclosure. Optionally, the memory 103 is a NAND flash memory device. The NAND flash memory device, for example, a three-dimensional (3D) NAND flash memory device.

[0114] According to some embodiments, the controller 104 is also coupled to the host 101. The controller 104 can manage data stored in the memory 10 and communicate with the host 101. The controller 104 may include a host interface (I / F) that is operatively coupled to a processor of the host 101, for example, through a processor bus and is configured to receive instructions from the processor of the host 101. The host interface may include serial attached SCSI (SAS), parallel SCSI, PCI Express (PCIe), NVM Express (NVMe), and Advanced Host Controller Interface (AHCI), etc.

[0115] In one possible implementation, the controller 104 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0116] In one possible implementation, the controller 104 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smart phones, tablets, laptops, etc., as well as enterprise storage arrays.

[0117] The controller 104 may be configured to control operations of the memory 103, such as read, erase, and program operations. The controller 104 may also be configured to manage various functions regarding data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In one possible implementation, the controller 104 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 103.

[0118] The controller 104 may also perform any other suitable functions, for example, formatting the memory 103. The controller 104 may communicate with an external device (e.g., the host 101) according to a specific communication protocol. For example, the controller 104 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0119] The controller 104 and one or more memories 103 may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the storage system 100 may be implemented and packaged into different types of terminal electronic products.

[0120] Combine the following Figure 2 and Figure 3 Two possible storage devices are shown as examples. Figure 2 is a schematic diagram of a memory card according to an exemplary embodiment. Figure 2 As shown, the controller 104 and the single memory 103 may be integrated into the memory card 200. The memory card 200 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 200 may also include a computer that connects the memory card 200 to a host (e.g., Figure 1 A memory card connector 201 coupled to a host 101 in the memory card module.

[0121] Figure 3 is a schematic diagram of a solid state drive according to an exemplary embodiment. Figure 3 As shown, the controller 104 and the plurality of memories 103 may be integrated into a solid state drive (SSD) 300. The solid state drive 300 may also include a computer that connects the solid state drive 300 to a host (eg, Figure 1 The solid-state drive connector 301 is coupled to the host 101 in the memory card. In one possible implementation, the storage capacity and / or operating speed of the solid-state drive 300 is greater than the storage capacity and / or operating speed of the memory card 200.

[0122] Figures 1 to 3The coupling method between the memory 103 and the controller 104 is introduced. Figures 4 to 10 The internal structures of the memory 103 and the controller 104 are introduced as follows.

[0123] Figure 4 is a schematic diagram of a memory according to an exemplary embodiment. Figure 4 As shown, the memory 103 includes a controller interface (I / F) 310, at least one signal bus 320, and at least one die (DIE) 310. The controller interface 310 is internally coupled to each signal bus 320, each signal bus is also coupled to at least one die 310, and different signal buses 320 are coupled to different die 320. The controller interface 310 is configured to: externally couple to the controller 104, receive a control signal sent by the controller 104 to any die 320, and send a control signal to the signal bus 320 coupled to any die 320. The signal bus 320 is configured to: transmit signals between the controller interface 310 and the die 310 coupled thereto, for example, transmit a control signal from the controller interface 310 to the coupled die 310, transmit a response signal of the die 310 to the control signal to the controller interface 310, and the controller interface 310 forwards the response signal to the controller 104. The signal bus includes an enable (CE) signal line and a channel (CH) signal line, wherein the CE signal line is used to transmit an enable signal. For example, if the enable signal transmitted to a certain tube core 320 is at a low level, it indicates that the tube core 302 is enabled (or chip selected), and if the enable signal transmitted to a certain tube core 320 is at a high level, it indicates that the tube core 302 is not enabled (not chip selected), or, if the enable signal transmitted to a certain tube core 320 is at a high level, it indicates that the tube core 302 is enabled, and if the enable signal transmitted to a certain tube core 320 is at a low level, it indicates that the tube core 302 is not enabled. The CH signal line is used to transmit the control signal of the controller and the response signal of the memory. The control signal refers to, for example, a read instruction for reading data, a write instruction for writing data, a delete instruction for deleting data, etc.

[0124] The die 330 is a module in the memory 103 for storing data. Figure 5 is a schematic diagram of a tube die according to an exemplary embodiment, such as Figure 5 As shown, the die 330 includes at least one plane 331 and a peripheral circuit 332, wherein: Figure 5 The tube core 300 is shown to include planes P0 to P3. In other embodiments, the tube core 330 may also include less than 4 or more than 4 planes 331. Here, the embodiment of the present application does not limit the number of planes 331 in the tube core 300.

[0125] Each plane 331 includes at least one cache 400 and a storage array 500 . The storage array 500 is coupled to the peripheral circuit 332 so that the peripheral circuit 332 reads and writes data in the storage array 500 according to a control signal from the controller 104 .

[0126] In the case where the plane 311 includes one cache 400, the cache 400 is coupled to the peripheral circuit 332 and the storage array in the die 331. In the case where the plane 311 includes multiple caches 400, the multiple caches 400 have different cache levels. According to the cache levels, the multiple caches 400 are connected in sequence, wherein the cache 400 with the lowest cache level is coupled to the storage array 500 in the die 311, and the cache 400 with the highest cache level is coupled to the peripheral circuit. The cache 400 is configured to: cache the data to be written to the storage array 500 of the die 311 by the peripheral circuit 332 and the data to be read from the storage array 500. Figure 5 Taking the example that the plane 311 includes two caches 400 , in other embodiments, the plane 311 may include more than three or less than three caches. In other embodiments, the plane 311 may not be provided with a cache 400 .

[0127] Next, combine Figure 6 According to a planar schematic diagram shown in an exemplary embodiment, the memory array 500 and the connection relationship between the memory array 500 and the peripheral circuit 332 are introduced as follows.

[0128] like Figure 6 As shown, the memory array 500 includes a plurality of memory strings 511, which are arranged in an array above a memory array substrate (not shown), and each memory string 511 extends vertically above the substrate.

[0129] The memory array 500 includes a plurality of memory strings 511, which are arranged in an array above a memory array substrate (not shown), and each memory string 511 extends vertically above the substrate. Each memory string 511 includes a plurality of memory cells 512, and a plurality of memory cells 512 in each memory string 511 are vertically stacked above the memory array 500 substrate. The memory cells 512 have the function of storing data, and each memory cell 512 is used to store N bits of data (i.e., N-bit data), where N is an integer greater than or equal to 1. For example, when N=1, the memory cell 512 is a single level cell (SLC); when N=2, the memory cell 512 is a multi-level cell (MLC); when N=3, the memory cell 512 is a triple level cell (TLC); when N=4, the memory cell 512 is a quad-level cell (QLC), and the embodiment of the present application does not limit the value of N.

[0130] One end of the memory string 511 is coupled to a bit line (BL) 513, and the other end of the memory string 511 is coupled to a common source line 514. The bit line 513 and the common source line 514 are both coupled to the peripheral circuit 332. Figure 6 As shown, the memory string 511 can be organized into a plurality of memory blocks 517, each memory block 517 having a common source line 314 (e.g., coupled to ground). Each memory block 517 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 517 are erased at the same time. The memory cells 512 of adjacent memory strings 511 can be coupled through a word line (WL) 515, for example, the memory cells 512 at the same height or similar height from the substrate support surface in different memory strings 511 are in the same layer, and the plurality of memory cells 512 in the same layer are coupled to the same word line 515. Each bit line 513 and each word line 515 are coupled to the peripheral circuit 332, and the peripheral circuit operates the memory cells 512 coupled to the bit line 513 and / or the word line 515 by applying a voltage to the bit line 513 and / or the word line 515.

[0131] In some embodiments, the memory cells 512 coupled to each word line 515 are organized into physical pages 516, which are basic data units for programming operations. According to the storage capacity of the memory cells 512, there is at least one physical page. The memory cells 512 in the same physical page store the same number of bits, while the memory cells in different physical pages store different numbers of bits. For example, SLC constitutes one physical page, and TLC constitutes one physical page 516. Each physical page 516 corresponds to at least one logical page, and the number of logical pages corresponding to the physical page is related to the storage capacity of the memory cells 512 in the physical page 516. For example, the physical page 516 includes M memory cells 512, and the storage capacity of the memory cell 512 is N bits. The physical page 516 stores M data, and each data is stored by a memory cell 512. Accordingly, each data includes a value of N bits, and the value of each bit is 0 or 1. The physical page 516 corresponds to N logical pages. The logical page is in bits, and each logical page corresponds to one bit in the N bits. Each logical page corresponds to one bit in the N bits. The logical page includes M-bit values, and the M-bit values ​​are the values ​​of each data in the corresponding bits of the M data, that is, each logical page includes the values ​​stored in the same bits of each storage unit 512 in the physical page 516. For example, a physical page composed of TLCs corresponds to three logical pages, namely, a high page (UP), a middle page (MP) and a low page (LP), wherein the high page includes the values ​​stored in the highest bits of each TLC in the physical page, the middle page includes the values ​​stored in the middle bits of each TLC in the physical page, and the low page includes the values ​​stored in the lowest bits of each TLC in the physical page.

[0132] The physical pages 516 in the plurality of dies 330 may be organized into stripes. For example, the plurality of physical pages in at least one plane 331 of the plurality of dies 330 may be organized into stripes. Different RAID strategies may be used to organize stripes in different ways. Taking the DIERAID strategy as an example, a plane 331 is selected from each of the plurality of dies 330, thereby selecting a plurality of planes 331, and the physical pages in the same layer of the plurality of planes 331 are organized into a stripe. In this case, the stripe includes a plurality of physical pages in a plane in each die 330. See Figure 7According to a schematic diagram of a DIE RAID strategy striping configuration shown in an exemplary embodiment, it is assumed that the memory includes 4 tube cores (DIE0 to DIE3), each tube core includes 4 planes (P0 to P3), each plane includes 4 storage blocks (B0 to B3), each storage block includes 32 layers (L0 to L31) of storage cells, and the storage cells of the same layer in the same plane in each tube core are coupled to the same word line. The storage cells of the same layer in each plane constitute at least one physical page, and the physical pages on the word line constitute a stripe. For example, the storage cells of the inner L0 layer of each plane P0 in DIE0 to DIE3 are coupled to the word line WL0, and the physical pages on the word line WL0 constitute stripe 0. For another example, the storage cells of the inner L0 layer of each plane P3 in DIE0 to DIE3 are coupled to the same word line WL1, and the physical pages on the word line WL0 constitute stripe 1.

[0133] Taking the Plane RAID strategy as an example, a stripe is formed from physical pages in the same layer in each plane of multiple tube cores 330. In this case, the stripe includes multiple physical pages in each plane of each tube core 330. Figure 8 According to a schematic diagram of a Plane RAID strategy striping configuration shown in an exemplary embodiment, it is assumed that the memory includes 4 tube cores (DIE0 to DIE3), each tube core includes 4 planes (P0 to P3), each plane includes 4 storage blocks (B0 to B3), each storage block includes 32 layers (L0 to L31) of storage cells, and the storage cells of the same layer in all planes in each tube core are coupled to the same word line, and each physical page on the word line constitutes a stripe. For example, the storage cells of the L0 layer in the plane P0 to the plane P3 in DIE0 to DIE3 are coupled to the word line WL0, and the physical pages on the word line WL0 constitute stripe 0.

[0134] According to the type of data stored in the physical page in the stripe, the physical page in the stripe is divided into a data page and a check page, wherein the data page refers to a physical page in the stripe for storing user data (i.e., data stored by the user), and the check page refers to a physical page in the stripe for storing the check data of the number of users, and the check data is the XOR calculation result between the data stored in each data page in the stripe. Each physical page in the same stripe is of the same type and corresponds to at least one logical page. For the convenience of description, each logical page corresponding to the data page is called a data logical page, and each logical page corresponding to the check page is called a check logical page. Assuming that the physical page in the stripe includes M storage units, the storage unit stores N bits of data, each physical page of the stripe stores M data, and each data includes an N-bit value, then the M data stored in the check page of the stripe are the M check data of the stripe, each check data is the XOR calculation result between the data at the same position in each data page of the stripe, and each check data packet has an N-bit check value, and each bit of the check value is the XOR calculation result between the values ​​at the same bit position in each data page of the stripe. For example, the i-th check data among M check data is: the XOR calculation result between the i-th data in each data page of the stripe, and the value of the j-th bit in the i-th check data is: the XOR calculation result between the values ​​of the j-th bit in each i-th data in each data page of the stripe, where i is greater than or equal to 1 and less than or equal to M, and j is greater than or equal to 1 and less than or equal to N.

[0135] The above describes the internal structure and striping configuration of the storage array 500 in the plane 331 of the tube core 330. Fig. 9 The internal structure of the peripheral circuit 332 in the die 330 is introduced as follows.

[0136] Fig. 9 is a schematic diagram of a peripheral circuit according to an exemplary embodiment. Fig. 9 As shown, the peripheral circuit 332 includes a page buffer / sense amplifier 601, a column decoder / bit line (BL) driver 602, a row decoder / word line (WL) driver 603, a voltage generator 604, a control logic unit 605, a register 606, an interface (I / F) 607, and a data bus 608. In some examples, it also includes Fig. 9601. The page buffer / sense amplifier 601 may be configured to read data from the memory array 500 and program (write) data to the memory array 500 according to a control signal from the control logic unit 605. In one example, the page buffer / sense amplifier 601 may store a page of programming data (write data) to be programmed into one physical page of the memory array 500. In another example, the page buffer / sense amplifier 601 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 512 coupled to the selected word line. In yet another example, the page buffer / sense amplifier 601 may also sense a low-power signal from a bit line representing a data bit stored in the memory cell 512, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 602 may be configured to be controlled by the control logic unit 605, and select one or more memory strings 511 by applying a bit line voltage generated from the voltage generator 604.

[0137] The row decoder / word line driver 603 may be configured to be controlled by the control logic unit 605, and select / deselect a memory block 517 of the memory array 500, select / deselect a word line 515 of a memory block 317. The row decoder / word line driver 603 may also be configured to drive a word line using a word line voltage generated from a voltage generator 604. As described in detail below, the row decoder / word line driver 603 is configured to perform an erase operation on a memory cell 512 coupled to (one or more) selected word lines. The voltage generator 604 may be configured to be controlled by the control logic unit 605, and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 500.

[0138] The control logic unit 605 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 606 may be coupled to the control logic unit 605, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 605. The interface 607 may be coupled to the control logic unit 605, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 605, and to buffer status information received from the control logic unit 605 and relay them to the host. The interface 607 may also be coupled to the column decoder / bit line driver 602 via a data bus 608, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 500 or relay or buffer data from the memory array 500.

[0139] As described in the background technology, in the related art, when a stripe in a memory is opened, the check data of the stripe is cached in the cache space of the memory controller. In order to reduce the occupation of the cache space of the controller, Figure 8 As shown, in the present application, a peripheral circuit 332 in at least one tube core 330 in the memory 103 sets a buffer 609 for at least one physical page. The number of buffers 609 set for each physical page depends on the number of bits that can be stored in the storage unit of the physical page in the tube core. Taking the storage unit for storing N bits of data as an example, N buffers are set for the physical page where the storage unit is located in the peripheral circuit 332, and each buffer corresponds to one bit in the N bits. Each buffer 609 is used to cache the check data of the data page of the stripe to which the storage unit belongs on the corresponding bit. Since each bit in the N bits belongs to a logical page of the physical page where the storage unit is located, in other words, the N buffers 609 correspond to a logical page of the physical page where the storage unit is located, and each buffer 609 is used to cache the check data and intermediate check data of the stripe where the storage unit is located in the corresponding logical page. Taking the storage unit as TLC as an example, the physical page where the storage unit is located corresponds to three logical pages, namely, a high page, a middle page, and a low page. Then, three buffers are set in the peripheral circuit 332 of the tube core 330 where the storage unit is located. The three buffers correspond to the high page, the middle page, and the low page respectively. The three buffers are used to cache the check values ​​in the logical check pages of the stripe in the high page, the middle page, and the low page respectively. In other embodiments, the buffer 609 may not be set for each physical page separately, but the buffer 609 is set for the physical page composed of the storage unit 512 with the largest storage capacity, and the other physical pages reuse the buffer 609 set for this physical page. For example, in order to take the storage unit 512 with the largest storage capacity as QLC, four buffers 609 are set for the physical page composed of QLC, corresponding to four logical pages respectively. In the case of TLC forming a physical page, any three buffers 609 of the four buffers 609 are allocated to the physical page composed of TLC, and the three buffers 609 correspond to three logical pages respectively. Here, the embodiment of the present application does not limit the number of buffers 609 provided in the peripheral circuit 332 .

[0140] Each buffer 609 provided in the peripheral circuit 332 may be a latch or a static random access memory. The buffer 609 may be capable of storing the verification data or intermediate verification data of the corresponding logical page. Here, the embodiment of the present application does not limit the implementation form of the buffer 609.

[0141] In order to facilitate the calculation and storage of stripe check data, such as Fig. 9As shown, in the peripheral circuit 332, an XOR circuit 610 is respectively set for each buffer 609, and the XOR circuit 610 is coupled to a buffer 609 and an interface 607, wherein each buffer 609 is configured to perform an XOR calculation on the input data and output the XOR calculation result to the coupled buffer 609, and the input data includes a value output by the coupled buffer 609 and a value read and written in the data page corresponding to the buffer 609. For example, when the control logic unit 604 writes a data to the data page according to the read and write instructions of the external controller 104, the N-bit value of the data is sent to an XOR circuit 610 respectively, and the XOR circuit 610 performs an XOR calculation on the value from the control logic unit 604 and the value in the coupled buffer 609, and inputs the XOR calculation result to the buffer 609, so that the XOR calculation result is used as the new output data of the buffer 609.

[0142] In some other embodiments, no new XOR circuit 610 is provided in the peripheral circuit 332, and the buffer 609 reuses XOR circuits in other modules in the peripheral circuit 332 or XOR circuits in other peripheral circuits.

[0143] Fig.10 is a schematic diagram of a controller according to an exemplary embodiment. Fig.10 As shown, the controller 104 controls the operation of the memory 103 by generating a control signal (or a control instruction) to control the striping of the read and write data in the memory 103, or to calculate and process the data. When the controller 104 receives the instruction of the host 102, it can also generate a control signal (or a control instruction) to control the operation of the memory 103 according to the instruction of the host 102. The controller 104 can have different modules in a single device, or a separate device with a dedicated function, such as an integrated circuit chip (such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA)). In some embodiments, the components of the controller 104 can be in an integrated device, or distributed in different locations to communicate with each other through a network.

[0144] like Fig.10 As shown, the controller 104 includes a processor 41, a memory 42, and an interface (I / F) 43. Processor 41. The processor 41 includes any appropriate type of general or special microprocessor, digital signal processor, or microcontroller. The processor 41 can be configured to generate one or more control signals based on instructions received from the host 101 to control the operation of the memory 103 (e.g., read, write, erase, and program operations). Optionally, the processor 41 is also configured to execute the controller-side method steps provided in the present application. Although in Fig.10Although not shown in the figure, the processor 41 may include multiple functional units or modules implemented using software, hardware, middleware, firmware or any combination thereof. The multiple functional units may execute the controller-side method steps provided in the present application based on a signal from the host 101 or any pre-stored control data.

[0145] There is at least one storage 42, and the storage 42 can be configured to store any type of information that the processor 104 may need to operate. For example, the memory 42 provides a cache space for the processor 104, and the cache space is used to store / cache information and / or data to be used by the processor 41, such as information and / or data received by the processor 41 from the host 101, data to be written to the memory 103, data read from the memory 103, etc. For another example, the storage 42 can also be configured to store at least one computer program, which is executed by the processor 41 to perform the method steps on the controller 104 side of the present application. The memory 103 can be a computer-readable storage medium, such as a static random access memory (SRAM), a CD-ROM read-only memory (ROM), a random access memory (RAM), a read-only compact disk (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0146] The interface 43 is configured to implement communication between various modules in the controller 104, such as communication between the processor 41 and the memory 42. The interface 43 is also configured to implement docking with devices or modules outside the controller 104 to implement communication between the modules in the controller 104 and the docked devices or modules, wherein the devices or modules outside the controller 104 docked by the interface 43 are, for example, the host 101 or the memory 103. For example, the interface 43 docks with an interface on the host 101 so that the host 101 communicates with the processor 41 in the controller 104, and the interface 43 also docks with the interface 310 in the memory 103 so that the processor 41 communicates with various dies 330 in the memory 103.

[0147] For the storage system introduced above, Fig.11 , the process of the memory controller writing data to a certain strip in the memory is described as follows:

[0148] Fig.11 It is a flowchart of a stripe-based data caching method according to an exemplary embodiment. The method is applied to a storage system, which includes a memory and a controller of the memory. The memory is any of the memories introduced above, and the controller is any of the controllers introduced above. The method includes steps 1101-1102.

[0149] 1101. A controller sends a first write instruction to a memory, where the first write instruction instructs writing first data to a first physical page of a first stripe, where the first stripe is provided by a plurality of dies in the memory.

[0150] The plurality of dies are all dies of the memory or some dies in the memory, and the first stripe is any stripe provided by the plurality of dies. Exemplarily, the plurality of dies are organized into stripes according to the DIE RAID strategy. At this time, the first stripe includes a plurality of physical pages in a plane of each of the plurality of dies, and each physical page on the first stripe is connected to the same WL. For example, the first stripe is Figure 7 Stripe 0 or stripe 1 in .

[0151] The first physical page is any data page on the first stripe. The first physical page is the physical page of the data to be written this time. The first data is the data to be written. The first write instruction includes address information of the first physical page and the first data. The address information indicates the position of the first physical page in the target die. The target die is the die where the first physical page is located.

[0152] by Fig.12 For example, assume that the memory includes four tube cores (DIE0-DIE3), and these four tube cores are controlled by CE0 signal line and CH0-CH3 signal lines, wherein CH0 signal line is connected to DIE0-DIE3, and CH0-CH3 signal lines are connected to DIE0-DIE3 respectively. Each tube core includes 4 planes (P0-P3), and the storage array in each plane is composed of SLC. According to the DIE RAID strategy, the physical pages in the 4 planes in the 4 tube cores are organized into stripes. Each stripe includes 4 physical pages, and the 4 physical pages are respectively located in the 4 tube cores. For example, physical page 0 in plane P0 in DIE0, physical page 4 in plane P0 in DIE1, physical page 8 in plane P0 in DIE2, and physical page 12 in plane P0 in DIE3 form the first stripe, wherein physical page 0, physical page 4, and physical page 8 are used as data pages in the first stripe, and physical page 12 is used as the check page of the first stripe. The data stored in physical page 0, physical page 4, and physical page 8 are respectively represented as D0, D4, and D8, and the check data stored in physical page 12 is represented as DR. The first physical page can be any physical page among physical page 0, physical page 4, and physical page 8.

[0153] In the case of being organized into stripes according to the DIE RAID strategy, a buffer (such as Fig. 9 The buffer 609 is called the first buffer, and the die where the first buffer is located is called the first die. Fig.12For example, the die where the physical page of the first stripe as the check page is located is the first die, and the buffer R3 corresponding to the physical page of the first stripe in the first die is used as the first buffer. In other embodiments, the die where the first logical page is located can also be the first die, and the buffer corresponding to the first physical page in the first die can be used as the first buffer. Fig.12 Each stripe includes 4 physical pages. Assuming that the storage units that make up the physical pages are SLC, the size of the buffer R3 (PU size) is at least 64KB, that is, 4*physical page size (pagesize). In order to adapt to the Plane RAID strategy, the size of the buffer R3 (PU size) may also be 256KB, that is, 16*physical page size. The parity ratio of DI-RAIN is 25%.

[0154] Before writing data to the first stripe for the first time, the controller first clears the data stored in the first buffer so that the check data of the first stripe can be cached in the first buffer. For example, the die to which the first stripe belongs is enabled, and a clear RAID buffer (CEB) instruction is sent to the memory, and the CEB indicates clearing the buffer corresponding to the first physical page in the corresponding die.

[0155] by Fig.12 For example, the controller sends to the CE0 signal line and CH3 signal line of the memory: an enable signal at a low level and a CEB instruction for instructing to clear the buffer R3. After receiving these signals, the peripheral circuit of DIE3 enables DIE0 and clears the data cached in the buffer Rx in DIE3 according to the CEB instruction.

[0156] After the first buffer is cleared, the controller writes data to the first stripe again. Before the writing to the first stripe is completed, the controller does not need to clear the data in the first buffer again. If the data in the first stripe is erased after the writing to the first stripe is completed, the data in the first buffer must be cleared again before the data is written to the first stripe for the first time. That is, the data in the first buffer must be cleared before writing data to the first stripe for the first time each time. The stripe writing completion means that all physical pages in the stripe have been written, and the physical page writing completion means that the physical page has been filled with data or that no data will be written to the physical page data within a preset time (at this time, the physical page may not be filled with data).

[0157] 1102. In response to a first write instruction, the memory caches first verification data between the first data and the written data of the first stripe through a first buffer in at least one die, and writes the first data to the first physical page.

[0158] Herein, this step 1102 may be executed by a peripheral circuit of the memory, such as by a logic control unit 605 in the peripheral circuit of the memory.

[0159] After receiving the first write instruction, the peripheral circuit of the first core device writes the first data to the first physical page according to the first write instruction and sends the first data to the XOR circuit, or the XOR circuit is set on the data path of the core where the first physical page is located, and when the first data is written to the first physical page through the data path, the first data is transmitted to the XOR circuit, thereby eliminating the need to send the first data to the XOR circuit separately.

[0160] Through the XOR circuit, the first data and the second check data in the first buffer are XORed to obtain the first check data, and the first check data is output to the first buffer. The second check data is the check data of the value 0 or the data written in the first stripe. If the stripe has not been written with data before the first data is written, that is, the first data is the data written to the first stripe for the first time, the second check data is 0. The first check data is the XOR result of the second check data and the first data.

[0161] For example, before writing the first data, the second verification data is stored in the first cache. When the first cache is in an enabled state, the first cache inputs the second verification data stored in it to the XOR circuit. At this time, the first data is input into the XOR circuit as another input data of the XOR circuit. The XOR circuit performs an XOR operation on the input first data and the second verification data to obtain the first verification data. The first verification data is input into the first cache to overwrite the second verification data stored in the first cache, so that the data stored in the first cache is updated from the second verification data to the first verification data. The first cache will input the first verification data as new input data to the XOR circuit. If the newly written data is input into the XOR circuit, the XOR circuit will perform an XOR operation on the newly written data and the first verification data to update the first verification data in the first cache. It can be seen that each time data is written to the data page of the first stripe, the verification data cached in the first cache will be updated once.

[0162] It should be understood that before writing the first data, the XOR circuit connected to the first buffer is enabled so that the XOR circuit can perform the XOR operation. In some embodiments, when the first data is organized into stripes according to the DIE RAID strategy, Fig.12For example, the controller sends an enable signal to the peripheral circuit of DIE3 for indicating an enable signal of the XOR circuit connected to the buffer RX. The peripheral circuit enables the XOR circuit based on the enable signal. Before receiving an enable signal indicating not to enable the XOR circuit, the XOR circuit is always in an enabled state. When the XOR circuit is in the enabled state, the controller writes data to the first stripe so that the XOR circuit calculates check data for the first stripe.

[0163] Before writing data to the first stripe for the first time, the value 0 is first stored in the first buffer so that the XOR circuit connected to the first buffer can perform an XOR operation on the data written to the first stripe for the first time using the value 0 as the check data. For example Fig.12 Step ① in .

[0164] In step ①, before writing data to the first stripe for the first time, the controller instructs the CH3 signal line to send a cache write (write RAID buffer, WRB) instruction to write verification data DR to buffer R3. At this time, the verification data DR=0. The peripheral circuit of DIE3 writes the value 0 (i.e., verification data DR) to buffer R3 in DIE3 according to the WRB instruction. At this time, the verification data (DR3) stored in buffer R3 is 0.

[0165] After step ① is completed, data is written to each data page in the first stripe in sequence. Each time data is written to a data page, the data page is the first physical page, and the data written to the data page is the first data. Fig.12 Steps ②, ③, and ④ in the following respectively describe the process of writing data to each data page in the first stripe.

[0166] In step ②, the controller sends a write instruction (indicated as D0 IN in the figure) to the CH0 signal line and the CH3 signal line respectively, indicating the writing of data D0, wherein the write instruction sent to the CH0 signal line indicates the writing of data D0 to the physical page 0 in DIE0, and the write instruction sent to the CH3 signal line indicates the writing of data D0 to the XOR circuit connected to the first buffer R3. The peripheral circuit of DIE0 writes data D0 to the physical page 0 in the plane P0 of DIE0 according to the write instruction transmitted by the CH0 signal line, and the peripheral circuit of DIE3 inputs data D0 to the XOR circuit connected to the first buffer R3 according to the write instruction transmitted by the CH3 signal line. The XOR circuit performs an XOR operation on the check data DR3 (i.e., 0) input by the buffer R3 and the data D0 to obtain new check data DR3, and returns the new check data DR3 to the buffer R3. At this time, the new check data DR3=0^D0=D0, wherein "^" refers to the XOR operation.

[0167] In step ③, the controller sends a write instruction (indicated as D4 IN in the figure) to the CH1 signal line and the CH3 signal line respectively, indicating the writing of data D4, wherein the write instruction sent to the CH1 signal line indicates the writing of data D4 to the physical page 4 in DIE1, and the write instruction sent to the CH3 signal line indicates the writing of data D4 to the XOR circuit connected to the first buffer R3. The peripheral circuit of DIE1 writes data D4 to the physical page 4 in the plane P0 of DIE1 according to the write instruction transmitted by the CH1 signal line, and the peripheral circuit of DIE3 inputs data D4 to the XOR circuit connected to the first buffer R3 according to the write instruction transmitted by the CH3 signal line. The XOR circuit performs an XOR operation on the check data DR3 (i.e., D0) input by the buffer R3 and the data D4 to obtain new check data DR3, and returns the new check data DR3 to the buffer R3. At this time, the new check data DR3=D0^D4.

[0168] In step ④, the controller sends a write instruction (indicated as D5 IN in the figure) to the CH2 signal line and the CH3 signal line respectively, indicating that the data D5 is to be written, wherein the write instruction sent to the CH2 signal line indicates that the data D8 is to be written to the physical page 8 in DIE2, and the write instruction sent to the CH3 signal line indicates that the data D8 is to be written to the XOR circuit connected to the first buffer R3. The peripheral circuit of DIE2 writes the data D8 to the physical page 8 in the plane P0 of DIE2 according to the write instruction transmitted by the CH2 signal line, and the peripheral circuit of DIE3 inputs the data D8 to the XOR circuit connected to the first buffer R3 according to the write instruction transmitted by the CH3 signal line. The XOR circuit performs an XOR operation on the check data DR3 (i.e., D0^D4) input by the buffer R3 and the data D8 to obtain new check data DR3, and returns the new check data DR3 to the buffer R3. At this time, the new check data DR3 = D0^D4^D8. At this time, all the data pages in the first stripe have been written, and the check data DR3 is the final check data DR of the first stripe.

[0169] Fig.12 The example of writing data to each data page in the first stripe in sequence is used as an example. In other embodiments, the controller may write data to the first stripe in a disorderly or random manner instead of in the order of the data pages in the first stripe. Fig.12 Steps ②, ③, and ④ in the embodiment are executed in this order. For example, step ④ may be executed first, and then step ② or ③. Therefore, the embodiment of the present application Fig.12 There is no restriction on the execution order of steps ②, ③, and ④.

[0170] In some embodiments, after the first physical page is written, and all data pages in the first stripe are written, the first verification data is the verification data of all data pages in the first stripe, then the controller controls the memory to store the first verification data cached in the first buffer to the verification page of the first stripe.

[0171] In a possible implementation, the controller first reads the first verification data from the first buffer, and then writes the first verification data to the verification page of the first stripe. Exemplarily, if the first physical page is the last data page of the first stripe, when all data pages in the first stripe are written, the controller sends a read instruction to the memory, the read instruction instructs to read the data cached in the first buffer, the memory responds to the read instruction, reads the first verification data from the first buffer, sends the first verification data to the controller, and the controller sends a third write instruction based on the read first verification data, the third write instruction instructs to write the first verification data to the verification page of the first stripe.

[0172] Still Fig.12 For example, assuming that the first data is D8, after data D8 is written to physical page 8, all data pages on the first stripe have been written, and DR3 stored in R3 at this time is the final verification data P of the first stripe. In step ⑤, the controller sends a read RAID buffer (RRB) instruction to the CH3 signal line. The RRB instruction is a read instruction that indicates reading the data cached in the buffer R3. After the peripheral circuit of DIE3 receives the RRB instruction, it returns the verification data DR3 stored in the buffer R3 to the controller. The controller can verify that the data DR3 is the final verification data P of the first stripe. Based on the final verification data P, the controller generates a third write instruction (indicated as DR IN in the figure) that indicates writing the final verification data P to the verification page of the first stripe, and sends the third write instruction to the CH3 signal line. After the peripheral circuit of DIE3 receives the third write instruction, according to the third write instruction, the final verification data P carried by the third write instruction is written to the physical page 12 of the plane 0 of DIE.

[0173] based on Fig.11 The method embodiment shown in the figure sets a cache (such as a first cache) in the tube core of the memory. When writing data to the data page of the stripe, the verification data between the currently written data and the data already written to the stripe is cached in the cache, thereby eliminating the need to allocate storage space for the verification page of the stripe from the cache space of the controller, so that more space in the cache space can be allocated to the data page, thereby improving the random read and write performance of the memory.

[0174] When multiple cores in the memory are organized into multiple stripes according to the DIE RAID strategy, each time a stripe is written, another stripe is written. Fig.12 For example, assume that physical page 1 in plane P1 in DIE0, physical page 5 in plane P1 in DIE1, physical page 9 in plane P1 in DIE2, and physical page 13 in plane P1 in DIE3 constitute a second stripe, wherein physical pages 1, 5, and 9 are used as data pages in the second stripe, and physical page 13 is used as the check page of the second stripe. The data stored in physical pages 1, 5, and 9 are represented as D1, D5, and D9 respectively, and physical page 13 is used to store the final check data P of the second stripe. Assume that physical page 2 in plane P2 in DIE0, physical page 6 in plane P2 in DIE1, physical page 10 in plane P2 in DIE2, and physical page 14 in plane P2 in DIE3 constitute a third stripe, wherein physical pages 2, 6, and 10 are used as data pages in the third stripe, and physical page 14 is used as a check page of the third stripe. The data stored in physical pages 2, 6, and 10 are represented as D2, D6, and DA, respectively, and physical page 14 is used to store the final check data P of the third stripe. Assume that physical page 3 in plane P3 of DIE0, physical page 7 in plane P3 of DIE1, physical page 11 in plane P3 of DIE2, and physical page 15 in plane P3 of DIE3 form the fourth stripe, where physical pages 3, 7, and 11 are used as data pages in the fourth stripe, and physical page 15 is used as the check page of the fourth stripe. The data stored in physical pages 3, 7, and 11 are represented as D3, D7, and DB respectively, and the final check data of the fourth stripe stored in physical page 15 is represented as DR. Fig.13 The process shown in FIG. 1 writes data into the second stripe. In the process of writing data into the second stripe, the intermediate check data and the final check data P of the second stripe are cached by the cache R3. Fig.14 The process shown writes data into the third stripe. In the process of writing data into the third stripe, the intermediate check data and the final check data P of the third stripe are cached by the cache R3. Fig.15 The process shown in FIG. 1 is to write data to the fourth stripe. In the process of writing data to the fourth stripe, the intermediate check data and the final check data P of the fourth stripe are both cached by the cache R3. The process of writing data to the second stripe and the fourth stripe can refer to FIG. 1 . Fig.12 The process of writing data to the first stripe is not described in detail here. The embodiment of the present application does not limit the order of writing to the first stripe, the second stripe, the third stripe, and the fourth stripe. For example, data can be written to the first stripe first, and after the first stripe is written, data is written to the second stripe. After the second stripe is written, data is written to the third stripe. For another example, data can be written to the fourth stripe first, and after the fourth stripe is written, data is written to the second stripe. After the second stripe is written, data is written to the third stripe. Figure 12 to Figure 11When the peripheral circuit of DIE writes data to a physical page in any plane, it can first write the data to the cache of the plane, and then read the data to the physical page in the storage array according to the cache instruction (R / B) of the controller to the cache. Fig.15 As shown in the instruction timing diagram, after DIE0 writes data D3 into the cache of the local plane P3, upon receiving the candidate cache instruction R / B_0 from the controller for data D3, it reads data D3 from the cache of the local plane P3 to physical page 3 of the storage array. After DIE1 writes data D7 into the cache of the local plane P3, upon receiving the candidate cache instruction R / B_1 from the controller for data D7, it reads data D7 from the cache of the local plane P3 to physical page 7 of the storage array. After DIE2 writes data DB into the cache of the local plane P3, upon receiving the candidate cache instruction R / B_2 from the controller for data DB, it reads data DB from the cache of the local plane P3 to physical page 11 of the storage array. After DIE3 writes data DR into the cache of the local plane P3, upon receiving the candidate cache instruction R / B_3 from the controller for data DR, it reads data DR from the cache of the local plane P3 to physical page 15 of the storage array.

[0175] When multiple tube cores in the memory are organized into multiple stripes according to the DIE RAID strategy, after any stripe is written, if there is an abnormal data page in the stripe, the controller can also calculate the intermediate verification data with the help of the buffer corresponding to the data of the stripe in each tube core and the XOR circuit connected to the buffer. The intermediate verification data is the verification data between the data in all normal physical pages on the stripe, and reconstruct the data stored in the abnormal data page based on the intermediate verification data. Among them, the abnormal data page refers to a data page with abnormal data storage. The data abnormality can be manifested as the data currently stored in the data page is different from the data previously stored in the data, or the data previously stored in the data page is lost. A normal physical page refers to a data page or verification page without data abnormality.

[0176] For example, suppose Fig.14 The data stored in physical page 6 on the third stripe in plane P2 of DIE2 is abnormal. Fig.16 Before reconstructing the data stored in physical page 6, the controller first clears the buffer corresponding to the physical page of the third stripe in DIE0-DIE3. Fig.16As shown, the controller sends CRB instructions to the CH0 signal line to the CH3 signal line respectively to instruct to clear the data in the corresponding buffer. Taking the CH0 signal line as an example, the CRB instruction sent by the controller to the CH0 signal line instructs to clear the buffer R0 corresponding to the physical page of the third stripe in DIE0 to initialize the buffer R0 (i.e., R0 init). After the peripheral circuit in DIE0 receives the CRB, it clears the data stored in the buffer R0. After the buffer R0 is cleared, the controller sends a write instruction to DIE0 through the CH0 signal line to instruct to write 0 in the buffer R0. According to the write instruction, the peripheral circuit of DIE0 writes the value 0 to the buffer R1.

[0177] Afterwards, the controller reads the data of the normal physical page of the third stripe in DIE0, DIE2, and DIE3 into the corresponding buffer, see Fig.17 , taking the reading of data D2 stored in physical page 2 on the third stripe in DIE0 as an example, the controller sends a RAID read (RAID read, RRD) instruction to the CH0 signal line to instruct the data D2 to be read into the buffer R0. After receiving the RRD instruction, the peripheral circuit of DIE0 reads the data D2 stored in physical page 2 in plane P2 of DIE0 into the XOR circuit connected to the buffer R0 according to the RRD instruction. The XOR circuit performs XOR calculation on the data D2 from the physical page and the value 0 input from the buffer R0 to obtain data D2, and inputs the data D2 into the buffer R0, so that the data DR0 stored in the buffer R0 changes from the value 0 to the data D2. In a similar manner, the controller reads the data DA in the physical page 10 in the plane P2 of DIE2 into the buffer R2 of DIE2, and reads the data P in the physical page 14 in the plane P2 of DIE3 (i.e., the final check data P of the third stripe previously written) into the buffer R3 of DIE3.

[0178] Then, the controller controls the memory to set any buffer among buffers R0-R3 as the target buffer, and stores the data cached in each non-target buffer among buffers R0-R3 into the target buffer. Fig.18, assuming that buffer R1 is the target buffer, and buffers R0, R2, and R3 are all non-target buffers, the controller first reads data from buffers R0, R2, and R3. Taking the reading of data D2 in buffer R0 as an example, the controller sends an RRB instruction (RAID read, RRD) to the CH0 signal line to indicate that R0 will be read. After the peripheral circuit of DIE0 receives the RRB read instruction, it reads the data D2 cached in buffer R1 according to the RRB read instruction and returns data D2 to the controller. In a similar manner, the controller reads data DA and data P from buffers R2 and R3, respectively. The controller sends three write instructions to the CH1 signal line in sequence. These three write instructions respectively instruct to write data D2, data DA and data P to the XOR circuit connected to the buffer R1. According to these three write instructions, the peripheral circuit of DIE1 inputs data D2, data DA and data P to the XOR circuit connected to the buffer R1. The XOR circuit performs XOR operation on data D2, data DA, data P and the value 0 cached in the buffer R1, and the obtained intermediate verification data = D2^DA^P. The intermediate verification data is input to the buffer R1, so that the verification data DR1 stored in the buffer R1 changes from the value 0 to D2^DA^P. Afterwards, the controller reads the intermediate verification data from the buffer R1, as shown in FIG. Fig.18 As shown, the controller sends an RRB instruction to the CH1 signal line to instruct to read the buffer R1. The peripheral circuit of DIE1 returns the check data DR1 cached in the buffer R1 to the controller according to the RRB instruction. The controller uses the returned check data DR1 as the intermediate check data, and then reconstructs the data D6 according to the intermediate check data. Fig.10 As shown, the processor 41 in the controller 104 performs an XOR operation on the data DR1 - DR3 read from the buffers R1 - R3 to reconstruct the data D5 , and stores the reconstructed data D5 in the buffer 104 through the interface 43 .

[0179] against Figure 16-18 The data reconstruction process calculates the intermediate check data used to reconstruct the abnormal data through the buffer in the tube core and the peripheral circuit, which can reduce the SRAM occupation of the controller, so that the controller has sufficient SRAM space to randomly read and write the memory, which is beneficial to improve the random read and write performance of the controller.

[0180] The above is organized into stripes according to the DIE RAID strategy. Fig.11 The method embodiment shown is introduced, Fig.11 The method embodiment shown in the figure is also applicable to stripes organized according to the Plane RAID strategy. The following takes the first stripe organized according to the Plane RAID strategy as an example to describe the above Fig.11 The method embodiment shown is described as follows:

[0181] In the case of organizing into the first stripe according to the Plane RAID strategy, the first stripe includes multiple physical pages in each plane of each of the multiple dies of the memory, and each physical page on the first stripe is connected to the same WL. For example, the first stripe is Figure 8 The stripe 0 in Fig.19 For example, assume that the memory includes 4 tube cores (DIE0-DIE3), and these 4 tube cores are controlled by CE0 signal line, CE1 signal line, CH0 signal line, and CH1 signal line, wherein DIE0 connects CH0 signal line and CE0 signal line and is controlled by these two signal lines, DIE1 connects CH0 signal line and CE1 signal line and is controlled by these two signal lines, DIE2 connects CH1 signal line and CE0 signal line and is controlled by these two signal lines, and DIE3 connects CH1 signal line and CE1 signal line and is controlled by these two signal lines. Each tube core includes 4 planes (P0-P3), and the storage array in each plane is composed of SLC. According to the PlaneRAID strategy, the physical pages in the 4 planes of the 4 tube cores are organized into stripes. Assuming that the stripe includes 16 physical pages, the 4 planes in each tube core respectively provide 1 physical page for the stripe. Since multiple physical pages in a stripe are located on the same die, each die provides a buffer for caching check data for its local physical page, so that when the controller writes data to any physical page of any stripe, the check data of the stripe calculated based on the written data can be cached in the buffer in the die where the physical page is located. Fig.19 The buffers provided by DIE0-DIE3 in the system are R0, R1, R2, and R3 respectively. Fig.19 The stripe in the memory is composed of SLCs, and the size (PU size) of the buffers R0, R1, R2, and R3 is at least 16*physical page size (page size)=256KB. At this time, the parity ratio of the stripe is 6.25%.

[0182] With respect to the above step 1101, the controller writes the first data to the first physical page of the first stripe, where the first stripe may be any stripe formed by a plurality of dies according to the Plane RAID strategy. Fig.19For example, assume that the first stripe includes 16 physical pages, including physical pages 0-15, among which physical pages 0-3 are respectively located in planes P0-P3 in DIE0, physical pages 4-7 are respectively located in planes P0-P3 in DIE1, physical pages 8-11 are respectively located in planes P0-P3 in DIE2, and physical pages 13-15 are respectively located in planes P0-P3 in DIE3. Physical pages 0-14 are all used as data pages in the first stripe. The data stored in physical pages 0-14 are respectively represented as D0-DB. Physical page 15 is used as the check page of the first stripe. In the process of writing data to each data page of the first stripe, the check data of the first stripe is represented as DR. The check page storage is used to store the final check data P of the first stripe. The first physical page can be any data page on the first stripe. For the purpose of description, when the first stripe is organized according to the Plane RAID strategy, the buffer corresponding to the first physical page in the tube core where the first physical page is located is called the first buffer. At this time, the tube core where the first physical page is located is the first tube core. Fig.19 For example, assuming that the first physical page is physical page 0 in the first stripe, the first die is DIE0, and the first buffer is buffer R0; assuming that the first physical page is physical page 4 in the first stripe, the first die is DIE1, and the first buffer is buffer R1.

[0183] Before writing data to the first stripe for the first time, the controller first clears the buffer corresponding to the physical page of the first stripe in the peripheral circuit of the die to which the first stripe belongs, so as to cache the check data of the first stripe through the buffer later. For example, the die to which the first stripe belongs is enabled, and a clear cache instruction is sent to the memory, the clear cache instruction instructing to clear the buffer corresponding to the physical page in the die.

[0184] like Fig.19As shown, it is assumed that the buffers corresponding to the SLC in the four dies are R0-R3 respectively. The controller sends an enable signal at a low level, an enable signal at a high level, and a CEB instruction to the CE0 signal line, CE1 signal line, and CH0 signal line of the memory, respectively, and then sends an enable signal at a high level, an enable signal at a low level, and a CEB instruction to the CE0 signal line, CE1 signal line, and CH0 signal line, respectively, and then sends an enable signal at a low level, an enable signal at a high level, and a CEB instruction to the CE0 signal line, CE1 signal line, and CH1 signal line of the memory, respectively, and then sends an enable signal at a high level, an enable signal at a low level, and a CEB instruction to the CE0 signal line, CE1 signal line, and CH1 signal line of the memory, respectively. The peripheral circuit of DIE0 enables DIE0 according to the enable signal at a low level transmitted by the CE0 signal line, and clears the data cached in the buffer R0 according to the CEB instruction transmitted by the CH0 signal line. The peripheral circuit of DIE1 enables DIE1 according to the low-level enable signal transmitted by the CE1 signal line, and clears the data cached in the buffer R1 according to the CEB instruction transmitted by the CH0 signal line. The peripheral circuit of DIE2 enables DIE2 according to the low-level enable signal transmitted by the CE0 signal line, and clears the data cached in the buffer R2 according to the CEB instruction transmitted by the CH1 signal line. The peripheral circuit of DIE2 enables DIE1 according to the low-level enable signal transmitted by the CE1 signal line, and clears the data cached in the buffer R3 according to the CEB instruction transmitted by the CH1 signal line.

[0185] After clearing the corresponding buffer in the peripheral circuit of the tube core in the first stripe, the controller writes data to the first stripe again. Before the writing of the first stripe is completed, the controller clears the data in the buffer again. If the data in the first stripe is erased after the writing of the first stripe is completed, the data in the buffer must be cleared again before writing data to the first stripe for the first time. That is, the data in the buffer must be cleared before writing data to the first stripe for the first time each time.

[0186] After the corresponding buffer in the peripheral circuit of the tube core in the first stripe is cleared, assuming that the controller wants to write data to the first physical page in the first stripe, the controller sends a first write instruction to the memory by executing the above step 1101. For example, the controller sends the first write instruction to the first tube core where the first physical page is located. For the above step 1102, after receiving the first write instruction, the peripheral circuit of the first tube core writes the first data to the first physical page according to the first write instruction, and sends the first data to the XOR circuit connected to the first buffer, or the XOR circuit is set on the data path of the tube core where the first physical page is located. When the first data is written to the first physical page through the data path, the first data is transmitted to the XOR circuit, so that the first data does not need to be sent to the XOR circuit separately.

[0187] Through an XOR circuit, an XOR operation is performed on the first data and the second verification data in the first buffer to obtain the first verification data, and the first verification data is output to the first buffer. The second verification data is the verification data of the value 0 or the data written to the first stripe. If no data has been written to the first stripe before the first data is written, that is, the first data is the first data written to the first stripe, then the second verification data is the value 0. The first verification data is the XOR result of the second verification data and the first data. Since the first buffer provides verification data caching services for the physical pages in the first tube core when organized into stripes according to the Plane RAID strategy, but does not provide verification data caching services for the physical pages in other tube cores. Therefore, the verification data between the written data of the first stripe cached in the first buffer refers to the verification data between the written data of the first stripe in the first tube core. Fig.19 For example, assuming the first physical page is Fig.19 In the physical page 2 of the plane P2 of DIE0, if the physical page 0 of the plane P0 of DIE0 and the physical page 1 of the plane P1 of DIE0 have data D0 and data D1 written therein respectively, then when writing data D2 to the physical page 2 of the plane P2 of DIE0, the second check data cached in the buffer R1 is D0^D1. In some embodiments, the check data between the written data of the first stripe cached in the first buffer refers to the check data between the written data of the first stripe in the first die and the written data of the first stripe in other die, or refers to the check data between the written data of the first stripe in other die, still in the form of Fig.19 For example, assuming the first physical page is Fig.19Physical page 4 in plane P0 of DIE1, cache R1 in DIE1 is the first cache, if physical pages 0-3 of the first stripe in DIE0 are written with data D0-D3 respectively, the second verification data cached in cache R1 is D0^D1^D2^D3, if physical page 4 of the first stripe in DIE1 is written with data D4, the first physical page is physical page 5 in plane P1 of DIE1, the second verification data cached in cache R1 is D0^D1^D2^D3^D4.

[0188] Next, combine Figure 19-Figure 23 , a process of writing the first data to the first physical page is described in detail by caching the first check data between the first data and the written data of the first stripe through the first buffer in at least one tube core in response to the first write instruction of the memory.

[0189] by Fig.19 For example, assuming that the first physical page in the first stripe is physical page 0 in the first stripe, physical page 0 is located in the storage array of plane P0 in DIE0, the first buffer is buffer R1 in DIE0, and the first data is D0, such as Fig. 20 As shown, before writing data D0, the controller sends an enable signal for instructing to enable the XOR circuit connected to the buffer R1 to the peripheral circuit of DIE0, and the peripheral circuit enables the XOR circuit based on the enable signal.

[0190] exist Fig. 20 In step ①, the controller sends an enable signal at a low level, an enable signal at a high level, and a WRB instruction indicating writing verification data DR to the buffer R0 to the CE0 signal line, the CE1 signal line, and the CH0 signal line respectively. At this time, the verification data DR=0. The peripheral circuit of DIE0 writes a value of 0 (i.e., verification data DR) to the buffer R0 according to the WRB instruction and the enable signal transmitted by the CE0 signal line. At this time, the verification data DR0 stored in the buffer R0=0.

[0191] exist Fig. 20In step ②, the controller sends an enable signal at a low level, an enable signal at a high level, and a write instruction (denoted as D0 IN in the figure) indicating writing data D0 to physical page 0 to the CE0 signal line, the CE1 signal line, and the CH0 signal line, respectively, wherein if physical page 0 is the first physical page, the write instruction is the first write instruction. The peripheral circuit of DIE0 writes data D0 to physical page 0 in plane P0 of DIE0 according to the write instruction and the enable signal transmitted by the CE0 signal line. Before being transmitted to plane P0, data D0 is also transmitted to the XOR circuit connected to the buffer R0, which performs an XOR operation on the check data DR0 (i.e., 0) input by the buffer R0 and the data D0 to obtain new check data DR0, and returns the new check data DR0 to the buffer R0. At this time, the new check data DR0=0^D0=D0.

[0192] After writing the first data to the first physical page, the controller can also write data to other physical pages of the first stripe in the first die. In one possible implementation, any physical page other than the first physical page on the first stripe in the first die is called a second physical page, and the controller generates a second write instruction based on the address information of the second physical page and the second data, and the second write instruction indicates to write the second data to the second physical page of the first stripe in the first die. The controller sends the second write instruction to the memory, and the memory responds to the second write instruction by caching the third verification data between the second data and the first verification data through the first buffer, and writes the second data to the second physical page, wherein the third verification data is the result of the XOR operation of the first verification data and the second data. Fig. 20 For example, assuming that the physical page 0 in the plane P0 in DIE0 is the first physical page of the first stripe, the physical page 1 in the plane P1 in DIE0 is the second physical page of the first stripe, and the second data is data D1, see Fig. 20 Step ③ in .

[0193] exist Fig. 20 In step ③, the controller sends an enable signal at a low level, an enable signal at a high level, and a write instruction (i.e., a second write instruction, represented as D1 IN in the figure) indicating that data D1 is written to physical page 1 to the CE0 signal line, the CE1 signal line, and the CH0 signal line respectively. The peripheral circuit of DIE0 writes data D1 to physical page 1 in plane P1 of DIE0 according to the write instruction and the enable signal transmitted by the CE0 signal line. Before being transmitted to plane P1, data D1 is also transmitted to the XOR circuit connected to the buffer R0. The XOR circuit performs an XOR operation on the verification data DR0 (such as D0) input by the buffer R0 and the data D1 to obtain new verification data DR0, and returns the new verification data DR0 to the buffer R0. At this time, the new verification data DR0=D0^D1, i.e., the third verification data.

[0194] Still Fig. 20 For example, assuming that the physical page 1 in the plane P1 in DIE0 is the first physical page of the first stripe, the physical page 2 in the plane P2 in DIE0 is the second physical page of the first stripe, and the second data is data D2, see Fig. 20 Step ④ in .

[0195] exist Fig. 20 In step ④, the controller sends an enable signal at a low level, an enable signal at a high level, and a write instruction (i.e., a second write instruction, represented as D2 IN in the figure) indicating writing data D2 to physical page 2 to CE0 signal line, CE1 signal line, and CH0 signal line respectively. The peripheral circuit of DIE0 writes data D2 to physical page 2 in plane P2 of DIE0 according to the write instruction and the enable signal transmitted by the CE0 signal line. Before being transmitted to plane P2, data D2 is also transmitted to the XOR circuit connected to the buffer R0. The XOR circuit performs an XOR operation on the verification data DR0 (such as D0^D1) input by the buffer R0 and the data D2 to obtain new verification data DR0, and returns the new verification data DR0 to the buffer R0. At this time, the new verification data DR0=D0^D1^D2, i.e., the third verification data.

[0196] Still Fig. 20 For example, assuming that the physical page 2 in the plane P2 in DIE0 is the first physical page of the first stripe, the physical page 3 in the plane P3 in DIE0 is the second physical page of the first stripe, and the second data is data D3, see Fig. 20 Step ⑤ in .

[0197] exist Fig. 20 In step ⑤, the controller sends an enable signal at a low level, an enable signal at a high level, and a write instruction (i.e., a second write instruction, represented as D3 IN in the figure) indicating writing data D3 to physical page 3 to the CE0 signal line, the CE1 signal line, and the CH0 signal line respectively. The peripheral circuit of DIE0 receives the write instruction and the enable signal transmitted by the CE0 signal line, and writes data D3 to physical page 3 in plane P3 of DIE0. Before being transmitted to plane P3, data D3 is also transmitted to the XOR circuit connected to the buffer R0. The XOR circuit performs an XOR operation on the verification data DR0 (such as D0^D1^D2) and the data D3 input by the buffer R0 to obtain new verification data DR0, and returns the new verification data DR0 to the buffer R0. At this time, the new verification data DR0=D0^D1^D2^D3, i.e., the third verification data.

[0198] In a possible implementation, if the first physical page is the last data page of the first stripe in the first die, and the first physical page is not the last data page of the first stripe, the controller may further control the memory to write the first check data in the first buffer into the second buffer of the second die, where the second die is the die where the next data page of the first physical page on the first stripe is located. Fig. 20 For example, assuming that the last data page of the first stripe is physical page 14 in plane P2 in DIE3, physical page 3 in plane P3 in DIE0 is the first physical page of the first stripe, and physical page 3 is the last data page of the first stripe in DIE0, but not the last data page of the first stripe. When physical page 3 is written, if other data pages on the first stripe in the first core device are also written, the controller controls the memory to cache the first verification data in the first buffer to the second buffer of the second core.

[0199] For example, if the first physical page is the last data page of the first stripe in the first tube core, and the first physical page is not the last data page of the first stripe, after the first physical write is completed, the controller sends a read instruction to the memory, the read instruction instructs to read the data cached in the first buffer, and the memory responds to the read instruction, reads the first verification data from the first buffer, and sends the first verification data to the controller; based on the first verification data, the controller sends a cache instruction to the memory, the cache instruction instructs to cache the first verification data in the second buffer, and then, the memory responds to the cache instruction and caches the first verification data in the second buffer.

[0200] Still Fig. 20 For example, assuming that physical page 3 in plane P3 in DIE0 is the first physical page of the first stripe, DIE1 is the second die, and buffer R1 in DIE1 is the second buffer, the process of caching the data stored in the first buffer to the second buffer can be referred to. Fig. 20 Step ⑥ in .

[0201] exist Fig. 20 In step ⑥, assuming that data D0-D3 has been written into DIE0, the controller sends a low-level enable signal, a high-level enable signal, and an RRB instruction (i.e., a read instruction) indicating reading buffer R0 to the CE0 signal line, the CE1 signal line, and the CH0 signal line, respectively. The peripheral circuit of DIE0 receives the RRB instruction and the enable signal transmitted by the CE0 signal line, reads the check data DR0 (D0^D1^D2^D3) cached in buffer R1, and returns the check data DR0 to the controller through the CH1 signal line. After the controller obtains the check data DR0, it uses the check data DR0 as the check data DR of the first stripe. See Fig.21In step ①, the controller generates a WRB instruction (i.e., a cache instruction) instructing the buffer R1 to write the verification data DR based on the verification data DR (i.e., DR0), and sends an enable signal at a high level, an enable signal at a low level, and the WRB instruction to the CE0 signal line, the CE1 signal line, and the CH0 signal line, respectively. The peripheral circuit of DIE1 writes the verification data DR to the buffer R1 according to the WRB instruction and the enable signal transmitted by the CE1 signal line.

[0202] Above Fig. 20 The example of writing data to each data page of the first stripe in the same die in sequence is used as an example. In other embodiments, the controller may write data to the data page of the first stripe in the same die in a disorderly or random manner instead of in the order of the data pages in the first stripe. Fig. 20 Steps ②, ③, and ④ in the embodiment are executed in this order. For example, step ④ may be executed first, and then step ② or ③. Therefore, the embodiment of the present application Fig. 20 There is no restriction on the execution order of steps ②, ③, and ④.

[0203] When the first stripe is provided by multiple tube cores and the first stripe is organized according to the Plane RAID strategy, in some embodiments, after the controller finishes writing the data page of the first stripe in a tube core, it caches the verification data of the data currently written in the first stripe in the tube core to the buffer in the next tube core, and then writes the data page of the first stripe in the tube core, so as to use the XOR circuit connected to the buffer of the next tube core to perform an XOR circuit on the verification data of the first stripe in the tube core and the data written in the data page of the first stripe in the next tube core, until all the data pages of the first stripe in multiple tube cores are written, and the verification data cached in the buffer in the tube core where the last data page written is located is the final verification data P of the first stripe, and the final verification data P is written to the verification page of the first stripe.

[0204] Still Fig. 20 For example, when all data pages of the first stripe in DIE0 are written, the controller caches the check data DR0 cached in the buffer R0 to the buffer R1 in DIE1, such as Fig.21 As shown, according to Fig. 20 In the method of writing data to the data page of the first stripe, continue to write data to each data page of the first stripe of DIE1. After all data pages of the first stripe in DIE1 are written, the check data DR1 cached in the buffer R1 is cached in the buffer R2 in DIE2. Fig. 22 As shown, according to Fig. 20In the manner of writing data to the data page of the first stripe, data is continuously written to each data page of the first stripe of DIE2. After all data pages of the first stripe in DIE2 are written, the check data DR2 cached in the buffer R2 is cached in the buffer R3 in DIE3. Fig.23 As shown, after all data pages of the first stripe in DIE3 are written, the check data DR3 cached in the buffer R3 is used as the final check data (RAID Parity) P of the first stripe, and P is written to the physical page 15 (i.e., the check page of the first stripe) in the plane P3 of DIE3.

[0205] The above is to write data pages to the first stripe in the order of the tube cores. In other embodiments, data may be written to the first stripe not in the order of the tube cores. For example, after the writing of each data page of the first stripe in any tube core is completed, the verification data of the first stripe in the buffer of the tube core is cached to the buffer of the tube core where the verification page of the first stripe is located. In this way, the first verification data of each first stripe in each tube core will be transmitted to the buffer of the tube core where the verification page is located, and then the final verification data of the first stripe can be calculated through the XOR circuit of the tube core where the verification page is located.

[0206] based on Figure 20-23 In the embodiment shown, a cache (such as a first cache) is set in the core of the memory. When the stripes are organized according to the Plane RAID strategy, when writing data to the data page of the stripe, the verification data between the currently written data and the data already written to the stripe is cached in the cache, thereby eliminating the need to allocate storage space for the verification page of the stripe from the cache space of the controller, so that more space in the cache space can be allocated to the data page, thereby improving the random read and write performance of the memory.

[0207] In the case where the first stripe is organized according to the Plane RAID strategy, in the case where the first data written to the first physical page in the first stripe is abnormal, for each of the multiple tube cores providing the first stripe, the controller controls the memory to read the data in the third physical page of the first stripe in the tube core to the XOR circuit in the tube core, and the XOR circuit performs XOR operation on the data in each third physical page on the first stripe in the tube core to obtain target intermediate verification data, and outputs the target intermediate verification data to the buffer in the tube core, and the third physical page is a physical page on the first stripe in the tube core where no data abnormality occurs. The controller controls the memory to read the target intermediate verification data from the buffers in the multiple tube cores respectively, and the controller reconstructs the first data based on the multiple target intermediate verification data read.

[0208] For example, suppose Fig. 20 The first stripe is composed of physical pages 0-15 provided by DIE0-DIE3. Fig.24 As shown, the data D5 stored in the physical page 5 in the first stripe is abnormal, and the physical pages 0-4 and the physical pages 6-15 are all the third physical pages in the first stripe. Before reconstructing the data stored in the physical page 5, the controller first clears the buffer corresponding to the physical pages of the first stripe in DIE0-DIE3. Fig.24 As shown, the controller sends an enable signal at a low level, an enable signal at a high level, and a CRB instruction to clear the corresponding buffer to the CE0 signal line, the CE1 signal line, and the CH0 signal line, and then sends an enable signal at a high level, an enable signal at a low level, and the CRB instruction to the CE0 signal line, the CE1 signal line, and the CH0 signal line, and then sends an enable signal at a low level, an enable signal at a high level, and the CRB instruction to the CE0 signal line, the CE1 signal line, and the CH1 signal line, and then sends an enable signal at a high level, an enable signal at a low level, and the CRB instruction to the CE0 signal line, the CE1 signal line, and the CH1 signal line, respectively. The peripheral circuit of DIE0 enables DIE0 according to the enable signal transmitted by the CE0 signal line, and clears the data cached in the buffer R1 according to the CRB instruction transmitted by the CH0 signal line. The peripheral circuit of DIE1 enables DIE1 according to the enable signal transmitted by the CE1 signal line, and clears the data cached in buffer R2 according to the CRB instruction transmitted by the CH0 signal line. The peripheral circuit of DIE2 enables DIE20 according to the enable signal transmitted by the CE0 signal line, and clears the data cached in buffer R2 according to the CRB instruction transmitted by the CH1 signal line. The peripheral circuit of DIE3 enables DIE3 according to the enable signal transmitted by the CE1 signal line, and clears the data cached in buffer R3 according to the CRB instruction transmitted by the CH1 signal line.

[0209] After clearing the buffers R1-R3, the controller controls the peripheral circuits in DIE0-DIE3 to write the value 0 into the buffers R1-R3 respectively to prepare for the subsequent calculation of the target verification data. Fig.25As shown, the controller sends an enable signal at a low level, an enable signal at a high level, and an RRD instruction to the CE0 signal line, the CE1 signal line, and the CH0 signal line, respectively. The RRD instruction indicates that physical pages 0-3 in DIE0 are read into the cache in the plane respectively. The peripheral circuit in DIE0 enables DIE0 according to the enable signal transmitted by the CE0 signal line, and reads the data in physical page 0 of plane P0 of DIE0 into the cache of plane P0, reads the data in physical page 1 of plane P1 of DIE0 into the cache of plane P1, reads the data in physical page 2 of plane P2 of DIE0 into the cache of plane P2, and reads the data in physical page 3 of plane P3 of DIE0 into the cache of plane P3 according to the RRD instruction transmitted by the CH0 signal line. Fig.25 In step ①, the controller sends a cache read instruction R / B_0 to the peripheral circuit of DIE0. According to the read instruction R / B_0, the peripheral circuit reads the data of physical page 0 cached in the cache of plane P0 of DIE0, the data of physical page 1 cached in the cache of plane P1 of DIE0, the data of physical page 2 cached in the cache of plane P2 of DIE0, and the data of physical page 3 cached in the cache of plane P3 of DIE0 to the XOR circuit connected to the cache R0. The XOR circuit performs an XOR operation on the input data of physical page 0-physical page 3 and the value 0 input to the cache R0 to obtain a target check data of the first stripe, and outputs the target check data to the cache R0. At this time, the target check data is the check data DR0 in the cache R0.

[0210] like Fig.25 As shown, after sending the first RRD instruction, the controller also sends a high-level enable signal, a low-level enable signal, and an RRD instruction to the CE0 signal line, the CE1 signal line, and the CH0 signal line, respectively. The RRD instruction indicates that physical pages 4, 6, and 7 in DIE1 are read into the cache in the plane respectively. The peripheral circuit in DIE1 enables DIE1 according to the enable signal transmitted by the CE1 signal line, and reads the data in physical page 4 of plane P0 of DIE1 into the cache of plane P0, reads the data in physical page 6 of plane P2 of DIE1 into the cache of plane P2, and reads the data in physical page 7 of plane P3 of DIE1 into the cache of plane P3 according to the RRD instruction transmitted by the CH0 signal line. Fig.25In step ②, the controller sends a cache read instruction R / B_1 to the peripheral circuit of DIE1. According to the read instruction R / B_1, the peripheral circuit reads the data of physical page 4 cached in the cache of plane P0 of DIE1, the data of physical page 6 cached in the cache of plane P2 of DIE0, and the data of physical page 7 cached in the cache of plane P3 of DIE1 to the XOR circuit connected to the cache R1. The XOR circuit performs an XOR operation on the input data of physical pages 4, 6, and 7 and the value 0 input to the cache R1 to obtain a target check data for the first stripe, and outputs the target check data to the cache R1. At this time, the target check data is the check data DR1 in the cache R1.

[0211] like Fig.25 As shown, after sending the second RRD instruction, the controller controls the peripheral circuit in DIE2 according to the control method of DIE0, and caches the physical pages 8-11 of the first strip in DIE2 to the cache of the plane where the physical pages 8-11 are located, and executes step ③ in a similar manner to step ① to obtain the XOR operation result between the data in physical pages 8-11 (i.e., a target verification data), and caches the target verification data to the buffer R2. At this time, the target verification data is the verification data DR2 cached in the buffer R2. After sending the third RRD instruction, the controller controls the peripheral circuit in DIE3 according to the control method of DIE0, and caches the physical pages 12-15 of the first strip in DIE3 to the cache of the plane where the physical pages 12-15 are located, and executes step 4 in a similar manner to step 1 to obtain the XOR operation result between the data in physical pages 12-15 (i.e., a target verification data), and caches the target verification data to the buffer R3. At this time, the target verification data is the verification data DR3 cached in the buffer R3. Afterwards, Fig.25 In step ⑤, the controller reads the verification data DR0 from the buffer R0, such as Fig.25 In step ⑥, the controller reads the verification data DR1 from the buffer R1, such as Fig.25 In step ⑦, the controller reads the verification data DR2 from the buffer R2, such as Fig.25 In step ⑧, the controller reads the verification data DR3 from the buffer R3. The verification data DR1-DR3 read by the controller are all target verification data of the first stripe. The controller reconstructs the abnormal data D5 based on the verification data DR1-DR3.

[0212] Fig.25The controller controls the memory to first read the data in each third physical page of the first stripe into the cache of the plane where the data is located, and then reads the third physical data in the cache into the XOR circuit as an example for explanation. In other embodiments, the controller does not control the memory to read the data in each third physical page of the first stripe into the cache of the plane where the data is located, but directly controls the memory to read the data stored in the third physical page of the first stripe into the XOR circuit, such as Fig.17 The data is read directly into the XOR circuit. It should be understood that Fig.17 When data reconstruction is performed, the data to be read may be first read into the cache of the plane where the data is located, and then the data to be read in the cache is read into the XOR circuit.

[0213] against Figure 24-25 The data reconstruction process calculates the intermediate check data used to reconstruct the abnormal data through the buffer in the tube core and the peripheral circuit, which can reduce the SRAM occupation of the controller, so that the controller has sufficient SRAM space to randomly read and write the memory, which is beneficial to improve the random read and write performance of the controller.

[0214] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A storage system, characterized in that: The system includes a memory and a controller, wherein the memory includes a plurality of dies, each of the dies includes a plurality of physical pages, the physical pages in the plurality of dies form a plurality of stripes, at least one of the plurality of dies further includes a buffer, and the memory is coupled to the controller; The controller is configured to send a first write instruction to the memory, wherein the first write instruction indicates writing first data to a first physical page of a first stripe among the plurality of stripes; The memory is configured to cache first check data between the first data and written data of the first stripe through a first buffer in the at least one die in response to the first write instruction, and write the first data to the first physical page.

2. The system according to claim 1, characterized in that The first die where the first buffer is located further includes an XOR circuit, and the XOR circuit is coupled to the first buffer; the memory is further configured as follows: The XOR circuit performs an XOR operation on the first data and the second verification data in the first buffer to obtain the first verification data, which is then output to the first buffer. The second verification data is verification data between the written data.

3. The system according to claim 1 or 2, characterized in that: Each die includes a plurality of planes, each plane includes a plurality of physical pages, and the first stripe includes a plurality of physical pages within a plane in each die.

4. The system according to claim 3, characterized in that The first buffer is located in the tube die where the check page of the first stripe is located.

5. The system according to claim 1 or 2, characterized in that: Each die includes a plurality of planes, each plane includes a plurality of physical pages, and the first stripe includes a plurality of physical pages within each plane in each die.

6. The system according to claim 5, characterized in that The first buffer and the first physical page are both located on a first die of the at least one die; The controller is further configured to send a second write instruction to the memory, wherein the second write instruction instructs writing second data to a second physical page of the first stripe in the first die; The memory is further configured to cache third verification data between the second data and the first verification data through the first buffer in response to the second write instruction, and write the second data to the second physical page.

7. The system according to claim 6, characterized in that Each die includes the buffer, and the controller is further configured to: If the first physical page is the last data page of the first stripe in the first core, and the first physical page is not the last data page of the first stripe, control the memory to write the first check data in the first buffer into the second buffer of the second core, and the second core is the core where the next data page of the first physical page on the first stripe is located.

8. The system according to claim 7, characterized in that The controller is further configured to send a read instruction to the memory if the first physical page is the last data page of the first stripe in the first die and the first physical page is not the last data page of the first stripe, the read instruction instructing to read data cached in the first buffer; The memory is further configured to read the first verification data from the first buffer in response to the read instruction, and send the first verification data to the controller; The controller is further configured to send a cache instruction to the memory based on the first verification data, wherein the cache instruction indicates to cache the first verification data in the second buffer; The memory is further configured to cache the first verification data in the second cache in response to the cache instruction.

9. The system according to any one of claims 5 to 8, characterized in that: Each die includes an XOR circuit and the buffer, and the XOR circuit of each die is coupled to the buffer of the die; the controller is further configured to: In the case where data in the first physical page is abnormal, the memory is controlled to read data in the third physical page of the first stripe in each tube core to the XOR circuit of each tube core respectively, and the XOR circuit performs an XOR operation on the data in the third physical page of the first stripe in the tube core to obtain target intermediate verification data, and outputs the target intermediate verification data to the buffer in the tube core, wherein the third physical page is a physical page on which no data abnormality occurs on the first stripe; The control memory reads the target intermediate verification data from the buffers in the plurality of dies respectively, and reconstructs the first data based on the plurality of the read target intermediate verification data.

10. The system according to any one of claims 1 to 9, characterized in that: The controller is also configured to: If the first physical page is the last data page of the first stripe, the memory is controlled to write the first check data in the first buffer into a check page of the stripe.

11. The system according to claim 10, characterized in that The controller is further configured to send a read instruction to the memory if the first physical page is the last data page of the first stripe, the read instruction instructing to read the data cached in the first buffer; The memory is further configured to read the first verification data from the first buffer in response to the read instruction, and send the first verification data to the controller; The controller is further configured to send a third write instruction to the memory based on the first verification data, wherein the third write instruction instructs writing the first verification data into the verification page; The memory is further configured to write the first verification data to the verification page in response to the third write instruction.

12. The system according to any one of claims 1 to 10, characterized in that: The physical page includes a storage unit, which is used to store N bits of data. Each of the at least one tube core includes N buffers, each buffer corresponds to one bit of the N bits, and each buffer is used to cache the check data of the data page of the stripe on the corresponding bit, and N is an integer greater than or equal to 1.

13. The system according to any one of claims 1 to 12, characterized in that: The buffer is a latch or a static random access memory.

14. A memory, characterized in that: The memory includes a plurality of dies, each of which includes a plurality of physical pages, the physical pages in the plurality of dies form a plurality of stripes, at least one of the plurality of dies further includes a buffer, and the memory is configured as follows: receiving a first write instruction, wherein the first write instruction instructs writing first data to a first physical page of a first stripe among the plurality of stripes; In response to the first write instruction, first check data between the first data and the written data of the first stripe is cached through a first buffer in the at least one die, and the first data is written to the first physical page.

15. The memory according to claim 14, characterized in that: The first die where the first buffer is located further includes an XOR circuit, and the XOR circuit is coupled to the first buffer; the memory is further configured as follows: The XOR circuit performs an XOR operation on the first data and the second verification data in the first buffer to obtain the first verification data, which is then output to the first buffer. The second verification data is verification data between the written data.

16. The memory according to claim 14 or 15, characterized in that: Each die includes a plurality of planes, each plane includes a plurality of physical pages, and the first stripe includes a plurality of physical pages within a plane in each die.

17. The memory according to claim 16, characterized in that: The first buffer is located in the tube die where the check page of the first stripe is located.

18. The memory according to claim 14 or 15, characterized in that: Each die includes a plurality of planes, each plane includes a plurality of physical pages, and the first stripe includes a plurality of physical pages within each plane in each die.

19. The memory according to claim 18, characterized in that: The first buffer and the first physical page are both located in a first die of the at least one die; the memory is further configured as: receiving a second write instruction, wherein the second write instruction instructs writing second data to a second physical page of the first stripe in the first die; In response to the second write instruction, third verification data between the second data and the first verification data is cached through the first buffer, and the second data is written to the second physical page.

20. The memory according to claim 19, characterized in that The memory is further configured to: receiving a read instruction from a controller, wherein the read instruction instructs reading data cached in the first buffer; In response to the read instruction, read the first verification data from the first buffer, and send the first verification data to the controller; receiving a cache instruction from the controller, the cache instruction instructing to cache the first verification data in a second cache of a second die, where the second die is a die where a next data page of the first physical page on the first stripe is located; In response to the cache instruction, the first verification data is cached in the second cache.

21. The memory according to any one of claims 18 to 20, characterized in that: Each die includes an XOR circuit and the buffer, and the XOR circuit of each die is coupled to the buffer of the die; the memory is configured as follows: In the event that the first physical page fails, the data stored in the third physical page on the third stripe in each tube core is read into the XOR circuit of each tube core, and the XOR circuit performs an XOR operation on the data stored in each third physical page on the third stripe in the tube core to obtain the target intermediate check data of the first stripe, and outputs the target intermediate check data to the connected buffer. The third physical page is a physical page on the first stripe where no data abnormality occurs.

22. The memory according to any one of claims 14 to 21, characterized in that: The memory is further configured to: receiving a read instruction from a controller, wherein the read instruction instructs reading data cached in the first buffer; In response to the read instruction, the first verification data is read from the first buffer, and the first verification data is sent to the controller.

23. The memory according to any one of claims 14 to 22, characterized in that: The physical page includes a storage unit, which is used to store N bits of data. Each of the at least one tube core includes N buffers, each buffer corresponds to one bit of the N bits, and each buffer is used to cache the check data of the data page of the stripe on the corresponding bit, and N is an integer greater than or equal to 1.

24. The memory according to any one of claims 14 to 23, characterized in that: The buffer is a latch or a static random access memory.

25. A stripe-based data caching method, characterized in that: The method is applied to a memory and a controller of the memory, and the method comprises: The controller sends a first write instruction to the memory, the first write instruction instructing to write first data to a first physical page of a first stripe, the first stripe being provided by a plurality of dies in the memory; In response to the first write instruction, the memory caches first check data between the first data and the written data of the first stripe through a first buffer in the at least one die, and writes the first data to the first physical page.

26. The method according to claim 25, characterized in that The caching, by means of a first buffer in the at least one die, first check data between the first data and the written data of the first stripe comprises: An XOR circuit connected to the first buffer performs an XOR operation on the first data and the second verification data in the first buffer to obtain the first verification data, which is output to the first buffer. The second verification data is the verification data between the written data.

27. The method according to claim 25 or 26, characterized in that The method further comprises: The controller sends a second write instruction to the memory, wherein the second write instruction instructs writing second data to a second physical page of the first stripe in the first die; In response to the second write instruction, the memory caches the third verification data between the second data and the first verification data through the first buffer, and writes the second data to the second physical page.

28. The method according to claim 27, characterized in that The method further comprises: If the first physical page is the last data page of the first stripe in the first die, and the first physical page is not the last data page of the first stripe, the controller controls the memory to write the first check data in the first buffer into the second buffer of the second die, the first die is the die where the first buffer and the first physical page are located, and the second die is the die where the next data page of the first physical page on the first stripe is located.

29. The method according to claim 28, characterized in that The controller controls the memory to write the first verification data in the first buffer into the second buffer of the second die, comprising: The controller sends a read instruction to the memory, wherein the read instruction instructs reading data cached in the first buffer; The memory reads the first verification data from the first buffer in response to the read instruction, and sends the first verification data to the controller; The controller sends a cache instruction to the memory based on the first verification data, wherein the cache instruction instructs to cache the first verification data in the second buffer; The memory caches the first verification data in the second cache in response to the cache instruction.

30. The method according to any one of claims 27 to 29, characterized in that The method further comprises: In the case that data in the first physical page is abnormal, the controller controls the memory to read data in the third physical page of the first stripe in each tube core to the XOR circuit of each tube core respectively, and the XOR circuit performs an XOR operation on the data in the third physical page of the first stripe in the tube core to obtain target intermediate verification data, and outputs the target intermediate verification data to the buffer in the tube core, wherein the third physical page is a physical page on which no data abnormality occurs on the first stripe; The controller controls the memory to read the target intermediate verification data from the buffers in the plurality of dies respectively, and reconstructs the first data based on the plurality of the read target intermediate verification data.

31. The method according to any one of claims 25 to 30, characterized in that The method further comprises: If the first physical page is the last data page of the first stripe, the controller controls the memory to write the first check data in the first buffer into the check page of the stripe.

32. The method according to claim 31, characterized in that The controller controls the memory to write the first check data in the first buffer into the check page of the stripe, comprising: The controller sends a read instruction to the memory, wherein the read instruction instructs reading data cached in the first buffer; The memory reads the first verification data from the first buffer in response to the read instruction, and sends the first verification data to the controller; The controller sends a third write instruction to the memory based on the first verification data, wherein the third write instruction instructs writing the first verification data into the verification page; The memory writes the first verification data to the verification page in response to the third write instruction.

33. A computer-readable storage medium applied to a storage system, characterized in that: The storage system includes a memory and a controller, and at least one program code is stored in the storage medium. The at least one program code is read by a processor in the memory so that the memory executes the method steps executed by the memory in the method described in any one of claims 25 to 32, or the at least one program code is read by a processor in the controller so that the controller executes the method steps executed by the controller in the method described in any one of claims 25 to 32.

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